initial commit, add dds_par module
This commit is contained in:
@@ -0,0 +1,15 @@
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####################################################################################
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## Copyright (c) 2018 - 2023 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := util_mii_to_rmii
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GENERIC_DEPS += mac_phy_link.v
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GENERIC_DEPS += phy_mac_link.v
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GENERIC_DEPS += util_mii_to_rmii.v
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XILINX_DEPS += util_mii_to_rmii_ip.tcl
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include ../scripts/library.mk
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@@ -0,0 +1,702 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<spirit:vendor>analog.com</spirit:vendor>
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||||
<spirit:library>user</spirit:library>
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||||
<spirit:name>util_mii_to_rmii</spirit:name>
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||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
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||||
<spirit:busInterface>
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||||
<spirit:name>GMII</spirit:name>
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||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="gmii" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="gmii_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
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||||
<spirit:name>COL</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>mii_col</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
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||||
<spirit:name>CRS</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
|
||||
<spirit:name>mii_crs</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RXD</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>mii_rxd</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RX_CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
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||||
<spirit:name>mii_rx_clk</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RX_DV</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>mii_rx_dv</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
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||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RX_ER</spirit:name>
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||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>mii_rx_er</spirit:name>
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||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TXD</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>mac_txd</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TX_CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>mii_tx_clk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TX_EN</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>mac_tx_en</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TX_ER</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>mac_tx_er</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:busInterfaceInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.GMII" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.INTF_CFG')) = 1)">false</xilinx:isEnabled>
|
||||
</xilinx:enablement>
|
||||
</xilinx:busInterfaceInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>MII</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mii" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mii_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>COL</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>mii_col</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CRS</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>mii_crs</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RXD</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>mii_rxd</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RX_CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>mii_rx_clk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RX_DV</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>mii_rx_dv</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RX_ER</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>mii_rx_er</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TXD</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>mac_txd</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TX_CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>mii_tx_clk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TX_EN</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>mac_tx_en</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TX_ER</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>mac_tx_er</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:busInterfaceInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.MII" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.INTF_CFG')) = 0)">true</xilinx:isEnabled>
|
||||
</xilinx:enablement>
|
||||
</xilinx:busInterfaceInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>RMII</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="rmii" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="rmii_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CRS_DV</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>phy_crs_dv</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RXD</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>phy_rxd</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RX_ER</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>phy_rx_er</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TXD</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>rmii_txd</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TX_EN</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>rmii_tx_en</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>reset_n</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>reset_n</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>ref_clk</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>ref_clk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:language>Verilog</spirit:language>
|
||||
<spirit:modelName>util_mii_to_rmii</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>7f96d891</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:language>Verilog</spirit:language>
|
||||
<spirit:modelName>util_mii_to_rmii</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>7f96d891</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_xpgui</spirit:name>
|
||||
<spirit:displayName>UI Layout</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>c554a0dc</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>mac_tx_en</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>mac_txd</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">3</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>mac_tx_er</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>mii_tx_clk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>mii_rx_clk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>mii_col</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>mii_crs</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>mii_rx_dv</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>mii_rx_er</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>mii_rxd</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">3</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>rmii_txd</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">1</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>rmii_tx_en</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>phy_rxd</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">1</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>phy_crs_dv</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>phy_rx_er</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>ref_clk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>reset_n</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>INTF_CFG</spirit:name>
|
||||
<spirit:displayName>Intf Cfg</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.INTF_CFG">0</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>RATE_10_100</spirit:name>
|
||||
<spirit:displayName>Rate 10 100</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RATE_10_100">0</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
<spirit:choices>
|
||||
<spirit:choice>
|
||||
<spirit:name>choice_pairs_7362e83f</spirit:name>
|
||||
<spirit:enumeration spirit:text="MII">0</spirit:enumeration>
|
||||
<spirit:enumeration spirit:text="GMII">1</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
<spirit:choice>
|
||||
<spirit:name>choice_pairs_bf1c9d7a</spirit:name>
|
||||
<spirit:enumeration spirit:text="100Mbps">0</spirit:enumeration>
|
||||
<spirit:enumeration spirit:text="10Mbps">1</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>mac_phy_link.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>phy_mac_link.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>util_mii_to_rmii.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>CHECKSUM_4eec8a2d</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>mac_phy_link.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>phy_mac_link.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>util_mii_to_rmii.v</spirit:name>
|
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<spirit:fileType>verilogSource</spirit:fileType>
|
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</spirit:file>
|
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</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>xgui/util_mii_to_rmii_v1_0.tcl</spirit:name>
|
||||
<spirit:fileType>tclSource</spirit:fileType>
|
||||
<spirit:userFileType>CHECKSUM_7db2218e</spirit:userFileType>
|
||||
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>MII to RMII Converter IP</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INTF_CFG</spirit:name>
|
||||
<spirit:displayName>Interface Selection</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.INTF_CFG" spirit:choiceRef="choice_pairs_7362e83f">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>RATE_10_100</spirit:name>
|
||||
<spirit:displayName>Rate Selection</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.RATE_10_100" spirit:choiceRef="choice_pairs_bf1c9d7a">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">util_mii_to_rmii_v1_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:supportedFamilies>
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<xilinx:family xilinx:lifeCycle="Production">virtex7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qvirtex7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">versal</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">kintex7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">kintex7l</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qkintex7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qkintex7l</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">akintex7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">artix7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">artix7l</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">aartix7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qartix7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qzynq</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">azynq</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">spartan7</xilinx:family>
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||||
<xilinx:family xilinx:lifeCycle="Production">aspartan7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">virtexu</xilinx:family>
|
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<xilinx:family xilinx:lifeCycle="Production">zynquplus</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">virtexuplus</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">virtexuplusHBM</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">virtexuplus58g</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">kintexuplus</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">artixuplus</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">kintexu</xilinx:family>
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</xilinx:supportedFamilies>
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<xilinx:taxonomies>
|
||||
<xilinx:taxonomy>/Analog_Devices</xilinx:taxonomy>
|
||||
</xilinx:taxonomies>
|
||||
<xilinx:displayName>util_mii_to_rmii</xilinx:displayName>
|
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<xilinx:autoFamilySupportLevel>level_2</xilinx:autoFamilySupportLevel>
|
||||
<xilinx:definitionSource>package_project</xilinx:definitionSource>
|
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<xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
|
||||
<xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
|
||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
||||
<xilinx:coreCreationDateTime>2024-01-14T03:55:44Z</xilinx:coreCreationDateTime>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="67b1a9b4"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="62d67d61"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="e10b60ca"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="c4cdb13a"/>
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||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
@@ -0,0 +1,139 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module mac_phy_link #(
|
||||
parameter RATE_10_100 = 0
|
||||
) (
|
||||
input ref_clk,
|
||||
input [3:0] mac_txd,
|
||||
input reset_n,
|
||||
input mac_tx_en,
|
||||
input mac_tx_er,
|
||||
output rmii_tx_en,
|
||||
output [1:0] rmii_txd,
|
||||
output mii_tx_clk
|
||||
);
|
||||
|
||||
wire dibit_sample;
|
||||
wire [3:0] num_w;
|
||||
wire tx_dibit;
|
||||
wire [4:0] reg_count_w;
|
||||
|
||||
reg [3:0] mac_txd_r = 4'b0;
|
||||
reg mac_tx_en_r = 1'b0;
|
||||
reg mac_tx_er_r = 1'b0;
|
||||
reg mii_tx_clk_10_100_r = 1'b0;
|
||||
reg [3:0] num_r = 4'b0;
|
||||
reg [1:0] rmii_txd_r = 2'b0;
|
||||
reg rmii_tx_en_r = 1'b0;
|
||||
reg rising_tx_clk_r0 = 1'b0;
|
||||
reg rising_tx_clk_r1 = 1'b0;
|
||||
reg [4:0] reg_count = 5'b0;
|
||||
|
||||
localparam DIV_REF_CLK = RATE_10_100 ? 10 : 1;
|
||||
|
||||
always @(posedge ref_clk) begin
|
||||
if (!reset_n) begin
|
||||
num_r <= 0;
|
||||
mii_tx_clk_10_100_r <= 1'b0;
|
||||
end else if (num_w == DIV_REF_CLK) begin
|
||||
num_r <= 0;
|
||||
mii_tx_clk_10_100_r <= ~mii_tx_clk_10_100_r;
|
||||
if (!mii_tx_clk_10_100_r) begin
|
||||
rising_tx_clk_r0 <= 1'b1;
|
||||
rising_tx_clk_r1 <= rising_tx_clk_r0;
|
||||
end else begin
|
||||
rising_tx_clk_r0 <= 1'b0;
|
||||
rising_tx_clk_r1 <= rising_tx_clk_r0;
|
||||
end
|
||||
rising_tx_clk_r1 <= rising_tx_clk_r0;
|
||||
end else begin
|
||||
num_r <= num_w;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge ref_clk) begin
|
||||
if (!reset_n) begin
|
||||
mac_txd_r <= 4'b0;
|
||||
mac_tx_en_r <= 1'b0;
|
||||
mac_tx_er_r <= 1'b0;
|
||||
end else begin
|
||||
if (dibit_sample == 1'b1) begin
|
||||
mac_txd_r <= mac_txd;
|
||||
mac_tx_en_r <= mac_tx_en;
|
||||
mac_tx_er_r <= mac_tx_er;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge ref_clk) begin
|
||||
if (!reset_n) begin
|
||||
rmii_txd_r <= 2'b0;
|
||||
rmii_tx_en_r <= 1'b0;
|
||||
end else begin
|
||||
if (!tx_dibit) begin
|
||||
rmii_txd_r[0] <= mac_txd_r[0] ^ mac_tx_er_r;
|
||||
rmii_txd_r[1] <= mac_txd_r[1] | mac_tx_er_r;
|
||||
rmii_tx_en_r <= mac_tx_en_r;
|
||||
end else begin
|
||||
rmii_txd_r[0] <= mac_txd_r[2] ^ mac_tx_er_r;
|
||||
rmii_txd_r[1] <= mac_txd_r[3] | mac_tx_er_r;
|
||||
rmii_tx_en_r <= mac_tx_en_r;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge ref_clk) begin
|
||||
if (!reset_n) begin
|
||||
reg_count <= 1'b0;
|
||||
end else begin
|
||||
if (reg_count_w == 5'b10011) begin
|
||||
reg_count <= 1'b0;
|
||||
end else begin
|
||||
reg_count <= reg_count + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign dibit_sample = RATE_10_100 ? ((reg_count_w == 5'b01001) ? 1'b1 : 1'b0) : rising_tx_clk_r1;
|
||||
assign num_w = num_r + 1;
|
||||
assign mii_tx_clk = mii_tx_clk_10_100_r;
|
||||
assign reg_count_w = reg_count;
|
||||
assign rmii_txd = rmii_txd_r;
|
||||
assign rmii_tx_en = rmii_tx_en_r;
|
||||
assign tx_dibit = ~mii_tx_clk;
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,281 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module phy_mac_link #(
|
||||
parameter RATE_10_100 = 0
|
||||
) (
|
||||
input ref_clk,
|
||||
input reset_n,
|
||||
input [1:0] phy_rxd,
|
||||
input phy_crs_dv,
|
||||
input phy_rx_er,
|
||||
output [3:0] mii_rxd,
|
||||
output mii_rx_dv,
|
||||
output mii_rx_er,
|
||||
output mii_crs,
|
||||
output mii_col,
|
||||
output mii_rx_clk
|
||||
);
|
||||
|
||||
wire clk_phase_res;
|
||||
wire data_valid_w;
|
||||
wire dibit_sample;
|
||||
wire eopack_w;
|
||||
wire [3:0] num_w;
|
||||
wire [3:0] reg_count_w;
|
||||
wire sopack_w;
|
||||
|
||||
reg mii_rx_clk_10_100_r = 1'b0;
|
||||
reg [3:0] num_r = 4'b0;
|
||||
reg [3:0] reg_count = 4'b0;
|
||||
|
||||
reg clk_phase_r = 1'b0;
|
||||
reg data_valid = 1'b0;
|
||||
reg data_valid_d = 1'b0;
|
||||
reg [1:0] eopack_r = 2'b0;
|
||||
reg nibble_valid = 1'b0;
|
||||
reg [1:0] sopack_r = 2'b0;
|
||||
|
||||
reg [3:0] mii_rxd_r0 = 4'b0;
|
||||
reg [3:0] mii_rxd_r1 = 4'b0;
|
||||
reg [3:0] mii_rxd_r2 = 4'b0;
|
||||
|
||||
reg mii_rx_er_r0 = 1'b0;
|
||||
reg mii_rx_er_r1 = 1'b0;
|
||||
reg mii_rx_er_r2 = 1'b0;
|
||||
|
||||
reg mii_rx_dv_r0 = 1'b0;
|
||||
reg mii_rx_dv_r1 = 1'b0;
|
||||
reg mii_rx_dv_r2 = 1'b0;
|
||||
reg mii_rx_dv_r3 = 1'b0;
|
||||
|
||||
localparam DIV_REF_CLK = RATE_10_100 ? 10 : 1;
|
||||
|
||||
always @(posedge ref_clk) begin
|
||||
if (!reset_n) begin
|
||||
num_r <= 0;
|
||||
mii_rx_clk_10_100_r <= 1'b0;
|
||||
end else if (num_w == DIV_REF_CLK) begin
|
||||
num_r <= 0;
|
||||
mii_rx_clk_10_100_r <= ~mii_rx_clk_10_100_r;
|
||||
end else begin
|
||||
num_r <= num_w;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge ref_clk) begin
|
||||
if (!reset_n) begin
|
||||
mii_rxd_r0 <= 4'b0;
|
||||
mii_rxd_r1 <= 4'b0;
|
||||
mii_rxd_r2 <= 4'b0;
|
||||
end else begin
|
||||
if (RATE_10_100) begin
|
||||
if (dibit_sample) begin
|
||||
mii_rxd_r0[3:2] <= phy_rxd;
|
||||
mii_rxd_r0[1:0] <= mii_rxd_r0[3:2];
|
||||
if (nibble_valid | sopack_w) begin
|
||||
mii_rxd_r1 <= mii_rxd_r0;
|
||||
end
|
||||
mii_rxd_r2 <= mii_rxd_r1;
|
||||
end
|
||||
end else begin
|
||||
mii_rxd_r0[3:2] <= phy_rxd;
|
||||
mii_rxd_r0[1:0] <= mii_rxd_r0[3:2];
|
||||
if (nibble_valid | sopack_w) begin
|
||||
mii_rxd_r1 <= mii_rxd_r0;
|
||||
end
|
||||
mii_rxd_r2 <= mii_rxd_r1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge ref_clk) begin
|
||||
if (!reset_n) begin
|
||||
mii_rx_er_r0 <= 1'b0;
|
||||
mii_rx_er_r1 <= 1'b0;
|
||||
mii_rx_er_r2 <= 1'b0;
|
||||
end else begin
|
||||
if (RATE_10_100) begin
|
||||
if (dibit_sample) begin
|
||||
mii_rx_er_r0 <= phy_rx_er;
|
||||
mii_rx_er_r1 <= mii_rx_er_r0;
|
||||
mii_rx_er_r2 <= mii_rx_er_r1;
|
||||
end
|
||||
end else begin
|
||||
mii_rx_er_r0 <= phy_rx_er;
|
||||
mii_rx_er_r1 <= mii_rx_er_r0;
|
||||
mii_rx_er_r2 <= mii_rx_er_r1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge ref_clk) begin
|
||||
if (!reset_n) begin
|
||||
mii_rx_dv_r0 <= 1'b0;
|
||||
mii_rx_dv_r1 <= 1'b0;
|
||||
mii_rx_dv_r2 <= 1'b0;
|
||||
mii_rx_dv_r3 <= 1'b0;
|
||||
end else begin
|
||||
if (RATE_10_100) begin
|
||||
if (dibit_sample) begin
|
||||
mii_rx_dv_r0 <= phy_crs_dv;
|
||||
mii_rx_dv_r1 <= mii_rx_dv_r0;
|
||||
mii_rx_dv_r2 <= mii_rx_dv_r1;
|
||||
mii_rx_dv_r3 <= mii_rx_dv_r2;
|
||||
end
|
||||
end else begin
|
||||
mii_rx_dv_r0 <= phy_crs_dv;
|
||||
mii_rx_dv_r1 <= mii_rx_dv_r0;
|
||||
mii_rx_dv_r2 <= mii_rx_dv_r1;
|
||||
mii_rx_dv_r3 <= mii_rx_dv_r2;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge ref_clk) begin
|
||||
if (!reset_n || eopack_w) begin
|
||||
sopack_r[1:0] <= 2'b0;
|
||||
end else begin
|
||||
if (RATE_10_100) begin
|
||||
if (dibit_sample) begin
|
||||
sopack_r[1] <= sopack_r[0];
|
||||
end
|
||||
if (dibit_sample && (mii_rxd_r0[3:2] == 2'b01) && (mii_rx_dv_r0 == 1'b1) && (sopack_w == 1'b0)) begin
|
||||
sopack_r[0] <= 1'b1;
|
||||
end
|
||||
end else begin
|
||||
sopack_r[1] <= sopack_r[0];
|
||||
if ((mii_rxd_r0[3:2] == 2'b01) && (mii_rx_dv_r0 == 1'b1) && (sopack_w == 1'b0)) begin
|
||||
sopack_r[0] <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge ref_clk) begin
|
||||
if (!reset_n || sopack_w) begin
|
||||
eopack_r[1:0] <= 2'b0;
|
||||
end else begin
|
||||
if (RATE_10_100) begin
|
||||
if (dibit_sample) begin
|
||||
eopack_r[1] <= eopack_r[0];
|
||||
end
|
||||
if (dibit_sample && (mii_rx_dv_r0 == 1'b0) && (mii_rx_dv_r1 == 1'b0) && (eopack_w == 1'b0)) begin
|
||||
eopack_r[0] <= 1'b1;
|
||||
end
|
||||
end else begin
|
||||
eopack_r[1] <= eopack_r[0];
|
||||
if ((mii_rx_dv_r0 == 1'b0) && (mii_rx_dv_r1 == 1'b0) && (eopack_w == 1'b0)) begin
|
||||
eopack_r[0] <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge ref_clk) begin
|
||||
if (!reset_n) begin
|
||||
data_valid <= 1'b0;
|
||||
end else begin
|
||||
if (RATE_10_100) begin
|
||||
if (dibit_sample && sopack_w) begin
|
||||
data_valid <= 1'b1;
|
||||
end else if (dibit_sample && eopack_w) begin
|
||||
data_valid <= 1'b0;
|
||||
end
|
||||
end else begin
|
||||
if (sopack_w) begin
|
||||
data_valid <= 1'b1;
|
||||
end else if (eopack_w) begin
|
||||
data_valid <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge ref_clk) begin
|
||||
if (!reset_n) begin
|
||||
data_valid_d <= 1'b0;
|
||||
end else begin
|
||||
data_valid_d <= data_valid;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge ref_clk) begin
|
||||
if (!reset_n) begin
|
||||
clk_phase_r <= 1'b0;
|
||||
nibble_valid <= 1'b0;
|
||||
end else begin
|
||||
if (sopack_w) begin
|
||||
clk_phase_r <= mii_rx_clk;
|
||||
nibble_valid <= 1'b0;
|
||||
end else begin
|
||||
if (RATE_10_100) begin
|
||||
if (dibit_sample) begin
|
||||
nibble_valid <= ~nibble_valid;
|
||||
end
|
||||
end else begin
|
||||
nibble_valid <= ~nibble_valid;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge ref_clk) begin
|
||||
if (!reset_n) begin
|
||||
reg_count <= 1'b0;
|
||||
end else begin
|
||||
if (reg_count_w == 4'b1001) begin
|
||||
reg_count <= 1'b0;
|
||||
end else begin
|
||||
reg_count <= reg_count + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign clk_phase_res = clk_phase_r;
|
||||
assign data_valid_w = RATE_10_100 ? data_valid : (clk_phase_res ? data_valid : data_valid_d);
|
||||
assign dibit_sample = (reg_count_w == 4'b0101) ? 1'b1 : 1'b0;
|
||||
assign eopack_w = eopack_r[0] & (!eopack_r[1]);
|
||||
assign mii_crs = mii_rx_dv_r0;
|
||||
assign mii_rxd = RATE_10_100 ? (mii_rx_dv ? mii_rxd_r1 : 4'b0) : (mii_rx_dv ? (clk_phase_res ? mii_rxd_r1 : mii_rxd_r2) : 4'b0);
|
||||
assign mii_rx_clk = mii_rx_clk_10_100_r;
|
||||
assign mii_rx_dv = data_valid_w ? 1'b1 : 1'b0;
|
||||
assign mii_rx_er = mii_rx_er_r2;
|
||||
assign num_w = num_r + 1;
|
||||
assign reg_count_w = reg_count;
|
||||
assign sopack_w = sopack_r[0] & (!sopack_r[1]);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,190 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module util_mii_to_rmii #(
|
||||
parameter INTF_CFG = 0,
|
||||
parameter RATE_10_100 = 0
|
||||
) (
|
||||
|
||||
// MAC to MII(PHY)
|
||||
input mac_tx_en,
|
||||
input [3:0] mac_txd,
|
||||
input mac_tx_er,
|
||||
//MII to MAC
|
||||
output mii_tx_clk,
|
||||
output mii_rx_clk,
|
||||
output mii_col,
|
||||
output mii_crs,
|
||||
output mii_rx_dv,
|
||||
output mii_rx_er,
|
||||
output [3:0] mii_rxd,
|
||||
// RMII to PHY
|
||||
output [1:0] rmii_txd,
|
||||
output rmii_tx_en,
|
||||
// PHY to RMII
|
||||
input [1:0] phy_rxd,
|
||||
input phy_crs_dv,
|
||||
input phy_rx_er,
|
||||
// External
|
||||
input ref_clk,
|
||||
input reset_n
|
||||
);
|
||||
|
||||
reg mac_tx_en_r1 = 1'b0;
|
||||
reg [3:0] mac_txd_r1 = 4'b0;
|
||||
reg mac_tx_er_r1 = 1'b0;
|
||||
reg phy_crs_dv_r1 = 1'b0;
|
||||
reg [1:0] phy_rxd_r1 = 2'b0;
|
||||
reg phy_rx_er_r1 = 1'b0;
|
||||
reg mii_tx_clk_r1 = 1'b0;
|
||||
reg mii_rx_clk_r1 = 1'b0;
|
||||
reg mii_col_r1 = 1'b0;
|
||||
reg mii_crs_r1 = 1'b0;
|
||||
reg mii_rx_dv_r1 = 1'b0;
|
||||
reg mii_rx_er_r1 = 1'b0;
|
||||
reg [3:0] mii_rxd_r1 = 4'b0;
|
||||
reg [1:0] rmii_txd_r1 = 2'b0;
|
||||
reg rmii_tx_en_r1 = 1'b0;
|
||||
reg mac_tx_en_r2 = 1'b0;
|
||||
reg [3:0] mac_txd_r2 = 4'b0;
|
||||
reg mac_tx_er_r2 = 1'b0;
|
||||
reg phy_crs_dv_r2 = 1'b0;
|
||||
reg [1:0] phy_rxd_r2 = 2'b0;
|
||||
reg phy_rx_er_r2 = 1'b0;
|
||||
|
||||
wire mii_tx_clk_r2;
|
||||
wire mii_rx_clk_r2;
|
||||
wire mii_col_r2;
|
||||
wire mii_crs_r2;
|
||||
wire mii_rx_dv_r2;
|
||||
wire mii_rx_er_r2;
|
||||
wire [3:0] mii_rxd_r2;
|
||||
wire [1:0] rmii_txd_r2;
|
||||
wire rmii_tx_en_r2;
|
||||
|
||||
//inputs
|
||||
always @(posedge ref_clk) begin
|
||||
if (!reset_n) begin
|
||||
mac_tx_en_r1 <= 1'b0;
|
||||
mac_tx_en_r2 <= 1'b0;
|
||||
mac_txd_r1 <= 4'b0;
|
||||
mac_txd_r2 <= 4'b0;
|
||||
mac_tx_er_r1 <= 1'b0;
|
||||
mac_tx_er_r2 <= 1'b0;
|
||||
phy_crs_dv_r1 <= 1'b0;
|
||||
phy_crs_dv_r2 <= 1'b0;
|
||||
phy_rxd_r1 <= 2'b0;
|
||||
phy_rx_er_r1 <= 1'b0;
|
||||
phy_rxd_r2 <= 2'b0;
|
||||
end else begin
|
||||
mac_tx_en_r1 <= mac_tx_en;
|
||||
mac_tx_en_r2 <= mac_tx_en_r1;
|
||||
mac_txd_r1 <= mac_txd;
|
||||
mac_txd_r2 <= mac_txd_r1;
|
||||
mac_tx_er_r1 <= mac_tx_er;
|
||||
mac_tx_er_r2 <= mac_tx_er_r1;
|
||||
phy_crs_dv_r1 <= phy_crs_dv;
|
||||
phy_crs_dv_r2 <= phy_crs_dv_r1;
|
||||
phy_rxd_r1 <= phy_rxd;
|
||||
phy_rxd_r2 <= phy_rxd_r1;
|
||||
phy_rx_er_r1 <= phy_rx_er;
|
||||
phy_rx_er_r2 <= phy_rx_er_r1;
|
||||
end
|
||||
end
|
||||
|
||||
//outputs
|
||||
always @(posedge ref_clk) begin
|
||||
if (!reset_n) begin
|
||||
mii_col_r1 <= 1'b0;
|
||||
mii_crs_r1 <= 1'b0;
|
||||
mii_rx_dv_r1 <= 1'b0;
|
||||
mii_rx_er_r1 <= 1'b0;
|
||||
mii_rxd_r1 <= 4'b0;
|
||||
rmii_txd_r1 <= 2'b0;
|
||||
rmii_tx_en_r1 <= 1'b0;
|
||||
mii_tx_clk_r1 <= 1'b0;
|
||||
mii_rx_clk_r1 <= 1'b0;
|
||||
end else begin
|
||||
mii_tx_clk_r1 <= mii_tx_clk_r2;
|
||||
mii_rx_clk_r1 <= mii_rx_clk_r2;
|
||||
mii_col_r1 <= mii_crs_r2 & mac_tx_en_r2;
|
||||
mii_crs_r1 <= mii_crs_r2;
|
||||
mii_rx_dv_r1 <= mii_rx_dv_r2;
|
||||
mii_rx_er_r1 <= mii_rx_er_r2;
|
||||
mii_rxd_r1 <= mii_rxd_r2;
|
||||
rmii_txd_r1 <= rmii_txd_r2;
|
||||
rmii_tx_en_r1 <= rmii_tx_en_r2;
|
||||
end
|
||||
end
|
||||
|
||||
assign mii_crs = mii_crs_r1;
|
||||
assign mii_col = mii_col_r1;
|
||||
assign mii_rx_dv = mii_rx_dv_r1;
|
||||
assign mii_rx_er = mii_rx_er_r1;
|
||||
assign mii_rxd = mii_rxd_r1;
|
||||
assign rmii_txd = rmii_txd_r1;
|
||||
assign rmii_tx_en = rmii_tx_en_r1;
|
||||
assign mii_rx_clk = mii_rx_clk_r1;
|
||||
assign mii_tx_clk = mii_tx_clk_r1;
|
||||
|
||||
mac_phy_link #(
|
||||
.RATE_10_100(RATE_10_100)
|
||||
) mac_phy_link_inst (
|
||||
.ref_clk(ref_clk),
|
||||
.reset_n(reset_n),
|
||||
.mac_tx_en(mac_tx_en_r2),
|
||||
.mac_txd(mac_txd_r2),
|
||||
.mac_tx_er(mac_tx_er_r2),
|
||||
.mii_tx_clk(mii_tx_clk_r2),
|
||||
.rmii_txd(rmii_txd_r2),
|
||||
.rmii_tx_en(rmii_tx_en_r2));
|
||||
|
||||
phy_mac_link #(
|
||||
.RATE_10_100(RATE_10_100)
|
||||
) phy_mac_link_inst (
|
||||
.ref_clk(ref_clk),
|
||||
.reset_n(reset_n),
|
||||
.mii_crs(mii_crs_r2),
|
||||
.mii_rx_dv(mii_rx_dv_r2),
|
||||
.mii_rx_er(mii_rx_er_r2),
|
||||
.mii_rxd(mii_rxd_r2),
|
||||
.mii_rx_clk(mii_rx_clk_r2),
|
||||
.phy_rxd(phy_rxd_r2),
|
||||
.phy_crs_dv(phy_crs_dv_r2),
|
||||
.phy_rx_er(phy_rx_er_r2));
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,413 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
|
||||
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/util_mii_to_rmii/util_mii_to_rmii.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="d2ba56029db044b2b968806552cee863"/>
|
||||
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorInstallDirVCS" Val=""/>
|
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<Option Name="SimulatorInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorVersionXsim" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
|
||||
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
|
||||
<Option Name="SimulatorVersionRiviera" Val="2022.10"/>
|
||||
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
|
||||
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
|
||||
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../library"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="EnableResourceEstimation" Val="FALSE"/>
|
||||
<Option Name="SimCompileState" Val="TRUE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
||||
<Option Name="ClassicSocBoot" Val="FALSE"/>
|
||||
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="32">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/mac_phy_link.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/phy_mac_link.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/util_mii_to_rmii.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/component.xml">
|
||||
<FileInfo SFType="IPXACT"/>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="util_mii_to_rmii"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||
<Option Name="PamDesignTestbench" Val=""/>
|
||||
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
||||
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="21">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
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||||
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="features"/>
|
||||
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|
||||
<MsgAttr Name="StringsToMatch" Val="NOT"/>
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||||
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||||
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|
||||
<MsgAttr Name="StringsToMatch" Val="in"/>
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||||
<MsgAttr Name="StringsToMatch" Val="production"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="systems."/>
|
||||
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|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
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||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
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||||
<MsgAttr Name="RuleId" Val="10"/>
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<MsgAttr Name="Note" Val=""/>
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||||
<MsgAttr Name="Author" Val=""/>
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||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
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||||
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Place 30-73"/>
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||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
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<MsgAttr Name="RuleSource" Val="2"/>
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<MsgAttr Name="RuleId" Val="11"/>
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<MsgAttr Name="Note" Val=""/>
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<MsgAttr Name="CreatedTimestamp" Val=""/>
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<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
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|
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<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
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||||
<MsgAttr Name="Limit" Val="-1"/>
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<MsgAttr Name="NewSeverity" Val="WARNING"/>
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||||
<MsgAttr Name="Id" Val=""/>
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||||
<MsgAttr Name="Severity" Val="ANY"/>
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<MsgAttr Name="ShowRule" Val="1"/>
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<MsgAttr Name="RuleSource" Val="2"/>
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<MsgAttr Name="StringIsRegExp" Val="0"/>
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<MsgAttr Name="RuleId" Val="12"/>
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<MsgAttr Name="Note" Val=""/>
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<MsgAttr Name="Author" Val=""/>
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<MsgAttr Name="CreatedTimestamp" Val=""/>
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||||
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
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||||
</MsgRule>
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<MsgRule>
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<MsgAttr Name="RuleType" Val="1"/>
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|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="2"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1306"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="3"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="ERROR"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1276"/>
|
||||
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="4"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="5"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-2490"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
</Project>
|
||||
@@ -0,0 +1,110 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
# ip
|
||||
source ../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
adi_ip_create util_mii_to_rmii
|
||||
|
||||
adi_ip_files util_mii_to_rmii [list \
|
||||
"mac_phy_link.v" \
|
||||
"phy_mac_link.v" \
|
||||
"util_mii_to_rmii.v" ]
|
||||
|
||||
adi_ip_properties_lite util_mii_to_rmii
|
||||
|
||||
adi_add_bus "GMII" "slave" \
|
||||
"xilinx.com:interface:gmii_rtl:1.0" \
|
||||
"xilinx.com:interface:gmii:1.0" \
|
||||
{
|
||||
{"mii_col" "COL"} \
|
||||
{"mii_crs" "CRS"} \
|
||||
{"mii_rxd" "RXD"} \
|
||||
{"mii_rx_clk" "RX_CLK"} \
|
||||
{"mii_rx_dv" "RX_DV"} \
|
||||
{"mii_rx_er" "RX_ER"} \
|
||||
{"mac_txd" "TXD"} \
|
||||
{"mii_tx_clk" "TX_CLK"} \
|
||||
{"mac_tx_en" "TX_EN"} \
|
||||
{"mac_tx_er" "TX_ER"} \
|
||||
}
|
||||
|
||||
adi_add_bus "MII" "slave" \
|
||||
"xilinx.com:interface:mii_rtl:1.0" \
|
||||
"xilinx.com:interface:mii:1.0" \
|
||||
{
|
||||
{"mii_col" "COL"} \
|
||||
{"mii_crs" "CRS"} \
|
||||
{"mii_rxd" "RXD"} \
|
||||
{"mii_rx_clk" "RX_CLK"} \
|
||||
{"mii_rx_dv" "RX_DV"} \
|
||||
{"mii_rx_er" "RX_ER"} \
|
||||
{"mac_txd" "TXD"} \
|
||||
{"mii_tx_clk" "TX_CLK"} \
|
||||
{"mac_tx_en" "TX_EN"} \
|
||||
{"mac_tx_er" "TX_ER"} \
|
||||
}
|
||||
|
||||
adi_add_bus "RMII" "master" \
|
||||
"xilinx.com:interface:rmii_rtl:1.0" \
|
||||
"xilinx.com:interface:rmii:1.0" \
|
||||
{
|
||||
{"phy_crs_dv" "CRS_DV"} \
|
||||
{"phy_rxd" "RXD"} \
|
||||
{"phy_rx_er" "RX_ER"} \
|
||||
{"rmii_txd" "TXD"} \
|
||||
{"rmii_tx_en" "TX_EN"} \
|
||||
}
|
||||
|
||||
adi_set_bus_dependency "MII" "MII" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.INTF_CFG')) = 0)"
|
||||
adi_set_bus_dependency "GMII" "GMII" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.INTF_CFG')) = 1)"
|
||||
|
||||
set cc [ipx::current_core]
|
||||
|
||||
ipx::infer_bus_interface reset_n xilinx.com:signal:reset_rtl:1.0 $cc
|
||||
ipx::infer_bus_interface ref_clk xilinx.com:signal:clock_rtl:1.0 $cc
|
||||
|
||||
## Customize XGUI layout
|
||||
|
||||
set_property display_name "util_mii_to_rmii" $cc
|
||||
set_property description "MII to RMII Converter IP" $cc
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "pairs" \
|
||||
"value_validation_pairs" { \
|
||||
"MII" "0" \
|
||||
"GMII" "1" \
|
||||
} \
|
||||
] \
|
||||
[ipx::get_user_parameters INTF_CFG -of_objects $cc]
|
||||
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "pairs" \
|
||||
"value_validation_pairs" { \
|
||||
"100Mbps" "0" \
|
||||
"10Mbps" "1" \
|
||||
} \
|
||||
] \
|
||||
[ipx::get_user_parameters RATE_10_100 -of_objects $cc]
|
||||
|
||||
ipgui::add_param -name "INTF_CFG" -component $cc
|
||||
set p [ipgui::get_guiparamspec -name "INTF_CFG" -component $cc]
|
||||
set_property -dict [list \
|
||||
"widget" "comboBox" \
|
||||
"display_name" "Interface Selection" \
|
||||
] $p
|
||||
|
||||
ipgui::add_param -name "RATE_10_100" -component $cc
|
||||
set p [ipgui::get_guiparamspec -name "RATE_10_100" -component $cc]
|
||||
set_property -dict [list \
|
||||
"widget" "comboBox" \
|
||||
"display_name" "Rate Selection" \
|
||||
] $p
|
||||
|
||||
adi_add_auto_fpga_spec_params
|
||||
ipx::create_xgui_files [ipx::current_core]
|
||||
ipx::save_core $cc
|
||||
@@ -0,0 +1,40 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "INTF_CFG" -parent ${Page_0} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "RATE_10_100" -parent ${Page_0} -widget comboBox
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.INTF_CFG { PARAM_VALUE.INTF_CFG } {
|
||||
# Procedure called to update INTF_CFG when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.INTF_CFG { PARAM_VALUE.INTF_CFG } {
|
||||
# Procedure called to validate INTF_CFG
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.RATE_10_100 { PARAM_VALUE.RATE_10_100 } {
|
||||
# Procedure called to update RATE_10_100 when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.RATE_10_100 { PARAM_VALUE.RATE_10_100 } {
|
||||
# Procedure called to validate RATE_10_100
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.INTF_CFG { MODELPARAM_VALUE.INTF_CFG PARAM_VALUE.INTF_CFG } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.INTF_CFG}] ${MODELPARAM_VALUE.INTF_CFG}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.RATE_10_100 { MODELPARAM_VALUE.RATE_10_100 PARAM_VALUE.RATE_10_100 } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.RATE_10_100}] ${MODELPARAM_VALUE.RATE_10_100}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user