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initial commit, add dds_par module

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josh
2024-01-15 09:36:08 +08:00
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adi_library/util_pack/tb/.gitignore
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run/
vcd/
adi_library/util_pack/tb/cpack_tb
Executable
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#!/bin/bash
SOURCE="cpack_tb.v"
SOURCE+=" ../util_cpack2/util_cpack2_impl.v"
SOURCE+=" ../util_pack_common/pack_ctrl.v"
SOURCE+=" ../util_pack_common/pack_interconnect.v"
SOURCE+=" ../util_pack_common/pack_network.v"
SOURCE+=" ../util_pack_common/pack_shell.v"
SOURCE+=" ../../common/ad_perfect_shuffle.v"
cd `dirname $0`
source ../../common/tb/run_tb.sh
adi_library/util_pack/tb/cpack_tb.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module cpack_tb;
parameter VCD_FILE = {`__FILE__,"cd"};
parameter NUM_OF_CHANNELS = 4;
parameter SAMPLES_PER_CHANNEL = 1;
parameter ENABLE_RANDOM = 0;
`define TIMEOUT 1500000
`include "tb_base.v"
localparam NUM_OF_PORTS = SAMPLES_PER_CHANNEL * NUM_OF_CHANNELS;
reg fifo_wr_en = 1'b1;
reg [NUM_OF_PORTS*8-1:0] fifo_wr_data = 'h00;
wire packed_fifo_wr_en;
wire [NUM_OF_PORTS*8-1:0] packed_fifo_wr_data;
reg [NUM_OF_PORTS*8-1:0] expected_packed_fifo_wr_data;
reg [NUM_OF_CHANNELS-1:0] enable = 'h1;
reg [NUM_OF_CHANNELS-1:0] next_enable = 'h1;
integer counter;
always @(*) begin
if (counter == 15) do_trigger_reset();
end
always @(posedge clk) begin
if (trigger_reset == 1'b1) begin
if (enable != {NUM_OF_CHANNELS{1'b1}}) begin
enable <= enable + 1'b1;
end else begin
if (failed == 1'b0)
$display("SUCCESS");
else
$display("FAILED");
$finish;
end
end
end
reg reset_data = 1'b0;
integer reset_counter = 'h00;
always @(posedge clk) begin
if (reset == 1'b1) begin
reset_data <= 1'b1;
reset_counter <= 'h00;
end else begin
reset_counter <= reset_counter + 1'b1;
if (reset_counter == 'h5) begin
reset_data <= 1'b0;
end
end
end
always @(posedge clk) begin
if (reset == 1'b1) begin
counter <= 'h00;
end else if (packed_fifo_wr_en == 1'b1) begin
counter <= counter + 1;
end
end
always @(posedge clk) begin
if (reset == 1'b0 && packed_fifo_wr_en == 1'b1 &&
expected_packed_fifo_wr_data !== packed_fifo_wr_data) begin
failed <= 1'b1;
$display("Failed for enable mask: %x. Expected data %x, got %x",
enable, expected_packed_fifo_wr_data, packed_fifo_wr_data);
end
end
integer i;
integer j;
integer h;
always @(posedge clk) begin
if (reset == 1'b1) begin
j = 0;
for (h = 0; h < SAMPLES_PER_CHANNEL; h = h + 1) begin
for (i = 0; i < NUM_OF_CHANNELS; i = i + 1) begin
if (enable[i] == 1'b1) begin
fifo_wr_data[(i*SAMPLES_PER_CHANNEL+h)*8+:8] <= j;
j = j + 1;
end else begin
fifo_wr_data[(i*SAMPLES_PER_CHANNEL+h)*8+:8] <= 'hxx;
end
end
end
end else if (fifo_wr_en == 1'b1) begin
for (h = 0; h < SAMPLES_PER_CHANNEL; h = h + 1) begin
for (i = 0; i < NUM_OF_CHANNELS; i = i + 1) begin
if (enable[i] == 1'b1) begin
fifo_wr_data[(i*SAMPLES_PER_CHANNEL+h)*8+:8] <= j;
j = j + 1;
end
end
end
end
end
always @(posedge clk) begin
if (reset == 1'b1) begin
for (i = 0; i < NUM_OF_PORTS; i = i + 1) begin
expected_packed_fifo_wr_data[i*8+:8] <= i;
end
end else if (packed_fifo_wr_en == 1'b1) begin
for (i = 0; i < NUM_OF_PORTS; i = i + 1) begin
expected_packed_fifo_wr_data[i*8+:8] <= expected_packed_fifo_wr_data[i*8+:8] + NUM_OF_PORTS;
end
end
end
always @(posedge clk) begin
if (reset_data == 1'b1) begin
fifo_wr_en <= 1'b0;
end else begin
fifo_wr_en <= ENABLE_RANDOM ? ($random & 1'b1) : ~fifo_wr_en;
end
end
util_cpack2_impl #(
.NUM_OF_CHANNELS(NUM_OF_CHANNELS),
.SAMPLES_PER_CHANNEL(SAMPLES_PER_CHANNEL),
.SAMPLE_DATA_WIDTH(8)
) i_cpack (
.clk(clk),
.reset(reset),
.enable(enable),
.fifo_wr_en({NUM_OF_CHANNELS{fifo_wr_en}}),
.fifo_wr_data(fifo_wr_data),
.packed_fifo_wr_en(packed_fifo_wr_en),
.packed_fifo_wr_data(packed_fifo_wr_data),
.packed_fifo_wr_overflow(1'b0));
endmodule
adi_library/util_pack/tb/tb_base.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
reg clk = 1'b1;
reg [3:0] reset_shift = 4'b1111;
reg trigger_reset = 1'b0;
wire reset;
reg failed = 1'b0;
initial
begin
if (VCD_FILE != "") begin
$dumpfile (VCD_FILE);
$dumpvars;
end
end
always @(*) #10 clk <= ~clk;
always @(posedge clk) begin
if (trigger_reset == 1'b1) begin
reset_shift <= 4'b1111;
end else begin
reset_shift <= {reset_shift[2:0],1'b0};
end
end
assign reset = reset_shift[3];
task do_trigger_reset;
begin
@(posedge clk) trigger_reset <= 1'b1;
@(posedge clk) trigger_reset <= 1'b0;
end
endtask
adi_library/util_pack/tb/underflow_tb
Executable
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#!/bin/bash
SOURCE="underflow_tb.v"
SOURCE+=" ../util_upack2/util_upack2_impl.v"
SOURCE+=" ../util_pack_common/pack_ctrl.v"
SOURCE+=" ../util_pack_common/pack_interconnect.v"
SOURCE+=" ../util_pack_common/pack_network.v"
SOURCE+=" ../util_pack_common/pack_shell.v"
SOURCE+=" ../../common/ad_perfect_shuffle.v"
cd `dirname $0`
source ../../common/tb/run_tb.sh
adi_library/util_pack/tb/underflow_tb.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module underflow_tb;
parameter VCD_FILE = {`__FILE__,"cd"};
parameter NUM_OF_CHANNELS = 8;
parameter SAMPLES_PER_CHANNEL = 4;
`include "tb_base.v"
initial
begin
#1500000
if (failed == 1'b0)
$display("SUCCESS");
else
$display("FAILED");
$finish;
end
localparam NUM_OF_PORTS = SAMPLES_PER_CHANNEL * NUM_OF_CHANNELS;
reg fifo_rd_en = 1'b1;
wire [NUM_OF_PORTS*8-1:0] fifo_rd_data;
wire fifo_rd_valid;
wire fifo_rd_underflow;
reg s_axis_valid = 1'b1;
wire s_axis_ready;
reg [NUM_OF_PORTS*8-1:0] s_axis_data = {NUM_OF_PORTS*8{1'b1}};
reg [NUM_OF_CHANNELS-1:0] enable = {NUM_OF_CHANNELS{1'b1}};
integer counter = 0;
always @(posedge clk) begin
if (fifo_rd_underflow == 1'b1 && fifo_rd_data != 'h00) begin
failed <= 1'b1;
end
if (fifo_rd_valid == 1'b1 && fifo_rd_data != {NUM_OF_PORTS*8{1'b1}}) begin
failed <= 1'b1;
end
end
always @(posedge clk) begin
if (reset == 1'b1) begin
counter <= 0;
s_axis_valid <= 1'b1;
end else begin
if (s_axis_valid == 1'b0) begin
if (counter == 8) begin
s_axis_valid <= 1'b1;
end
counter <= counter + 1;
end else if (s_axis_ready == 1'b1) begin
s_axis_valid <= 1'b0;
counter <= 0;
end
end
end
always @(posedge clk) begin
fifo_rd_en <= $random & 1;
end
util_upack2_impl #(
.NUM_OF_CHANNELS(NUM_OF_CHANNELS),
.SAMPLES_PER_CHANNEL(SAMPLES_PER_CHANNEL),
.SAMPLE_DATA_WIDTH(8)
) i_unpack (
.clk(clk),
.reset(reset),
.enable(enable),
.fifo_rd_en({NUM_OF_CHANNELS{fifo_rd_en}}),
.fifo_rd_data(fifo_rd_data),
.fifo_rd_valid(fifo_rd_valid),
.fifo_rd_underflow(fifo_rd_underflow),
.s_axis_valid(s_axis_valid),
.s_axis_ready(s_axis_ready),
.s_axis_data(s_axis_data));
endmodule
adi_library/util_pack/tb/upack_tb
Executable
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#!/bin/bash
SOURCE="upack_tb.v"
SOURCE+=" ../util_upack2/util_upack2_impl.v"
SOURCE+=" ../util_pack_common/pack_ctrl.v"
SOURCE+=" ../util_pack_common/pack_interconnect.v"
SOURCE+=" ../util_pack_common/pack_network.v"
SOURCE+=" ../util_pack_common/pack_shell.v"
SOURCE+=" ../../common/ad_perfect_shuffle.v"
cd `dirname $0`
source ../../common/tb/run_tb.sh
adi_library/util_pack/tb/upack_tb.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module upack_tb;
parameter VCD_FILE = {`__FILE__,"cd"};
parameter NUM_OF_CHANNELS = 8;
parameter SAMPLES_PER_CHANNEL = 1;
parameter ENABLE_RANDOM = 0;
`define TIMEOUT 1500000
`include "tb_base.v"
localparam NUM_OF_PORTS = SAMPLES_PER_CHANNEL * NUM_OF_CHANNELS;
reg fifo_rd_en = 1'b1;
wire [NUM_OF_PORTS*8-1:0] fifo_rd_data;
reg [NUM_OF_PORTS*8-1:0] expected_fifo_rd_data = 'h00;
wire fifo_rd_valid;
reg s_axis_valid = 1'b1;
wire s_axis_ready;
reg [NUM_OF_PORTS*8-1:0] s_axis_data = 'h00;
reg [NUM_OF_CHANNELS-1:0] enable = 'h1;
reg [NUM_OF_CHANNELS-1:0] next_enable = 'h1;
integer counter;
always @(*) begin
if (counter == 15) do_trigger_reset();
end
always @(posedge clk) begin
if (trigger_reset == 1'b1) begin
if (enable != {NUM_OF_CHANNELS{1'b1}}) begin
enable <= enable + 1'b1;
end else begin
if (failed == 1'b0)
$display("SUCCESS");
else
$display("FAILED");
$finish;
end
end
end
always @(posedge clk) begin
if (reset == 1'b1) begin
counter <= 'h00;
end else if (s_axis_ready == 1'b1 && s_axis_valid == 1'b1) begin
counter <= counter + 1;
end
end
integer i;
always @(posedge clk) begin
for (i = 0; i < NUM_OF_PORTS; i = i + 1) begin
if (reset == 1'b0 && fifo_rd_valid == 1'b1 && enable[i/SAMPLES_PER_CHANNEL] == 1'b1 &&
fifo_rd_data[i*8+:8] !== expected_fifo_rd_data[i*8+:8]) begin
failed <= 1'b1;
$display("Failed for enable mask: %x. Expected data %x, got %x",
enable, expected_fifo_rd_data, fifo_rd_data);
i = NUM_OF_PORTS;
end
end
end
integer j;
integer h;
always @(posedge clk) begin
if (reset == 1'b1) begin
j = 0;
for (h = 0; h < SAMPLES_PER_CHANNEL; h = h + 1) begin
for (i = 0; i < NUM_OF_CHANNELS; i = i + 1) begin
if (enable[i] == 1'b1) begin
expected_fifo_rd_data[(i*SAMPLES_PER_CHANNEL+h)*8+:8] <= j;
j = j + 1;
end else begin
expected_fifo_rd_data[(i*SAMPLES_PER_CHANNEL+h)*8+:8] <= 'hxx;
end
end
end
end else if (fifo_rd_valid == 1'b1) begin
for (h = 0; h < SAMPLES_PER_CHANNEL; h = h + 1) begin
for (i = 0; i < NUM_OF_CHANNELS; i = i + 1) begin
if (enable[i] == 1'b1) begin
expected_fifo_rd_data[(i*SAMPLES_PER_CHANNEL+h)*8+:8] <= j;
j = j + 1;
end
end
end
end
end
always @(posedge clk) begin
if (reset == 1'b1) begin
for (i = 0; i < NUM_OF_PORTS; i = i + 1) begin
s_axis_data[i*8+:8] <= i;
end
end else if (s_axis_ready == 1'b1 && s_axis_valid == 1'b1) begin
for (i = 0; i < NUM_OF_PORTS; i = i + 1) begin
s_axis_data[i*8+:8] <= s_axis_data[i*8+:8] + NUM_OF_PORTS;
end
end
end
always @(posedge clk) begin
fifo_rd_en <= ENABLE_RANDOM ? ($random & 1) : 1'b1;
if (s_axis_valid == 1'b0 || s_axis_ready == 1'b1) begin
s_axis_valid <= ENABLE_RANDOM ? ($random % 20) : 1'b1;
end
end
util_upack2_impl #(
.NUM_OF_CHANNELS(NUM_OF_CHANNELS),
.SAMPLES_PER_CHANNEL(SAMPLES_PER_CHANNEL),
.SAMPLE_DATA_WIDTH(8)
) i_unpack (
.clk(clk),
.reset(reset),
.enable(enable),
.fifo_rd_en({NUM_OF_CHANNELS{fifo_rd_en}}),
.fifo_rd_data(fifo_rd_data),
.fifo_rd_valid(fifo_rd_valid),
.s_axis_valid(s_axis_valid),
.s_axis_ready(s_axis_ready),
.s_axis_data(s_axis_valid ? s_axis_data : {NUM_OF_PORTS{8'hx}}));
endmodule
adi_library/util_pack/util_cpack2/Makefile
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####################################################################################
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := util_cpack2
GENERIC_DEPS += ../../common/ad_perfect_shuffle.v
GENERIC_DEPS += ../util_pack_common/pack_ctrl.v
GENERIC_DEPS += ../util_pack_common/pack_interconnect.v
GENERIC_DEPS += ../util_pack_common/pack_network.v
GENERIC_DEPS += ../util_pack_common/pack_shell.v
GENERIC_DEPS += util_cpack2_impl.v
XILINX_DEPS += util_cpack2.v
XILINX_DEPS += util_cpack2_ip.tcl
XILINX_DEPS += ../../interfaces/fifo_wr.xml
XILINX_DEPS += ../../interfaces/fifo_wr_rtl.xml
INTEL_DEPS += util_cpack2_hw.tcl
include ../../scripts/library.mk
adi_library/util_pack/util_cpack2/component.xml
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adi_library/util_pack/util_cpack2/util_cpack2.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module util_cpack2 #(
parameter NUM_OF_CHANNELS = 4,
parameter SAMPLES_PER_CHANNEL = 1,
parameter SAMPLE_DATA_WIDTH = 16
) (
input clk,
input reset,
input enable_0,
input enable_1,
input enable_2,
input enable_3,
input enable_4,
input enable_5,
input enable_6,
input enable_7,
input enable_8,
input enable_9,
input enable_10,
input enable_11,
input enable_12,
input enable_13,
input enable_14,
input enable_15,
input enable_16,
input enable_17,
input enable_18,
input enable_19,
input enable_20,
input enable_21,
input enable_22,
input enable_23,
input enable_24,
input enable_25,
input enable_26,
input enable_27,
input enable_28,
input enable_29,
input enable_30,
input enable_31,
input enable_32,
input enable_33,
input enable_34,
input enable_35,
input enable_36,
input enable_37,
input enable_38,
input enable_39,
input enable_40,
input enable_41,
input enable_42,
input enable_43,
input enable_44,
input enable_45,
input enable_46,
input enable_47,
input enable_48,
input enable_49,
input enable_50,
input enable_51,
input enable_52,
input enable_53,
input enable_54,
input enable_55,
input enable_56,
input enable_57,
input enable_58,
input enable_59,
input enable_60,
input enable_61,
input enable_62,
input enable_63,
input fifo_wr_en,
output fifo_wr_overflow,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_0,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_1,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_2,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_3,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_4,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_5,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_6,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_7,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_8,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_9,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_10,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_11,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_12,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_13,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_14,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_15,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_16,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_17,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_18,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_19,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_20,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_21,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_22,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_23,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_24,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_25,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_26,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_27,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_28,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_29,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_30,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_31,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_32,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_33,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_34,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_35,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_36,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_37,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_38,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_39,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_40,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_41,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_42,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_43,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_44,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_45,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_46,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_47,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_48,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_49,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_50,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_51,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_52,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_53,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_54,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_55,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_56,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_57,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_58,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_59,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_60,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_61,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_62,
input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_63,
output packed_fifo_wr_en,
input packed_fifo_wr_overflow,
output packed_fifo_wr_sync,
output [2**$clog2(NUM_OF_CHANNELS)*SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] packed_fifo_wr_data
);
localparam CHANNEL_DATA_WIDTH = SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL;
/*
* Round up to the next power of two and zero out the additional channels
* internally.
*/
localparam REAL_NUM_OF_CHANNELS = NUM_OF_CHANNELS > 32 ? 64 :
NUM_OF_CHANNELS > 16 ? 32 :
NUM_OF_CHANNELS > 8 ? 16 :
NUM_OF_CHANNELS > 4 ? 8 :
NUM_OF_CHANNELS > 2 ? 4 :
NUM_OF_CHANNELS > 1 ? 2 : 1;
/* FIXME: Find out how to do this in the IP-XACT */
wire [REAL_NUM_OF_CHANNELS-1:0] enable;
wire [63:0] enable_s;
wire [CHANNEL_DATA_WIDTH*REAL_NUM_OF_CHANNELS-1:0] fifo_wr_data;
wire [CHANNEL_DATA_WIDTH*64-1:0] fifo_wr_data_s;
assign enable_s = {
enable_63,enable_62,enable_61,enable_60,enable_59,enable_58,enable_57,enable_56,
enable_55,enable_54,enable_53,enable_52,enable_51,enable_50,enable_49,enable_48,
enable_47,enable_46,enable_45,enable_44,enable_43,enable_42,enable_41,enable_40,
enable_39,enable_38,enable_37,enable_36,enable_35,enable_34,enable_33,enable_32,
enable_31,enable_30,enable_29,enable_28,enable_27,enable_26,enable_25,enable_24,
enable_23,enable_22,enable_21,enable_20,enable_19,enable_18,enable_17,enable_16,
enable_15,enable_14,enable_13,enable_12,enable_11,enable_10,enable_9,enable_8,
enable_7,enable_6,enable_5,enable_4,enable_3,enable_2,enable_1,enable_0
};
assign enable = enable_s[REAL_NUM_OF_CHANNELS-1:0];
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*0+:CHANNEL_DATA_WIDTH] = fifo_wr_data_0;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*1+:CHANNEL_DATA_WIDTH] = fifo_wr_data_1;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*2+:CHANNEL_DATA_WIDTH] = fifo_wr_data_2;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*3+:CHANNEL_DATA_WIDTH] = fifo_wr_data_3;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*4+:CHANNEL_DATA_WIDTH] = fifo_wr_data_4;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*5+:CHANNEL_DATA_WIDTH] = fifo_wr_data_5;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*6+:CHANNEL_DATA_WIDTH] = fifo_wr_data_6;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*7+:CHANNEL_DATA_WIDTH] = fifo_wr_data_7;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*8+:CHANNEL_DATA_WIDTH] = fifo_wr_data_8;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*9+:CHANNEL_DATA_WIDTH] = fifo_wr_data_9;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*10+:CHANNEL_DATA_WIDTH] = fifo_wr_data_10;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*11+:CHANNEL_DATA_WIDTH] = fifo_wr_data_11;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*12+:CHANNEL_DATA_WIDTH] = fifo_wr_data_12;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*13+:CHANNEL_DATA_WIDTH] = fifo_wr_data_13;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*14+:CHANNEL_DATA_WIDTH] = fifo_wr_data_14;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*15+:CHANNEL_DATA_WIDTH] = fifo_wr_data_15;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*16+:CHANNEL_DATA_WIDTH] = fifo_wr_data_16;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*17+:CHANNEL_DATA_WIDTH] = fifo_wr_data_17;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*18+:CHANNEL_DATA_WIDTH] = fifo_wr_data_18;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*19+:CHANNEL_DATA_WIDTH] = fifo_wr_data_19;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*20+:CHANNEL_DATA_WIDTH] = fifo_wr_data_20;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*21+:CHANNEL_DATA_WIDTH] = fifo_wr_data_21;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*22+:CHANNEL_DATA_WIDTH] = fifo_wr_data_22;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*23+:CHANNEL_DATA_WIDTH] = fifo_wr_data_23;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*24+:CHANNEL_DATA_WIDTH] = fifo_wr_data_24;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*25+:CHANNEL_DATA_WIDTH] = fifo_wr_data_25;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*26+:CHANNEL_DATA_WIDTH] = fifo_wr_data_26;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*27+:CHANNEL_DATA_WIDTH] = fifo_wr_data_27;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*28+:CHANNEL_DATA_WIDTH] = fifo_wr_data_28;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*29+:CHANNEL_DATA_WIDTH] = fifo_wr_data_29;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*30+:CHANNEL_DATA_WIDTH] = fifo_wr_data_30;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*31+:CHANNEL_DATA_WIDTH] = fifo_wr_data_31;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*32+:CHANNEL_DATA_WIDTH] = fifo_wr_data_32;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*33+:CHANNEL_DATA_WIDTH] = fifo_wr_data_33;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*34+:CHANNEL_DATA_WIDTH] = fifo_wr_data_34;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*35+:CHANNEL_DATA_WIDTH] = fifo_wr_data_35;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*36+:CHANNEL_DATA_WIDTH] = fifo_wr_data_36;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*37+:CHANNEL_DATA_WIDTH] = fifo_wr_data_37;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*38+:CHANNEL_DATA_WIDTH] = fifo_wr_data_38;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*39+:CHANNEL_DATA_WIDTH] = fifo_wr_data_39;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*40+:CHANNEL_DATA_WIDTH] = fifo_wr_data_40;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*41+:CHANNEL_DATA_WIDTH] = fifo_wr_data_41;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*42+:CHANNEL_DATA_WIDTH] = fifo_wr_data_42;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*43+:CHANNEL_DATA_WIDTH] = fifo_wr_data_43;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*44+:CHANNEL_DATA_WIDTH] = fifo_wr_data_44;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*45+:CHANNEL_DATA_WIDTH] = fifo_wr_data_45;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*46+:CHANNEL_DATA_WIDTH] = fifo_wr_data_46;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*47+:CHANNEL_DATA_WIDTH] = fifo_wr_data_47;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*48+:CHANNEL_DATA_WIDTH] = fifo_wr_data_48;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*49+:CHANNEL_DATA_WIDTH] = fifo_wr_data_49;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*50+:CHANNEL_DATA_WIDTH] = fifo_wr_data_50;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*51+:CHANNEL_DATA_WIDTH] = fifo_wr_data_51;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*52+:CHANNEL_DATA_WIDTH] = fifo_wr_data_52;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*53+:CHANNEL_DATA_WIDTH] = fifo_wr_data_53;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*54+:CHANNEL_DATA_WIDTH] = fifo_wr_data_54;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*55+:CHANNEL_DATA_WIDTH] = fifo_wr_data_55;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*56+:CHANNEL_DATA_WIDTH] = fifo_wr_data_56;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*57+:CHANNEL_DATA_WIDTH] = fifo_wr_data_57;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*58+:CHANNEL_DATA_WIDTH] = fifo_wr_data_58;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*59+:CHANNEL_DATA_WIDTH] = fifo_wr_data_59;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*60+:CHANNEL_DATA_WIDTH] = fifo_wr_data_60;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*61+:CHANNEL_DATA_WIDTH] = fifo_wr_data_61;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*62+:CHANNEL_DATA_WIDTH] = fifo_wr_data_62;
assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*63+:CHANNEL_DATA_WIDTH] = fifo_wr_data_63;
assign fifo_wr_data = fifo_wr_data_s[0+:REAL_NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH];
util_cpack2_impl #(
.NUM_OF_CHANNELS (REAL_NUM_OF_CHANNELS),
.SAMPLE_DATA_WIDTH (SAMPLE_DATA_WIDTH),
.SAMPLES_PER_CHANNEL (SAMPLES_PER_CHANNEL)
) i_cpack (
.clk (clk),
.reset (reset),
.enable (enable),
.fifo_wr_en ({REAL_NUM_OF_CHANNELS{fifo_wr_en}}),
.fifo_wr_overflow (fifo_wr_overflow),
.fifo_wr_data (fifo_wr_data),
.packed_fifo_wr_en (packed_fifo_wr_en),
.packed_fifo_wr_overflow (packed_fifo_wr_overflow),
.packed_fifo_wr_data (packed_fifo_wr_data),
.packed_fifo_wr_sync (packed_fifo_wr_sync));
endmodule
adi_library/util_pack/util_cpack2/util_cpack2.xpr
+441
View File
@@ -0,0 +1,441 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
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<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
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<Option Name="IPCachePermission" Val="read"/>
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</Simulators>
<Runs Version="1" Minor="21">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
</Runs>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="1"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
<MsgAttr Name="StringsToMatch" Val="features"/>
<MsgAttr Name="StringsToMatch" Val="should"/>
<MsgAttr Name="StringsToMatch" Val="NOT"/>
<MsgAttr Name="StringsToMatch" Val="be"/>
<MsgAttr Name="StringsToMatch" Val="used"/>
<MsgAttr Name="StringsToMatch" Val="in"/>
<MsgAttr Name="StringsToMatch" Val="production"/>
<MsgAttr Name="StringsToMatch" Val="systems."/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="10"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="Place 30-73"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
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<MsgAttr Name="Note" Val=""/>
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<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val=""/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="12"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="BD 41-1343"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
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<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="2"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="BD 41-1306"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="3"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="ERROR"/>
<MsgAttr Name="Id" Val="BD 41-1276"/>
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="4"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="5"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
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<MsgAttr Name="RuleId" Val="6"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="7"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="Synth 8-3331"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="8"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="Synth 8-2490"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="9"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<Board/>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">
<Gadgets>
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
</Gadget>
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
</Gadget>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
</Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
</Project>
adi_library/util_pack/util_cpack2/util_cpack2_hw.tcl
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###############################################################################
## Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
package require qsys 14.0
source ../../../scripts/adi_env.tcl
source ../../scripts/adi_ip_intel.tcl
ad_ip_create util_cpack2 {Channel Pack Utility v2} util_cpack_elab
ad_ip_files util_cpack2_impl [list \
$ad_hdl_dir/library/common/ad_perfect_shuffle.v \
../util_pack_common/pack_ctrl.v \
../util_pack_common/pack_interconnect.v \
../util_pack_common/pack_network.v \
../util_pack_common/pack_shell.v \
util_cpack2_impl.v ]
# parameters
ad_ip_parameter NUM_OF_CHANNELS INTEGER 4 true [list \
DISPLAY_NAME "Number of Channels" \
ALLOWED_RANGES {2, 4, 8, 16}
]
ad_ip_parameter SAMPLES_PER_CHANNEL INTEGER 1 true [list \
DISPLAY_NAME "Samples per Channel"
]
ad_ip_parameter SAMPLE_DATA_WIDTH INTEGER 16 true [list \
DISPLAY_NAME "Sample Data Width"
]
# defaults
proc util_cpack_elab {} {
set num_channels [get_parameter_value NUM_OF_CHANNELS]
set samples_per_channel [get_parameter_value SAMPLES_PER_CHANNEL]
set sample_data_width [get_parameter_value SAMPLE_DATA_WIDTH]
set channel_data_width [expr $sample_data_width * $samples_per_channel]
set total_data_width [expr $num_channels * $channel_data_width]
add_interface clk clock end
add_interface_port clk clk clk Input 1
add_interface reset reset end
add_interface_port reset reset reset Input 1
set_interface_property reset associatedClock clk
ad_interface signal packed_fifo_wr_en output 1 valid
ad_interface signal packed_fifo_wr_sync output 1 sync
ad_interface signal packed_fifo_wr_data output $total_data_width data
ad_interface signal packed_fifo_wr_overflow input 1 ovf
ad_interface signal fifo_wr_overflow output 1 ovf
for {set n 0} {$n < $num_channels} {incr n} {
add_interface adc_ch_$n conduit end
add_interface_port adc_ch_$n enable_$n enable Input 1
set_port_property enable_$n fragment_list [format "enable(%d:%d)" $n $n]
add_interface_port adc_ch_$n fifo_wr_en_$n valid Input 1
set_port_property fifo_wr_en_$n fragment_list [format "fifo_wr_en(%d)" $n]
add_interface_port adc_ch_$n fifo_wr_data_$n data Input $channel_data_width
set_port_property fifo_wr_data_$n fragment_list [format "fifo_wr_data(%d:%d)" \
[expr ($n+1) * $channel_data_width - 1] [expr $n * $channel_data_width]]
set_interface_property adc_ch_$n associatedClock clk
set_interface_property adc_ch_$n associatedReset ""
}
}
adi_library/util_pack/util_cpack2/util_cpack2_impl.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module util_cpack2_impl #(
parameter NUM_OF_CHANNELS = 4,
parameter SAMPLES_PER_CHANNEL = 1,
parameter SAMPLE_DATA_WIDTH = 16
) (
input clk,
input reset,
input [NUM_OF_CHANNELS-1:0] enable,
input [NUM_OF_CHANNELS-1:0] fifo_wr_en,
output fifo_wr_overflow,
input [NUM_OF_CHANNELS*SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data,
output reg packed_fifo_wr_en = 1'b0,
input packed_fifo_wr_overflow,
output reg packed_fifo_wr_sync = 1'b1,
output reg [NUM_OF_CHANNELS*SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] packed_fifo_wr_data = 'h00
);
localparam TOTAL_DATA_WIDTH = SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL * NUM_OF_CHANNELS;
// Control signals from the pack shell.
wire reset_data;
wire ready;
// Interleaved version of `fifo_wr_data`.
wire [TOTAL_DATA_WIDTH-1:0] interleaved_data;
// Output data and corresponding control signal from the routing network.
wire [TOTAL_DATA_WIDTH-1:0] out_data;
wire out_sync;
wire [NUM_OF_CHANNELS*SAMPLES_PER_CHANNEL-1:0] out_valid;
/*
* Only the first signal of fifo_rd_en is used. All others are ignored. The
* only reason why fifo_rd_en has multiple entries is to keep the interface
* somewhat backwards compatible to the previous upack.
*/
wire data_wr_en = fifo_wr_en[0];
/*
* The cpack core itself has no backpressure. Overflows can only happen
* downstream.
*/
assign fifo_wr_overflow = packed_fifo_wr_overflow;
/*
* Data at the input of the routing network should be interleaved. The cpack
* core is supposed to accept deinterleaved data. This just rearrange the bits
* in the data vector and does not consume any FPGA resources.
*/
ad_perfect_shuffle #(
.NUM_GROUPS (NUM_OF_CHANNELS),
.WORDS_PER_GROUP (SAMPLES_PER_CHANNEL),
.WORD_WIDTH (SAMPLE_DATA_WIDTH)
) i_interleave (
.data_in (fifo_wr_data),
.data_out (interleaved_data));
pack_shell #(
.NUM_OF_CHANNELS (NUM_OF_CHANNELS),
.SAMPLES_PER_CHANNEL (SAMPLES_PER_CHANNEL),
.SAMPLE_DATA_WIDTH (SAMPLE_DATA_WIDTH),
.PACK (1)
) i_pack_shell (
.clk (clk),
.reset (reset),
.reset_data (reset_data),
.enable (enable),
.ce (data_wr_en),
.ready (ready),
.in_data (interleaved_data),
.out_data (out_data),
.out_sync (out_sync),
.out_valid (out_valid));
always @(posedge clk) begin
if (reset_data == 1'b1) begin
packed_fifo_wr_en <= 1'b0;
packed_fifo_wr_sync <= 1'b0;
end else if (ready == 1'b1 && data_wr_en == 1'b1) begin
packed_fifo_wr_en <= 1'b1;
packed_fifo_wr_sync <= out_sync;
end else begin
packed_fifo_wr_en <= 1'b0;
packed_fifo_wr_sync <= 1'b0;
end
end
always @(posedge clk) begin: gen_packed_fifo_wr_data
integer i;
if (data_wr_en == 1'b1) begin
for (i = 0; i < NUM_OF_CHANNELS * SAMPLES_PER_CHANNEL; i = i + 1) begin
if (out_valid[i] == 1'b1) begin
packed_fifo_wr_data[i*SAMPLE_DATA_WIDTH+:SAMPLE_DATA_WIDTH] <= out_data[i*SAMPLE_DATA_WIDTH+:SAMPLE_DATA_WIDTH];
end
end
end
end
endmodule
adi_library/util_pack/util_cpack2/util_cpack2_ip.tcl
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###############################################################################
## Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
source ../../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
adi_ip_create util_cpack2
adi_ip_files util_cpack2 [list \
"../../common/ad_perfect_shuffle.v" \
"../util_pack_common/pack_ctrl.v" \
"../util_pack_common/pack_interconnect.v" \
"../util_pack_common/pack_network.v" \
"../util_pack_common/pack_shell.v" \
"util_cpack2_impl.v" \
"util_cpack2.v" ]
adi_ip_properties_lite util_cpack2
adi_add_bus "packed_fifo_wr" "master" \
"analog.com:interface:fifo_wr_rtl:1.0" \
"analog.com:interface:fifo_wr:1.0" \
{ \
{"packed_fifo_wr_en" "EN"} \
{"packed_fifo_wr_data" "DATA"} \
{"packed_fifo_wr_overflow" "OVERFLOW"} \
{"packed_fifo_wr_sync" "SYNC"} \
}
adi_add_bus_clock "clk" "packed_fifo_wr" "reset"
set cc [ipx::current_core]
for {set i 1} {$i < 64} {incr i} {
set_property enablement_dependency "spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > $i" \
[ipx::get_ports *_$i -of_objects $cc]
}
foreach {k v} { \
"NUM_OF_CHANNELS" "Number of Channels" \
"SAMPLES_PER_CHANNEL" "Samples per Channel" \
"SAMPLE_DATA_WIDTH" "Sample Width" \
} { \
set p [ipgui::get_guiparamspec -name $k -component $cc]
# ipgui::move_param -component $cc -order $i $p -parent $
set_property -dict [list \
DISPLAY_NAME $v \
] $p
incr i
}
ipx::save_core [ipx::current_core]
adi_library/util_pack/util_cpack2/xgui/util_cpack2_v1_0.tcl
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# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
ipgui::add_param $IPINST -name "NUM_OF_CHANNELS" -parent ${Page_0}
ipgui::add_param $IPINST -name "SAMPLES_PER_CHANNEL" -parent ${Page_0}
ipgui::add_param $IPINST -name "SAMPLE_DATA_WIDTH" -parent ${Page_0}
}
proc update_PARAM_VALUE.NUM_OF_CHANNELS { PARAM_VALUE.NUM_OF_CHANNELS } {
# Procedure called to update NUM_OF_CHANNELS when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.NUM_OF_CHANNELS { PARAM_VALUE.NUM_OF_CHANNELS } {
# Procedure called to validate NUM_OF_CHANNELS
return true
}
proc update_PARAM_VALUE.SAMPLES_PER_CHANNEL { PARAM_VALUE.SAMPLES_PER_CHANNEL } {
# Procedure called to update SAMPLES_PER_CHANNEL when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.SAMPLES_PER_CHANNEL { PARAM_VALUE.SAMPLES_PER_CHANNEL } {
# Procedure called to validate SAMPLES_PER_CHANNEL
return true
}
proc update_PARAM_VALUE.SAMPLE_DATA_WIDTH { PARAM_VALUE.SAMPLE_DATA_WIDTH } {
# Procedure called to update SAMPLE_DATA_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.SAMPLE_DATA_WIDTH { PARAM_VALUE.SAMPLE_DATA_WIDTH } {
# Procedure called to validate SAMPLE_DATA_WIDTH
return true
}
proc update_MODELPARAM_VALUE.NUM_OF_CHANNELS { MODELPARAM_VALUE.NUM_OF_CHANNELS PARAM_VALUE.NUM_OF_CHANNELS } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.NUM_OF_CHANNELS}] ${MODELPARAM_VALUE.NUM_OF_CHANNELS}
}
proc update_MODELPARAM_VALUE.SAMPLES_PER_CHANNEL { MODELPARAM_VALUE.SAMPLES_PER_CHANNEL PARAM_VALUE.SAMPLES_PER_CHANNEL } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.SAMPLES_PER_CHANNEL}] ${MODELPARAM_VALUE.SAMPLES_PER_CHANNEL}
}
proc update_MODELPARAM_VALUE.SAMPLE_DATA_WIDTH { MODELPARAM_VALUE.SAMPLE_DATA_WIDTH PARAM_VALUE.SAMPLE_DATA_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.SAMPLE_DATA_WIDTH}] ${MODELPARAM_VALUE.SAMPLE_DATA_WIDTH}
}
adi_library/util_pack/util_pack_common/pack_ctrl.v
+113
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module pack_ctrl #(
parameter PORT_ADDRESS_WIDTH = 2,
parameter MUX_ORDER = 1,
parameter MIN_STAGE = 0,
parameter NUM_STAGES = 2,
parameter PACK = 0
) (
input [PORT_ADDRESS_WIDTH-1:0] rotate,
input [2**PORT_ADDRESS_WIDTH*PORT_ADDRESS_WIDTH-1:0] prefix_count,
output [2**PORT_ADDRESS_WIDTH*MUX_ORDER*NUM_STAGES-1:0] ctrl
);
/*
* This module computes the control bits that are used to configure the MUXes
* in the pack interconect network. The controls are configured according to
* the specified global rotation and the prefix count of each of the outputs.
*/
localparam NUM_OF_PORTS = 2**PORT_ADDRESS_WIDTH;
wire [NUM_OF_PORTS*MUX_ORDER*NUM_STAGES-1:0] ctrl1;
reg [NUM_OF_PORTS*MUX_ORDER*NUM_STAGES-1:0] ctrl2;
generate
genvar i, j, k;
integer n;
localparam z = 2**MUX_ORDER;
// This part is magic
for (i = 0; i < NUM_STAGES; i = i + 1) begin: ctrl_gen_outer
localparam k0 = 2**(PORT_ADDRESS_WIDTH - MUX_ORDER*(i+1)-MIN_STAGE);
localparam k1 = 2**(MUX_ORDER*(1+i)+MIN_STAGE);
for (j = 0; j < NUM_OF_PORTS; j = j + 1) begin: ctrl_gen_inner
// Offset in the ctrl signal
localparam s = (i*NUM_OF_PORTS+j)*MUX_ORDER;
localparam m = (j % k1) * k0;
localparam n = j / k1;
if (MUX_ORDER == 1 && j % 2 == 0) begin
// This is an optimization that only works for 2:1 MUXes
assign ctrl1[s] = ~ctrl1[s+1];
end else begin
assign ctrl1[s+:MUX_ORDER] = (j - (prefix_count[m*PORT_ADDRESS_WIDTH+:PORT_ADDRESS_WIDTH] + n - rotate) / k0) % z;
end
end
end
if (PACK == 0 || MUX_ORDER == 1) begin
// For 2:1 MUXes pack and unpack control is the same
assign ctrl = ctrl1;
end else begin
/*
* Transform demux control into mux control. The implementation here uses a
* priority encoder.
*/
for (i = 0; i < NUM_STAGES*NUM_OF_PORTS; i = i + z) begin: demux_gen_outer
localparam base = i*MUX_ORDER;
for (k = 0; k < z; k = k + 1) begin: demux_gen_inner
always @(ctrl1) begin
ctrl2[base+k*MUX_ORDER+:MUX_ORDER] <= {MUX_ORDER{1'b1}};
for (n = 0; n < z; n = n + 1) begin
if (ctrl1[base+n*MUX_ORDER+:MUX_ORDER] == k) begin
ctrl2[base+k*MUX_ORDER+:MUX_ORDER] <= n[MUX_ORDER-1:0];
end
end
end
end
end
assign ctrl = ctrl2;
end
endgenerate
endmodule
adi_library/util_pack/util_pack_common/pack_interconnect.v
+130
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module pack_interconnect #(
parameter PORT_DATA_WIDTH = 16,
parameter PORT_ADDRESS_WIDTH = 3,
parameter MUX_ORDER = 2,
parameter NUM_STAGES = 2,
parameter PACK = 0 // 0 = Unpack, 1 = Pack
) (
input [2**PORT_ADDRESS_WIDTH*MUX_ORDER*NUM_STAGES-1:0] ctrl,
input [PORT_DATA_WIDTH * 2**PORT_ADDRESS_WIDTH-1:0] data_in,
output [PORT_DATA_WIDTH * 2**PORT_ADDRESS_WIDTH-1:0] data_out
);
/*
* This module implements the interconnect for pack or unpack core.
* The interconnect is made up of NUM_STAGES stages. Each stage is made up of
* multiple MUXs (one for each port) and a perfect shuffle.
*
* The number of inputs per MUX is 2**MUX_ORDER.
* The number of ports is 2**PORT_ADDRESS_WIDTH.
*/
localparam NUM_PORTS = 2**PORT_ADDRESS_WIDTH;
localparam TOTAL_DATA_WIDTH = PORT_DATA_WIDTH * NUM_PORTS;
wire [TOTAL_DATA_WIDTH-1:0] interconnect[0:NUM_STAGES];
assign interconnect[0] = data_in;
assign data_out = interconnect[NUM_STAGES];
generate
genvar i, j;
localparam z = 2**MUX_ORDER;
localparam w = PORT_DATA_WIDTH;
localparam NUM_SWITCHES = NUM_PORTS / z;
// Do perfect shuffle, either in forward or reverse direction
for (i = 0; i < NUM_STAGES; i = i + 1) begin: gen_stages
// Pack network are in the opposite direction
localparam ctrl_stage = PACK ? NUM_STAGES - i - 1 : i;
wire [TOTAL_DATA_WIDTH-1:0] shuffle_in;
wire [TOTAL_DATA_WIDTH-1:0] shuffle_out;
wire [TOTAL_DATA_WIDTH-1:0] mux_in;
wire [TOTAL_DATA_WIDTH-1:0] mux_out;
// Unpack uses forward shuffle and pack a reverse shuffle
ad_perfect_shuffle #(
.NUM_GROUPS (PACK ? NUM_SWITCHES : z),
.WORDS_PER_GROUP (PACK ? z : NUM_SWITCHES),
.WORD_WIDTH (w)
) i_shuffle (
.data_in (shuffle_in),
.data_out (shuffle_out));
for (j = 0; j < NUM_PORTS; j = j + 1) begin: gen_ports
localparam ctrl_base = (ctrl_stage * NUM_PORTS + j) * MUX_ORDER;
localparam sel_base = j & ~(z-1); // base increments in 2**MUX_ORDER steps
/*
* To be able to better share MUX control signals and reduce overall
* resource consumption the control signal gets rotated by the offset of
* MUX in a switch.
*
* E.g. a control signal of 0 for the first MUX means that the first
* input should be selected. A control signal of 0 for the second switch
* means that the second input will be used. To implement this (j % z)
* is added to the control signal when selecting the input bits. This
* addition does not result in additional resources being used. It just
* results in a different look-up table.
*/
wire [MUX_ORDER-1:0] sel = ctrl[ctrl_base+:MUX_ORDER];// + j % z;
assign mux_out[j*w+:w] = mux_in[(sel_base+sel)*w+:w];
end
/*
* Pack is MUX followed by shuffle.
* Unpack is shuffle followed by MUX.
*/
if (PACK) begin
assign mux_in = interconnect[i];
assign shuffle_in = mux_out;
assign interconnect[i+1] = shuffle_out;
end else begin
assign shuffle_in = interconnect[i];
assign mux_in = shuffle_out;
assign interconnect[i+1] = mux_out;
end
end
endgenerate
endmodule
adi_library/util_pack/util_pack_common/pack_network.v
+107
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module pack_network #(
parameter PORT_ADDRESS_WIDTH = 1,
parameter MUX_ORDER = 1,
parameter MIN_STAGE = 1,
parameter NUM_STAGES = 1,
parameter PACK = 0,
parameter PORT_DATA_WIDTH = 16
) (
input clk,
input ce_ctrl,
input [PORT_ADDRESS_WIDTH-1:0] rotate,
input [2**PORT_ADDRESS_WIDTH*PORT_ADDRESS_WIDTH-1:0] prefix_count,
input [PORT_DATA_WIDTH * 2**PORT_ADDRESS_WIDTH-1:0] data_in,
output [PORT_DATA_WIDTH * 2**PORT_ADDRESS_WIDTH-1:0] data_out
);
localparam CTRL_WIDTH = 2**PORT_ADDRESS_WIDTH * NUM_STAGES * MUX_ORDER;
wire [CTRL_WIDTH-1:0] ctrl_s;
reg [CTRL_WIDTH-1:0] ctrl = 'h00;
wire [CTRL_WIDTH-1:0] ctrl_;
pack_ctrl #(
.PORT_ADDRESS_WIDTH (PORT_ADDRESS_WIDTH),
.MUX_ORDER (MUX_ORDER),
.MIN_STAGE (MIN_STAGE),
.NUM_STAGES (NUM_STAGES),
.PACK (PACK)
) i_ctrl (
.rotate(rotate),
.prefix_count(prefix_count),
.ctrl(ctrl_s));
always @(posedge clk) begin
if (ce_ctrl == 1'b1) begin
ctrl <= ctrl_s;
end
end
/*
* Special optimization for 2-MUXes. In this case both control signals are
* the same.
*/
generate
genvar i;
if (MUX_ORDER == 1) begin
for (i = 1; i < CTRL_WIDTH; i = i + 2) begin: gen_ctrl
assign ctrl_[i] = ctrl[i];
assign ctrl_[i-1] = ~ctrl[i];
end
end else begin
assign ctrl_ = ctrl;
end
endgenerate
pack_interconnect #(
.PORT_DATA_WIDTH (PORT_DATA_WIDTH),
.PORT_ADDRESS_WIDTH (PORT_ADDRESS_WIDTH),
.MUX_ORDER (MUX_ORDER),
.NUM_STAGES (NUM_STAGES),
.PACK (PACK)
) i_interconnect (
.ctrl(ctrl_),
.data_in(data_in),
.data_out(data_out));
endmodule
adi_library/util_pack/util_pack_common/pack_shell.v
+528
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@@ -0,0 +1,528 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module pack_shell #(
parameter NUM_OF_CHANNELS = 4,
parameter SAMPLES_PER_CHANNEL = 1,
parameter SAMPLE_DATA_WIDTH = 16,
parameter PACK = 0
) (
input clk,
input reset,
output reg reset_data = 1'b0,
input [NUM_OF_CHANNELS-1:0] enable,
input ce,
output reg ready = 1'b0,
input [NUM_OF_CHANNELS*SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] in_data,
output [NUM_OF_CHANNELS*SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] out_data,
output out_sync,
output [NUM_OF_CHANNELS*SAMPLES_PER_CHANNEL-1:0] out_valid
);
// If the number of active channels can be a non-power of two
localparam NON_POWER_OF_TWO = NUM_OF_CHANNELS > 2;
localparam CHANNEL_DATA_WIDTH = SAMPLES_PER_CHANNEL * SAMPLE_DATA_WIDTH;
localparam TOTAL_DATA_WIDTH = CHANNEL_DATA_WIDTH * NUM_OF_CHANNELS;
localparam NUM_OF_SAMPLES = NUM_OF_CHANNELS * SAMPLES_PER_CHANNEL;
/*
* Reset and control signals for the state machine. Data and control have
* separate resets since control is pipelined and needs to be taken out of
* reset before data so it can compute the control signals for the first data
* cycle.
*/
reg reset_ctrl = 1'b1;
reg startup_ctrl = 1'b0;
reg startup_ctrl2 = 1'b0;
reg [NUM_OF_CHANNELS-1:0] enable_int = 'h00;
/*
* Internal copy of the enable signals. This is used to detect changes in the
* channel selection and reset the internal state when that happens.
*/
always @(posedge clk) begin
if (reset == 1'b1) begin
enable_int <= {NUM_OF_CHANNELS{1'b0}};
end else begin
enable_int <= enable;
end
end
/*
* The internal state is reset whenever the selected channels change. The
* control path is pipelined and computed one clock cycle in advance. This
* means the control path needs to be taken out of reset one clock cycle
* before the data path and a special startup cycles are required to compute
* the first sets of control signals.
*
* In the case where there is only one channel no control signals are needed
* and hence no startup cycle. In the case where there are two channels the
* control signal pipeline is one cycle, so one startup cycle is required. For
* more than two channels the startup pipeline is two channels and two startup
* cycles are required.
*/
always @(posedge clk) begin
if (reset == 1'b1 || enable == {NUM_OF_CHANNELS{1'b0}}) begin
reset_ctrl <= 1'b1;
reset_data <= 1'b1;
startup_ctrl <= 1'b0;
startup_ctrl2 <= 1'b0;
end else if (enable != enable_int) begin
reset_ctrl <= 1'b1;
reset_data <= 1'b1;
startup_ctrl <= 1'b1;
startup_ctrl2 <= 1'b1;
end else begin
reset_ctrl <= 1'b0;
reset_data <= NUM_OF_CHANNELS != 1 ? startup_ctrl2 : 1'b0;
startup_ctrl2 <= NON_POWER_OF_TWO && PACK == 0 ? reset_ctrl : 1'b0;
startup_ctrl <= reset_ctrl | startup_ctrl2;
end
end
generate
if (NUM_OF_CHANNELS == 1) begin
/*
* In the one channel case there is not much to do. Nevertheless we should
* support it to allow generic designs where the number of channels is
* selected programmatically.
*/
assign out_data = in_data;
assign out_sync = 1'b1;
assign out_valid = {NUM_OF_SAMPLES{1'b1}};
always @(*) begin
ready <= ce & ~reset_data;
end
end else begin
localparam SAMPLE_ADDRESS_WIDTH =
NUM_OF_SAMPLES > 512 ? 10 :
NUM_OF_SAMPLES > 256 ? 9 :
NUM_OF_SAMPLES > 128 ? 8 :
NUM_OF_SAMPLES > 64 ? 7 :
NUM_OF_SAMPLES > 32 ? 6 :
NUM_OF_SAMPLES > 16 ? 5 :
NUM_OF_SAMPLES > 8 ? 4 :
NUM_OF_SAMPLES > 4 ? 3 :
NUM_OF_SAMPLES > 2 ? 2 : 1;
/*
* `rotate` is used as an offset into the input data vector. When not all
* samples are enabled it can take multiple cycles for the input vector to
* be consumed. `rotate` points to the first sample in the input vector
* that should consumed next. E.g. when there are 4 channels, but only 2
* are enabled `rotate` will oscillate between 0 and 2. If there are 4
* channels and 3 are enabled it will cycle through the sequence 0, 3, 2,
* 1.
*/
reg [SAMPLE_ADDRESS_WIDTH-1:0] rotate = 'h00;
/*
* `prefix_count` counts the number of disabled channels that precede a
* channel. E.g. if channel 0 is enabled and channel 1 and 2 are disabled
* the prefix count for channel 3 is 2.
*/
reg [SAMPLE_ADDRESS_WIDTH*NUM_OF_SAMPLES-1:0] prefix_count;
/*
* Clock enable for all the control signals. When asserted the next cycle
* for the control signals should computed
*/
wire ce_ctrl;
/*
* Extended version of the `enable` signal that takes SAMPLES_PER_CHANNEL
* into account.
*/
wire [NUM_OF_SAMPLES-1:0] samples_enable;
/*
* Used to connect the different intermediary stages of the routing
* network. There can be up to three sub-networks.
*/
wire [TOTAL_DATA_WIDTH-1:0] data[0:2];
/*
* Unregistered version of `prefix_count`. This is used to add up the
* enable ports.
*/
wire [SAMPLE_ADDRESS_WIDTH-1:0] prefix_count_s[0:NUM_OF_SAMPLES];
/*
* Samples are interleaved, so the sample mask is just the channel mask
* concatenated with itself SAMPLES_PER_CHANNEL times.
*/
assign samples_enable = {SAMPLES_PER_CHANNEL{enable_int}};
/*
* Control pipeline is active and should compute the next state either
* during the startup phase or when a output data set is consumed.
*/
assign ce_ctrl = startup_ctrl | ce;
/* First channel has no other channels before it */
assign prefix_count_s[0] = 'h0;
genvar i;
for (i = 0; i < NUM_OF_SAMPLES; i = i + 1) begin: gen_prefix_count
assign prefix_count_s[i+1] = prefix_count_s[i] + (samples_enable[i] ? 1'b0 : 1'b1);
if (i < 2 || NUM_OF_CHANNELS <= 2) begin
/* This will only be one bit, no need to register it */
always @(prefix_count_s[i]) begin
prefix_count[i*SAMPLE_ADDRESS_WIDTH+:SAMPLE_ADDRESS_WIDTH] <= prefix_count_s[i];
end
end else begin
always @(posedge clk) begin
prefix_count[i*SAMPLE_ADDRESS_WIDTH+:SAMPLE_ADDRESS_WIDTH] <= prefix_count_s[i];
end
end
end
/*
* Number of enabled channels - 1. Zero enabled channels is not a valid
* configuration and storing it this way allows for better utilization.
*/
reg [SAMPLE_ADDRESS_WIDTH-1:0] enable_count = 'h0;
always @(posedge clk) begin
/*
* `prefix_count` tracks the number of disabled channels. Invert it to
* get the number of enabled channels - 1
*/
enable_count <= ~prefix_count_s[NUM_OF_SAMPLES];
end
if (NON_POWER_OF_TWO == 1 && PACK == 0) begin: gen_input_buffer
/* Delayed data vector. Data from the previous cycle. */
reg [TOTAL_DATA_WIDTH-2*CHANNEL_DATA_WIDTH-1:0] data_d1 = 'h00;
/*
* Same as `rotate`, but two pipeline stages ahead of the data path.
* This is needed to compute some of the other control signals ahead of
* time.
*/
reg [SAMPLE_ADDRESS_WIDTH:0] rotate_next;
/*
* MSB of the rotate control signal. This is used to move the source
* data index to the delayed data vector. This will only ever be
* asserted for one clock cycle at a time.
*/
reg rotate_msb = 1'b0;
/*
* Extended version of the normal control and data signals that can
* handle 2*NUM_OF_CHANNELS channels.
*/
wire [(SAMPLE_ADDRESS_WIDTH+1)*(2*NUM_OF_SAMPLES)-1:0] ext_prefix_count;
wire [TOTAL_DATA_WIDTH*2-1:0] ext_data_in;
wire [TOTAL_DATA_WIDTH*2-1:0] ext_data_out;
wire [TOTAL_DATA_WIDTH*2-1:0] ext_data_shuffled;
wire [SAMPLE_ADDRESS_WIDTH:0] rotate_next_next;
/*
* This stage needs to handle 2*NUM_OF_CHANNELS channels so the prefix
* count needs to padded with an extra bit.
*/
for (i = 0; i < NUM_OF_SAMPLES; i = i + 1) begin: gen_ext_prefix_count1
assign ext_prefix_count[i*(SAMPLE_ADDRESS_WIDTH+1)+:SAMPLE_ADDRESS_WIDTH+1] = {1'b0,prefix_count[i*SAMPLE_ADDRESS_WIDTH+:SAMPLE_ADDRESS_WIDTH]};
end
/*
* The inversion and the addition of the constant will be folded into
* the LUT that generates the control signals. This does not use up any
* extra resources.
*/
for (i = NUM_OF_SAMPLES; i < NUM_OF_SAMPLES * 2; i = i + 1) begin: gen_ext_prefix_count2
assign ext_prefix_count[i*(SAMPLE_ADDRESS_WIDTH+1)+:SAMPLE_ADDRESS_WIDTH+1] = ~enable_count + i;
end
/*
* For non power of two channel masks the previous data needs to be
* saved since a single read can span over two consecutive input data
* words. The lower two channels don't need to be saved since there are
* no configurations in which they'd be required.
*/
always @(posedge clk) begin
if (ce == 1'b1 && ready == 1'b1) begin /* Just ready ??? */
data_d1 <= in_data[TOTAL_DATA_WIDTH-1:2*CHANNEL_DATA_WIDTH];
end
end
/* Three pipeline steps ahead of data */
assign rotate_next_next = rotate_next[SAMPLE_ADDRESS_WIDTH-1:0] + enable_count + 1'b1;
always @(posedge clk) begin
if (reset_ctrl == 1'b1) begin
ready <= 1'b0;
rotate_msb <= 1'b0;
rotate <= 'h0;
rotate_next <= 'h0;
end else if (ce_ctrl == 1'b1) begin
ready <= 1'b0;
rotate_msb <= 1'b0;
/*
* If the next cycle will consume more data than what is still
* available ready needs to be asserted and the network needs to be
* updated to source data from the delayed data register.
*/
if (rotate_next_next[SAMPLE_ADDRESS_WIDTH] &
|rotate_next_next[SAMPLE_ADDRESS_WIDTH-1:0]) begin
ready <= 1'b1;
rotate_msb <= 1'b1;
end
/*
* If the current cycle consumes all available data ready needs to
* be asserted, but only if it wasn't already asserted on the
* previous cycle due to overconsumption.
*/
if (rotate_next[SAMPLE_ADDRESS_WIDTH] == 1'b1 && rotate_msb == 1'b0) begin
ready <= 1'b1;
end
rotate <= rotate_next;
rotate_next <= rotate_next_next;
end
end
/*
* First stage of the routing network. We know that we have at least 4
* channels and hence 8 input to the network, so we'll always use a
* 4-MUX based stage here.
*/
pack_network #(
.PORT_ADDRESS_WIDTH (SAMPLE_ADDRESS_WIDTH + 1),
.MUX_ORDER (2),
.MIN_STAGE (0),
.NUM_STAGES (1),
.PORT_DATA_WIDTH (SAMPLE_DATA_WIDTH)
) i_ext_ctrl_interconnect (
.clk (clk),
.ce_ctrl (ce_ctrl),
.rotate ({rotate_msb,rotate}),
.prefix_count (ext_prefix_count),
.data_in (ext_data_in),
.data_out (ext_data_out));
/*
* In order to go from this stage that has 2 * NUM_OF_SAMPLES inputs
* and output to the remainder of the network that has only NUM_OF_SAMPLES
* inputs and outputs every second two ports need to be skipped. I.e.
* port 2, 3, 6, 7...
* The shuffle groups all ports that are wanted into the first half of
* `ext_data_shuffled` and the unwanted ports into the second half which
* will be discarded.
*/
ad_perfect_shuffle #(
.NUM_GROUPS (NUM_OF_SAMPLES / 2),
.WORDS_PER_GROUP (2),
.WORD_WIDTH (2 * SAMPLE_DATA_WIDTH)
) i_ext_shuffle (
.data_in (ext_data_out),
.data_out (ext_data_shuffled));
assign ext_data_in = {data_d1,{2*CHANNEL_DATA_WIDTH{1'b0}},in_data};
assign data[0] = ext_data_shuffled[0+:TOTAL_DATA_WIDTH];
end else begin
always @(posedge clk) begin
if (reset_ctrl == 1'b1) begin
ready <= 1'b0;
rotate <= 'h0;
end else if (ce_ctrl == 1'b1) begin
/*
* When all samples in the input vector has been consumed ready is
* asserted for a single clock cycle. Here the number of enabled
* channels is always a power of two. That means the input vector is
* evenly divisible into the output data and there is no fractional
* residual data. I.e. when ready is asserted rotate is 0.
*/
{ready,rotate} <= rotate + enable_count + 1'b1;
end
end
assign data[0] = in_data;
end
/*
* The routing network can be built from any type of MUX. When it comes to
* resource usage 2:1 MUXes and 4:1 MUXes are the most efficient, both will
* require the same amount of LUTs. But a network built from 4:1 MUXes only uses
* half the number of stages of a network built from 2:1 MUXes, so it has a
* shorter routing delay and is the preferred architecture.
*
* For a pure 4:1 MUX network the number of ports is a power of 4. For a 2:1 MUX
* network the number of ports is a power of 2. To get the best from both worlds
* build the last stage from 2:1 MUXes when the number of ports is a power of
* 2 and use 4:1 MUXes for the other stages.
*/
for (i = 0; i < 2; i = i + 1) begin: gen_network
localparam MUX_ORDER = i == 0 ? 2 : 1;
localparam MIN_STAGE = PACK ? (i == 0 ? SAMPLE_ADDRESS_WIDTH % 2 : 0) :
(i == 0 ? NON_POWER_OF_TWO : SAMPLE_ADDRESS_WIDTH - 1);
localparam NUM_STAGES = PACK ? (i == 0 ? SAMPLE_ADDRESS_WIDTH / 2 : SAMPLE_ADDRESS_WIDTH % 2) :
(i == 0 ? (SAMPLE_ADDRESS_WIDTH - NON_POWER_OF_TWO) / 2 :
(SAMPLE_ADDRESS_WIDTH - NON_POWER_OF_TWO) % 2);
if (NUM_STAGES > 0) begin
pack_network #(
.PACK (PACK),
.PORT_ADDRESS_WIDTH (SAMPLE_ADDRESS_WIDTH),
.MUX_ORDER (MUX_ORDER),
.MIN_STAGE (MIN_STAGE),
.NUM_STAGES (NUM_STAGES),
.PORT_DATA_WIDTH (SAMPLE_DATA_WIDTH)
) i_ctrl_interconnect (
.clk (clk),
.ce_ctrl (ce_ctrl),
.rotate (rotate),
.prefix_count (prefix_count),
.data_in (data[i]),
.data_out (data[i+1]));
end else begin
assign data[i+1] = data[i];
end
end
if (PACK == 1) begin: gen_pack
/*
* Mask the qualifies the samples in the out_data vector. There is on
* entry for each sample. If the entry is 1 that means the corresponding
* sample has valid data. If the entry is 0 the data is undefined.
*/
reg [NUM_OF_SAMPLES-1:0] valid = 'h00;
/*
* Mask that qualifies the samples that overflowed in the previous
* cycle.
*/
reg [NUM_OF_SAMPLES-2*SAMPLES_PER_CHANNEL-1:0] prev_valid = 'h00;
always @(posedge clk) begin
if (ce_ctrl == 1'b1) begin
{prev_valid,valid} <= (({NUM_OF_SAMPLES{1'b1}} >> ~enable_count) << rotate) | prev_valid;
end
end
if (NON_POWER_OF_TWO == 1) begin: gen_output_buffer
localparam DELAYED_DATA_WIDTH = TOTAL_DATA_WIDTH - 2 * CHANNEL_DATA_WIDTH;
/*
* Delayed data from the previous cycle. When the number of enabled
* channels is not a power of two it is possible that not all
* incoming data can be consumed in one cycle since there might not
* be enough room in the output vector anymore. In this case it needs
* to be delayed and will be used in the next cycle.
*/
reg [DELAYED_DATA_WIDTH-1:0] data_d1 = 'h00;
/*
* `prev_valid` delayed by one clock cyle. This is to compensate for
* the control pipeline delay.
*/
reg [NUM_OF_SAMPLES-2*SAMPLES_PER_CHANNEL-1:0] prev_valid_d1 = 'h00;
/*
* synchronization signal that indicates whether the first enabled
* channel is in the first output sample. This will always be true if
* the number of enabled channels is a power of two.
*/
reg sync = 1'b1;
always @(posedge clk) begin
if (reset_ctrl == 1'b1) begin
sync <= 1'b1;
end else if (ready == 1'b1 && ce == 1'b1) begin
if (rotate == 'h0) begin
sync <= 1'b1;
end else begin
sync <= 1'b0;
end
end
end
always @(posedge clk) begin
if (ce_ctrl == 1'b1) begin
prev_valid_d1 <= prev_valid;
end
end
always @(posedge clk) begin
if (ce == 1'b1) begin
data_d1 <= data[2][DELAYED_DATA_WIDTH-1:0];
end
end
for (i = 0; i < NUM_OF_SAMPLES; i = i + 1) begin: gen_out_data
localparam w = SAMPLE_DATA_WIDTH;
localparam base = i * w;
if (base >= DELAYED_DATA_WIDTH) begin
assign out_data[base+:w] = data[2][base+:w];
end else begin
assign out_data[base+:w] = prev_valid_d1[i] == 1'b1 ? data_d1[base+:w] : data[2][base+:w];
end
end
assign out_sync = sync;
end else begin
assign out_data = data[2];
assign out_sync = 1'b1;
end
assign out_valid = valid;
end else begin
assign out_sync = 1'b1;
assign out_valid = {NUM_OF_SAMPLES{1'b1}};
assign out_data = data[2];
end
end
endgenerate
endmodule
adi_library/util_pack/util_upack2/Makefile
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####################################################################################
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := util_upack2
GENERIC_DEPS += ../../common/ad_perfect_shuffle.v
GENERIC_DEPS += ../util_pack_common/pack_ctrl.v
GENERIC_DEPS += ../util_pack_common/pack_interconnect.v
GENERIC_DEPS += ../util_pack_common/pack_network.v
GENERIC_DEPS += ../util_pack_common/pack_shell.v
GENERIC_DEPS += util_upack2_impl.v
XILINX_DEPS += util_upack2.v
XILINX_DEPS += util_upack2_ip.tcl
INTEL_DEPS += util_upack2_hw.tcl
include ../../scripts/library.mk
adi_library/util_pack/util_upack2/component.xml
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adi_library/util_pack/util_upack2/util_upack2.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module util_upack2 #(
parameter NUM_OF_CHANNELS = 4,
parameter SAMPLES_PER_CHANNEL = 1,
parameter SAMPLE_DATA_WIDTH = 16
) (
input clk,
input reset,
input enable_0,
input enable_1,
input enable_2,
input enable_3,
input enable_4,
input enable_5,
input enable_6,
input enable_7,
input enable_8,
input enable_9,
input enable_10,
input enable_11,
input enable_12,
input enable_13,
input enable_14,
input enable_15,
input enable_16,
input enable_17,
input enable_18,
input enable_19,
input enable_20,
input enable_21,
input enable_22,
input enable_23,
input enable_24,
input enable_25,
input enable_26,
input enable_27,
input enable_28,
input enable_29,
input enable_30,
input enable_31,
input enable_32,
input enable_33,
input enable_34,
input enable_35,
input enable_36,
input enable_37,
input enable_38,
input enable_39,
input enable_40,
input enable_41,
input enable_42,
input enable_43,
input enable_44,
input enable_45,
input enable_46,
input enable_47,
input enable_48,
input enable_49,
input enable_50,
input enable_51,
input enable_52,
input enable_53,
input enable_54,
input enable_55,
input enable_56,
input enable_57,
input enable_58,
input enable_59,
input enable_60,
input enable_61,
input enable_62,
input enable_63,
input fifo_rd_en,
output fifo_rd_valid,
output fifo_rd_underflow,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_0,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_1,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_2,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_3,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_4,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_5,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_6,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_7,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_8,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_9,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_10,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_11,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_12,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_13,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_14,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_15,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_16,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_17,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_18,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_19,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_20,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_21,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_22,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_23,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_24,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_25,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_26,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_27,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_28,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_29,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_30,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_31,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_32,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_33,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_34,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_35,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_36,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_37,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_38,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_39,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_40,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_41,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_42,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_43,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_44,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_45,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_46,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_47,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_48,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_49,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_50,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_51,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_52,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_53,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_54,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_55,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_56,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_57,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_58,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_59,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_60,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_61,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_62,
output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_63,
input s_axis_valid,
output s_axis_ready,
input [2**$clog2(NUM_OF_CHANNELS)*SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] s_axis_data
);
localparam CHANNEL_DATA_WIDTH = SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL;
/*
* Round up to the next power of two and zero out the additional channels
* internally.
*/
localparam REAL_NUM_OF_CHANNELS = NUM_OF_CHANNELS > 32 ? 64 :
NUM_OF_CHANNELS > 16 ? 32 :
NUM_OF_CHANNELS > 8 ? 16 :
NUM_OF_CHANNELS > 4 ? 8 :
NUM_OF_CHANNELS > 2 ? 4 :
NUM_OF_CHANNELS > 1 ? 2 : 1;
/* FIXME: Find out how to do this in the IP-XACT */
wire [63:0] enable_s;
wire [CHANNEL_DATA_WIDTH*REAL_NUM_OF_CHANNELS-1:0] fifo_rd_data;
wire [CHANNEL_DATA_WIDTH*64-1:0] fifo_rd_data_s;
util_upack2_impl #(
.NUM_OF_CHANNELS(REAL_NUM_OF_CHANNELS),
.SAMPLE_DATA_WIDTH(SAMPLE_DATA_WIDTH),
.SAMPLES_PER_CHANNEL(SAMPLES_PER_CHANNEL)
) i_upack (
.clk (clk),
.reset (reset),
.enable (enable_s[REAL_NUM_OF_CHANNELS-1:0]),
.fifo_rd_en ({REAL_NUM_OF_CHANNELS{fifo_rd_en}}),
.fifo_rd_valid (fifo_rd_valid),
.fifo_rd_underflow (fifo_rd_underflow),
.fifo_rd_data (fifo_rd_data),
.s_axis_valid (s_axis_valid),
.s_axis_ready (s_axis_ready),
.s_axis_data (s_axis_data));
assign enable_s = {
enable_63,enable_62,enable_61,enable_60,enable_59,enable_58,enable_57,enable_56,
enable_55,enable_54,enable_53,enable_52,enable_51,enable_50,enable_49,enable_48,
enable_47,enable_46,enable_45,enable_44,enable_43,enable_42,enable_41,enable_40,
enable_39,enable_38,enable_37,enable_36,enable_35,enable_34,enable_33,enable_32,
enable_31,enable_30,enable_29,enable_28,enable_27,enable_26,enable_25,enable_24,
enable_23,enable_22,enable_21,enable_20,enable_19,enable_18,enable_17,enable_16,
enable_15,enable_14,enable_13,enable_12,enable_11,enable_10,enable_9,enable_8,
enable_7,enable_6,enable_5,enable_4,enable_3,enable_2,enable_1,enable_0
};
assign fifo_rd_data_s = {{(64-NUM_OF_CHANNELS)*CHANNEL_DATA_WIDTH{1'b0}},fifo_rd_data};
assign fifo_rd_data_0 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*0+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_1 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*1+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_2 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*2+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_3 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*3+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_4 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*4+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_5 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*5+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_6 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*6+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_7 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*7+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_8 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*8+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_9 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*9+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_10 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*10+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_11 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*11+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_12 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*12+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_13 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*13+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_14 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*14+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_15 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*15+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_16 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*16+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_17 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*17+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_18 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*18+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_19 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*19+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_20 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*20+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_21 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*21+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_22 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*22+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_23 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*23+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_24 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*24+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_25 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*25+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_26 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*26+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_27 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*27+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_28 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*28+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_29 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*29+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_30 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*30+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_31 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*31+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_32 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*32+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_33 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*33+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_34 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*34+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_35 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*35+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_36 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*36+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_37 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*37+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_38 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*38+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_39 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*39+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_40 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*40+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_41 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*41+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_42 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*42+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_43 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*43+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_44 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*44+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_45 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*45+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_46 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*46+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_47 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*47+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_48 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*48+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_49 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*49+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_50 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*50+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_51 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*51+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_52 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*52+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_53 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*53+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_54 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*54+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_55 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*55+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_56 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*56+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_57 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*57+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_58 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*58+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_59 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*59+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_60 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*60+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_61 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*61+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_62 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*62+:CHANNEL_DATA_WIDTH];
assign fifo_rd_data_63 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*63+:CHANNEL_DATA_WIDTH];
endmodule
adi_library/util_pack/util_upack2/util_upack2.xpr
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/util_pack/util_upack2/util_upack2.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
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adi_library/util_pack/util_upack2/util_upack2_hw.tcl
+94
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@@ -0,0 +1,94 @@
###############################################################################
## Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
package require qsys 14.0
source ../../../scripts/adi_env.tcl
source ../../scripts/adi_ip_intel.tcl
ad_ip_create util_upack2 {Channel Unpack Utility v2} util_upack_elab
ad_ip_files util_upack2_impl [list \
$ad_hdl_dir/library/common/ad_perfect_shuffle.v \
../util_pack_common/pack_ctrl.v \
../util_pack_common/pack_interconnect.v \
../util_pack_common/pack_network.v \
../util_pack_common/pack_shell.v \
util_upack2_impl.v ]
# parameters
ad_ip_parameter NUM_OF_CHANNELS INTEGER 4 true [list \
DISPLAY_NAME "Number of Channels"
]
ad_ip_parameter SAMPLES_PER_CHANNEL INTEGER 1 true [list \
DISPLAY_NAME "Samples per Channel"
]
ad_ip_parameter SAMPLE_DATA_WIDTH INTEGER 16 true [list \
DISPLAY_NAME "Sample Data Width"
]
ad_ip_parameter INTERFACE_TYPE INTEGER 0 false [list \
DISPLAY_NAME "Interface Type" \
ALLOWED_RANGES {"0:AXIS" "1:FIFO"} \
]
# defaults
proc util_upack_elab {} {
set num_channels [get_parameter_value NUM_OF_CHANNELS]
set samples_per_channel [get_parameter_value SAMPLES_PER_CHANNEL]
set sample_data_width [get_parameter_value SAMPLE_DATA_WIDTH]
set interface_type [get_parameter_value INTERFACE_TYPE]
set channel_data_width [expr $sample_data_width * $samples_per_channel]
set total_data_width [expr $num_channels * $channel_data_width]
add_interface clk clock end
add_interface_port clk clk clk Input 1
add_interface reset reset end
add_interface_port reset reset reset Input 1
set_interface_property reset associatedClock clk
# This is a temporary hack and should be removed once all projects have been
# updated to use the AXI streaming interface to connect the the upack
if {$interface_type == 0} {
add_interface s_axis axi4stream end
set_interface_property s_axis associatedClock clk
set_interface_property s_axis associatedReset reset
add_interface_port s_axis s_axis_valid tvalid Input 1
add_interface_port s_axis s_axis_ready tready Output 1
add_interface_port s_axis s_axis_data tdata Input $total_data_width
} else {
ad_interface signal packed_fifo_rd_en output 1 valid
set_port_property packed_fifo_rd_en fragment_list "s_axis_ready"
ad_interface signal packed_fifo_rd_data input $total_data_width data
set_port_property packed_fifo_rd_data fragment_list \
[format "s_axis_data(%d:0)" [expr $total_data_width - 1]]
ad_interface signal s_axis_valid input 1 valid
set_port_property s_axis_valid TERMINATION TRUE
set_port_property s_axis_valid TERMINATION_VALUE 1
}
ad_interface signal fifo_rd_underflow output 1 unf
for {set n 0} {$n < $num_channels} {incr n} {
add_interface dac_ch_${n} conduit end
add_interface_port dac_ch_${n} enable_${n} enable Input 1
set_port_property enable_${n} fragment_list "enable(${n}:${n})"
add_interface_port dac_ch_${n} fifo_rd_en_${n} valid Input 1
set_port_property fifo_rd_en_${n} fragment_list "fifo_rd_en(${n})"
add_interface_port dac_ch_${n} fifo_rd_valid_${n} data_valid Output 1
set_port_property fifo_rd_valid_${n} fragment_list "fifo_rd_valid(0)"
add_interface_port dac_ch_${n} fifo_rd_data_${n} data Output $channel_data_width
set_port_property fifo_rd_data_${n} fragment_list [format "fifo_rd_data(%d:%d)" \
[expr ($n+1) * $channel_data_width - 1] [expr $n * $channel_data_width]]
set_interface_property dac_ch_${n} associatedClock clk
set_interface_property dac_ch_${n} associatedReset ""
}
}
adi_library/util_pack/util_upack2/util_upack2_impl.v
+144
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@@ -0,0 +1,144 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module util_upack2_impl #(
parameter NUM_OF_CHANNELS = 4,
parameter SAMPLES_PER_CHANNEL = 1,
parameter SAMPLE_DATA_WIDTH = 16
) (
input clk,
input reset,
input [NUM_OF_CHANNELS-1:0] enable,
input [NUM_OF_CHANNELS-1:0] fifo_rd_en,
output reg fifo_rd_valid,
output reg fifo_rd_underflow,
output reg [NUM_OF_CHANNELS*SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data,
input s_axis_valid,
output s_axis_ready,
input [NUM_OF_CHANNELS*SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] s_axis_data
);
/*
* Final output data of the routing network that will be written to
* `fifo_rd_data` after being deinterleaved.
*/
wire [NUM_OF_CHANNELS*SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] out_data;
/*
* Deinterleaved version of `out_data`
*/
wire [NUM_OF_CHANNELS*SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] deinterleaved_data;
/*
* Internal read signal.
*/
wire data_rd_en;
/*
* Control signals from/to the pack shell.
*/
wire ce;
wire ready;
wire reset_data;
/*
* Only the first signal of fifo_rd_en is used. All others are ignored. The
* only reason why fifo_rd_en has multiple entries is to keep the interface
* somewhat backwards compatible to the previous upack.
*/
assign data_rd_en = fifo_rd_en[0];
assign ce = s_axis_valid & data_rd_en;
assign s_axis_ready = ready & ce;
pack_shell #(
.NUM_OF_CHANNELS (NUM_OF_CHANNELS),
.SAMPLES_PER_CHANNEL (SAMPLES_PER_CHANNEL),
.SAMPLE_DATA_WIDTH (SAMPLE_DATA_WIDTH),
.PACK (0)
) i_pack_shell (
.clk (clk),
.reset (reset),
.reset_data (reset_data),
.enable (enable),
.ce (ce),
.ready (ready),
.in_data (s_axis_data),
.out_data (out_data),
.out_valid (),
.out_sync ());
/*
* Data at the output of the routing network is interleaved. The upack
* core is supposed to produce deinterleaved data. This just rearrange the
* bits in the data vector and does not consume any FPGA resources.
*/
ad_perfect_shuffle #(
.NUM_GROUPS (SAMPLES_PER_CHANNEL),
.WORDS_PER_GROUP (NUM_OF_CHANNELS),
.WORD_WIDTH (SAMPLE_DATA_WIDTH)
) i_deinterleave (
.data_in (out_data),
.data_out (deinterleaved_data));
always @(posedge clk) begin
/* In case of an underflow the output vector should be zeroed */
if (reset_data == 1'b1 ||
(data_rd_en == 1'b1 && s_axis_valid == 1'b0)) begin
fifo_rd_data <= 'h00;
end else if (data_rd_en == 1'b1) begin
fifo_rd_data <= deinterleaved_data;
end
end
always @(posedge clk) begin
if (data_rd_en == 1'b1) begin
fifo_rd_valid <= s_axis_valid & ~reset_data;
fifo_rd_underflow <= ~(s_axis_valid & ~reset_data);
end else begin
fifo_rd_valid <= 1'b0;
fifo_rd_underflow <= 1'b0;
end
end
endmodule
adi_library/util_pack/util_upack2/util_upack2_ip.tcl
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###############################################################################
## Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
source ../../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
adi_ip_create util_upack2
adi_ip_files util_upack2 [list \
"../../common/ad_perfect_shuffle.v" \
"../util_pack_common/pack_ctrl.v" \
"../util_pack_common/pack_interconnect.v" \
"../util_pack_common/pack_network.v" \
"../util_pack_common/pack_shell.v" \
"util_upack2_impl.v" \
"util_upack2.v" ]
set_property source_mgmt_mode DisplayOnly [current_project]
adi_ip_properties_lite util_upack2
adi_add_bus "s_axis" "slave" \
"xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \
[list {"s_axis_ready" "TREADY"} \
{"s_axis_valid" "TVALID"} \
{"s_axis_data" "TDATA"} \
]
adi_add_bus_clock "clk" "s_axis" "reset"
set cc [ipx::current_core]
for {set i 1} {$i < 64} {incr i} {
set_property enablement_dependency "spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > $i" \
[ipx::get_ports *_$i -of_objects $cc]
}
foreach {k v} { \
"NUM_OF_CHANNELS" "Number of Channels" \
"SAMPLES_PER_CHANNEL" "Samples per Channel" \
"SAMPLE_DATA_WIDTH" "Sample Width" \
} { \
set p [ipgui::get_guiparamspec -name $k -component $cc]
# ipgui::move_param -component $cc -order $i $p -parent $
set_property -dict [list \
DISPLAY_NAME $v \
] $p
incr i
}
ipx::save_core [ipx::current_core]
adi_library/util_pack/util_upack2/xgui/util_upack2_v1_0.tcl
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# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
ipgui::add_param $IPINST -name "NUM_OF_CHANNELS" -parent ${Page_0}
ipgui::add_param $IPINST -name "SAMPLES_PER_CHANNEL" -parent ${Page_0}
ipgui::add_param $IPINST -name "SAMPLE_DATA_WIDTH" -parent ${Page_0}
}
proc update_PARAM_VALUE.NUM_OF_CHANNELS { PARAM_VALUE.NUM_OF_CHANNELS } {
# Procedure called to update NUM_OF_CHANNELS when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.NUM_OF_CHANNELS { PARAM_VALUE.NUM_OF_CHANNELS } {
# Procedure called to validate NUM_OF_CHANNELS
return true
}
proc update_PARAM_VALUE.SAMPLES_PER_CHANNEL { PARAM_VALUE.SAMPLES_PER_CHANNEL } {
# Procedure called to update SAMPLES_PER_CHANNEL when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.SAMPLES_PER_CHANNEL { PARAM_VALUE.SAMPLES_PER_CHANNEL } {
# Procedure called to validate SAMPLES_PER_CHANNEL
return true
}
proc update_PARAM_VALUE.SAMPLE_DATA_WIDTH { PARAM_VALUE.SAMPLE_DATA_WIDTH } {
# Procedure called to update SAMPLE_DATA_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.SAMPLE_DATA_WIDTH { PARAM_VALUE.SAMPLE_DATA_WIDTH } {
# Procedure called to validate SAMPLE_DATA_WIDTH
return true
}
proc update_MODELPARAM_VALUE.NUM_OF_CHANNELS { MODELPARAM_VALUE.NUM_OF_CHANNELS PARAM_VALUE.NUM_OF_CHANNELS } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.NUM_OF_CHANNELS}] ${MODELPARAM_VALUE.NUM_OF_CHANNELS}
}
proc update_MODELPARAM_VALUE.SAMPLES_PER_CHANNEL { MODELPARAM_VALUE.SAMPLES_PER_CHANNEL PARAM_VALUE.SAMPLES_PER_CHANNEL } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.SAMPLES_PER_CHANNEL}] ${MODELPARAM_VALUE.SAMPLES_PER_CHANNEL}
}
proc update_MODELPARAM_VALUE.SAMPLE_DATA_WIDTH { MODELPARAM_VALUE.SAMPLE_DATA_WIDTH PARAM_VALUE.SAMPLE_DATA_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.SAMPLE_DATA_WIDTH}] ${MODELPARAM_VALUE.SAMPLE_DATA_WIDTH}
}