initial commit, add dds_par module
This commit is contained in:
@@ -0,0 +1,15 @@
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####################################################################################
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## Copyright (c) 2018 - 2023 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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||||
####################################################################################
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LIBRARY_NAME := util_tdd_sync
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GENERIC_DEPS += ../common/util_pulse_gen.v
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GENERIC_DEPS += util_tdd_sync.v
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XILINX_DEPS += util_tdd_sync_constr.xdc
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XILINX_DEPS += util_tdd_sync_ip.tcl
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include ../scripts/library.mk
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@@ -0,0 +1,282 @@
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|
||||
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|
||||
<spirit:vendor>analog.com</spirit:vendor>
|
||||
<spirit:library>user</spirit:library>
|
||||
<spirit:name>util_tdd_sync</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>clk</spirit:name>
|
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||||
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|
||||
<spirit:name>CLK</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
|
||||
<spirit:name>clk</spirit:name>
|
||||
</spirit:physicalPort>
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||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
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||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET">rstn</spirit:value>
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||||
</spirit:parameter>
|
||||
</spirit:parameters>
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||||
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<spirit:name>rstn</spirit:name>
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<spirit:name>rstn</spirit:name>
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<spirit:value spirit:id="BUSIFPARAM_VALUE.RSTN.POLARITY" spirit:choiceRef="choice_list_74b5137e">ACTIVE_LOW</spirit:value>
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<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
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<spirit:modelName>util_tdd_sync</spirit:modelName>
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<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
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<spirit:name>rstn</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:port>
|
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<spirit:name>sync_mode</spirit:name>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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<spirit:port>
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<spirit:name>sync_in</spirit:name>
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||||
<spirit:port>
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||||
<spirit:name>sync_out</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDef>
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<spirit:typeName>reg</spirit:typeName>
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</spirit:ports>
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<spirit:modelParameters>
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<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>TDD_SYNC_PERIOD</spirit:name>
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||||
<spirit:displayName>Tdd Sync Period</spirit:displayName>
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||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.TDD_SYNC_PERIOD">100000000</spirit:value>
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<spirit:name>util_tdd_sync_constr.xdc</spirit:name>
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<spirit:userFileType>xdc</spirit:userFileType>
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</spirit:file>
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<spirit:file>
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<spirit:name>../common/util_pulse_gen.v</spirit:name>
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<spirit:fileType>verilogSource</spirit:fileType>
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<spirit:file>
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<spirit:name>util_tdd_sync.v</spirit:name>
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<spirit:name>../common/util_pulse_gen.v</spirit:name>
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<spirit:fileType>verilogSource</spirit:fileType>
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<spirit:name>util_tdd_sync.v</spirit:name>
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<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
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<spirit:file>
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<spirit:name>xgui/util_tdd_sync_v1_0.tcl</spirit:name>
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<spirit:fileType>tclSource</spirit:fileType>
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<spirit:userFileType>CHECKSUM_fdcef067</spirit:userFileType>
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<spirit:description>util_tdd_sync_v1_0</spirit:description>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>TDD_SYNC_PERIOD</spirit:name>
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<spirit:displayName>Tdd Sync Period</spirit:displayName>
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<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.TDD_SYNC_PERIOD">100000000</spirit:value>
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<spirit:name>Component_Name</spirit:name>
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<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">util_tdd_sync_v1_0</spirit:value>
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<xilinx:taxonomies>
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<xilinx:taxonomy>/Analog_Devices</xilinx:taxonomy>
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</xilinx:taxonomies>
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<xilinx:displayName>util_tdd_sync_v1_0</xilinx:displayName>
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@@ -0,0 +1,98 @@
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||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
//
|
||||
// Simple pulse generator for TDD control
|
||||
// The module has two modes. In function of the state of sync_mode,
|
||||
// the syncronization signal (sync_out) can get its value from an external
|
||||
// source or from its internal generator.
|
||||
//
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module util_tdd_sync #(
|
||||
|
||||
parameter TDD_SYNC_PERIOD = 100000000
|
||||
) (
|
||||
input clk,
|
||||
input rstn,
|
||||
|
||||
input sync_mode,
|
||||
|
||||
input sync_in,
|
||||
output reg sync_out
|
||||
);
|
||||
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||||
reg sync_mode_d1 = 1'b0;
|
||||
reg sync_mode_d2 = 1'b0;
|
||||
|
||||
wire sync_internal;
|
||||
wire sync_external;
|
||||
|
||||
// pulse generator
|
||||
|
||||
util_pulse_gen #(
|
||||
.PULSE_PERIOD(TDD_SYNC_PERIOD)
|
||||
) i_tdd_sync (
|
||||
.clk (clk),
|
||||
.rstn (rstn),
|
||||
.pulse_width (32'd0),
|
||||
.pulse_period (32'd0),
|
||||
.load_config (1'd0),
|
||||
.pulse (sync_internal));
|
||||
|
||||
// synchronization logic
|
||||
|
||||
always @(posedge clk) begin
|
||||
if(rstn == 1'b0) begin
|
||||
sync_mode_d1 <= 1'b0;
|
||||
sync_mode_d2 <= 1'b0;
|
||||
end else begin
|
||||
sync_mode_d1 <= sync_mode;
|
||||
sync_mode_d2 <= sync_mode_d1;
|
||||
end
|
||||
end
|
||||
|
||||
// output logic
|
||||
|
||||
assign sync_external = sync_in;
|
||||
always @(posedge clk) begin
|
||||
if(rstn == 1'b0) begin
|
||||
sync_out <= 1'b0;
|
||||
end else begin
|
||||
sync_out <= (sync_mode_d2 == 1'b0) ? sync_internal : sync_external;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
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|
||||
<MsgAttr Name="Id" Val="Synth 8-2490"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
</Project>
|
||||
@@ -0,0 +1,10 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
set_property ASYNC_REG TRUE \
|
||||
[get_cells -hier *sync_mode_d*]
|
||||
|
||||
set_false_path -to [get_pins -hier -filter {NAME =~ */sync_mode_d1_reg/D}]
|
||||
|
||||
@@ -0,0 +1,23 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
# ip
|
||||
|
||||
source ../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
adi_ip_create util_tdd_sync
|
||||
adi_ip_files util_tdd_sync [list \
|
||||
"$ad_hdl_dir/library/common/util_pulse_gen.v" \
|
||||
"util_tdd_sync_constr.xdc" \
|
||||
"util_tdd_sync.v"]
|
||||
|
||||
adi_ip_properties_lite util_tdd_sync
|
||||
|
||||
ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
ipx::infer_bus_interface rstn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
|
||||
@@ -0,0 +1,25 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "TDD_SYNC_PERIOD" -parent ${Page_0}
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.TDD_SYNC_PERIOD { PARAM_VALUE.TDD_SYNC_PERIOD } {
|
||||
# Procedure called to update TDD_SYNC_PERIOD when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.TDD_SYNC_PERIOD { PARAM_VALUE.TDD_SYNC_PERIOD } {
|
||||
# Procedure called to validate TDD_SYNC_PERIOD
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.TDD_SYNC_PERIOD { MODELPARAM_VALUE.TDD_SYNC_PERIOD PARAM_VALUE.TDD_SYNC_PERIOD } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.TDD_SYNC_PERIOD}] ${MODELPARAM_VALUE.TDD_SYNC_PERIOD}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user