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initial commit, add dds_par module

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josh
2024-01-15 09:36:08 +08:00
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adi_library/xilinx/axi_adcfifo/Makefile
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####################################################################################
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := axi_adcfifo
XILINX_DEPS += ../../common/ad_axis_inf_rx.v
XILINX_DEPS += ../../common/ad_mem.v
XILINX_DEPS += ../../common/ad_mem_asym.v
XILINX_DEPS += ../../common/up_xfer_status.v
XILINX_DEPS += axi_adcfifo.v
XILINX_DEPS += axi_adcfifo_adc.v
XILINX_DEPS += axi_adcfifo_constr.xdc
XILINX_DEPS += axi_adcfifo_dma.v
XILINX_DEPS += axi_adcfifo_ip.tcl
XILINX_DEPS += axi_adcfifo_rd.v
XILINX_DEPS += axi_adcfifo_wr.v
include ../../scripts/library.mk
adi_library/xilinx/axi_adcfifo/axi_adcfifo.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_adcfifo #(
parameter ADC_DATA_WIDTH = 128,
parameter DMA_DATA_WIDTH = 64,
parameter AXI_DATA_WIDTH = 512,
parameter DMA_READY_ENABLE = 1,
parameter AXI_SIZE = 2,
parameter AXI_LENGTH = 16,
parameter AXI_ADDRESS = 32'h00000000,
parameter AXI_ADDRESS_LIMIT = 32'hffffffff
) (
// fifo interface
input adc_rst,
input adc_clk,
input adc_wr,
input [ADC_DATA_WIDTH-1:0] adc_wdata,
output adc_wovf,
// dma interface
input dma_clk,
output dma_wr,
output [DMA_DATA_WIDTH-1:0] dma_wdata,
input dma_wready,
input dma_xfer_req,
output [ 3:0] dma_xfer_status,
// axi interface
input axi_clk,
input axi_resetn,
output axi_awvalid,
output [ 3:0] axi_awid,
output [ 1:0] axi_awburst,
output axi_awlock,
output [ 3:0] axi_awcache,
output [ 2:0] axi_awprot,
output [ 3:0] axi_awqos,
output [ 3:0] axi_awuser,
output [ 7:0] axi_awlen,
output [ 2:0] axi_awsize,
output [ 31:0] axi_awaddr,
input axi_awready,
output axi_wvalid,
output [AXI_DATA_WIDTH-1:0] axi_wdata,
output [(AXI_DATA_WIDTH/8)-1:0] axi_wstrb,
output axi_wlast,
output [ 3:0] axi_wuser,
input axi_wready,
input axi_bvalid,
input [ 3:0] axi_bid,
input [ 1:0] axi_bresp,
input [ 3:0] axi_buser,
output axi_bready,
output axi_arvalid,
output [ 3:0] axi_arid,
output [ 1:0] axi_arburst,
output axi_arlock,
output [ 3:0] axi_arcache,
output [ 2:0] axi_arprot,
output [ 3:0] axi_arqos,
output [ 3:0] axi_aruser,
output [ 7:0] axi_arlen,
output [ 2:0] axi_arsize,
output [ 31:0] axi_araddr,
input axi_arready,
input axi_rvalid,
input [ 3:0] axi_rid,
input [ 3:0] axi_ruser,
input [ 1:0] axi_rresp,
input axi_rlast,
input [AXI_DATA_WIDTH-1:0] axi_rdata,
output axi_rready
);
// internal signals
wire adc_dwr_s;
wire [AXI_DATA_WIDTH-1:0] adc_ddata_s;
wire axi_rd_req_s;
wire [ 31:0] axi_rd_addr_s;
wire [ 3:0] axi_xfer_status_s;
wire axi_drst_s;
wire axi_dvalid_s;
wire [AXI_DATA_WIDTH-1:0] axi_ddata_s;
wire axi_dready_s;
// instantiations
axi_adcfifo_adc #(
.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
.ADC_DATA_WIDTH (ADC_DATA_WIDTH)
) i_adc_if (
.adc_rst (adc_rst),
.adc_clk (adc_clk),
.adc_wr (adc_wr),
.adc_wdata (adc_wdata),
.adc_wovf (adc_wovf),
.adc_dwr (adc_dwr_s),
.adc_ddata (adc_ddata_s),
.axi_drst (axi_drst_s),
.axi_clk (axi_clk),
.axi_xfer_status (axi_xfer_status_s));
axi_adcfifo_wr #(
.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
.AXI_SIZE (AXI_SIZE),
.AXI_LENGTH (AXI_LENGTH),
.AXI_ADDRESS (AXI_ADDRESS),
.AXI_ADDRESS_LIMIT (AXI_ADDRESS_LIMIT)
) i_wr (
.dma_xfer_req (dma_xfer_req),
.axi_rd_req (axi_rd_req_s),
.axi_rd_addr (axi_rd_addr_s),
.adc_rst (adc_rst),
.adc_clk (adc_clk),
.adc_wr (adc_dwr_s),
.adc_wdata (adc_ddata_s),
.axi_clk (axi_clk),
.axi_resetn (axi_resetn),
.axi_awvalid (axi_awvalid),
.axi_awid (axi_awid),
.axi_awburst (axi_awburst),
.axi_awlock (axi_awlock),
.axi_awcache (axi_awcache),
.axi_awprot (axi_awprot),
.axi_awqos (axi_awqos),
.axi_awuser (axi_awuser),
.axi_awlen (axi_awlen),
.axi_awsize (axi_awsize),
.axi_awaddr (axi_awaddr),
.axi_awready (axi_awready),
.axi_wvalid (axi_wvalid),
.axi_wdata (axi_wdata),
.axi_wstrb (axi_wstrb),
.axi_wlast (axi_wlast),
.axi_wuser (axi_wuser),
.axi_wready (axi_wready),
.axi_bvalid (axi_bvalid),
.axi_bid (axi_bid),
.axi_bresp (axi_bresp),
.axi_buser (axi_buser),
.axi_bready (axi_bready),
.axi_dwovf (axi_xfer_status_s[0]),
.axi_dwunf (axi_xfer_status_s[1]),
.axi_werror (axi_xfer_status_s[2]));
axi_adcfifo_rd #(
.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
.AXI_SIZE (AXI_SIZE),
.AXI_LENGTH (AXI_LENGTH),
.AXI_ADDRESS (AXI_ADDRESS),
.AXI_ADDRESS_LIMIT (AXI_ADDRESS_LIMIT)
) i_rd (
.dma_xfer_req (dma_xfer_req),
.axi_rd_req (axi_rd_req_s),
.axi_rd_addr (axi_rd_addr_s),
.axi_clk (axi_clk),
.axi_resetn (axi_resetn),
.axi_arvalid (axi_arvalid),
.axi_arid (axi_arid),
.axi_arburst (axi_arburst),
.axi_arlock (axi_arlock),
.axi_arcache (axi_arcache),
.axi_arprot (axi_arprot),
.axi_arqos (axi_arqos),
.axi_aruser (axi_aruser),
.axi_arlen (axi_arlen),
.axi_arsize (axi_arsize),
.axi_araddr (axi_araddr),
.axi_arready (axi_arready),
.axi_rvalid (axi_rvalid),
.axi_rid (axi_rid),
.axi_ruser (axi_ruser),
.axi_rresp (axi_rresp),
.axi_rlast (axi_rlast),
.axi_rdata (axi_rdata),
.axi_rready (axi_rready),
.axi_rerror (axi_xfer_status_s[3]),
.axi_drst (axi_drst_s),
.axi_dvalid (axi_dvalid_s),
.axi_ddata (axi_ddata_s),
.axi_dready (axi_dready_s));
axi_adcfifo_dma #(
.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
.DMA_DATA_WIDTH (DMA_DATA_WIDTH),
.DMA_READY_ENABLE (DMA_READY_ENABLE)
) i_dma_if (
.axi_clk (axi_clk),
.axi_drst (axi_drst_s),
.axi_dvalid (axi_dvalid_s),
.axi_ddata (axi_ddata_s),
.axi_dready (axi_dready_s),
.axi_xfer_status (axi_xfer_status_s),
.dma_clk (dma_clk),
.dma_wr (dma_wr),
.dma_wdata (dma_wdata),
.dma_wready (dma_wready),
.dma_xfer_req (dma_xfer_req),
.dma_xfer_status (dma_xfer_status));
endmodule
adi_library/xilinx/axi_adcfifo/axi_adcfifo.xpr
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<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
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<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val=""/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="12"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="BD 41-1343"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="2"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="BD 41-1306"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="3"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="ERROR"/>
<MsgAttr Name="Id" Val="BD 41-1276"/>
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="4"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="5"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="6"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="7"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="Synth 8-3331"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="8"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="Synth 8-2490"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="9"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<Board/>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">
<Gadgets>
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
</Gadget>
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
</Gadget>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
</Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
</Project>
adi_library/xilinx/axi_adcfifo/axi_adcfifo_adc.v
+126
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@@ -0,0 +1,126 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_adcfifo_adc #(
parameter ADC_DATA_WIDTH = 128,
parameter AXI_DATA_WIDTH = 512
) (
// fifo interface
input adc_rst,
input adc_clk,
input adc_wr,
input [ADC_DATA_WIDTH-1:0] adc_wdata,
output reg adc_wovf,
output reg adc_dwr,
output reg [AXI_DATA_WIDTH-1:0] adc_ddata,
// axi interface
input axi_drst,
input axi_clk,
input [ 3:0] axi_xfer_status
);
localparam ADC_MEM_RATIO = AXI_DATA_WIDTH/ADC_DATA_WIDTH;
// internal registers
reg [ 2:0] adc_wcnt_int = 'd0;
// internal signals
wire [ 3:0] adc_xfer_status_s;
// write interface: supports only 64, 128, 256 and 512 against 512
always @(posedge adc_clk) begin
if (adc_rst == 1'b1) begin
adc_wovf <= 'd0;
adc_wcnt_int <= 'd0;
adc_dwr <= 'd0;
adc_ddata <= 'd0;
end else begin
adc_wovf <= | adc_xfer_status_s;
adc_dwr <= (ADC_MEM_RATIO == 8) ? adc_wr & adc_wcnt_int[0] & adc_wcnt_int[1] & adc_wcnt_int[2] :
(ADC_MEM_RATIO == 4) ? adc_wr & adc_wcnt_int[0] & adc_wcnt_int[1] :
(ADC_MEM_RATIO == 2) ? adc_wr & adc_wcnt_int[0] :
(ADC_MEM_RATIO == 1) ? adc_wr : 'd0;
if (adc_wr == 1'b1) begin
adc_wcnt_int <= adc_wcnt_int + 1'b1;
case (ADC_MEM_RATIO)
8: begin
adc_ddata[((ADC_DATA_WIDTH*8)-1):(ADC_DATA_WIDTH*7)] <= adc_wdata;
adc_ddata[((ADC_DATA_WIDTH*7)-1):(ADC_DATA_WIDTH*0)] <=
adc_ddata[((ADC_DATA_WIDTH*8)-1):(ADC_DATA_WIDTH*1)];
end
4: begin
adc_ddata[((ADC_DATA_WIDTH*4)-1):(ADC_DATA_WIDTH*3)] <= adc_wdata;
adc_ddata[((ADC_DATA_WIDTH*3)-1):(ADC_DATA_WIDTH*0)] <=
adc_ddata[((ADC_DATA_WIDTH*4)-1):(ADC_DATA_WIDTH*1)];
end
2: begin
adc_ddata[((ADC_DATA_WIDTH*2)-1):(ADC_DATA_WIDTH*1)] <= adc_wdata;
adc_ddata[((ADC_DATA_WIDTH*1)-1):(ADC_DATA_WIDTH*0)] <=
adc_ddata[((ADC_DATA_WIDTH*2)-1):(ADC_DATA_WIDTH*1)];
end
1: begin
adc_ddata <= adc_wdata;
end
default: begin
adc_ddata <= 'd0;
end
endcase
end
end
end
// instantiations
up_xfer_status #(
.DATA_WIDTH(4)
) i_xfer_status (
.up_rstn (~adc_rst),
.up_clk (adc_clk),
.up_data_status (adc_xfer_status_s),
.d_rst (axi_drst),
.d_clk (axi_clk),
.d_data_status (axi_xfer_status));
endmodule
adi_library/xilinx/axi_adcfifo/axi_adcfifo_constr.xdc
+34
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###############################################################################
## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_property ASYNC_REG TRUE \
[get_cells -hier *axi_waddr_m1_reg*] \
[get_cells -hier *axi_waddr_m2_reg*] \
[get_cells -hier *adc_xfer_req_m_reg[0]*] \
[get_cells -hier *axi_xfer_req_m_reg[0]*]
set_false_path -from [get_cells -hier -filter {name =~ *dma_* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *axi_*_m* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *axi_* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *dma_*_m* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *adc_* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *axi_*_m* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *axi_* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *adc_*_m* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *up_* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *d_xfer_* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *adc_rel_waddr* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *axi_rel_waddr* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *axi_waddr_rel_reg* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *dma_waddr_rel_reg* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *dma_raddr_rel_reg* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *axi_raddr_rel_reg* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *adc_xfer_req_m_reg[0]* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *axi_xfer_req_m_reg[0]* && IS_SEQUENTIAL}]
adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v
+227
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@@ -0,0 +1,227 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_adcfifo_dma #(
parameter AXI_DATA_WIDTH = 512,
parameter DMA_DATA_WIDTH = 64,
parameter DMA_READY_ENABLE = 1
) (
input axi_clk,
input axi_drst,
input axi_dvalid,
input [AXI_DATA_WIDTH-1:0] axi_ddata,
output reg axi_dready,
input [ 3:0] axi_xfer_status,
input dma_clk,
output dma_wr,
output [DMA_DATA_WIDTH-1:0] dma_wdata,
input dma_wready,
input dma_xfer_req,
output [ 3:0] dma_xfer_status
);
localparam DMA_MEM_RATIO = AXI_DATA_WIDTH/DMA_DATA_WIDTH;
localparam DMA_ADDRESS_WIDTH = 8;
localparam AXI_ADDRESS_WIDTH = (DMA_MEM_RATIO == 2) ? (DMA_ADDRESS_WIDTH - 1) :
((DMA_MEM_RATIO == 4) ? (DMA_ADDRESS_WIDTH - 2) : (DMA_ADDRESS_WIDTH - 3));
// internal registers
reg [AXI_ADDRESS_WIDTH-1:0] axi_waddr = 'd0;
reg [ 2:0] axi_waddr_rel_count = 'd0;
reg axi_waddr_rel_t = 'd0;
reg [AXI_ADDRESS_WIDTH-1:0] axi_waddr_rel = 'd0;
reg [ 2:0] axi_raddr_rel_t_m = 'd0;
reg [DMA_ADDRESS_WIDTH-1:0] axi_raddr_rel = 'd0;
reg [DMA_ADDRESS_WIDTH-1:0] axi_addr_diff = 'd0;
reg dma_rst = 'd0;
reg [ 2:0] dma_waddr_rel_t_m = 'd0;
reg [AXI_ADDRESS_WIDTH-1:0] dma_waddr_rel = 'd0;
reg dma_rd = 'd0;
reg dma_rd_d = 'd0;
reg [DMA_DATA_WIDTH-1:0] dma_rdata_d = 'd0;
reg [DMA_ADDRESS_WIDTH-1:0] dma_raddr = 'd0;
reg [ 2:0] dma_raddr_rel_count = 'd0;
reg dma_raddr_rel_t = 'd0;
reg [DMA_ADDRESS_WIDTH-1:0] dma_raddr_rel = 'd0;
// internal signals
wire [DMA_ADDRESS_WIDTH:0] axi_addr_diff_s;
wire axi_raddr_rel_t_s;
wire [DMA_ADDRESS_WIDTH-1:0] axi_waddr_s;
wire dma_waddr_rel_t_s;
wire [DMA_ADDRESS_WIDTH-1:0] dma_waddr_rel_s;
wire dma_wready_s;
wire dma_rd_s;
wire [DMA_DATA_WIDTH-1:0] dma_rdata_s;
// write interface
always @(posedge axi_clk) begin
if (axi_drst == 1'b1) begin
axi_waddr <= 'd0;
axi_waddr_rel_count <= 'd0;
axi_waddr_rel_t <= 'd0;
axi_waddr_rel <= 'd0;
end else begin
if (axi_dvalid == 1'b1) begin
axi_waddr <= axi_waddr + 1'b1;
end
axi_waddr_rel_count <= axi_waddr_rel_count + 1'b1;
if (axi_waddr_rel_count == 3'd7) begin
axi_waddr_rel_t <= ~axi_waddr_rel_t;
axi_waddr_rel <= axi_waddr;
end
end
end
assign axi_addr_diff_s = {1'b1, axi_waddr_s} - axi_raddr_rel;
assign axi_raddr_rel_t_s = axi_raddr_rel_t_m[2] ^ axi_raddr_rel_t_m[1];
assign axi_waddr_s = (DMA_MEM_RATIO == 2) ? {axi_waddr, 1'd0} :
((DMA_MEM_RATIO == 4) ? {axi_waddr, 2'd0} : {axi_waddr, 3'd0});
always @(posedge axi_clk) begin
if (axi_drst == 1'b1) begin
axi_raddr_rel_t_m <= 'd0;
axi_raddr_rel <= 'd0;
axi_addr_diff <= 'd0;
axi_dready <= 'd0;
end else begin
axi_raddr_rel_t_m <= {axi_raddr_rel_t_m[1:0], dma_raddr_rel_t};
if (axi_raddr_rel_t_s == 1'b1) begin
axi_raddr_rel <= dma_raddr_rel;
end
axi_addr_diff <= axi_addr_diff_s[DMA_ADDRESS_WIDTH-1:0];
if (axi_addr_diff >= 180) begin
axi_dready <= 1'b0;
end else if (axi_addr_diff <= 8) begin
axi_dready <= 1'b1;
end
end
end
// read interface
assign dma_waddr_rel_t_s = dma_waddr_rel_t_m[2] ^ dma_waddr_rel_t_m[1];
assign dma_waddr_rel_s = (DMA_MEM_RATIO == 2) ? {dma_waddr_rel, 1'd0} :
((DMA_MEM_RATIO == 4) ? {dma_waddr_rel, 2'd0} : {dma_waddr_rel, 3'd0});
always @(posedge dma_clk) begin
if (dma_xfer_req == 1'b0) begin
dma_rst <= 1'b1;
dma_waddr_rel_t_m <= 'd0;
dma_waddr_rel <= 'd0;
end else begin
dma_rst <= 1'b0;
dma_waddr_rel_t_m <= {dma_waddr_rel_t_m[1:0], axi_waddr_rel_t};
if (dma_waddr_rel_t_s == 1'b1) begin
dma_waddr_rel <= axi_waddr_rel;
end
end
end
assign dma_wready_s = (DMA_READY_ENABLE == 0) ? 1'b1 : dma_wready;
assign dma_rd_s = (dma_raddr == dma_waddr_rel_s) ? 1'b0 : dma_wready_s;
always @(posedge dma_clk) begin
if (dma_xfer_req == 1'b0) begin
dma_rd <= 'd0;
dma_rd_d <= 'd0;
dma_rdata_d <= 'd0;
dma_raddr <= 'd0;
dma_raddr_rel_count <= 'd0;
dma_raddr_rel_t <= 'd0;
dma_raddr_rel <= 'd0;
end else begin
dma_rd <= dma_rd_s;
dma_rd_d <= dma_rd;
dma_rdata_d <= dma_rdata_s;
if (dma_rd_s == 1'b1) begin
dma_raddr <= dma_raddr + 1'b1;
end
dma_raddr_rel_count <= dma_raddr_rel_count + 1'b1;
if (dma_raddr_rel_count == 3'd7) begin
dma_raddr_rel_t <= ~dma_raddr_rel_t;
dma_raddr_rel <= dma_raddr;
end
end
end
// instantiations
ad_mem_asym #(
.A_ADDRESS_WIDTH (AXI_ADDRESS_WIDTH),
.A_DATA_WIDTH (AXI_DATA_WIDTH),
.B_ADDRESS_WIDTH (DMA_ADDRESS_WIDTH),
.B_DATA_WIDTH (DMA_DATA_WIDTH)
) i_mem_asym (
.clka (axi_clk),
.wea (axi_dvalid),
.addra (axi_waddr),
.dina (axi_ddata),
.clkb (dma_clk),
.reb (1'b1),
.addrb (dma_raddr),
.doutb (dma_rdata_s));
ad_axis_inf_rx #(
.DATA_WIDTH(DMA_DATA_WIDTH)
) i_axis_inf (
.clk (dma_clk),
.rst (dma_rst),
.valid (dma_rd_d),
.last (1'd0),
.data (dma_rdata_d),
.inf_valid (dma_wr),
.inf_last (),
.inf_data (dma_wdata),
.inf_ready (dma_wready));
up_xfer_status #(
.DATA_WIDTH(4)
) i_xfer_status (
.up_rstn (~dma_rst),
.up_clk (dma_clk),
.up_data_status (dma_xfer_status),
.d_rst (axi_drst),
.d_clk (axi_clk),
.d_data_status (axi_xfer_status));
endmodule
adi_library/xilinx/axi_adcfifo/axi_adcfifo_ip.tcl
+91
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###############################################################################
## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# ip
source ../../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
adi_ip_create axi_adcfifo
adi_ip_files axi_adcfifo [list \
"$ad_hdl_dir/library/common/ad_mem.v" \
"$ad_hdl_dir/library/common/ad_mem_asym.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/ad_axis_inf_rx.v" \
"axi_adcfifo_adc.v" \
"axi_adcfifo_dma.v" \
"axi_adcfifo_wr.v" \
"axi_adcfifo_rd.v" \
"axi_adcfifo.v" \
"axi_adcfifo_constr.xdc" ]
adi_ip_properties_lite axi_adcfifo
ipx::infer_bus_interface {\
axi_awvalid \
axi_awid \
axi_awburst \
axi_awlock \
axi_awcache \
axi_awprot \
axi_awqos \
axi_awuser \
axi_awlen \
axi_awsize \
axi_awaddr \
axi_awready \
axi_wvalid \
axi_wdata \
axi_wstrb \
axi_wlast \
axi_wuser \
axi_wready \
axi_bvalid \
axi_bid \
axi_bresp \
axi_buser \
axi_bready \
axi_arvalid \
axi_arid \
axi_arburst \
axi_arlock \
axi_arcache \
axi_arprot \
axi_arqos \
axi_aruser \
axi_arlen \
axi_arsize \
axi_araddr \
axi_arready \
axi_rvalid \
axi_rid \
axi_ruser \
axi_rresp \
axi_rlast \
axi_rdata \
axi_rready} \
xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface axi_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface axi_resetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces axi_clk \
-of_objects [ipx::current_core]]
set_property value axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \
-of_objects [ipx::get_bus_interfaces axi_clk \
-of_objects [ipx::current_core]]]
ipx::add_address_space axi [ipx::current_core]
set_property master_address_space_ref axi [ipx::get_bus_interfaces axi \
-of_objects [ipx::current_core]]
set_property range 4294967296 [ipx::get_address_spaces axi \
-of_objects [ipx::current_core]]
set_property width 512 [ipx::get_address_spaces axi \
-of_objects [ipx::current_core]]
ipx::infer_bus_interface dma_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::save_core [ipx::current_core]
adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v
+201
View File
@@ -0,0 +1,201 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_adcfifo_rd #(
parameter AXI_DATA_WIDTH = 512,
parameter AXI_SIZE = 2,
parameter AXI_LENGTH = 16,
parameter AXI_ADDRESS = 32'h00000000,
parameter AXI_ADDRESS_LIMIT = 32'h00000000
) (
// request and synchronization
input dma_xfer_req,
// read interface
input axi_rd_req,
input [ 31:0] axi_rd_addr,
// axi interface
input axi_clk,
input axi_resetn,
output reg axi_arvalid,
output [ 3:0] axi_arid,
output [ 1:0] axi_arburst,
output axi_arlock,
output [ 3:0] axi_arcache,
output [ 2:0] axi_arprot,
output [ 3:0] axi_arqos,
output [ 3:0] axi_aruser,
output [ 7:0] axi_arlen,
output [ 2:0] axi_arsize,
output reg [ 31:0] axi_araddr,
input axi_arready,
input axi_rvalid,
input [ 3:0] axi_rid,
input [ 3:0] axi_ruser,
input [ 1:0] axi_rresp,
input axi_rlast,
input [AXI_DATA_WIDTH-1:0] axi_rdata,
output reg axi_rready,
// axi status
output reg axi_rerror,
// fifo interface
output reg axi_drst,
output reg axi_dvalid,
output reg [AXI_DATA_WIDTH-1:0] axi_ddata,
input axi_dready
);
localparam AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8;
localparam AXI_AWINCR = AXI_LENGTH * AXI_BYTE_WIDTH;
localparam BUF_THRESHOLD_LO = 6'd3;
localparam BUF_THRESHOLD_HI = 6'd60;
// internal registers
reg [ 31:0] axi_rd_addr_h = 'd0;
reg axi_rd = 'd0;
reg axi_rd_active = 'd0;
reg [ 2:0] axi_xfer_req_m = 'd0;
reg axi_xfer_init = 'd0;
reg axi_xfer_enable = 'd0;
// internal signals
wire axi_ready_s;
// read is way too slow- buffer mode
assign axi_ready_s = (~axi_arvalid | axi_arready) & axi_dready;
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_rd_addr_h <= 'd0;
axi_rd <= 'd0;
axi_rd_active <= 'd0;
axi_xfer_req_m <= 'd0;
axi_xfer_init <= 'd0;
axi_xfer_enable <= 'd0;
end else begin
if (axi_xfer_init == 1'b1) begin
axi_rd_addr_h <= AXI_ADDRESS;
end else if (axi_rd_req == 1'b1) begin
axi_rd_addr_h <= axi_rd_addr;
end
if (axi_rd_active == 1'b1) begin
axi_rd <= 1'b0;
if ((axi_rvalid == 1'b1) && (axi_rlast == 1'b1)) begin
axi_rd_active <= 1'b0;
end
end else if ((axi_ready_s == 1'b1) && (axi_araddr < axi_rd_addr_h)) begin
axi_rd <= axi_xfer_enable;
axi_rd_active <= axi_xfer_enable;
end
axi_xfer_req_m <= {axi_xfer_req_m[1:0], dma_xfer_req};
axi_xfer_init <= axi_xfer_req_m[1] & ~axi_xfer_req_m[2];
axi_xfer_enable <= axi_xfer_req_m[2];
end
end
// address channel
assign axi_arid = 4'b0000;
assign axi_arburst = 2'b01;
assign axi_arlock = 1'b0;
assign axi_arcache = 4'b0010;
assign axi_arprot = 3'b000;
assign axi_arqos = 4'b0000;
assign axi_aruser = 4'b0001;
assign axi_arlen = AXI_LENGTH - 1;
assign axi_arsize = AXI_SIZE;
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_arvalid <= 'd0;
axi_araddr <= 'd0;
end else begin
if (axi_arvalid == 1'b1) begin
if (axi_arready == 1'b1) begin
axi_arvalid <= 1'b0;
end
end else begin
if (axi_rd == 1'b1) begin
axi_arvalid <= 1'b1;
end
end
if (axi_xfer_init == 1'b1) begin
axi_araddr <= AXI_ADDRESS;
end else if ((axi_arvalid == 1'b1) && (axi_arready == 1'b1)) begin
axi_araddr <= axi_araddr + AXI_AWINCR;
end
end
end
// read data channel
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_drst <= 'd1;
axi_dvalid <= 'd0;
axi_ddata <= 'd0;
axi_rready <= 'd0;
end else begin
axi_drst <= ~axi_xfer_req_m[1];
axi_dvalid <= axi_rvalid;
axi_ddata <= axi_rdata;
axi_rready <= 1'b1;
end
end
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_rerror <= 'd0;
end else begin
axi_rerror <= axi_rvalid & axi_rresp[1];
end
end
endmodule
adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v
+422
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@@ -0,0 +1,422 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_adcfifo_wr #(
parameter AXI_DATA_WIDTH = 512,
parameter AXI_SIZE = 2,
parameter AXI_LENGTH = 16,
parameter AXI_ADDRESS = 32'h00000000,
parameter AXI_ADDRESS_LIMIT = 32'h00000000
) (
// request and synchronization
input dma_xfer_req,
// read interface
output reg axi_rd_req,
output reg [ 31:0] axi_rd_addr,
// fifo interface
input adc_rst,
input adc_clk,
input adc_wr,
input [AXI_DATA_WIDTH-1:0] adc_wdata,
// axi interface
input axi_clk,
input axi_resetn,
output reg axi_awvalid,
output [ 3:0] axi_awid,
output [ 1:0] axi_awburst,
output axi_awlock,
output [ 3:0] axi_awcache,
output [ 2:0] axi_awprot,
output [ 3:0] axi_awqos,
output [ 3:0] axi_awuser,
output [ 7:0] axi_awlen,
output [ 2:0] axi_awsize,
output reg [ 31:0] axi_awaddr,
input axi_awready,
output axi_wvalid,
output [AXI_DATA_WIDTH-1:0] axi_wdata,
output [AXI_BYTE_WIDTH-1:0] axi_wstrb,
output axi_wlast,
output [ 3:0] axi_wuser,
input axi_wready,
input axi_bvalid,
input [ 3:0] axi_bid,
input [ 1:0] axi_bresp,
input [ 3:0] axi_buser,
output axi_bready,
// axi status
output reg axi_dwovf,
output reg axi_dwunf,
output reg axi_werror
);
localparam AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8;
localparam AXI_AWINCR = AXI_LENGTH * AXI_BYTE_WIDTH;
localparam BUF_THRESHOLD_LO = 8'd6;
localparam BUF_THRESHOLD_HI = 8'd250;
// internal registers
reg [ 2:0] adc_xfer_req_m = 'd0;
reg adc_xfer_init = 'd0;
reg adc_xfer_limit = 'd0;
reg adc_xfer_enable = 'd0;
reg [ 31:0] adc_xfer_addr = 'd0;
reg [ 7:0] adc_waddr = 'd0;
reg [ 7:0] adc_waddr_g = 'd0;
reg adc_rel_enable = 'd0;
reg adc_rel_toggle = 'd0;
reg [ 7:0] adc_rel_waddr = 'd0;
reg [ 2:0] axi_rel_toggle_m = 'd0;
reg [ 7:0] axi_rel_waddr = 'd0;
reg [ 7:0] axi_waddr_m1 = 'd0;
reg [ 7:0] axi_waddr_m2 = 'd0;
reg [ 7:0] axi_waddr = 'd0;
reg [ 7:0] axi_addr_diff = 'd0;
reg axi_almost_full = 'd0;
reg axi_almost_empty = 'd0;
reg [ 2:0] axi_xfer_req_m = 'd0;
reg axi_xfer_init = 'd0;
reg [ 7:0] axi_raddr = 'd0;
reg axi_rd = 'd0;
reg axi_rlast = 'd0;
reg axi_rd_d = 'd0;
reg axi_rlast_d = 'd0;
reg [AXI_DATA_WIDTH-1:0] axi_rdata_d = 'd0;
reg axi_reset = 'd0;
// internal signals
wire axi_rel_toggle_s;
wire [ 8:0] axi_addr_diff_s;
wire axi_wready_s;
wire axi_rd_s;
wire axi_req_s;
wire axi_rlast_s;
wire [AXI_DATA_WIDTH-1:0] axi_rdata_s;
// binary to grey conversion
function [7:0] b2g;
input [7:0] b;
reg [7:0] g;
begin
g[7] = b[7];
g[6] = b[7] ^ b[6];
g[5] = b[6] ^ b[5];
g[4] = b[5] ^ b[4];
g[3] = b[4] ^ b[3];
g[2] = b[3] ^ b[2];
g[1] = b[2] ^ b[1];
g[0] = b[1] ^ b[0];
b2g = g;
end
endfunction
// grey to binary conversion
function [7:0] g2b;
input [7:0] g;
reg [7:0] b;
begin
b[7] = g[7];
b[6] = b[7] ^ g[6];
b[5] = b[6] ^ g[5];
b[4] = b[5] ^ g[4];
b[3] = b[4] ^ g[3];
b[2] = b[3] ^ g[2];
b[1] = b[2] ^ g[1];
b[0] = b[1] ^ g[0];
g2b = b;
end
endfunction
// fifo interface
always @(posedge adc_clk) begin
if (adc_rst == 1'b1) begin
adc_waddr <= 'd0;
adc_waddr_g <= 'd0;
adc_xfer_req_m <= 'd0;
adc_xfer_init <= 'd0;
adc_xfer_limit <= 'd0;
adc_xfer_enable <= 'd0;
adc_xfer_addr <= 'd0;
adc_rel_enable <= 'd0;
adc_rel_toggle <= 'd0;
adc_rel_waddr <= 'd0;
end else begin
if ((adc_wr == 1'b1) && (adc_xfer_enable == 1'b1)) begin
adc_waddr <= adc_waddr + 1'b1;
end
adc_waddr_g <= b2g(adc_waddr);
adc_xfer_req_m <= {adc_xfer_req_m[1:0], dma_xfer_req};
adc_xfer_init <= adc_xfer_req_m[1] & ~adc_xfer_req_m[2];
if (adc_xfer_init == 1'b1) begin
adc_xfer_limit <= 1'd1;
end else if ((adc_xfer_addr >= AXI_ADDRESS_LIMIT) || (adc_xfer_enable == 1'b0)) begin
adc_xfer_limit <= 1'd0;
end
if (adc_xfer_init == 1'b1) begin
adc_xfer_enable <= 1'b1;
adc_xfer_addr <= AXI_ADDRESS;
end else if ((adc_waddr[1:0] == 2'h3) && (adc_wr == 1'b1)) begin
adc_xfer_enable <= adc_xfer_req_m[2] & adc_xfer_limit;
adc_xfer_addr <= adc_xfer_addr + AXI_AWINCR;
end
if (adc_waddr[1:0] == 2'h3) begin
adc_rel_enable <= adc_wr;
end else begin
adc_rel_enable <= 1'd0;
end
if (adc_rel_enable == 1'b1) begin
adc_rel_toggle <= ~adc_rel_toggle;
adc_rel_waddr <= adc_waddr;
end
end
end
// fifo signals on axi side
assign axi_rel_toggle_s = axi_rel_toggle_m[2] ^ axi_rel_toggle_m[1];
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_rel_toggle_m <= 'd0;
axi_rel_waddr <= 'd0;
axi_waddr_m1 <= 'd0;
axi_waddr_m2 <= 'd0;
axi_waddr <= 'd0;
end else begin
axi_rel_toggle_m <= {axi_rel_toggle_m[1:0], adc_rel_toggle};
if (axi_rel_toggle_s == 1'b1) begin
axi_rel_waddr <= adc_rel_waddr;
end
axi_waddr_m1 <= adc_waddr_g;
axi_waddr_m2 <= axi_waddr_m1;
axi_waddr <= g2b(axi_waddr_m2);
end
end
// overflow (no underflow possible)
assign axi_addr_diff_s = {1'b1, axi_waddr} - axi_raddr;
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_addr_diff <= 'd0;
axi_almost_full <= 'd0;
axi_dwunf <= 'd0;
axi_almost_empty <= 'd0;
axi_dwovf <= 'd0;
end else begin
axi_addr_diff <= axi_addr_diff_s[7:0];
if (axi_addr_diff > BUF_THRESHOLD_HI) begin
axi_almost_full <= 1'b1;
axi_dwunf <= axi_almost_empty;
end else begin
axi_almost_full <= 1'b0;
axi_dwunf <= 1'b0;
end
if (axi_addr_diff < BUF_THRESHOLD_LO) begin
axi_almost_empty <= 1'b1;
axi_dwovf <= axi_almost_full;
end else begin
axi_almost_empty <= 1'b0;
axi_dwovf <= 1'b0;
end
end
end
// transfer request is required to keep things in sync
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_xfer_req_m <= 'd0;
axi_xfer_init <= 'd0;
end else begin
axi_xfer_req_m <= {axi_xfer_req_m[1:0], dma_xfer_req};
axi_xfer_init <= axi_xfer_req_m[1] & ~axi_xfer_req_m[2];
end
end
// read is initiated if xfer enabled
assign axi_wready_s = ~axi_wvalid | axi_wready;
assign axi_rd_s = (axi_rel_waddr == axi_raddr) ? 1'b0 : axi_wready_s;
assign axi_req_s = (axi_raddr[1:0] == 2'h0) ? axi_rd_s : 1'b0;
assign axi_rlast_s = (axi_raddr[1:0] == 2'h3) ? axi_rd_s : 1'b0;
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_raddr <= 'd0;
axi_rd <= 'd0;
axi_rlast <= 'd0;
axi_rd_d <= 'd0;
axi_rlast_d <= 'd0;
axi_rdata_d <= 'd0;
end else begin
if (axi_rd_s == 1'b1) begin
axi_raddr <= axi_raddr + 1'b1;
end
axi_rd <= axi_rd_s;
axi_rlast <= axi_rlast_s;
axi_rd_d <= axi_rd;
axi_rlast_d <= axi_rlast;
axi_rdata_d <= axi_rdata_s;
end
end
// send read request for every burst about to be completed
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_rd_req <= 'd0;
axi_rd_addr <= 'd0;
end else begin
axi_rd_req <= axi_rlast_s;
if (axi_xfer_init == 1'b1) begin
axi_rd_addr <= AXI_ADDRESS;
end else if (axi_rd_req == 1'b1) begin
axi_rd_addr <= axi_rd_addr + AXI_AWINCR;
end
end
end
// address channel
assign axi_awid = 4'b0000;
assign axi_awburst = 2'b01;
assign axi_awlock = 1'b0;
assign axi_awcache = 4'b0010;
assign axi_awprot = 3'b000;
assign axi_awqos = 4'b0000;
assign axi_awuser = 4'b0001;
assign axi_awlen = AXI_LENGTH - 1;
assign axi_awsize = AXI_SIZE;
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_awvalid <= 'd0;
axi_awaddr <= 'd0;
end else begin
if (axi_awvalid == 1'b1) begin
if (axi_awready == 1'b1) begin
axi_awvalid <= 1'b0;
end
end else begin
if (axi_req_s == 1'b1) begin
axi_awvalid <= 1'b1;
end
end
if (axi_xfer_init == 1'b1) begin
axi_awaddr <= AXI_ADDRESS;
end else if ((axi_awvalid == 1'b1) && (axi_awready == 1'b1)) begin
axi_awaddr <= axi_awaddr + AXI_AWINCR;
end
end
end
// write channel
assign axi_wstrb = {AXI_BYTE_WIDTH{1'b1}};
assign axi_wuser = 4'b0000;
// response channel
assign axi_bready = 1'b1;
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_werror <= 'd0;
end else begin
axi_werror <= axi_bvalid & axi_bready & axi_bresp[1];
end
end
// fifo needs a reset
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_reset <= 1'b1;
end else begin
axi_reset <= 1'b0;
end
end
// interface handler
ad_axis_inf_rx #(
.DATA_WIDTH(AXI_DATA_WIDTH)
) i_axis_inf (
.clk (axi_clk),
.rst (axi_reset),
.valid (axi_rd_d),
.last (axi_rlast_d),
.data (axi_rdata_d),
.inf_valid (axi_wvalid),
.inf_last (axi_wlast),
.inf_data (axi_wdata),
.inf_ready (axi_wready));
// buffer
ad_mem #(
.DATA_WIDTH(AXI_DATA_WIDTH),
.ADDRESS_WIDTH(8)
) i_mem (
.clka (adc_clk),
.wea (adc_wr),
.addra (adc_waddr),
.dina (adc_wdata),
.clkb (axi_clk),
.reb (1'b1),
.addrb (axi_raddr),
.doutb (axi_rdata_s));
endmodule
adi_library/xilinx/axi_adcfifo/component.xml
+1632
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File diff suppressed because it is too large Load Diff
adi_library/xilinx/axi_adcfifo/xgui/axi_adcfifo_v1_0.tcl
+130
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@@ -0,0 +1,130 @@
# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
ipgui::add_param $IPINST -name "ADC_DATA_WIDTH" -parent ${Page_0}
ipgui::add_param $IPINST -name "AXI_ADDRESS" -parent ${Page_0}
ipgui::add_param $IPINST -name "AXI_ADDRESS_LIMIT" -parent ${Page_0}
ipgui::add_param $IPINST -name "AXI_DATA_WIDTH" -parent ${Page_0}
ipgui::add_param $IPINST -name "AXI_LENGTH" -parent ${Page_0}
ipgui::add_param $IPINST -name "AXI_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "DMA_DATA_WIDTH" -parent ${Page_0}
ipgui::add_param $IPINST -name "DMA_READY_ENABLE" -parent ${Page_0}
}
proc update_PARAM_VALUE.ADC_DATA_WIDTH { PARAM_VALUE.ADC_DATA_WIDTH } {
# Procedure called to update ADC_DATA_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.ADC_DATA_WIDTH { PARAM_VALUE.ADC_DATA_WIDTH } {
# Procedure called to validate ADC_DATA_WIDTH
return true
}
proc update_PARAM_VALUE.AXI_ADDRESS { PARAM_VALUE.AXI_ADDRESS } {
# Procedure called to update AXI_ADDRESS when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.AXI_ADDRESS { PARAM_VALUE.AXI_ADDRESS } {
# Procedure called to validate AXI_ADDRESS
return true
}
proc update_PARAM_VALUE.AXI_ADDRESS_LIMIT { PARAM_VALUE.AXI_ADDRESS_LIMIT } {
# Procedure called to update AXI_ADDRESS_LIMIT when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.AXI_ADDRESS_LIMIT { PARAM_VALUE.AXI_ADDRESS_LIMIT } {
# Procedure called to validate AXI_ADDRESS_LIMIT
return true
}
proc update_PARAM_VALUE.AXI_DATA_WIDTH { PARAM_VALUE.AXI_DATA_WIDTH } {
# Procedure called to update AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.AXI_DATA_WIDTH { PARAM_VALUE.AXI_DATA_WIDTH } {
# Procedure called to validate AXI_DATA_WIDTH
return true
}
proc update_PARAM_VALUE.AXI_LENGTH { PARAM_VALUE.AXI_LENGTH } {
# Procedure called to update AXI_LENGTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.AXI_LENGTH { PARAM_VALUE.AXI_LENGTH } {
# Procedure called to validate AXI_LENGTH
return true
}
proc update_PARAM_VALUE.AXI_SIZE { PARAM_VALUE.AXI_SIZE } {
# Procedure called to update AXI_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.AXI_SIZE { PARAM_VALUE.AXI_SIZE } {
# Procedure called to validate AXI_SIZE
return true
}
proc update_PARAM_VALUE.DMA_DATA_WIDTH { PARAM_VALUE.DMA_DATA_WIDTH } {
# Procedure called to update DMA_DATA_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.DMA_DATA_WIDTH { PARAM_VALUE.DMA_DATA_WIDTH } {
# Procedure called to validate DMA_DATA_WIDTH
return true
}
proc update_PARAM_VALUE.DMA_READY_ENABLE { PARAM_VALUE.DMA_READY_ENABLE } {
# Procedure called to update DMA_READY_ENABLE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.DMA_READY_ENABLE { PARAM_VALUE.DMA_READY_ENABLE } {
# Procedure called to validate DMA_READY_ENABLE
return true
}
proc update_MODELPARAM_VALUE.ADC_DATA_WIDTH { MODELPARAM_VALUE.ADC_DATA_WIDTH PARAM_VALUE.ADC_DATA_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.ADC_DATA_WIDTH}] ${MODELPARAM_VALUE.ADC_DATA_WIDTH}
}
proc update_MODELPARAM_VALUE.DMA_DATA_WIDTH { MODELPARAM_VALUE.DMA_DATA_WIDTH PARAM_VALUE.DMA_DATA_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.DMA_DATA_WIDTH}] ${MODELPARAM_VALUE.DMA_DATA_WIDTH}
}
proc update_MODELPARAM_VALUE.AXI_DATA_WIDTH { MODELPARAM_VALUE.AXI_DATA_WIDTH PARAM_VALUE.AXI_DATA_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.AXI_DATA_WIDTH}
}
proc update_MODELPARAM_VALUE.DMA_READY_ENABLE { MODELPARAM_VALUE.DMA_READY_ENABLE PARAM_VALUE.DMA_READY_ENABLE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.DMA_READY_ENABLE}] ${MODELPARAM_VALUE.DMA_READY_ENABLE}
}
proc update_MODELPARAM_VALUE.AXI_SIZE { MODELPARAM_VALUE.AXI_SIZE PARAM_VALUE.AXI_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.AXI_SIZE}] ${MODELPARAM_VALUE.AXI_SIZE}
}
proc update_MODELPARAM_VALUE.AXI_LENGTH { MODELPARAM_VALUE.AXI_LENGTH PARAM_VALUE.AXI_LENGTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.AXI_LENGTH}] ${MODELPARAM_VALUE.AXI_LENGTH}
}
proc update_MODELPARAM_VALUE.AXI_ADDRESS { MODELPARAM_VALUE.AXI_ADDRESS PARAM_VALUE.AXI_ADDRESS } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.AXI_ADDRESS}] ${MODELPARAM_VALUE.AXI_ADDRESS}
}
proc update_MODELPARAM_VALUE.AXI_ADDRESS_LIMIT { MODELPARAM_VALUE.AXI_ADDRESS_LIMIT PARAM_VALUE.AXI_ADDRESS_LIMIT } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.AXI_ADDRESS_LIMIT}] ${MODELPARAM_VALUE.AXI_ADDRESS_LIMIT}
}