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initial commit, add dds_par module

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josh
2024-01-15 09:36:08 +08:00
commit 315a673005
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adi_library/xilinx/axi_adxcvr/Makefile
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####################################################################################
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := axi_adxcvr
XILINX_DEPS += ../../common/up_axi.v
XILINX_DEPS += axi_adxcvr.v
XILINX_DEPS += axi_adxcvr_es.v
XILINX_DEPS += axi_adxcvr_ip.tcl
XILINX_DEPS += axi_adxcvr_mdrp.v
XILINX_DEPS += axi_adxcvr_mstatus.v
XILINX_DEPS += axi_adxcvr_up.v
XILINX_DEPS += ../../interfaces/if_xcvr_ch.xml
XILINX_DEPS += ../../interfaces/if_xcvr_ch_rtl.xml
XILINX_DEPS += ../../interfaces/if_xcvr_cm.xml
XILINX_DEPS += ../../interfaces/if_xcvr_cm_rtl.xml
XILINX_INTERFACE_DEPS += interfaces
include ../../scripts/library.mk
adi_library/xilinx/axi_adxcvr/axi_adxcvr.v
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adi_library/xilinx/axi_adxcvr/axi_adxcvr.xpr
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/xilinx/axi_adxcvr/axi_adxcvr.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
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<Option Name="Part" Val="xc7vx485tffg1157-1"/>
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<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
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<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
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<Option Name="SimulatorGccInstallDirVCS" Val=""/>
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<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorVersionXsim" Val="2023.2"/>
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
<Option Name="SimulatorVersionRiviera" Val="2022.10"/>
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
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<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
<Option Name="BoardPart" Val=""/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
<Option Name="IPRepoPath" Val="$PPRDIR/../../../library"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="EnableResourceEstimation" Val="FALSE"/>
<Option Name="SimCompileState" Val="TRUE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="0"/>
<Option Name="WTModelSimExportSim" Val="0"/>
<Option Name="WTQuestaExportSim" Val="0"/>
<Option Name="WTIesExportSim" Val="0"/>
<Option Name="WTVcsExportSim" Val="0"/>
<Option Name="WTRivieraExportSim" Val="0"/>
<Option Name="WTActivehdlExportSim" Val="0"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
<Option Name="XSimTraceLimit" Val="65536"/>
<Option Name="SimTypes" Val="rtl"/>
<Option Name="SimTypes" Val="bfm"/>
<Option Name="SimTypes" Val="tlm"/>
<Option Name="SimTypes" Val="tlm_dpi"/>
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
<Option Name="DcpsUptoDate" Val="TRUE"/>
<Option Name="ClassicSocBoot" Val="FALSE"/>
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
</Configuration>
<FileSets Version="1" Minor="32">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/axi_adxcvr_es.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/axi_adxcvr_mdrp.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/axi_adxcvr_mstatus.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/axi_adxcvr_up.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../common/up_axi.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/axi_adxcvr.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../scripts/adi_xilinx_device_info_enc.tcl">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/component.xml">
<FileInfo SFType="IPXACT"/>
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<FileInfo>
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<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="axi_adxcvr"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
<Filter Type="Constrs"/>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SelectedSimModel" Val="rtl"/>
<Option Name="PamDesignTestbench" Val=""/>
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
<Filter Type="Utils"/>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
</FileSets>
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<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
<Option Name="CompiledLib" Val="0"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="Xcelium">
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
</Simulator>
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="21">
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<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
</Runs>
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<Board/>
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<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
</Gadget>
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
</Gadget>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
</Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
</Project>
adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_adxcvr_es (
// up interface
input up_rstn,
input up_clk,
output up_es_enb,
output [11:0] up_es_addr,
output up_es_wr,
output [15:0] up_es_wdata,
input [15:0] up_es_rdata,
input up_es_ready,
input up_ch_lpm_dfe_n,
input up_es_req,
output up_es_ack,
input [ 4:0] up_es_pscale,
input [ 1:0] up_es_vrange,
input [ 7:0] up_es_vstep,
input [ 7:0] up_es_vmax,
input [ 7:0] up_es_vmin,
input [11:0] up_es_hmax,
input [11:0] up_es_hmin,
input [11:0] up_es_hstep,
input [31:0] up_es_saddr,
output up_es_status,
// axi interface
output up_axi_awvalid,
output [31:0] up_axi_awaddr,
output [ 2:0] up_axi_awprot,
input up_axi_awready,
output up_axi_wvalid,
output [31:0] up_axi_wdata,
output [ 3:0] up_axi_wstrb,
input up_axi_wready,
input up_axi_bvalid,
input [ 1:0] up_axi_bresp,
output up_axi_bready,
output up_axi_arvalid,
output [31:0] up_axi_araddr,
output [ 2:0] up_axi_arprot,
input up_axi_arready,
input up_axi_rvalid,
input [31:0] up_axi_rdata,
input [ 1:0] up_axi_rresp,
output up_axi_rready
);
// parameters
parameter integer XCVR_TYPE = 0;
parameter integer TX_OR_RX_N = 0;
// local parameters
localparam GTXE2 = 2;
localparam GTHE3 = 5;
localparam GTHE4 = 8;
localparam GTYE4 = 9;
// addresses
localparam [11:0] ES_DRP_CTRL_ADDR = (XCVR_TYPE == GTXE2) ? 12'h03d : (XCVR_TYPE == GTHE3) ? 12'h03c : 12'h03c;
localparam [11:0] ES_DRP_HOFFSET_ADDR = (XCVR_TYPE == GTXE2) ? 12'h03c : (XCVR_TYPE == GTHE3) ? 12'h04f : 12'h04f;
localparam [11:0] ES_DRP_VOFFSET_ADDR = (XCVR_TYPE == GTXE2) ? 12'h03b : (XCVR_TYPE == GTHE3) ? 12'h097 : 12'h097;
localparam [11:0] ES_DRP_STATUS_ADDR = (XCVR_TYPE == GTXE2) ? 12'h151 : (XCVR_TYPE == GTHE3) ? 12'h153 : 12'h253;
localparam [11:0] ES_DRP_SCNT_ADDR = (XCVR_TYPE == GTXE2) ? 12'h150 : (XCVR_TYPE == GTHE3) ? 12'h152 : 12'h252;
localparam [11:0] ES_DRP_ECNT_ADDR = (XCVR_TYPE == GTXE2) ? 12'h14f : (XCVR_TYPE == GTHE3) ? 12'h151 : 12'h251;
// fsm-states
localparam [ 4:0] ES_FSM_IDLE = 6'h00;
localparam [ 4:0] ES_FSM_HOFFSET_READ = 6'h01;
localparam [ 4:0] ES_FSM_HOFFSET_RRDY = 6'h02;
localparam [ 4:0] ES_FSM_HOFFSET_WRITE = 6'h03;
localparam [ 4:0] ES_FSM_HOFFSET_WRDY = 6'h04;
localparam [ 4:0] ES_FSM_VOFFSET_READ = 6'h05;
localparam [ 4:0] ES_FSM_VOFFSET_RRDY = 6'h06;
localparam [ 4:0] ES_FSM_VOFFSET_WRITE = 6'h07;
localparam [ 4:0] ES_FSM_VOFFSET_WRDY = 6'h08;
localparam [ 4:0] ES_FSM_CTRL_READ = 6'h09;
localparam [ 4:0] ES_FSM_CTRL_RRDY = 6'h0a;
localparam [ 4:0] ES_FSM_START_WRITE = 6'h0b;
localparam [ 4:0] ES_FSM_START_WRDY = 6'h0c;
localparam [ 4:0] ES_FSM_STATUS_READ = 6'h0d;
localparam [ 4:0] ES_FSM_STATUS_RRDY = 6'h0e;
localparam [ 4:0] ES_FSM_STOP_WRITE = 6'h0f;
localparam [ 4:0] ES_FSM_STOP_WRDY = 6'h10;
localparam [ 4:0] ES_FSM_SCNT_READ = 6'h11;
localparam [ 4:0] ES_FSM_SCNT_RRDY = 6'h12;
localparam [ 4:0] ES_FSM_ECNT_READ = 6'h13;
localparam [ 4:0] ES_FSM_ECNT_RRDY = 6'h14;
localparam [ 4:0] ES_FSM_AXI_WRITE = 6'h15;
localparam [ 4:0] ES_FSM_AXI_READY = 6'h16;
localparam [ 4:0] ES_FSM_UPDATE = 6'h17;
// internal registers
reg up_awvalid = 'd0;
reg [31:0] up_awaddr = 'd0;
reg up_wvalid = 'd0;
reg [31:0] up_wdata = 'd0;
reg up_status = 'd0;
reg up_ut = 'd0;
reg [31:0] up_daddr = 'd0;
reg [11:0] up_hindex = 'd0;
reg [ 7:0] up_vindex = 'd0;
reg [15:0] up_hdata = 'd0;
reg [15:0] up_vdata = 'd0;
reg [15:0] up_cdata = 'd0;
reg [15:0] up_sdata = 'd0;
reg [15:0] up_edata = 'd0;
reg up_req_d = 'd0;
reg up_ack = 'd0;
reg [ 4:0] up_fsm = 'd0;
reg up_enb = 'd0;
reg [11:0] up_addr = 'd0;
reg up_wr = 'd0;
reg [15:0] up_data = 'd0;
// internal signals
wire up_heos_s;
wire up_eos_s;
wire up_ut_s;
wire [ 7:0] up_vindex_m_s;
wire [ 7:0] up_vindex_n_s;
wire [ 7:0] up_vindex_s;
wire up_start_s;
// axi interface
generate
if (TX_OR_RX_N == 1) begin
assign up_axi_awvalid = 1'b0;
assign up_axi_awaddr = 32'd0;
assign up_axi_awprot = 3'd0;
assign up_axi_wvalid = 1'b0;
assign up_axi_wdata = 32'd0;
assign up_axi_wstrb = 4'hf;
assign up_axi_bready = 1'b1;
assign up_axi_arvalid = 1'b0;
assign up_axi_araddr = 32'd0;
assign up_axi_arprot = 3'd0;
assign up_axi_rready = 1'b1;
end else begin
assign up_axi_awvalid = up_awvalid;
assign up_axi_awaddr = up_awaddr;
assign up_axi_awprot = 3'd0;
assign up_axi_wvalid = up_wvalid;
assign up_axi_wdata = up_wdata;
assign up_axi_wstrb = 4'hf;
assign up_axi_bready = 1'b1;
assign up_axi_arvalid = 1'b0;
assign up_axi_araddr = 32'd0;
assign up_axi_arprot = 3'd0;
assign up_axi_rready = 1'b1;
end
endgenerate
// reconfig interface
generate
if (TX_OR_RX_N == 1) begin
assign up_es_ack = 1'b1;
assign up_es_enb = 1'b0;
assign up_es_addr = 12'd0;
assign up_es_wr = 1'd0;
assign up_es_wdata = 16'd0;
assign up_es_status = 1'd0;
end else begin
assign up_es_ack = up_ack;
assign up_es_enb = up_enb;
assign up_es_addr = up_addr;
assign up_es_wr = up_wr;
assign up_es_wdata = up_data;
assign up_es_status = up_status;
end
endgenerate
// axi write
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_awvalid <= 'b0;
up_awaddr <= 'd0;
up_wvalid <= 'b0;
up_wdata <= 'd0;
up_status <= 'd0;
end else begin
if ((up_awvalid == 1'b1) && (up_axi_awready == 1'b1)) begin
up_awvalid <= 1'b0;
up_awaddr <= 32'd0;
end else if (up_fsm == ES_FSM_AXI_WRITE) begin
up_awvalid <= 1'b1;
up_awaddr <= up_daddr;
end
if ((up_wvalid == 1'b1) && (up_axi_wready == 1'b1)) begin
up_wvalid <= 1'b0;
up_wdata <= 32'd0;
end else if (up_fsm == ES_FSM_AXI_WRITE) begin
up_wvalid <= 1'b1;
up_wdata <= {up_sdata, up_edata};
end
if (up_axi_bvalid == 1'b1) begin
up_status <= | up_axi_bresp;
end
end
end
// prescale, horizontal and vertical offsets
assign up_heos_s = (up_hindex == up_es_hmax) ? up_ut : 1'b0;
assign up_eos_s = (up_vindex == up_es_vmax) ? up_heos_s : 1'b0;
assign up_ut_s = up_ut & ~up_ch_lpm_dfe_n;
assign up_vindex_m_s = ~up_vindex + 1'b1;
assign up_vindex_n_s = {1'b1, up_vindex_m_s[6:0]};
assign up_vindex_s = (up_vindex[7] == 1'b1) ? up_vindex_n_s : up_vindex;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_ut <= 'd0;
up_daddr <= 'd0;
up_hindex <= 'd0;
up_vindex <= 'd0;
end else begin
if (up_fsm == ES_FSM_IDLE) begin
up_ut <= up_ch_lpm_dfe_n;
up_daddr <= up_es_saddr;
up_hindex <= up_es_hmin;
up_vindex <= up_es_vmin;
end else if (up_fsm == ES_FSM_UPDATE) begin
up_ut <= ~up_ut | up_ch_lpm_dfe_n;
up_daddr <= up_daddr + 3'd4;
if (up_heos_s == 1'b1) begin
up_hindex <= up_es_hmin;
end else if (up_ut == 1'b1) begin
up_hindex <= up_hindex + up_es_hstep;
end
if (up_heos_s == 1'b1) begin
up_vindex <= up_vindex + up_es_vstep;
end
end
end
end
// read-modify-write
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_hdata <= 'd0;
up_vdata <= 'd0;
up_cdata <= 'd0;
up_sdata <= 'd0;
up_edata <= 'd0;
end else begin
if ((up_fsm == ES_FSM_HOFFSET_RRDY) && (up_es_ready == 1'b1)) begin
up_hdata <= up_es_rdata;
end
if ((up_fsm == ES_FSM_VOFFSET_RRDY) && (up_es_ready == 1'b1)) begin
up_vdata <= up_es_rdata;
end
if ((up_fsm == ES_FSM_CTRL_RRDY) && (up_es_ready == 1'b1)) begin
up_cdata <= up_es_rdata;
end
if ((up_fsm == ES_FSM_SCNT_RRDY) && (up_es_ready == 1'b1)) begin
up_sdata <= up_es_rdata;
end
if ((up_fsm == ES_FSM_ECNT_RRDY) && (up_es_ready == 1'b1)) begin
up_edata <= up_es_rdata;
end
end
end
// request, start and ack
assign up_start_s = up_es_req & ~up_req_d;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_req_d <= 1'b0;
up_ack <= 1'b0;
end else begin
up_req_d <= up_es_req;
if (up_fsm == ES_FSM_UPDATE) begin
up_ack <= up_eos_s | ~up_es_req;
end else begin
up_ack <= 1'b0;
end
end
end
// es-fsm
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_fsm <= ES_FSM_IDLE;
end else begin
case (up_fsm)
ES_FSM_IDLE: begin
if (up_start_s == 1'b1) begin
up_fsm <= ES_FSM_HOFFSET_READ;
end else begin
up_fsm <= ES_FSM_IDLE;
end
end
ES_FSM_HOFFSET_READ: begin
up_fsm <= ES_FSM_HOFFSET_RRDY;
end
ES_FSM_HOFFSET_RRDY: begin
if (up_es_ready == 1'b1) begin
up_fsm <= ES_FSM_HOFFSET_WRITE;
end else begin
up_fsm <= ES_FSM_HOFFSET_RRDY;
end
end
ES_FSM_HOFFSET_WRITE: begin
up_fsm <= ES_FSM_HOFFSET_WRDY;
end
ES_FSM_HOFFSET_WRDY: begin
if (up_es_ready == 1'b1) begin
up_fsm <= ES_FSM_VOFFSET_READ;
end else begin
up_fsm <= ES_FSM_HOFFSET_WRDY;
end
end
ES_FSM_VOFFSET_READ: begin
up_fsm <= ES_FSM_VOFFSET_RRDY;
end
ES_FSM_VOFFSET_RRDY: begin
if (up_es_ready == 1'b1) begin
up_fsm <= ES_FSM_VOFFSET_WRITE;
end else begin
up_fsm <= ES_FSM_VOFFSET_RRDY;
end
end
ES_FSM_VOFFSET_WRITE: begin
up_fsm <= ES_FSM_VOFFSET_WRDY;
end
ES_FSM_VOFFSET_WRDY: begin
if (up_es_ready == 1'b1) begin
up_fsm <= ES_FSM_CTRL_READ;
end else begin
up_fsm <= ES_FSM_VOFFSET_WRDY;
end
end
ES_FSM_CTRL_READ: begin
up_fsm <= ES_FSM_CTRL_RRDY;
end
ES_FSM_CTRL_RRDY: begin
if (up_es_ready == 1'b1) begin
up_fsm <= ES_FSM_START_WRITE;
end else begin
up_fsm <= ES_FSM_CTRL_RRDY;
end
end
ES_FSM_START_WRITE: begin
up_fsm <= ES_FSM_START_WRDY;
end
ES_FSM_START_WRDY: begin
if (up_es_ready == 1'b1) begin
up_fsm <= ES_FSM_STATUS_READ;
end else begin
up_fsm <= ES_FSM_START_WRDY;
end
end
ES_FSM_STATUS_READ: begin
up_fsm <= ES_FSM_STATUS_RRDY;
end
ES_FSM_STATUS_RRDY: begin
if (up_es_ready == 1'b0) begin
up_fsm <= ES_FSM_STATUS_RRDY;
end else if (up_es_rdata[3:0] == 4'b0101) begin
up_fsm <= ES_FSM_STOP_WRITE;
end else begin
up_fsm <= ES_FSM_STATUS_READ;
end
end
ES_FSM_STOP_WRITE: begin
up_fsm <= ES_FSM_STOP_WRDY;
end
ES_FSM_STOP_WRDY: begin
if (up_es_ready == 1'b1) begin
up_fsm <= ES_FSM_SCNT_READ;
end else begin
up_fsm <= ES_FSM_STOP_WRDY;
end
end
ES_FSM_SCNT_READ: begin
up_fsm <= ES_FSM_SCNT_RRDY;
end
ES_FSM_SCNT_RRDY: begin
if (up_es_ready == 1'b1) begin
up_fsm <= ES_FSM_ECNT_READ;
end else begin
up_fsm <= ES_FSM_SCNT_RRDY;
end
end
ES_FSM_ECNT_READ: begin
up_fsm <= ES_FSM_ECNT_RRDY;
end
ES_FSM_ECNT_RRDY: begin
if (up_es_ready == 1'b1) begin
up_fsm <= ES_FSM_AXI_WRITE;
end else begin
up_fsm <= ES_FSM_ECNT_RRDY;
end
end
ES_FSM_AXI_WRITE: begin
up_fsm <= ES_FSM_AXI_READY;
end
ES_FSM_AXI_READY: begin
if (up_axi_bvalid == 1'b1) begin
up_fsm <= ES_FSM_UPDATE;
end else begin
up_fsm <= ES_FSM_AXI_READY;
end
end
ES_FSM_UPDATE: begin
if ((up_eos_s == 1'b1) || (up_es_req == 1'b0)) begin
up_fsm <= ES_FSM_IDLE;
end else if (up_ut == 1'b1) begin
up_fsm <= ES_FSM_HOFFSET_READ;
end else begin
up_fsm <= ES_FSM_VOFFSET_READ;
end
end
default: begin
up_fsm <= ES_FSM_IDLE;
end
endcase
end
end
// channel access
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_enb <= 'd0;
up_addr <= 'd0;
up_wr <= 'd0;
up_data <= 'd0;
end else begin
case (up_fsm)
ES_FSM_HOFFSET_READ: begin
up_enb <= 1'b1;
up_addr <= ES_DRP_HOFFSET_ADDR;
up_wr <= 1'b0;
up_data <= 16'h0000;
end
ES_FSM_HOFFSET_WRITE: begin
up_enb <= 1'b1;
up_addr <= ES_DRP_HOFFSET_ADDR;
up_wr <= 1'b1;
if (XCVR_TYPE != GTXE2) begin
up_data <= {up_hindex, up_hdata[3:0]};
end else begin
up_data <= {up_hdata[15:12], up_hindex};
end
end
ES_FSM_VOFFSET_READ: begin
up_enb <= 1'b1;
up_addr <= ES_DRP_VOFFSET_ADDR;
up_wr <= 1'b0;
up_data <= 16'h0000;
end
ES_FSM_VOFFSET_WRITE: begin
up_enb <= 1'b1;
up_addr <= ES_DRP_VOFFSET_ADDR;
up_wr <= 1'b1;
if (XCVR_TYPE != GTXE2) begin
up_data <= {up_vdata[15:11], up_vindex_s[7], up_ut_s, up_vindex_s[6:0], up_es_vrange};
end else begin
up_data <= {up_es_pscale, up_vdata[10:9], up_ut_s, up_vindex_s};
end
end
ES_FSM_CTRL_READ: begin
up_enb <= 1'b1;
up_addr <= ES_DRP_CTRL_ADDR;
up_wr <= 1'b0;
up_data <= 16'h0000;
end
ES_FSM_START_WRITE: begin
up_enb <= 1'b1;
up_addr <= ES_DRP_CTRL_ADDR;
up_wr <= 1'b1;
if (XCVR_TYPE != GTXE2) begin
up_data <= {6'd1, 2'b11, up_cdata[7:5], up_es_pscale};
end else begin
up_data <= {up_cdata[15:10], 2'b11, up_cdata[7:6], 6'd1};
end
end
ES_FSM_STATUS_READ: begin
up_enb <= 1'b1;
up_addr <= ES_DRP_STATUS_ADDR;
up_wr <= 1'b0;
up_data <= 16'h0000;
end
ES_FSM_STOP_WRITE: begin
up_enb <= 1'b1;
up_addr <= ES_DRP_CTRL_ADDR;
up_wr <= 1'b1;
if (XCVR_TYPE != GTXE2) begin
up_data <= {6'd0, 2'b11, up_cdata[7:5], up_es_pscale};
end else begin
up_data <= {up_cdata[15:10], 2'b11, up_cdata[7:6], 6'd0};
end
end
ES_FSM_SCNT_READ: begin
up_enb <= 1'b1;
up_addr <= ES_DRP_SCNT_ADDR;
up_wr <= 1'b0;
up_data <= 16'h0000;
end
ES_FSM_ECNT_READ: begin
up_enb <= 1'b1;
up_addr <= ES_DRP_ECNT_ADDR;
up_wr <= 1'b0;
up_data <= 16'h0000;
end
default: begin
up_enb <= 1'b0;
up_addr <= 9'h000;
up_wr <= 1'b0;
up_data <= 16'h0000;
end
endcase
end
end
endmodule
adi_library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl
+417
View File
@@ -0,0 +1,417 @@
###############################################################################
## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
## AUTO GENERATED BY axi_adxcvr.pl, DO NOT MODIFY!
source ../../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
adi_ip_create axi_adxcvr
adi_ip_files axi_adxcvr [list \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl" \
"axi_adxcvr_es.v" \
"axi_adxcvr_up.v" \
"axi_adxcvr_mdrp.v" \
"axi_adxcvr_mstatus.v" \
"axi_adxcvr.v" ]
adi_ip_properties axi_adxcvr
adi_ip_infer_mm_interfaces axi_adxcvr
adi_init_bd_tcl
adi_ip_bd axi_adxcvr "bd/bd.tcl"
set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_adxcvr} [ipx::current_core]
set cc [ipx::current_core]
# Arrange GUI page layout
set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
# Link layer mode
set p [ipgui::get_guiparamspec -name "LINK_MODE" -component $cc]
ipgui::move_param -component $cc -order 0 $p -parent $page0
set_property -dict [list \
"display_name" "Link Layer mode" \
"tooltip" "Link Layer mode" \
"widget" "comboBox" \
] $p
set_property -dict [list \
value_validation_type pairs \
value_validation_pairs {64B66B 2 8B10B 1} \
] [ipx::get_user_parameters $p -of_objects $cc]
set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects [ipx::current_core]]
set_property master_address_space_ref m_axi \
[ipx::get_bus_interfaces m_axi \
-of_objects [ipx::current_core]]
for {set n 0} {$n < 32} {incr n} {
if {($n%4) == 0} {
adi_if_infer_bus analog.com:interface:if_xcvr_cm master up_cm_${n} [list \
"enb up_cm_enb_${n} "\
"addr up_cm_addr_${n} "\
"wr up_cm_wr_${n} "\
"wdata up_cm_wdata_${n} "\
"rdata up_cm_rdata_${n} "\
"ready up_cm_ready_${n} "]
}
adi_if_infer_bus analog.com:interface:if_xcvr_cm master up_es_${n} [list \
"enb up_es_enb_${n} "\
"addr up_es_addr_${n} "\
"wr up_es_wr_${n} "\
"reset up_es_reset_${n} "\
"wdata up_es_wdata_${n} "\
"rdata up_es_rdata_${n} "\
"ready up_es_ready_${n} "]
adi_if_infer_bus analog.com:interface:if_xcvr_ch master up_ch_${n} [list \
"pll_locked up_ch_pll_locked_${n} "\
"rst up_ch_rst_${n} "\
"user_ready up_ch_user_ready_${n} "\
"rst_done up_ch_rst_done_${n} "\
"prbsforceerr up_ch_prbsforceerr_${n}"\
"prbssel up_ch_prbssel_${n} "\
"prbscntreset up_ch_prbscntreset_${n}"\
"prbserr up_ch_prbserr_${n} "\
"prbslocked up_ch_prbslocked_${n} "\
"bufstatus up_ch_bufstatus_${n} "\
"bufstatus_rst up_ch_bufstatus_rst_${n}"\
"lpm_dfe_n up_ch_lpm_dfe_n_${n} "\
"rate up_ch_rate_${n} "\
"sys_clk_sel up_ch_sys_clk_sel_${n} "\
"out_clk_sel up_ch_out_clk_sel_${n} "\
"tx_diffctrl up_ch_tx_diffctrl_${n} "\
"tx_postcursor up_ch_tx_postcursor_${n} "\
"tx_precursor up_ch_tx_precursor_${n} "\
"enb up_ch_enb_${n} "\
"addr up_ch_addr_${n} "\
"wr up_ch_wr_${n} "\
"wdata up_ch_wdata_${n} "\
"rdata up_ch_rdata_${n} "\
"ready up_ch_ready_${n} "]
}
ipx::infer_bus_interface up_pll_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::add_bus_parameter POLARITY [ipx::get_bus_interfaces up_pll_rst -of_objects [ipx::current_core]]
set_property VALUE ACTIVE_HIGH [ipx::get_bus_parameters POLARITY -of [ipx::get_bus_interfaces up_pll_rst]]
ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::associate_bus_interfaces -clock s_axi_aclk -reset up_pll_rst -remove [ipx::current_core]
set_property value s_axi:m_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \
-of_objects [ipx::get_bus_interfaces s_axi_aclk -of_objects [ipx::current_core]]]
set_property enablement_dependency \
{spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0} \
[ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 0))} \
[ipx::get_bus_interfaces up_es_0 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 0} \
[ipx::get_bus_interfaces up_ch_0 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 0))} \
[ipx::get_bus_interfaces up_cm_0 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 1))} \
[ipx::get_bus_interfaces up_es_1 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 1} \
[ipx::get_bus_interfaces up_ch_1 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 2))} \
[ipx::get_bus_interfaces up_es_2 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 2} \
[ipx::get_bus_interfaces up_ch_2 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 3))} \
[ipx::get_bus_interfaces up_es_3 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 3} \
[ipx::get_bus_interfaces up_ch_3 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 4))} \
[ipx::get_bus_interfaces up_es_4 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 4} \
[ipx::get_bus_interfaces up_ch_4 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 4))} \
[ipx::get_bus_interfaces up_cm_4 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 5))} \
[ipx::get_bus_interfaces up_es_5 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 5} \
[ipx::get_bus_interfaces up_ch_5 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 6))} \
[ipx::get_bus_interfaces up_es_6 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 6} \
[ipx::get_bus_interfaces up_ch_6 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 7))} \
[ipx::get_bus_interfaces up_es_7 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 7} \
[ipx::get_bus_interfaces up_ch_7 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 8))} \
[ipx::get_bus_interfaces up_es_8 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 8} \
[ipx::get_bus_interfaces up_ch_8 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 8))} \
[ipx::get_bus_interfaces up_cm_8 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 9))} \
[ipx::get_bus_interfaces up_es_9 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 9} \
[ipx::get_bus_interfaces up_ch_9 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 10))} \
[ipx::get_bus_interfaces up_es_10 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 10} \
[ipx::get_bus_interfaces up_ch_10 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 11))} \
[ipx::get_bus_interfaces up_es_11 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 11} \
[ipx::get_bus_interfaces up_ch_11 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 12))} \
[ipx::get_bus_interfaces up_es_12 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 12} \
[ipx::get_bus_interfaces up_ch_12 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 12))} \
[ipx::get_bus_interfaces up_cm_12 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 13))} \
[ipx::get_bus_interfaces up_es_13 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 13} \
[ipx::get_bus_interfaces up_ch_13 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 14))} \
[ipx::get_bus_interfaces up_es_14 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 14} \
[ipx::get_bus_interfaces up_ch_14 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 15))} \
[ipx::get_bus_interfaces up_es_15 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 15} \
[ipx::get_bus_interfaces up_ch_15 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 16))} \
[ipx::get_bus_interfaces up_es_16 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 16} \
[ipx::get_bus_interfaces up_ch_16 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 16))} \
[ipx::get_bus_interfaces up_cm_16 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 17))} \
[ipx::get_bus_interfaces up_es_17 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 17} \
[ipx::get_bus_interfaces up_ch_17 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 18))} \
[ipx::get_bus_interfaces up_es_18 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 18} \
[ipx::get_bus_interfaces up_ch_18 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 19))} \
[ipx::get_bus_interfaces up_es_19 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 19} \
[ipx::get_bus_interfaces up_ch_19 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 20))} \
[ipx::get_bus_interfaces up_es_20 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 20} \
[ipx::get_bus_interfaces up_ch_20 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 20))} \
[ipx::get_bus_interfaces up_cm_20 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 21))} \
[ipx::get_bus_interfaces up_es_21 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 21} \
[ipx::get_bus_interfaces up_ch_21 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 22))} \
[ipx::get_bus_interfaces up_es_22 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 22} \
[ipx::get_bus_interfaces up_ch_22 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 23))} \
[ipx::get_bus_interfaces up_es_23 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 23} \
[ipx::get_bus_interfaces up_ch_23 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 24))} \
[ipx::get_bus_interfaces up_es_24 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 24} \
[ipx::get_bus_interfaces up_ch_24 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 24))} \
[ipx::get_bus_interfaces up_cm_24 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 25))} \
[ipx::get_bus_interfaces up_es_25 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 25} \
[ipx::get_bus_interfaces up_ch_25 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 26))} \
[ipx::get_bus_interfaces up_es_26 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 26} \
[ipx::get_bus_interfaces up_ch_26 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 27))} \
[ipx::get_bus_interfaces up_es_27 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 27} \
[ipx::get_bus_interfaces up_ch_27 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 28))} \
[ipx::get_bus_interfaces up_es_28 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 28} \
[ipx::get_bus_interfaces up_ch_28 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 28))} \
[ipx::get_bus_interfaces up_cm_28 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 29))} \
[ipx::get_bus_interfaces up_es_29 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 29} \
[ipx::get_bus_interfaces up_ch_29 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 30))} \
[ipx::get_bus_interfaces up_es_30 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 30} \
[ipx::get_bus_interfaces up_ch_30 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 31))} \
[ipx::get_bus_interfaces up_es_31 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 31} \
[ipx::get_bus_interfaces up_ch_31 -of_objects [ipx::current_core]]
adi_add_auto_fpga_spec_params
ipx::create_xgui_files [ipx::current_core]
ipx::save_core [ipx::current_core]
adi_library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v
+159
View File
@@ -0,0 +1,159 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ps
module axi_adxcvr_mdrp (
input up_rstn,
input up_clk,
input [ 7:0] up_sel,
input up_enb,
output up_enb_out,
input [15:0] up_rdata_in,
input up_ready_in,
input [15:0] up_rdata,
input up_ready,
output [15:0] up_rdata_out,
output up_ready_out
);
// parameters
parameter integer XCVR_ID = 0;
parameter integer NUM_OF_LANES = 8;
// internal registers
reg [15:0] up_rdata_int = 'd0;
reg up_ready_int = 'd0;
reg up_ready_mi = 'd0;
reg [15:0] up_rdata_i = 'd0;
reg up_ready_i = 'd0;
reg [15:0] up_rdata_m = 'd0;
reg up_ready_m = 'd0;
// internal signals
wire up_ready_s;
wire [15:0] up_rdata_mi_s;
wire up_ready_mi_s;
// disable if not selected
assign up_rdata_out = up_rdata_int;
assign up_ready_out = up_ready_int;
assign up_enb_out = (up_sel == 8'hff || up_sel == XCVR_ID) ? up_enb : 1'b0;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_rdata_int <= 16'd0;
up_ready_int <= 1'b0;
end else begin
case (up_sel)
8'hff: begin
up_rdata_int <= up_rdata_mi_s;
up_ready_int <= up_ready_mi_s & ~up_ready_mi;
end
XCVR_ID: begin
up_rdata_int <= up_rdata;
up_ready_int <= up_ready;
end
default: begin
up_rdata_int <= up_rdata_in;
up_ready_int <= up_ready_in;
end
endcase
end
end
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_ready_mi <= 1'b0;
end else begin
up_ready_mi <= up_ready_mi_s;
end
end
assign up_rdata_mi_s = up_rdata_m | up_rdata_i;
assign up_ready_mi_s = up_ready_m & up_ready_i;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_rdata_i <= 16'd0;
up_ready_i <= 1'b0;
end else begin
if (up_ready_in == 1'b1 || XCVR_ID == 0) begin
up_rdata_i <= up_rdata_in;
up_ready_i <= 1'b1;
end else if (up_enb == 1'b1) begin
up_rdata_i <= 16'd0;
up_ready_i <= 1'b0;
end
end
end
generate
if (XCVR_ID < NUM_OF_LANES) begin
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_rdata_m <= 16'd0;
up_ready_m <= 1'b0;
end else begin
if (up_ready == 1'b1) begin
up_rdata_m <= up_rdata;
up_ready_m <= 1'b1;
end else if (up_enb == 1'b1) begin
up_rdata_m <= 16'd0;
up_ready_m <= 1'b0;
end
end
end
end else begin
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_rdata_m <= 16'd0;
up_ready_m <= 1'b0;
end else begin
up_rdata_m <= 16'd0;
up_ready_m <= 1'b1;
end
end
end
endgenerate
endmodule
adi_library/xilinx/axi_adxcvr/axi_adxcvr_mstatus.v
+112
View File
@@ -0,0 +1,112 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ps
module axi_adxcvr_mstatus (
input up_rstn,
input up_clk,
input up_pll_locked_in,
input up_rst_done_in,
input up_prbserr_in,
input up_prbslocked_in,
input [ 1:0] up_bufstatus_in,
input up_pll_locked,
input up_rst_done,
input up_prbserr,
input up_prbslocked,
input [ 1:0] up_bufstatus,
output up_pll_locked_out,
output up_rst_done_out,
output up_prbserr_out,
output up_prbslocked_out,
output [ 1:0] up_bufstatus_out
);
// parameters
parameter integer XCVR_ID = 0;
parameter integer NUM_OF_LANES = 8;
// internal registers
reg up_pll_locked_int = 'd0;
reg up_rst_done_int = 'd0;
reg up_prbserr_int = 'd0;
reg up_prbslocked_int = 'd0;
reg [ 1:0] up_bufstatus_int = 2'd00;
// internal signals
wire up_pll_locked_s;
wire up_rst_done_s;
wire up_prbserr_s;
wire up_prbslocked_s;
wire [ 1:0] up_bufstatus_s;
// daisy-chain the signals
assign up_pll_locked_out = up_pll_locked_int;
assign up_rst_done_out = up_rst_done_int;
assign up_prbserr_out = up_prbserr_int;
assign up_prbslocked_out = up_prbslocked_int;
assign up_bufstatus_out = up_bufstatus_int;
assign up_pll_locked_s = (XCVR_ID < NUM_OF_LANES) ? up_pll_locked : 1'b1;
assign up_rst_done_s = (XCVR_ID < NUM_OF_LANES) ? up_rst_done : 1'b1;
assign up_prbserr_s = (XCVR_ID < NUM_OF_LANES) ? up_prbserr : 1'b0;
assign up_prbslocked_s = (XCVR_ID < NUM_OF_LANES) ? up_prbslocked : 1'b1;
assign up_bufstatus_s = (XCVR_ID < NUM_OF_LANES) ? up_bufstatus : 2'b00;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_pll_locked_int <= 1'd0;
up_rst_done_int <= 1'd0;
up_prbserr_int <= 1'd0;
up_prbslocked_int <= 1'd0;
up_bufstatus_int <= 2'd00;
end else begin
up_pll_locked_int <= up_pll_locked_in & up_pll_locked_s;
up_rst_done_int <= up_rst_done_in & up_rst_done_s;
up_prbserr_int <= up_prbserr_in | up_prbserr_s;
up_prbslocked_int <= up_prbslocked_in & up_prbslocked_s;
up_bufstatus_int[0] <= up_bufstatus_in[0] | up_bufstatus_s[0];
up_bufstatus_int[1] <= up_bufstatus_in[1] | up_bufstatus_s[1];
end
end
endmodule
adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_adxcvr_up #(
// parameters
parameter integer ID = 0,
parameter integer NUM_OF_LANES = 8,
parameter integer XCVR_TYPE = 0,
parameter integer LINK_MODE = 1, // 2 - 64B/66B; 1 - 8B/10B
parameter [ 7:0] FPGA_TECHNOLOGY = 0,
parameter [ 7:0] FPGA_FAMILY = 0,
parameter [ 7:0] SPEED_GRADE = 0,
parameter [ 7:0] DEV_PACKAGE = 0,
parameter [15:0] FPGA_VOLTAGE = 0,
parameter integer TX_OR_RX_N = 0,
parameter integer QPLL_ENABLE = 1,
parameter LPM_OR_DFE_N = 1,
parameter [ 2:0] RATE = 3'd0,
parameter [ 3:0] TX_DIFFCTRL = 4'd8,
parameter [ 4:0] TX_POSTCURSOR = 5'd0,
parameter [ 4:0] TX_PRECURSOR = 5'd0,
parameter [ 1:0] SYS_CLK_SEL = 2'd3,
parameter [ 2:0] OUT_CLK_SEL = 3'd4
) (
// common
output [ 7:0] up_cm_sel,
output up_cm_enb,
output [11:0] up_cm_addr,
output up_cm_wr,
output [15:0] up_cm_wdata,
input [15:0] up_cm_rdata,
input up_cm_ready,
// channel
input up_ch_pll_locked,
output up_ch_rst,
output up_ch_user_ready,
input up_ch_rst_done,
output up_ch_prbsforceerr,
output [ 3:0] up_ch_prbssel,
output up_ch_prbscntreset,
input up_ch_prbserr,
input up_ch_prbslocked,
input [ 1:0] up_ch_bufstatus,
output up_ch_bufstatus_rst,
output up_ch_lpm_dfe_n,
output [ 2:0] up_ch_rate,
output [ 1:0] up_ch_sys_clk_sel,
output [ 2:0] up_ch_out_clk_sel,
output [ 4:0] up_ch_tx_diffctrl,
output [ 4:0] up_ch_tx_postcursor,
output [ 4:0] up_ch_tx_precursor,
output [ 7:0] up_ch_sel,
output up_ch_enb,
output [11:0] up_ch_addr,
output up_ch_wr,
output [15:0] up_ch_wdata,
input [15:0] up_ch_rdata,
input up_ch_ready,
// eye-scan
output [ 7:0] up_es_sel,
output up_es_req,
output reg [15:0] up_es_reset = 'h0,
input up_es_ack,
output [ 4:0] up_es_pscale,
output [ 1:0] up_es_vrange,
output [ 7:0] up_es_vstep,
output [ 7:0] up_es_vmax,
output [ 7:0] up_es_vmin,
output [11:0] up_es_hmax,
output [11:0] up_es_hmin,
output [11:0] up_es_hstep,
output [31:0] up_es_saddr,
input up_es_status,
// status
output up_status,
output up_pll_rst,
// bus interface
input up_rstn,
input up_clk,
input up_wreq,
input [ 9:0] up_waddr,
input [31:0] up_wdata,
output up_wack,
input up_rreq,
input [ 9:0] up_raddr,
output [31:0] up_rdata,
output up_rack
);
// parameters
localparam [31:0] VERSION = 32'h00110561;
// internal registers
reg up_wreq_d = 'd0;
reg [31:0] up_scratch = 'd0;
reg up_resetn = 'd0;
reg [ 3:0] up_pll_rst_cnt = 'd0;
reg [ 3:0] up_rst_cnt = 'd0;
reg [ 6:0] up_user_ready_cnt = 'd0;
reg up_status_int = 'd0;
reg up_lpm_dfe_n = LPM_OR_DFE_N;
reg [ 2:0] up_rate = RATE;
reg [ 1:0] up_sys_clk_sel = SYS_CLK_SEL;
reg [ 2:0] up_out_clk_sel = OUT_CLK_SEL;
reg [ 4:0] up_tx_diffctrl = TX_DIFFCTRL;
reg [ 4:0] up_tx_postcursor = TX_POSTCURSOR;
reg [ 4:0] up_tx_precursor = TX_PRECURSOR;
reg [ 7:0] up_icm_sel = 'd0;
reg up_icm_enb = 'd0;
reg up_icm_wr = 'd0;
reg [28:0] up_icm_data = 'd0;
reg [15:0] up_icm_rdata = 'd0;
reg up_icm_busy = 'd0;
reg [ 7:0] up_ich_sel = 'd0;
reg up_ich_enb = 'd0;
reg up_ich_wr = 'd0;
reg [28:0] up_ich_data = 'd0;
reg [15:0] up_ich_rdata = 'd0;
reg up_ich_busy = 'd0;
reg [ 7:0] up_ies_sel = 'd0;
reg up_ies_req = 'd0;
reg [ 4:0] up_ies_prescale = 'd0;
reg [ 1:0] up_ies_voffset_range = 'd0;
reg [ 7:0] up_ies_voffset_step = 'd0;
reg [ 7:0] up_ies_voffset_max = 'd0;
reg [ 7:0] up_ies_voffset_min = 'd0;
reg [11:0] up_ies_hoffset_max = 'd0;
reg [11:0] up_ies_hoffset_min = 'd0;
reg [11:0] up_ies_hoffset_step = 'd0;
reg [31:0] up_ies_start_addr = 'd0;
reg up_ies_status = 'd0;
reg up_rreq_d = 'd0;
reg [31:0] up_rdata_d = 'd0;
reg [3:0] up_prbssel = 'd0;
reg up_prbscntreset = 'd1;
reg up_prbsforceerr = 'd0;
reg up_bufstatus_rst = 'd1;
// internal signals
wire [31:0] up_rparam_s;
// defaults
assign up_wack = up_wreq_d;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wreq_d <= 'd0;
up_scratch <= 'd0;
end else begin
up_wreq_d <= up_wreq;
if ((up_wreq == 1'b1) && (up_waddr == 10'h002)) begin
up_scratch <= up_wdata;
end
end
end
// reset-controller
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_resetn <= 'd0;
up_bufstatus_rst <= 1'b1;
end else begin
if ((up_wreq == 1'b1) && (up_waddr == 10'h004)) begin
up_resetn <= up_wdata[0];
up_bufstatus_rst <= up_wdata[1];
end
end
end
assign up_pll_rst = up_pll_rst_cnt[3];
assign up_ch_rst = up_rst_cnt[3];
assign up_ch_user_ready = up_user_ready_cnt[6];
assign up_status = up_status_int;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_pll_rst_cnt <= 4'h8;
up_rst_cnt <= 4'h8;
up_user_ready_cnt <= 7'h00;
up_status_int <= 1'b0;
end else begin
if (up_resetn == 1'b0) begin
up_pll_rst_cnt <= 4'h8;
end else if (up_pll_rst_cnt[3] == 1'b1) begin
up_pll_rst_cnt <= up_pll_rst_cnt + 1'b1;
end
if ((up_resetn == 1'b0) || (up_pll_rst_cnt[3] == 1'b1) ||
(up_ch_pll_locked == 1'b0)) begin
up_rst_cnt <= 4'h8;
end else if (up_rst_cnt[3] == 1'b1) begin
up_rst_cnt <= up_rst_cnt + 1'b1;
end
if ((up_resetn == 1'b0) || (up_rst_cnt[3] == 1'b1)) begin
up_user_ready_cnt <= 7'h00;
end else if (up_user_ready_cnt[6] == 1'b0) begin
up_user_ready_cnt <= up_user_ready_cnt + 1'b1;
end
if ((up_resetn == 1'b0) || (up_ch_pll_locked == 1'b0)) begin
up_status_int <= 1'b0;
end else if (up_ch_rst_done == 1'b1) begin
up_status_int <= 1'b1;
end
end
end
// control signals
assign up_ch_lpm_dfe_n = up_lpm_dfe_n;
assign up_ch_rate = up_rate;
assign up_ch_sys_clk_sel = up_sys_clk_sel;
assign up_ch_out_clk_sel = up_out_clk_sel;
assign up_ch_tx_diffctrl = up_tx_diffctrl;
assign up_ch_tx_postcursor = up_tx_postcursor;
assign up_ch_tx_precursor = up_tx_precursor;
assign up_ch_prbssel = up_prbssel;
assign up_ch_prbscntreset = up_prbscntreset;
assign up_ch_prbsforceerr = up_prbsforceerr;
assign up_ch_bufstatus_rst = up_bufstatus_rst;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_lpm_dfe_n <= LPM_OR_DFE_N;
up_rate <= RATE;
up_sys_clk_sel <= SYS_CLK_SEL;
up_out_clk_sel <= OUT_CLK_SEL;
up_tx_diffctrl <= TX_DIFFCTRL;
up_tx_postcursor <= TX_POSTCURSOR;
up_tx_precursor <= TX_PRECURSOR;
up_prbssel <= 4'b0;
up_prbscntreset <= 1'b1;
up_prbsforceerr <= 1'b0;
end else begin
if ((up_wreq == 1'b1) && (up_waddr == 10'h008)) begin
up_lpm_dfe_n <= up_wdata[12];
up_rate <= up_wdata[10:8];
up_sys_clk_sel <= up_wdata[5:4];
up_out_clk_sel <= up_wdata[2:0];
end
if ((up_wreq == 1'b1) && (up_waddr == 10'h030)) begin
up_tx_diffctrl <= up_wdata[4:0];
end
if ((up_wreq == 1'b1) && (up_waddr == 10'h031)) begin
up_tx_postcursor <= up_wdata[4:0];
end
if ((up_wreq == 1'b1) && (up_waddr == 10'h032)) begin
up_tx_precursor <= up_wdata[4:0];
end
if ((up_wreq == 1'b1) && (up_waddr == 10'h060)) begin
up_prbssel <= up_wdata[3:0];
up_prbscntreset <= up_wdata[8];
up_prbsforceerr <= up_wdata[16];
end
end
end
// common access
assign up_cm_sel = up_icm_sel;
assign up_cm_enb = up_icm_enb;
assign up_cm_wr = up_icm_wr;
assign up_cm_addr = up_icm_data[27:16];
assign up_cm_wdata = up_icm_data[15:0];
generate
if (QPLL_ENABLE == 0) begin
always @(posedge up_clk) begin
up_icm_sel <= 'd0;
up_icm_enb <= 'd0;
up_icm_wr <= 'd0;
up_icm_data <= 'd0;
up_icm_rdata <= 'd0;
up_icm_busy <= 'd0;
end
end else begin
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_icm_sel <= 'd0;
up_icm_enb <= 'd0;
up_icm_wr <= 'd0;
up_icm_data <= 'd0;
up_icm_rdata <= 'd0;
up_icm_busy <= 'd0;
end else begin
if ((up_wreq == 1'b1) && (up_waddr == 10'h010)) begin
up_icm_sel <= up_wdata[7:0];
end
if ((up_wreq == 1'b1) && (up_waddr == 10'h011)) begin
up_icm_enb <= 1'b1;
up_icm_wr <= up_wdata[28];
end else begin
up_icm_enb <= 1'b0;
up_icm_wr <= 1'b0;
end
if ((up_wreq == 1'b1) && (up_waddr == 10'h011)) begin
up_icm_data <= up_wdata[28:0];
end
if (up_cm_ready == 1'b1) begin
up_icm_rdata <= up_cm_rdata;
up_icm_busy <= 1'b0;
end else if ((up_wreq == 1'b1) && (up_waddr == 10'h011)) begin
up_icm_rdata <= 16'd0;
up_icm_busy <= 1'b1;
end
end
end
end
endgenerate
// channel access
assign up_ch_sel = up_ich_sel;
assign up_ch_enb = up_ich_enb;
assign up_ch_wr = up_ich_wr;
assign up_ch_addr = up_ich_data[27:16];
assign up_ch_wdata = up_ich_data[15:0];
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_ich_sel <= 'd0;
up_ich_enb <= 'd0;
up_ich_wr <= 'd0;
up_ich_data <= 'd0;
up_ich_rdata <= 'd0;
up_ich_busy <= 'd0;
end else begin
if ((up_wreq == 1'b1) && (up_waddr == 10'h018)) begin
up_ich_sel <= up_wdata[7:0];
end
if ((up_wreq == 1'b1) && (up_waddr == 10'h019)) begin
up_ich_enb <= 1'b1;
up_ich_wr <= up_wdata[28];
end else begin
up_ich_enb <= 1'b0;
up_ich_wr <= 1'b0;
end
if ((up_wreq == 1'b1) && (up_waddr == 10'h019)) begin
up_ich_data <= up_wdata[28:0];
end
if (up_ch_ready == 1'b1) begin
up_ich_rdata <= up_ch_rdata;
up_ich_busy <= 1'b0;
end else if ((up_wreq == 1'b1) && (up_waddr == 10'h019)) begin
up_ich_rdata <= 16'd0;
up_ich_busy <= 1'b1;
end
end
end
// eye-scan
assign up_es_sel = up_ies_sel;
assign up_es_req = up_ies_req;
assign up_es_pscale = up_ies_prescale;
assign up_es_vrange = up_ies_voffset_range;
assign up_es_vstep = up_ies_voffset_step;
assign up_es_vmax = up_ies_voffset_max;
assign up_es_vmin = up_ies_voffset_min;
assign up_es_hmax = up_ies_hoffset_max;
assign up_es_hmin = up_ies_hoffset_min;
assign up_es_hstep = up_ies_hoffset_step;
assign up_es_saddr = up_ies_start_addr;
generate
if (TX_OR_RX_N == 1) begin
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_ies_sel <= 'd0;
up_ies_req <= 'd0;
up_ies_prescale <= 'd0;
up_ies_voffset_range <= 'd0;
up_ies_voffset_step <= 'd0;
up_ies_voffset_max <= 'd0;
up_ies_voffset_min <= 'd0;
up_ies_hoffset_max <= 'd0;
up_ies_hoffset_min <= 'd0;
up_ies_hoffset_step <= 'd0;
up_ies_start_addr <= 'd0;
up_ies_status <= 'd0;
up_es_reset <= 'd0;
end else begin
up_ies_sel <= 'd0;
up_ies_req <= 'd0;
up_ies_prescale <= 'd0;
up_ies_voffset_range <= 'd0;
up_ies_voffset_step <= 'd0;
up_ies_voffset_max <= 'd0;
up_ies_voffset_min <= 'd0;
up_ies_hoffset_max <= 'd0;
up_ies_hoffset_min <= 'd0;
up_ies_hoffset_step <= 'd0;
up_ies_start_addr <= 'd0;
up_ies_status <= 'd0;
up_es_reset <= 'd0;
end
end
end else begin
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_ies_sel <= 'd0;
up_ies_req <= 'd0;
up_ies_prescale <= 'd0;
up_ies_voffset_range <= 'd0;
up_ies_voffset_step <= 'd0;
up_ies_voffset_max <= 'd0;
up_ies_voffset_min <= 'd0;
up_ies_hoffset_max <= 'd0;
up_ies_hoffset_min <= 'd0;
up_ies_hoffset_step <= 'd0;
up_ies_start_addr <= 'd0;
up_ies_status <= 'd0;
up_es_reset <= 'd0;
end else begin
if ((up_wreq == 1'b1) && (up_waddr == 10'h020)) begin
up_ies_sel <= up_wdata[7:0];
end
if (up_es_ack == 1'b1) begin
up_ies_req <= 1'b0;
end else if ((up_wreq == 1'b1) && (up_waddr == 10'h028)) begin
up_ies_req <= up_wdata[0];
end
if ((up_wreq == 1'b1) && (up_waddr == 10'h029)) begin
up_ies_prescale <= up_wdata[4:0];
end
if ((up_wreq == 1'b1) && (up_waddr == 10'h02a)) begin
up_ies_voffset_range <= up_wdata[25:24];
up_ies_voffset_step <= up_wdata[23:16];
up_ies_voffset_max <= up_wdata[15:8];
up_ies_voffset_min <= up_wdata[7:0];
end
if ((up_wreq == 1'b1) && (up_waddr == 10'h02b)) begin
up_ies_hoffset_max <= up_wdata[27:16];
up_ies_hoffset_min <= up_wdata[11:0];
end
if ((up_wreq == 1'b1) && (up_waddr == 10'h02c)) begin
up_ies_hoffset_step <= up_wdata[11:0];
end
if ((up_wreq == 1'b1) && (up_waddr == 10'h02d)) begin
up_ies_start_addr <= up_wdata;
end
if (up_es_status == 1'b1) begin
up_ies_status <= 1'b1;
end else if ((up_wreq == 1'b1) && (up_waddr == 10'h02e)) begin
up_ies_status <= up_ies_status & ~up_wdata[0];
end
if ((up_wreq == 1'b1) && (up_waddr == 10'h02f)) begin
up_es_reset <= up_wdata[15:0];
end
end
end
end
endgenerate
// read interface
assign up_rack = up_rreq_d;
assign up_rdata = up_rdata_d;
assign up_rparam_s[31:24] = 8'd0;
// xilinx specific
assign up_rparam_s[23:21] = 3'd0;
assign up_rparam_s[20:20] = (QPLL_ENABLE == 0) ? 1'b0 : 1'b1;
assign up_rparam_s[19:16] = XCVR_TYPE[3:0];
// generic
assign up_rparam_s[15:14] = 2'd0;
assign up_rparam_s[13:12] = LINK_MODE[1:0];
assign up_rparam_s[11: 9] = 3'd0;
assign up_rparam_s[ 8: 8] = (TX_OR_RX_N == 0) ? 1'b0 : 1'b1;
assign up_rparam_s[ 7: 0] = NUM_OF_LANES;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rreq_d <= 'd0;
up_rdata_d <= 'd0;
end else begin
up_rreq_d <= up_rreq;
if (up_rreq == 1'b1) begin
case (up_raddr)
10'h000: up_rdata_d <= VERSION;
10'h001: up_rdata_d <= ID;
10'h002: up_rdata_d <= up_scratch;
10'h004: up_rdata_d <= {30'd0, up_bufstatus_rst, up_resetn};
10'h005: up_rdata_d <= {25'd0, up_ch_bufstatus[1], up_ch_bufstatus[0], ~up_ch_pll_locked, 3'b0, up_status_int};
10'h006: up_rdata_d <= {17'd0, up_user_ready_cnt, up_rst_cnt, up_pll_rst_cnt};
10'h007: up_rdata_d <= {FPGA_TECHNOLOGY,FPGA_FAMILY,SPEED_GRADE,DEV_PACKAGE}; // [8,8,8,8]
10'h008: up_rdata_d <= {19'd0, up_lpm_dfe_n, 1'd0, up_rate, 2'd0, up_sys_clk_sel, 1'd0, up_out_clk_sel};
10'h009: up_rdata_d <= up_rparam_s;
10'h010: up_rdata_d <= {24'd0, up_icm_sel};
10'h011: up_rdata_d <= {3'd0, up_icm_data};
10'h012: up_rdata_d <= {15'd0, up_icm_busy, up_icm_rdata};
10'h018: up_rdata_d <= {24'd0, up_ich_sel};
10'h019: up_rdata_d <= {3'd0, up_ich_data};
10'h01a: up_rdata_d <= {15'd0, up_ich_busy, up_ich_rdata};
10'h020: up_rdata_d <= {24'd0, up_ies_sel};
10'h028: up_rdata_d <= {31'd0, up_ies_req};
10'h029: up_rdata_d <= {27'd0, up_ies_prescale};
10'h02a: up_rdata_d <= {6'd0, up_ies_voffset_range, up_ies_voffset_step, up_ies_voffset_max, up_ies_voffset_min};
10'h02b: up_rdata_d <= {4'd0, up_ies_hoffset_max, 4'd0, up_ies_hoffset_min};
10'h02c: up_rdata_d <= {20'd0, up_ies_hoffset_step};
10'h02d: up_rdata_d <= up_ies_start_addr;
10'h02e: up_rdata_d <= {31'd0, up_es_status};
10'h02f: up_rdata_d <= {16'd0, up_es_reset};
10'h030: up_rdata_d <= up_tx_diffctrl;
10'h031: up_rdata_d <= up_tx_postcursor;
10'h032: up_rdata_d <= up_tx_precursor;
10'h050: up_rdata_d <= {16'd0, FPGA_VOLTAGE}; // mV
10'h060: up_rdata_d <= {8'b0,
7'b0,up_prbsforceerr,
7'b0,up_prbscntreset,
4'b0,up_prbssel};
10'h061: up_rdata_d <= {16'b0,
7'b0,up_ch_prbserr,
7'b0,up_ch_prbslocked};
default: up_rdata_d <= 32'd0;
endcase
end else begin
up_rdata_d <= 32'd0;
end
end
end
endmodule
adi_library/xilinx/axi_adxcvr/bd/bd.tcl
+51
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# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
DEV_PACKAGE \
SPEED_GRADE \
FPGA_FAMILY \
FPGA_TECHNOLOGY"
bd::mark_propagate_override $ip " \
FPGA_VOLTAGE \
XCVR_TYPE"
adi_auto_assign_device_spec $cellpath
}
# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)
proc adi_auto_assign_device_spec {cellpath} {
set ip [get_bd_cells $cellpath]
set ip_param_list [list_property $ip]
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
set parent_dir "../"
for {set x 1} {$x<=4} {incr x} {
set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl
if { [file exists $linkname] } {
source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl
break
}
append parent_dir "../"
}
# Find predefindes auto assignable parameters
foreach i $auto_set_param_list {
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
set val [adi_device_spec $cellpath $i]
set_property CONFIG.$i $val $ip
}
}
# Find predefindes auto assignable/overwritable parameters
foreach i $auto_set_param_list_overwritable {
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
set val [adi_device_spec $cellpath $i]
set_property CONFIG.$i $val $ip
}
}
}
adi_library/xilinx/axi_adxcvr/component.xml
+27269
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adi_library/xilinx/axi_adxcvr/temporary_case_dependencies.mk
+2
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@@ -0,0 +1,2 @@
CLEAN_TARGET += bd
CLEAN_TARGET += temporary_case_dependencies.mk
adi_library/xilinx/axi_adxcvr/xgui/axi_adxcvr_v1_0.tcl
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# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
ipgui::add_param $IPINST -name "LINK_MODE" -parent ${Page_0} -widget comboBox
ipgui::add_param $IPINST -name "ID" -parent ${Page_0}
ipgui::add_param $IPINST -name "LPM_OR_DFE_N" -parent ${Page_0}
ipgui::add_param $IPINST -name "NUM_OF_LANES" -parent ${Page_0}
ipgui::add_param $IPINST -name "OUT_CLK_SEL" -parent ${Page_0}
ipgui::add_param $IPINST -name "QPLL_ENABLE" -parent ${Page_0}
ipgui::add_param $IPINST -name "RATE" -parent ${Page_0}
ipgui::add_param $IPINST -name "SYS_CLK_SEL" -parent ${Page_0}
ipgui::add_param $IPINST -name "TX_DIFFCTRL" -parent ${Page_0}
ipgui::add_param $IPINST -name "TX_OR_RX_N" -parent ${Page_0}
ipgui::add_param $IPINST -name "TX_POSTCURSOR" -parent ${Page_0}
ipgui::add_param $IPINST -name "TX_PRECURSOR" -parent ${Page_0}
#Adding Group
set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}]
ipgui::add_param $IPINST -name "XCVR_TYPE" -parent ${FPGA_info} -widget comboBox
ipgui::add_param $IPINST -name "FPGA_VOLTAGE" -parent ${FPGA_info} -widget comboBox
ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox
ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${FPGA_info} -widget comboBox
ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${FPGA_info} -widget comboBox
ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${FPGA_info} -widget comboBox
}
proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
# Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
# Procedure called to validate DEV_PACKAGE
return true
}
proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
# Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
# Procedure called to validate FPGA_FAMILY
return true
}
proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
# Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
# Procedure called to validate FPGA_TECHNOLOGY
return true
}
proc update_PARAM_VALUE.FPGA_VOLTAGE { PARAM_VALUE.FPGA_VOLTAGE } {
# Procedure called to update FPGA_VOLTAGE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.FPGA_VOLTAGE { PARAM_VALUE.FPGA_VOLTAGE } {
# Procedure called to validate FPGA_VOLTAGE
return true
}
proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } {
# Procedure called to update ID when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } {
# Procedure called to validate ID
return true
}
proc update_PARAM_VALUE.LINK_MODE { PARAM_VALUE.LINK_MODE } {
# Procedure called to update LINK_MODE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.LINK_MODE { PARAM_VALUE.LINK_MODE } {
# Procedure called to validate LINK_MODE
return true
}
proc update_PARAM_VALUE.LPM_OR_DFE_N { PARAM_VALUE.LPM_OR_DFE_N } {
# Procedure called to update LPM_OR_DFE_N when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.LPM_OR_DFE_N { PARAM_VALUE.LPM_OR_DFE_N } {
# Procedure called to validate LPM_OR_DFE_N
return true
}
proc update_PARAM_VALUE.NUM_OF_LANES { PARAM_VALUE.NUM_OF_LANES } {
# Procedure called to update NUM_OF_LANES when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.NUM_OF_LANES { PARAM_VALUE.NUM_OF_LANES } {
# Procedure called to validate NUM_OF_LANES
return true
}
proc update_PARAM_VALUE.OUT_CLK_SEL { PARAM_VALUE.OUT_CLK_SEL } {
# Procedure called to update OUT_CLK_SEL when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.OUT_CLK_SEL { PARAM_VALUE.OUT_CLK_SEL } {
# Procedure called to validate OUT_CLK_SEL
return true
}
proc update_PARAM_VALUE.QPLL_ENABLE { PARAM_VALUE.QPLL_ENABLE } {
# Procedure called to update QPLL_ENABLE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.QPLL_ENABLE { PARAM_VALUE.QPLL_ENABLE } {
# Procedure called to validate QPLL_ENABLE
return true
}
proc update_PARAM_VALUE.RATE { PARAM_VALUE.RATE } {
# Procedure called to update RATE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.RATE { PARAM_VALUE.RATE } {
# Procedure called to validate RATE
return true
}
proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
# Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
# Procedure called to validate SPEED_GRADE
return true
}
proc update_PARAM_VALUE.SYS_CLK_SEL { PARAM_VALUE.SYS_CLK_SEL } {
# Procedure called to update SYS_CLK_SEL when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.SYS_CLK_SEL { PARAM_VALUE.SYS_CLK_SEL } {
# Procedure called to validate SYS_CLK_SEL
return true
}
proc update_PARAM_VALUE.TX_DIFFCTRL { PARAM_VALUE.TX_DIFFCTRL } {
# Procedure called to update TX_DIFFCTRL when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.TX_DIFFCTRL { PARAM_VALUE.TX_DIFFCTRL } {
# Procedure called to validate TX_DIFFCTRL
return true
}
proc update_PARAM_VALUE.TX_OR_RX_N { PARAM_VALUE.TX_OR_RX_N } {
# Procedure called to update TX_OR_RX_N when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.TX_OR_RX_N { PARAM_VALUE.TX_OR_RX_N } {
# Procedure called to validate TX_OR_RX_N
return true
}
proc update_PARAM_VALUE.TX_POSTCURSOR { PARAM_VALUE.TX_POSTCURSOR } {
# Procedure called to update TX_POSTCURSOR when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.TX_POSTCURSOR { PARAM_VALUE.TX_POSTCURSOR } {
# Procedure called to validate TX_POSTCURSOR
return true
}
proc update_PARAM_VALUE.TX_PRECURSOR { PARAM_VALUE.TX_PRECURSOR } {
# Procedure called to update TX_PRECURSOR when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.TX_PRECURSOR { PARAM_VALUE.TX_PRECURSOR } {
# Procedure called to validate TX_PRECURSOR
return true
}
proc update_PARAM_VALUE.XCVR_TYPE { PARAM_VALUE.XCVR_TYPE } {
# Procedure called to update XCVR_TYPE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.XCVR_TYPE { PARAM_VALUE.XCVR_TYPE } {
# Procedure called to validate XCVR_TYPE
return true
}
proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID}
}
proc update_MODELPARAM_VALUE.NUM_OF_LANES { MODELPARAM_VALUE.NUM_OF_LANES PARAM_VALUE.NUM_OF_LANES } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.NUM_OF_LANES}] ${MODELPARAM_VALUE.NUM_OF_LANES}
}
proc update_MODELPARAM_VALUE.XCVR_TYPE { MODELPARAM_VALUE.XCVR_TYPE PARAM_VALUE.XCVR_TYPE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.XCVR_TYPE}] ${MODELPARAM_VALUE.XCVR_TYPE}
}
proc update_MODELPARAM_VALUE.LINK_MODE { MODELPARAM_VALUE.LINK_MODE PARAM_VALUE.LINK_MODE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.LINK_MODE}] ${MODELPARAM_VALUE.LINK_MODE}
}
proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY}
}
proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY}
}
proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE}
}
proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE}
}
proc update_MODELPARAM_VALUE.FPGA_VOLTAGE { MODELPARAM_VALUE.FPGA_VOLTAGE PARAM_VALUE.FPGA_VOLTAGE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.FPGA_VOLTAGE}] ${MODELPARAM_VALUE.FPGA_VOLTAGE}
}
proc update_MODELPARAM_VALUE.TX_OR_RX_N { MODELPARAM_VALUE.TX_OR_RX_N PARAM_VALUE.TX_OR_RX_N } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.TX_OR_RX_N}] ${MODELPARAM_VALUE.TX_OR_RX_N}
}
proc update_MODELPARAM_VALUE.QPLL_ENABLE { MODELPARAM_VALUE.QPLL_ENABLE PARAM_VALUE.QPLL_ENABLE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.QPLL_ENABLE}] ${MODELPARAM_VALUE.QPLL_ENABLE}
}
proc update_MODELPARAM_VALUE.LPM_OR_DFE_N { MODELPARAM_VALUE.LPM_OR_DFE_N PARAM_VALUE.LPM_OR_DFE_N } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.LPM_OR_DFE_N}] ${MODELPARAM_VALUE.LPM_OR_DFE_N}
}
proc update_MODELPARAM_VALUE.RATE { MODELPARAM_VALUE.RATE PARAM_VALUE.RATE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.RATE}] ${MODELPARAM_VALUE.RATE}
}
proc update_MODELPARAM_VALUE.TX_DIFFCTRL { MODELPARAM_VALUE.TX_DIFFCTRL PARAM_VALUE.TX_DIFFCTRL } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.TX_DIFFCTRL}] ${MODELPARAM_VALUE.TX_DIFFCTRL}
}
proc update_MODELPARAM_VALUE.TX_POSTCURSOR { MODELPARAM_VALUE.TX_POSTCURSOR PARAM_VALUE.TX_POSTCURSOR } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.TX_POSTCURSOR}] ${MODELPARAM_VALUE.TX_POSTCURSOR}
}
proc update_MODELPARAM_VALUE.TX_PRECURSOR { MODELPARAM_VALUE.TX_PRECURSOR PARAM_VALUE.TX_PRECURSOR } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.TX_PRECURSOR}] ${MODELPARAM_VALUE.TX_PRECURSOR}
}
proc update_MODELPARAM_VALUE.SYS_CLK_SEL { MODELPARAM_VALUE.SYS_CLK_SEL PARAM_VALUE.SYS_CLK_SEL } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.SYS_CLK_SEL}] ${MODELPARAM_VALUE.SYS_CLK_SEL}
}
proc update_MODELPARAM_VALUE.OUT_CLK_SEL { MODELPARAM_VALUE.OUT_CLK_SEL PARAM_VALUE.OUT_CLK_SEL } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.OUT_CLK_SEL}] ${MODELPARAM_VALUE.OUT_CLK_SEL}
}