initial commit, add dds_par module
This commit is contained in:
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####################################################################################
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## Copyright (c) 2018 - 2023 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := axi_xcvrlb
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XILINX_DEPS += ../../common/ad_pnmon.v
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XILINX_DEPS += ../../common/up_axi.v
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XILINX_DEPS += ../../common/up_xfer_status.v
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XILINX_DEPS += ../../xilinx/util_adxcvr/util_adxcvr_xch.v
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XILINX_DEPS += axi_xcvrlb.v
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XILINX_DEPS += axi_xcvrlb_1.v
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XILINX_DEPS += axi_xcvrlb_constr.xdc
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XILINX_DEPS += axi_xcvrlb_ip.tcl
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XILINX_LIB_DEPS += util_cdc
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include ../../scripts/library.mk
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@@ -0,0 +1,219 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ps
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module axi_xcvrlb #(
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// parameters
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parameter integer CPLL_FBDIV = 1,
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parameter integer CPLL_FBDIV_4_5 = 5,
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parameter NUM_OF_LANES = 1,
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parameter integer XCVR_TYPE = 2
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) (
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// transceiver interface
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input ref_clk,
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input [(NUM_OF_LANES-1):0] rx_p,
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input [(NUM_OF_LANES-1):0] rx_n,
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output [(NUM_OF_LANES-1):0] tx_p,
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output [(NUM_OF_LANES-1):0] tx_n,
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// axi interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [15:0] s_axi_awaddr,
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input [ 2:0] s_axi_awprot,
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output s_axi_awready,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [15:0] s_axi_araddr,
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input [ 2:0] s_axi_arprot,
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output s_axi_arready,
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output s_axi_rvalid,
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output [ 1:0] s_axi_rresp,
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output [31:0] s_axi_rdata,
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input s_axi_rready
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);
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// internal registers
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reg up_wack = 'd0;
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reg [31:0] up_scratch = 'd0;
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reg up_resetn = 'd0;
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reg [31:0] up_status = 'd0;
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reg [31:0] up_pll_locked = 'd0;
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reg up_rack = 'd0;
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reg [31:0] up_rdata = 'd0;
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// internal signals
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wire up_rstn;
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wire up_clk;
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wire up_wreq_s;
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wire [ 7:0] up_waddr_s;
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wire [31:0] up_wdata_s;
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wire up_rreq_s;
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wire [ 7:0] up_raddr_s;
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wire [31:0] up_status_s;
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wire [31:0] up_pll_locked_s;
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// parameters
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localparam [31:0] VERSION = 32'h00100161;
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// defaults
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assign up_rstn = s_axi_aresetn;
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assign up_clk = s_axi_aclk;
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assign up_status_s[31:NUM_OF_LANES] = 'd0;
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assign up_pll_locked_s[31:NUM_OF_LANES] = 'd0;
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// register access
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_wack <= 'd0;
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up_scratch <= 'd0;
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up_resetn <= 'd0;
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up_status <= 'd0;
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up_pll_locked <= 'd0;
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end else begin
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up_wack <= up_wreq_s;
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if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h02)) begin
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up_scratch <= up_wdata_s;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h04)) begin
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up_resetn <= up_wdata_s[0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h05)) begin
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up_status <= up_status_s | (up_status & ~up_wdata_s);
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end else begin
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up_status <= up_status_s | up_status;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h06)) begin
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up_pll_locked <= up_pll_locked_s | (up_pll_locked & ~up_wdata_s);
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end else begin
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up_pll_locked <= up_pll_locked_s | up_pll_locked;
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end
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end
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end
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_rack <= 'd0;
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up_rdata <= 'd0;
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end else begin
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up_rack <= up_rreq_s;
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if (up_rreq_s == 1'b1) begin
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case (up_raddr_s)
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10'h000: up_rdata <= VERSION;
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10'h002: up_rdata <= up_scratch;
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10'h004: up_rdata <= {31'd0, up_resetn};
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10'h005: up_rdata <= up_status;
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10'h006: up_rdata <= up_pll_locked;
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default: up_rdata <= 32'd0;
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endcase
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end else begin
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up_rdata <= 32'd0;
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end
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end
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end
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// instantiations
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genvar n;
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generate
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for (n = 0; n < NUM_OF_LANES; n = n + 1) begin: g_lanes
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axi_xcvrlb_1 #(
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.XCVR_TYPE (XCVR_TYPE),
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.CPLL_FBDIV_4_5(CPLL_FBDIV_4_5),
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.CPLL_FBDIV(CPLL_FBDIV)
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) i_xcvrlb_1 (
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.ref_clk (ref_clk),
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.rx_p (rx_p[n]),
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.rx_n (rx_n[n]),
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.tx_p (tx_p[n]),
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.tx_n (tx_n[n]),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_resetn (up_resetn),
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.up_status (up_status_s[n]),
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.up_pll_locked (up_pll_locked_s[n]));
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end
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endgenerate
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up_axi #(
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.AXI_ADDRESS_WIDTH (10)
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) i_axi (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_axi_awvalid (s_axi_awvalid),
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.up_axi_awaddr (s_axi_awaddr),
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.up_axi_awready (s_axi_awready),
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.up_axi_wvalid (s_axi_wvalid),
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.up_axi_wdata (s_axi_wdata),
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.up_axi_wstrb (s_axi_wstrb),
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.up_axi_wready (s_axi_wready),
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.up_axi_bvalid (s_axi_bvalid),
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.up_axi_bresp (s_axi_bresp),
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.up_axi_bready (s_axi_bready),
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.up_axi_arvalid (s_axi_arvalid),
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.up_axi_araddr (s_axi_araddr),
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.up_axi_arready (s_axi_arready),
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.up_axi_rvalid (s_axi_rvalid),
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.up_axi_rresp (s_axi_rresp),
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.up_axi_rdata (s_axi_rdata),
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.up_axi_rready (s_axi_rready),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata),
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.up_rack (up_rack));
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endmodule
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@@ -0,0 +1,447 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
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<!-- -->
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<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
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||||
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
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||||
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||||
<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/xilinx/axi_xcvrlb/axi_xcvrlb.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="0820422988594cc5932574f6f5fce3c1"/>
|
||||
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
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||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
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<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
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<Option Name="SimulatorInstallDirModelSim" Val=""/>
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<Option Name="SimulatorInstallDirQuesta" Val=""/>
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<Option Name="SimulatorInstallDirXcelium" Val=""/>
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<Option Name="SimulatorInstallDirVCS" Val=""/>
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<Option Name="SimulatorInstallDirRiviera" Val=""/>
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<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
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<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
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<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
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<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
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<Option Name="SimulatorGccInstallDirVCS" Val=""/>
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<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
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<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
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<Option Name="SimulatorVersionXsim" Val="2023.2"/>
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<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
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<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
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<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
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<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
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<Option Name="SimulatorVersionRiviera" Val="2022.10"/>
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<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
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||||
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
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||||
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
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<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
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<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
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||||
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
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<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
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<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
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||||
<Option Name="BoardPart" Val=""/>
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||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
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||||
<Option Name="ProjectType" Val="Default"/>
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||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../library"/>
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||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
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||||
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
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||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="EnableResourceEstimation" Val="FALSE"/>
|
||||
<Option Name="SimCompileState" Val="TRUE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
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||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
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||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
||||
<Option Name="ClassicSocBoot" Val="FALSE"/>
|
||||
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="32">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
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<File Path="$PPRDIR/../../common/ad_pnmon.v">
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||||
<FileInfo>
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||||
<Attr Name="UsedIn" Val="synthesis"/>
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||||
<Attr Name="UsedIn" Val="implementation"/>
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||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/axi_xcvrlb_1.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../common/up_axi.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../common/up_xfer_status.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../util_adxcvr/util_adxcvr_xch.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
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||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
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|
||||
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|
||||
<File Path="$PPRDIR/axi_xcvrlb.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
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||||
<Attr Name="UsedIn" Val="implementation"/>
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||||
<Attr Name="UsedIn" Val="simulation"/>
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||||
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||||
</File>
|
||||
<File Path="$PPRDIR/component.xml">
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||||
<FileInfo SFType="IPXACT"/>
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||||
</File>
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||||
<File Path="$PPRDIR/bd/bd.tcl">
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||||
<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="axi_xcvrlb"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PPRDIR/axi_xcvrlb_constr.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||
<Option Name="PamDesignTestbench" Val=""/>
|
||||
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
||||
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="21">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="1"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="features"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="should"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="NOT"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="be"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="used"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="in"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="production"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="systems."/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="10"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Place 30-73"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="11"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val=""/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="12"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1343"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="2"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1306"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="3"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="ERROR"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1276"/>
|
||||
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="4"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="5"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-2490"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
</Project>
|
||||
@@ -0,0 +1,326 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module axi_xcvrlb_1 #(
|
||||
|
||||
// parameters
|
||||
|
||||
parameter CPLL_FBDIV = 1,
|
||||
parameter CPLL_FBDIV_4_5 = 5,
|
||||
parameter XCVR_TYPE = 2
|
||||
) (
|
||||
|
||||
// transceiver interface
|
||||
|
||||
input ref_clk,
|
||||
input rx_p,
|
||||
input rx_n,
|
||||
output tx_p,
|
||||
output tx_n,
|
||||
|
||||
// processor interface
|
||||
|
||||
input up_rstn,
|
||||
input up_clk,
|
||||
input up_resetn,
|
||||
output up_status,
|
||||
output up_pll_locked
|
||||
);
|
||||
|
||||
// internal registers
|
||||
|
||||
reg [ 3:0] rx_kcount = 'd0;
|
||||
reg rx_calign = 'd0;
|
||||
reg [31:0] rx_data = 'd0;
|
||||
reg [31:0] rx_pn_data = 'd0;
|
||||
reg tx_charisk = 'd0;
|
||||
reg [31:0] tx_data = 'd0;
|
||||
reg [31:0] tx_pn_data = 'd0;
|
||||
reg [ 3:0] up_pll_rst_cnt = 'd0;
|
||||
reg [ 3:0] up_rst_cnt = 'd0;
|
||||
reg [ 6:0] up_user_ready_cnt = 'd0;
|
||||
reg up_status_int = 'd1;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire clk;
|
||||
wire rx_status_s;
|
||||
wire [31:0] rx_pn_data_s;
|
||||
wire rx_pn_oos_s;
|
||||
wire rx_pn_err_s;
|
||||
wire [ 3:0] rx_charisk_s;
|
||||
wire [ 7:0] rx_error_s;
|
||||
wire [31:0] rx_data_s;
|
||||
wire up_pll_rst_s;
|
||||
wire up_rst_s;
|
||||
wire up_user_ready_s;
|
||||
wire up_pll_locked_s;
|
||||
wire up_rst_done_s;
|
||||
wire up_pn_oos_s;
|
||||
wire up_pn_err_s;
|
||||
wire up_rx_pll_locked_s;
|
||||
wire up_rx_rst_done_s;
|
||||
wire up_tx_pll_locked_s;
|
||||
wire up_tx_rst_done_s;
|
||||
|
||||
// pn31 function
|
||||
|
||||
function [31:0] pn31;
|
||||
input [31:0] din;
|
||||
reg [31:0] dout;
|
||||
begin
|
||||
dout[31] = din[31] ^ din[28];
|
||||
dout[30] = din[30] ^ din[27];
|
||||
dout[29] = din[29] ^ din[26];
|
||||
dout[28] = din[28] ^ din[25];
|
||||
dout[27] = din[27] ^ din[24];
|
||||
dout[26] = din[26] ^ din[23];
|
||||
dout[25] = din[25] ^ din[22];
|
||||
dout[24] = din[24] ^ din[21];
|
||||
dout[23] = din[23] ^ din[20];
|
||||
dout[22] = din[22] ^ din[19];
|
||||
dout[21] = din[21] ^ din[18];
|
||||
dout[20] = din[20] ^ din[17];
|
||||
dout[19] = din[19] ^ din[16];
|
||||
dout[18] = din[18] ^ din[15];
|
||||
dout[17] = din[17] ^ din[14];
|
||||
dout[16] = din[16] ^ din[13];
|
||||
dout[15] = din[15] ^ din[12];
|
||||
dout[14] = din[14] ^ din[11];
|
||||
dout[13] = din[13] ^ din[10];
|
||||
dout[12] = din[12] ^ din[ 9];
|
||||
dout[11] = din[11] ^ din[ 8];
|
||||
dout[10] = din[10] ^ din[ 7];
|
||||
dout[ 9] = din[ 9] ^ din[ 6];
|
||||
dout[ 8] = din[ 8] ^ din[ 5];
|
||||
dout[ 7] = din[ 7] ^ din[ 4];
|
||||
dout[ 6] = din[ 6] ^ din[ 3];
|
||||
dout[ 5] = din[ 5] ^ din[ 2];
|
||||
dout[ 4] = din[ 4] ^ din[ 1];
|
||||
dout[ 3] = din[ 3] ^ din[ 0];
|
||||
dout[ 2] = din[ 2] ^ din[31] ^ din[28];
|
||||
dout[ 1] = din[ 1] ^ din[30] ^ din[27];
|
||||
dout[ 0] = din[ 0] ^ din[29] ^ din[26];
|
||||
pn31 = dout;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// receive
|
||||
|
||||
assign rx_status_s = ~(| rx_error_s);
|
||||
assign rx_pn_data_s = (rx_pn_oos_s == 1'b1) ? rx_data : rx_pn_data;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rx_status_s == 1'b0) begin
|
||||
rx_kcount <= 4'd0;
|
||||
rx_calign <= 1'd1;
|
||||
end else if ((rx_charisk_s == 4'hf) && (rx_data_s == {4{8'hbc}})) begin
|
||||
rx_kcount <= rx_kcount + 1'b1;
|
||||
if (rx_kcount == 4'hf) begin
|
||||
rx_calign <= 1'd0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rx_status_s == 1'b1) begin
|
||||
rx_data[31:24] = rx_data_s[ 7: 0];
|
||||
rx_data[23:16] = rx_data_s[15: 8];
|
||||
rx_data[15: 8] = rx_data_s[23:16];
|
||||
rx_data[ 7: 0] = rx_data_s[31:24];
|
||||
end else begin
|
||||
rx_data[31:24] = 8'hff;
|
||||
rx_data[23:16] = 8'hff;
|
||||
rx_data[15: 8] = 8'hff;
|
||||
rx_data[ 7: 0] = 8'hff;
|
||||
end
|
||||
rx_pn_data <= pn31(rx_pn_data_s);
|
||||
end
|
||||
|
||||
// transmit
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rx_calign == 1'b0) begin
|
||||
tx_charisk <= 1'd0;
|
||||
tx_data[31:24] <= tx_pn_data[ 7: 0];
|
||||
tx_data[23:16] <= tx_pn_data[15: 8];
|
||||
tx_data[15: 8] <= tx_pn_data[23:16];
|
||||
tx_data[ 7: 0] <= tx_pn_data[31:24];
|
||||
tx_pn_data <= pn31(tx_pn_data);
|
||||
end else begin
|
||||
tx_charisk <= 1'd1;
|
||||
tx_data[31:24] <= 8'hbc;
|
||||
tx_data[23:16] <= 8'hbc;
|
||||
tx_data[15: 8] <= 8'hbc;
|
||||
tx_data[ 7: 0] <= 8'hbc;
|
||||
tx_pn_data <= {32{1'b1}};
|
||||
end
|
||||
end
|
||||
|
||||
// reset & init
|
||||
|
||||
assign up_status = up_status_int;
|
||||
assign up_pll_rst_s = up_pll_rst_cnt[3];
|
||||
assign up_rst_s = up_rst_cnt[3];
|
||||
assign up_user_ready_s = up_user_ready_cnt[6];
|
||||
assign up_pll_locked_s = up_rx_pll_locked_s & up_tx_pll_locked_s;
|
||||
assign up_pll_locked = up_pll_locked_s;
|
||||
assign up_rst_done_s = up_rx_rst_done_s & up_tx_rst_done_s;
|
||||
|
||||
always @(negedge up_rstn or posedge up_clk) begin
|
||||
if (up_rstn == 0) begin
|
||||
up_pll_rst_cnt <= 4'h8;
|
||||
up_rst_cnt <= 4'h8;
|
||||
up_user_ready_cnt <= 7'h00;
|
||||
up_status_int <= 1'b1;
|
||||
end else begin
|
||||
if (up_resetn == 1'b0) begin
|
||||
up_pll_rst_cnt <= 4'h8;
|
||||
end else if (up_pll_rst_cnt[3] == 1'b1) begin
|
||||
up_pll_rst_cnt <= up_pll_rst_cnt + 1'b1;
|
||||
end
|
||||
if ((up_resetn == 1'b0) || (up_pll_rst_cnt[3] == 1'b1) ||
|
||||
(up_pll_locked_s == 1'b0)) begin
|
||||
up_rst_cnt <= 4'h8;
|
||||
end else if (up_rst_cnt[3] == 1'b1) begin
|
||||
up_rst_cnt <= up_rst_cnt + 1'b1;
|
||||
end
|
||||
if ((up_resetn == 1'b0) || (up_rst_cnt[3] == 1'b1)) begin
|
||||
up_user_ready_cnt <= 7'h00;
|
||||
end else if (up_user_ready_cnt[6] == 1'b0) begin
|
||||
up_user_ready_cnt <= up_user_ready_cnt + 1'b1;
|
||||
end
|
||||
if ((up_resetn == 1'b0) || (up_rst_done_s == 1'b0)) begin
|
||||
up_status_int <= 1'b1;
|
||||
end else begin
|
||||
up_status_int <= up_pn_oos_s | up_pn_err_s;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// instantiations
|
||||
|
||||
ad_pnmon #(
|
||||
.DATA_WIDTH(32)
|
||||
) i_pnmon (
|
||||
.adc_clk (clk),
|
||||
.adc_valid_in (1'b1),
|
||||
.adc_data_in (rx_data),
|
||||
.adc_data_pn (rx_pn_data),
|
||||
.adc_pn_oos (rx_pn_oos_s),
|
||||
.adc_pn_err (rx_pn_err_s));
|
||||
|
||||
up_xfer_status #(
|
||||
.DATA_WIDTH(2)
|
||||
) i_xfer_status (
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_data_status ({up_pn_err_s, up_pn_oos_s}),
|
||||
.d_rst (1'b0),
|
||||
.d_clk (clk),
|
||||
.d_data_status ({rx_pn_err_s, rx_pn_oos_s}));
|
||||
|
||||
util_adxcvr_xch #(
|
||||
.XCVR_TYPE (XCVR_TYPE),
|
||||
.CPLL_FBDIV (CPLL_FBDIV),
|
||||
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
|
||||
.TX_OUT_DIV (1),
|
||||
.TX_CLK25_DIV (10),
|
||||
.RX_OUT_DIV (1),
|
||||
.RX_CLK25_DIV (10),
|
||||
.RX_DFE_LPM_CFG (16'h0904),
|
||||
.RX_PMA_CFG ('h00018480),
|
||||
.RX_CDR_CFG ('h03000023ff10200020)
|
||||
) i_xch (
|
||||
.qpll2ch_clk (1'b0),
|
||||
.qpll2ch_ref_clk (1'b0),
|
||||
.qpll2ch_locked (1'b1),
|
||||
.cpll_ref_clk (ref_clk),
|
||||
.up_cpll_rst (up_pll_rst_s),
|
||||
.rx_p (rx_p),
|
||||
.rx_n (rx_n),
|
||||
.rx_out_clk (clk),
|
||||
.rx_clk (clk),
|
||||
.rx_charisk (rx_charisk_s),
|
||||
.rx_disperr (rx_error_s[3:0]),
|
||||
.rx_notintable (rx_error_s[7:4]),
|
||||
.rx_data (rx_data_s),
|
||||
.rx_calign (rx_calign),
|
||||
.tx_p (tx_p),
|
||||
.tx_n (tx_n),
|
||||
.tx_out_clk (),
|
||||
.tx_clk (clk),
|
||||
.tx_charisk ({4{tx_charisk}}),
|
||||
.tx_data (tx_data),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_es_enb (1'd0),
|
||||
.up_es_addr (12'd0),
|
||||
.up_es_wr (1'd0),
|
||||
.up_es_wdata (16'd0),
|
||||
.up_es_rdata (),
|
||||
.up_es_ready (),
|
||||
.up_rx_pll_locked (up_rx_pll_locked_s),
|
||||
.up_rx_rst (up_rst_s),
|
||||
.up_rx_user_ready (up_user_ready_s),
|
||||
.up_rx_rst_done (up_rx_rst_done_s),
|
||||
.up_rx_lpm_dfe_n (1'd0),
|
||||
.up_rx_rate (3'd0),
|
||||
.up_rx_sys_clk_sel (2'd0),
|
||||
.up_rx_out_clk_sel (3'd2),
|
||||
.up_rx_enb (1'd0),
|
||||
.up_rx_addr (12'd0),
|
||||
.up_rx_wr (1'd0),
|
||||
.up_rx_wdata (16'd0),
|
||||
.up_rx_rdata (),
|
||||
.up_rx_ready (),
|
||||
.up_tx_pll_locked (up_tx_pll_locked_s),
|
||||
.up_tx_rst (up_rst_s),
|
||||
.up_tx_user_ready (up_user_ready_s),
|
||||
.up_tx_rst_done (up_tx_rst_done_s),
|
||||
.up_tx_lpm_dfe_n (1'd0),
|
||||
.up_tx_rate (3'd0),
|
||||
.up_tx_sys_clk_sel (2'd0),
|
||||
.up_tx_out_clk_sel (3'd2),
|
||||
.up_tx_enb (1'd0),
|
||||
.up_tx_addr (12'd0),
|
||||
.up_tx_wr (1'd0),
|
||||
.up_tx_wdata (16'd0),
|
||||
.up_tx_rdata (),
|
||||
.up_tx_ready ());
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,16 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *d_xfer_state*}]
|
||||
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_xfer_toggle*}]
|
||||
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_rx_rst_done*}]
|
||||
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_tx_rst_done*}]
|
||||
|
||||
set_false_path -to [get_cells -hier -filter {name =~ *up_rx_rst_done_m1_reg && IS_SEQUENTIAL}]
|
||||
set_false_path -to [get_cells -hier -filter {name =~ *up_tx_rst_done_m1_reg && IS_SEQUENTIAL}]
|
||||
set_false_path -to [get_cells -hier -filter {name =~ *d_xfer_state_m1_reg && IS_SEQUENTIAL}]
|
||||
set_false_path -to [get_cells -hier -filter {name =~ *up_xfer_toggle_m1_reg && IS_SEQUENTIAL}]
|
||||
set_false_path -to [get_cells -hier -filter {name =~ *up_data_status* && IS_SEQUENTIAL}]
|
||||
|
||||
@@ -0,0 +1,73 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
source ../../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
global VIVADO_IP_LIBRARY
|
||||
|
||||
adi_ip_create axi_xcvrlb
|
||||
adi_ip_files axi_xcvrlb [list \
|
||||
"$ad_hdl_dir/library/xilinx/util_adxcvr/util_adxcvr_xch.v" \
|
||||
"$ad_hdl_dir/library/common/up_xfer_status.v" \
|
||||
"$ad_hdl_dir/library/common/ad_pnmon.v" \
|
||||
"$ad_hdl_dir/library/common/up_axi.v" \
|
||||
"axi_xcvrlb_constr.xdc" \
|
||||
"axi_xcvrlb_1.v" \
|
||||
"axi_xcvrlb.v" ]
|
||||
|
||||
adi_ip_properties_lite axi_xcvrlb
|
||||
|
||||
adi_init_bd_tcl
|
||||
adi_ip_bd axi_xcvrlb "bd/bd.tcl"
|
||||
|
||||
adi_ip_add_core_dependencies [list \
|
||||
analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \
|
||||
]
|
||||
|
||||
ipx::remove_all_bus_interface [ipx::current_core]
|
||||
|
||||
set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects [ipx::current_core]]
|
||||
|
||||
ipx::infer_bus_interface {\
|
||||
s_axi_awvalid \
|
||||
s_axi_awaddr \
|
||||
s_axi_awprot \
|
||||
s_axi_awready \
|
||||
s_axi_wvalid \
|
||||
s_axi_wdata \
|
||||
s_axi_wstrb \
|
||||
s_axi_wready \
|
||||
s_axi_bvalid \
|
||||
s_axi_bresp \
|
||||
s_axi_bready \
|
||||
s_axi_arvalid \
|
||||
s_axi_araddr \
|
||||
s_axi_arprot \
|
||||
s_axi_arready \
|
||||
s_axi_rvalid \
|
||||
s_axi_rdata \
|
||||
s_axi_rresp \
|
||||
s_axi_rready} \
|
||||
xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
|
||||
|
||||
ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
||||
|
||||
ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces s_axi_aclk \
|
||||
-of_objects [ipx::current_core]]
|
||||
set_property value s_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \
|
||||
-of_objects [ipx::get_bus_interfaces s_axi_aclk \
|
||||
-of_objects [ipx::current_core]]]
|
||||
|
||||
ipx::add_memory_map {s_axi} [ipx::current_core]
|
||||
set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
|
||||
ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]
|
||||
set_property range {1024} [ipx::get_address_blocks axi_lite \
|
||||
-of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]]
|
||||
|
||||
adi_add_auto_fpga_spec_params
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
@@ -0,0 +1,44 @@
|
||||
# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!
|
||||
proc init {cellpath otherInfo} {
|
||||
set ip [get_bd_cells $cellpath]
|
||||
|
||||
bd::mark_propagate_override $ip " \
|
||||
XCVR_TYPE"
|
||||
|
||||
adi_auto_assign_device_spec $cellpath
|
||||
}
|
||||
|
||||
# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)
|
||||
proc adi_auto_assign_device_spec {cellpath} {
|
||||
|
||||
set ip [get_bd_cells $cellpath]
|
||||
set ip_param_list [list_property $ip]
|
||||
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
|
||||
|
||||
set parent_dir "../"
|
||||
for {set x 1} {$x<=4} {incr x} {
|
||||
set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl
|
||||
if { [file exists $linkname] } {
|
||||
source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl
|
||||
break
|
||||
}
|
||||
append parent_dir "../"
|
||||
}
|
||||
|
||||
# Find predefindes auto assignable parameters
|
||||
foreach i $auto_set_param_list {
|
||||
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
|
||||
set val [adi_device_spec $cellpath $i]
|
||||
set_property CONFIG.$i $val $ip
|
||||
}
|
||||
}
|
||||
|
||||
# Find predefindes auto assignable/overwritable parameters
|
||||
foreach i $auto_set_param_list_overwritable {
|
||||
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
|
||||
set val [adi_device_spec $cellpath $i]
|
||||
set_property CONFIG.$i $val $ip
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,971 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>analog.com</spirit:vendor>
|
||||
<spirit:library>user</spirit:library>
|
||||
<spirit:name>axi_xcvrlb</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>s_axi</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave>
|
||||
<spirit:memoryMapRef spirit:memoryMapRef="s_axi"/>
|
||||
</spirit:slave>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>AWADDR</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axi_awaddr</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>AWPROT</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axi_awprot</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>AWVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axi_awvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
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|
||||
<xilinx:componentRef xilinx:vendor="analog.com" xilinx:library="user" xilinx:name="util_cdc" xilinx:version="1.0">
|
||||
<xilinx:mode xilinx:name="copy_mode"/>
|
||||
</xilinx:componentRef>
|
||||
</xilinx:subCoreRef>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>xgui/axi_xcvrlb_v1_0.tcl</spirit:name>
|
||||
<spirit:fileType>tclSource</spirit:fileType>
|
||||
<spirit:userFileType>CHECKSUM_b1ece077</spirit:userFileType>
|
||||
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset</spirit:name>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:subCoreRef>
|
||||
<xilinx:componentRef xilinx:vendor="analog.com" xilinx:library="user" xilinx:name="util_cdc" xilinx:version="1.0"/>
|
||||
</xilinx:subCoreRef>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_blockdiagram_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>bd/bd.tcl</spirit:name>
|
||||
<spirit:fileType>tclSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_blockdiagram_analog_com_user_util_cdc_1_0__ref_view_fileset</spirit:name>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:subCoreRef>
|
||||
<xilinx:componentRef xilinx:vendor="analog.com" xilinx:library="user" xilinx:name="util_cdc" xilinx:version="1.0"/>
|
||||
</xilinx:subCoreRef>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>axi_xcvrlb_v1_0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CPLL_FBDIV</spirit:name>
|
||||
<spirit:displayName>Cpll Fbdiv</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CPLL_FBDIV">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CPLL_FBDIV_4_5</spirit:name>
|
||||
<spirit:displayName>Cpll Fbdiv 4 5</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CPLL_FBDIV_4_5">5</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>NUM_OF_LANES</spirit:name>
|
||||
<spirit:displayName>Num Of Lanes</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_OF_LANES">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>XCVR_TYPE</spirit:name>
|
||||
<spirit:displayName>Xcvr Type</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.XCVR_TYPE" spirit:choiceRef="choice_pairs_07421b06">2</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">axi_xcvrlb_v1_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:supportedFamilies>
|
||||
<xilinx:family xilinx:lifeCycle="Production">virtex7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qvirtex7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">versal</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">kintex7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">kintex7l</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qkintex7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qkintex7l</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">akintex7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">artix7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">artix7l</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">aartix7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qartix7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qzynq</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">azynq</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">spartan7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">aspartan7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">virtexu</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">zynquplus</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">virtexuplus</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">virtexuplusHBM</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">virtexuplus58g</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">kintexuplus</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">artixuplus</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">kintexu</xilinx:family>
|
||||
</xilinx:supportedFamilies>
|
||||
<xilinx:taxonomies>
|
||||
<xilinx:taxonomy>/Analog_Devices</xilinx:taxonomy>
|
||||
</xilinx:taxonomies>
|
||||
<xilinx:displayName>axi_xcvrlb_v1_0</xilinx:displayName>
|
||||
<xilinx:autoFamilySupportLevel>level_2</xilinx:autoFamilySupportLevel>
|
||||
<xilinx:definitionSource>package_project</xilinx:definitionSource>
|
||||
<xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
|
||||
<xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
|
||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
||||
<xilinx:coreCreationDateTime>2024-01-14T03:57:51Z</xilinx:coreCreationDateTime>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="2fd94af6"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="b0d1cc30"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="8232f07a"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="48bfcb3f"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
@@ -0,0 +1,2 @@
|
||||
CLEAN_TARGET += bd
|
||||
CLEAN_TARGET += temporary_case_dependencies.mk
|
||||
@@ -0,0 +1,70 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "CPLL_FBDIV" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "CPLL_FBDIV_4_5" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "NUM_OF_LANES" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "XCVR_TYPE" -parent ${Page_0}
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.CPLL_FBDIV { PARAM_VALUE.CPLL_FBDIV } {
|
||||
# Procedure called to update CPLL_FBDIV when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.CPLL_FBDIV { PARAM_VALUE.CPLL_FBDIV } {
|
||||
# Procedure called to validate CPLL_FBDIV
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.CPLL_FBDIV_4_5 { PARAM_VALUE.CPLL_FBDIV_4_5 } {
|
||||
# Procedure called to update CPLL_FBDIV_4_5 when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.CPLL_FBDIV_4_5 { PARAM_VALUE.CPLL_FBDIV_4_5 } {
|
||||
# Procedure called to validate CPLL_FBDIV_4_5
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.NUM_OF_LANES { PARAM_VALUE.NUM_OF_LANES } {
|
||||
# Procedure called to update NUM_OF_LANES when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.NUM_OF_LANES { PARAM_VALUE.NUM_OF_LANES } {
|
||||
# Procedure called to validate NUM_OF_LANES
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.XCVR_TYPE { PARAM_VALUE.XCVR_TYPE } {
|
||||
# Procedure called to update XCVR_TYPE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.XCVR_TYPE { PARAM_VALUE.XCVR_TYPE } {
|
||||
# Procedure called to validate XCVR_TYPE
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.CPLL_FBDIV { MODELPARAM_VALUE.CPLL_FBDIV PARAM_VALUE.CPLL_FBDIV } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.CPLL_FBDIV}] ${MODELPARAM_VALUE.CPLL_FBDIV}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.CPLL_FBDIV_4_5 { MODELPARAM_VALUE.CPLL_FBDIV_4_5 PARAM_VALUE.CPLL_FBDIV_4_5 } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.CPLL_FBDIV_4_5}] ${MODELPARAM_VALUE.CPLL_FBDIV_4_5}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.NUM_OF_LANES { MODELPARAM_VALUE.NUM_OF_LANES PARAM_VALUE.NUM_OF_LANES } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.NUM_OF_LANES}] ${MODELPARAM_VALUE.NUM_OF_LANES}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.XCVR_TYPE { MODELPARAM_VALUE.XCVR_TYPE PARAM_VALUE.XCVR_TYPE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.XCVR_TYPE}] ${MODELPARAM_VALUE.XCVR_TYPE}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user