initial commit, add dds_par module
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// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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// serial data output interface: serdes(x8)
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`timescale 1ps/1ps
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module ad_serdes_out #(
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parameter FPGA_TECHNOLOGY = 0,
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parameter CMOS_LVDS_N = 0,
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parameter DDR_OR_SDR_N = 1,
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parameter SERDES_FACTOR = 8,
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parameter DATA_WIDTH = 16
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) (
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// reset and clocks
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input rst,
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input clk,
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input div_clk,
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// data interface
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input data_oe,
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input [(DATA_WIDTH-1):0] data_s0, // 1st bit to be transmitted
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input [(DATA_WIDTH-1):0] data_s1,
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input [(DATA_WIDTH-1):0] data_s2,
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input [(DATA_WIDTH-1):0] data_s3,
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input [(DATA_WIDTH-1):0] data_s4,
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input [(DATA_WIDTH-1):0] data_s5,
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input [(DATA_WIDTH-1):0] data_s6,
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input [(DATA_WIDTH-1):0] data_s7, // last bit to be transmitted
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output [(DATA_WIDTH-1):0] data_out_se,
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output [(DATA_WIDTH-1):0] data_out_p,
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output [(DATA_WIDTH-1):0] data_out_n
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);
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localparam SEVEN_SERIES = 1;
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localparam ULTRASCALE = 2;
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localparam ULTRASCALE_PLUS = 3;
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localparam DR_OQ_DDR = DDR_OR_SDR_N == 1'b1 ? "DDR": "SDR";
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localparam SIM_DEVICE = FPGA_TECHNOLOGY == SEVEN_SERIES ? "7SERIES" :
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FPGA_TECHNOLOGY == ULTRASCALE ? "ULTRASCALE" :
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FPGA_TECHNOLOGY == ULTRASCALE_PLUS ? "ULTRASCALE_PLUS" :
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"UNSUPPORTED";
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// internal registers
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reg [6:0] serdes_rst_seq;
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// internal signals
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wire [(DATA_WIDTH-1):0] data_out_s;
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wire [(DATA_WIDTH-1):0] serdes_shift1_s;
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wire [(DATA_WIDTH-1):0] serdes_shift2_s;
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wire [(DATA_WIDTH-1):0] data_t;
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wire buffer_disable;
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wire serdes_rst = serdes_rst_seq[6];
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// instantiations
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assign data_out_se = data_out_s;
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assign buffer_disable = ~data_oe;
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always @ (posedge div_clk) begin
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if (rst) begin
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serdes_rst_seq [6:0] <= 7'b0001110;
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end else begin
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serdes_rst_seq [6:0] <= {serdes_rst_seq [5:0], 1'b0};
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end
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end
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// transmit data path: oserdes -> obuf
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genvar l_inst;
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generate
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for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_data
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// oserdes
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if (FPGA_TECHNOLOGY == SEVEN_SERIES) begin
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OSERDESE2 #(
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.DATA_RATE_OQ (DR_OQ_DDR),
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.DATA_RATE_TQ ("SDR"),
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.DATA_WIDTH (SERDES_FACTOR),
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.TRISTATE_WIDTH (1),
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.SERDES_MODE ("MASTER")
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) i_serdes (
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.D1 (data_s0[l_inst]),
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.D2 (data_s1[l_inst]),
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.D3 (data_s2[l_inst]),
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.D4 (data_s3[l_inst]),
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.D5 (data_s4[l_inst]),
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.D6 (data_s5[l_inst]),
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.D7 (data_s6[l_inst]),
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.D8 (data_s7[l_inst]),
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.T1 (buffer_disable),
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.T2 (buffer_disable),
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.T3 (buffer_disable),
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.T4 (buffer_disable),
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.SHIFTIN1 (1'b0),
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.SHIFTIN2 (1'b0),
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.SHIFTOUT1 (),
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.SHIFTOUT2 (),
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.OCE (1'b1),
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.CLK (clk),
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.CLKDIV (div_clk),
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.OQ (data_out_s[l_inst]),
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.TQ (data_t[l_inst]),
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.OFB (),
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.TFB (),
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.TBYTEIN (1'b0),
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.TBYTEOUT (),
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.TCE (1'b1),
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.RST (serdes_rst));
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end
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if (FPGA_TECHNOLOGY == ULTRASCALE || FPGA_TECHNOLOGY == ULTRASCALE_PLUS) begin
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OSERDESE3 #(
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.DATA_WIDTH (SERDES_FACTOR),
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.SIM_DEVICE (SIM_DEVICE)
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) i_serdes (
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.D ({data_s7[l_inst],
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data_s6[l_inst],
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data_s5[l_inst],
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data_s4[l_inst],
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data_s3[l_inst],
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data_s2[l_inst],
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data_s1[l_inst],
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data_s0[l_inst]}),
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.T (buffer_disable),
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.CLK (clk),
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.CLKDIV (div_clk),
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.OQ (data_out_s[l_inst]),
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.T_OUT (data_t[l_inst]),
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.RST (serdes_rst));
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end
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// obuf
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if (CMOS_LVDS_N == 0) begin
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OBUFTDS i_obuftds (
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.T (data_t[l_inst]),
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.I (data_out_s[l_inst]),
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.O (data_out_p[l_inst]),
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.OB (data_out_n[l_inst]));
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end else begin
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OBUFT i_obuf (
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.T (data_t[l_inst]),
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.I (data_out_s[l_inst]),
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.O (data_out_p[l_inst]));
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end
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end
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endgenerate
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endmodule
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