initial commit, add dds_par module
This commit is contained in:
@@ -0,0 +1,26 @@
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####################################################################################
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## Copyright (c) 2018 - 2023 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := util_adxcvr
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XILINX_DEPS += ../../jesd204/jesd204_common/sync_header_align.v
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XILINX_DEPS += bd/bd.tcl
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XILINX_DEPS += util_adxcvr.v
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XILINX_DEPS += util_adxcvr_constr.xdc
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XILINX_DEPS += util_adxcvr_ip.tcl
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XILINX_DEPS += util_adxcvr_xch.v
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XILINX_DEPS += util_adxcvr_xcm.v
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XILINX_DEPS += ../../interfaces/if_xcvr_ch.xml
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XILINX_DEPS += ../../interfaces/if_xcvr_ch_rtl.xml
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XILINX_DEPS += ../../interfaces/if_xcvr_cm.xml
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XILINX_DEPS += ../../interfaces/if_xcvr_cm_rtl.xml
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XILINX_LIB_DEPS += util_cdc
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XILINX_INTERFACE_DEPS += interfaces
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include ../../scripts/library.mk
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@@ -0,0 +1,49 @@
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###############################################################################
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## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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proc init {cellpath otherInfo} {
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set ip [get_bd_cells $cellpath]
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bd::mark_propagate_override $ip " \
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XCVR_TYPE CH_HSPMUX PPF0_CFG RXPI_CFG0 RXPI_CFG1 RTX_BUF_CML_CTRL \
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QPLL_LPF RXCDR_CFG3_GEN2 RXCDR_CFG3_GEN3 RXCDR_CFG3_GEN4 TX_PI_BIASSET"
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adi_auto_assign_device_spec $cellpath
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}
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# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)
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proc adi_auto_assign_device_spec {cellpath} {
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set ip [get_bd_cells $cellpath]
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set ip_param_list [list_property $ip]
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set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
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set parent_dir "../"
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for {set x 1} {$x<=4} {incr x} {
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set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl
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if { [file exists $linkname] } {
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source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl
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break
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}
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append parent_dir "../"
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}
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# Find predefindes auto assignable parameters
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foreach i $auto_set_param_list {
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if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
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set val [adi_device_spec $cellpath $i]
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set_property CONFIG.$i $val $ip
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}
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}
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# Find predefindes auto assignable/overwritable parameters
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foreach i $auto_set_param_list_overwritable {
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if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
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set val [adi_device_spec $cellpath $i]
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set_property CONFIG.$i $val $ip
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}
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}
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}
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,12 @@
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# This file is automatically written. Do not modify.
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proc gen_USERPARAMETER_DATA_PATH_WIDTH_ENABLEMENT {LINK_MODE } {expr $LINK_MODE==1}
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proc gen_USERPARAMETER_DATA_PATH_WIDTH_VALUE {LINK_MODE } {expr $LINK_MODE*4}
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proc gen_USERPARAMETER_PPF0_CFG_VALUE {XCVR_TYPE } {expr [format "0x%x" [expr {$XCVR_TYPE == 9} ? 0x800 : 0x600]]}
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proc gen_USERPARAMETER_QPLL_LPF_VALUE {XCVR_TYPE } {expr [format "0x%x" [expr {$XCVR_TYPE == 9} ? 0x37f : 0x137]]}
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proc gen_USERPARAMETER_CH_HSPMUX_VALUE {XCVR_TYPE } {expr [format "0x%x" [expr {$XCVR_TYPE == 8} ? 0x2424 : {$XCVR_TYPE == 9} ? 0x2020 : 0x0]]}
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proc gen_USERPARAMETER_RXPI_CFG0_VALUE {XCVR_TYPE } {expr [format "0x%x" [expr {$XCVR_TYPE == 8} ? 0x2 : {$XCVR_TYPE == 9} ? 0x100 : 0x0]]}
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proc gen_USERPARAMETER_RXPI_CFG1_VALUE {XCVR_TYPE } {expr [format "0x%x" [expr {$XCVR_TYPE == 8} ? 0x15 : 0x0]]}
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proc gen_USERPARAMETER_RTX_BUF_CML_CTRL_VALUE {XCVR_TYPE } {expr [format "0x%x" [expr {$XCVR_TYPE == 9} ? 0x3 : 0x0]]}
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proc gen_USERPARAMETER_TX_PI_BIASSET_VALUE {XCVR_TYPE } {expr {$XCVR_TYPE == 9} ? 0 : 1}
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proc gen_USERPARAMETER_RXCDR_CFG3_GEN2_VALUE {XCVR_TYPE } {expr [format "0x%x" [expr {$XCVR_TYPE == 9} ? 0x12 : 0x1a ]]}
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proc gen_USERPARAMETER_RXCDR_CFG3_GEN4_VALUE {XCVR_TYPE } {expr [format "0x%x" [expr {$XCVR_TYPE == 9} ? 0x12 : 0x24 ]]}
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,440 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
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<!-- -->
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<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
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<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
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<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/xilinx/util_adxcvr/util_adxcvr.xpr">
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||||
<DefaultLaunch Dir="$PRUNDIR"/>
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||||
<Configuration>
|
||||
<Option Name="Id" Val="f878f19e3bc741f591d4c52ce47e0e6e"/>
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||||
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
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||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorVersionXsim" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
|
||||
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
|
||||
<Option Name="SimulatorVersionRiviera" Val="2022.10"/>
|
||||
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
|
||||
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
|
||||
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../library"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="EnableResourceEstimation" Val="FALSE"/>
|
||||
<Option Name="SimCompileState" Val="TRUE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
||||
<Option Name="ClassicSocBoot" Val="FALSE"/>
|
||||
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="32">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../../jesd204/jesd204_common/sync_header_align.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
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||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/util_adxcvr_xch.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/util_adxcvr_xcm.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/util_adxcvr.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../scripts/adi_xilinx_device_info_enc.tcl">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/bd/bd.tcl">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/component.xml">
|
||||
<FileInfo SFType="IPXACT"/>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="util_adxcvr"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PPRDIR/util_adxcvr_constr.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||
<Option Name="PamDesignTestbench" Val=""/>
|
||||
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
||||
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="21">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="1"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="features"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="should"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="NOT"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="be"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="used"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="in"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="production"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="systems."/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="10"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Place 30-73"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="11"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val=""/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="12"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1343"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="2"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1306"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="3"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="ERROR"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1276"/>
|
||||
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="4"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="5"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-2490"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
</Project>
|
||||
@@ -0,0 +1,44 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
set_property ASYNC_REG TRUE -quiet [get_cells -hier -filter {name =~ *up_rx_rst_done*}]
|
||||
set_property ASYNC_REG TRUE -quiet [get_cells -hier -filter {name =~ *up_tx_rst_done*}]
|
||||
set_property ASYNC_REG TRUE -quiet [get_cells -hier -filter {name =~ *rx_rate*}]
|
||||
set_property ASYNC_REG TRUE -quiet [get_cells -hier -filter {name =~ *tx_rate*}]
|
||||
|
||||
set_false_path -to [get_cells -hier -filter {name =~ *up_rx_rst_done_m1_reg && IS_SEQUENTIAL}]
|
||||
set_false_path -to [get_cells -hier -filter {name =~ *up_tx_rst_done_m1_reg && IS_SEQUENTIAL}]
|
||||
set_false_path -to [get_cells -hier -filter {name =~ *rx_rate_m1_reg* && IS_SEQUENTIAL}]
|
||||
set_false_path -to [get_cells -hier -filter {name =~ *tx_rate_m1_reg* && IS_SEQUENTIAL}]
|
||||
|
||||
# sync bits i_sync_bits_tx_prbs_in
|
||||
set_false_path \
|
||||
-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
|
||||
-filter {NAME =~ *i_sync_bits_tx_prbs_in* && IS_SEQUENTIAL}
|
||||
]
|
||||
|
||||
# sync bits i_sync_bits_rx_prbs_in
|
||||
set_false_path \
|
||||
-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
|
||||
-filter {NAME =~ *i_sync_bits_rx_prbs_in* && IS_SEQUENTIAL}
|
||||
]
|
||||
|
||||
# sync bits i_sync_bits_rx_prbs_out
|
||||
set_false_path \
|
||||
-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
|
||||
-filter {NAME =~ *i_sync_bits_rx_prbs_out* && IS_SEQUENTIAL}
|
||||
]
|
||||
|
||||
# sync bits i_sync_bits_rx_bufstatus_in
|
||||
set_false_path \
|
||||
-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
|
||||
-filter {NAME =~ *i_sync_bits_rx_bufstatus_in* && IS_SEQUENTIAL}
|
||||
]
|
||||
|
||||
# sync bits i_sync_bits_bufstatus_out
|
||||
set_false_path \
|
||||
-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
|
||||
-filter {NAME =~ *i_sync_bits_bufstatus_out* && IS_SEQUENTIAL}]
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,740 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module util_adxcvr_xcm #(
|
||||
|
||||
// parameters
|
||||
|
||||
parameter integer XCVR_TYPE = 0,
|
||||
parameter integer QPLL_REFCLK_DIV = 1,
|
||||
parameter integer QPLL_FBDIV_RATIO = 1,
|
||||
parameter [15:0] POR_CFG = 16'b0000000000000110,
|
||||
parameter [15:0] PPF0_CFG = 16'b0000011000000000,
|
||||
parameter [15:0] PPF1_CFG = 16'b0000011000000000,
|
||||
parameter [26:0] QPLL_CFG = 27'h0680181,
|
||||
parameter [ 9:0] QPLL_FBDIV = 10'b0000110000,
|
||||
parameter [15:0] QPLL_CFG0 = 16'b0011001100011100,
|
||||
parameter [15:0] QPLL_CFG1 = 16'b1101000000111000,
|
||||
parameter [15:0] QPLL_CFG1_G3 = 16'b1101000000111000,
|
||||
parameter [15:0] QPLL_CFG2 = 16'b0000111111000000,
|
||||
parameter [15:0] QPLL_CFG2_G3 = 16'b0000111111000000,
|
||||
parameter [15:0] QPLL_CFG3 = 16'b0000000100100000,
|
||||
parameter [15:0] QPLL_CFG4 = 16'b0000000000000011,
|
||||
parameter [15:0] QPLL_CP_G3 = 10'b0000011111,
|
||||
parameter [15:0] QPLL_LPF = 10'b0100110111,
|
||||
parameter [15:0] QPLL_CP = 10'b0001111111
|
||||
) (
|
||||
|
||||
// reset and clocks
|
||||
|
||||
input qpll_ref_clk,
|
||||
input qpll_sel,
|
||||
output qpll2ch_clk,
|
||||
output qpll2ch_ref_clk,
|
||||
output qpll2ch_locked,
|
||||
|
||||
output qpll1_clk,
|
||||
output qpll1_ref_clk,
|
||||
output qpll1_locked,
|
||||
|
||||
// drp interface
|
||||
|
||||
input up_rstn,
|
||||
input up_clk,
|
||||
input up_qpll_rst,
|
||||
input up_cm_enb,
|
||||
input [11:0] up_cm_addr,
|
||||
input up_cm_wr,
|
||||
input [15:0] up_cm_wdata,
|
||||
output [15:0] up_cm_rdata,
|
||||
output up_cm_ready
|
||||
);
|
||||
|
||||
localparam GTXE2_TRANSCEIVERS = 2;
|
||||
localparam GTHE3_TRANSCEIVERS = 5;
|
||||
localparam GTHE4_TRANSCEIVERS = 8;
|
||||
localparam GTYE4_TRANSCEIVERS = 9;
|
||||
|
||||
// internal registers
|
||||
|
||||
reg up_enb_int = 'd0;
|
||||
reg [11:0] up_addr_int = 'd0;
|
||||
reg up_wr_int = 'd0;
|
||||
reg [15:0] up_wdata_int = 'd0;
|
||||
reg [15:0] up_rdata_int = 'd0;
|
||||
reg up_ready_int = 'd0;
|
||||
reg up_sel_int = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [15:0] up_rdata_s;
|
||||
wire up_ready_s;
|
||||
|
||||
// drp access
|
||||
|
||||
assign up_cm_rdata = up_rdata_int;
|
||||
assign up_cm_ready = up_ready_int;
|
||||
|
||||
always @(negedge up_rstn or posedge up_clk) begin
|
||||
if (up_rstn == 1'b0) begin
|
||||
up_enb_int <= 1'd0;
|
||||
up_addr_int <= 12'd0;
|
||||
up_wr_int <= 1'd0;
|
||||
up_wdata_int <= 16'd0;
|
||||
up_rdata_int <= 16'd0;
|
||||
up_ready_int <= 1'd0;
|
||||
up_sel_int <= 1'b0;
|
||||
end else begin
|
||||
if (up_cm_enb == 1'b1) begin
|
||||
up_enb_int <= up_cm_enb;
|
||||
up_addr_int <= up_cm_addr;
|
||||
up_wr_int <= up_cm_wr;
|
||||
up_wdata_int <= up_cm_wdata;
|
||||
end else begin
|
||||
up_enb_int <= 1'd0;
|
||||
up_addr_int <= 12'd0;
|
||||
up_wr_int <= 1'd0;
|
||||
up_wdata_int <= 16'd0;
|
||||
end
|
||||
|
||||
if (up_cm_enb == 1'b1) begin
|
||||
up_sel_int <= 1'b1;
|
||||
end else if (up_ready_s == 1'b1) begin
|
||||
up_sel_int <= 1'b0;
|
||||
end
|
||||
|
||||
if (up_sel_int == 1'b1) begin
|
||||
up_ready_int <= up_ready_s;
|
||||
up_rdata_int <= up_rdata_s;
|
||||
end else begin
|
||||
up_ready_int <= 1'b0;
|
||||
up_rdata_int <= 'h00;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// instantiations
|
||||
|
||||
generate
|
||||
if (XCVR_TYPE == GTXE2_TRANSCEIVERS) begin
|
||||
assign qpll1_locked = 1'b0;
|
||||
assign qpll1_clk = 1'b0;
|
||||
assign qpll1_ref_clk = 1'b0;
|
||||
GTXE2_COMMON #(
|
||||
.BIAS_CFG (64'h0000040000001000),
|
||||
.COMMON_CFG (32'h00000000),
|
||||
.IS_DRPCLK_INVERTED (1'b0),
|
||||
.IS_GTGREFCLK_INVERTED (1'b0),
|
||||
.IS_QPLLLOCKDETCLK_INVERTED (1'b0),
|
||||
.QPLL_CFG (QPLL_CFG),
|
||||
.QPLL_CLKOUT_CFG (4'b0000),
|
||||
.QPLL_COARSE_FREQ_OVRD (6'b010000),
|
||||
.QPLL_COARSE_FREQ_OVRD_EN (1'b0),
|
||||
.QPLL_CP (10'b0000011111),
|
||||
.QPLL_CP_MONITOR_EN (1'b0),
|
||||
.QPLL_DMONITOR_SEL (1'b0),
|
||||
.QPLL_FBDIV (QPLL_FBDIV),
|
||||
.QPLL_FBDIV_MONITOR_EN (1'b0),
|
||||
.QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO),
|
||||
.QPLL_INIT_CFG (24'h000006),
|
||||
.QPLL_LOCK_CFG (16'h21E8),
|
||||
.QPLL_LPF (4'b1111),
|
||||
.QPLL_REFCLK_DIV (QPLL_REFCLK_DIV),
|
||||
.SIM_QPLLREFCLK_SEL (3'b001),
|
||||
.SIM_RESET_SPEEDUP ("TRUE"),
|
||||
.SIM_VERSION ("4.0"))
|
||||
i_gtxe2_common (
|
||||
.QPLLDMONITOR (),
|
||||
.QPLLFBCLKLOST (),
|
||||
.REFCLKOUTMONITOR (),
|
||||
.BGBYPASSB (1'h1),
|
||||
.BGMONITORENB (1'h1),
|
||||
.BGPDB (1'h1),
|
||||
.BGRCALOVRD (5'h1f),
|
||||
.DRPADDR (up_addr_int[7:0]),
|
||||
.DRPCLK (up_clk),
|
||||
.DRPDI (up_wdata_int),
|
||||
.DRPDO (up_rdata_s),
|
||||
.DRPEN (up_enb_int),
|
||||
.DRPRDY (up_ready_s),
|
||||
.DRPWE (up_wr_int),
|
||||
.GTGREFCLK (1'h0),
|
||||
.GTNORTHREFCLK0 (1'h0),
|
||||
.GTNORTHREFCLK1 (1'h0),
|
||||
.GTREFCLK0 (qpll_ref_clk),
|
||||
.GTREFCLK1 (1'h0),
|
||||
.GTSOUTHREFCLK0 (1'h0),
|
||||
.GTSOUTHREFCLK1 (1'h0),
|
||||
.PMARSVD (8'h0),
|
||||
.QPLLLOCK (qpll2ch_locked),
|
||||
.QPLLLOCKDETCLK (up_clk),
|
||||
.QPLLLOCKEN (1'h1),
|
||||
.QPLLOUTCLK (qpll2ch_clk),
|
||||
.QPLLOUTREFCLK (qpll2ch_ref_clk),
|
||||
.QPLLOUTRESET (1'h0),
|
||||
.QPLLPD (1'h0),
|
||||
.QPLLREFCLKLOST (),
|
||||
.QPLLREFCLKSEL (3'h1),
|
||||
.QPLLRESET (up_qpll_rst),
|
||||
.QPLLRSVD1 (16'h0),
|
||||
.QPLLRSVD2 (5'h1f),
|
||||
.RCALENB (1'h1));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
if (XCVR_TYPE == GTHE3_TRANSCEIVERS) begin
|
||||
GTHE3_COMMON #(
|
||||
.BIAS_CFG0 (16'h0000),
|
||||
.BIAS_CFG1 (16'h0000),
|
||||
.BIAS_CFG2 (16'h0000),
|
||||
.BIAS_CFG3 (16'h0040),
|
||||
.BIAS_CFG4 (16'h0000),
|
||||
.BIAS_CFG_RSVD (10'b0000000000),
|
||||
.COMMON_CFG0 (16'h0000),
|
||||
.COMMON_CFG1 (16'h0000),
|
||||
.POR_CFG (16'h0004),
|
||||
.QPLL0_CFG0 (16'h321c),
|
||||
.QPLL0_CFG1 (16'h1018),
|
||||
.QPLL0_CFG1_G3 (16'h1018),
|
||||
.QPLL0_CFG2 (16'h0048),
|
||||
.QPLL0_CFG2_G3 (16'h0048),
|
||||
.QPLL0_CFG3 (16'h0120),
|
||||
.QPLL0_CFG4 (16'h0000),
|
||||
.QPLL0_CP (10'b0000011111),
|
||||
.QPLL0_CP_G3 (10'b1111111111),
|
||||
.QPLL0_FBDIV (QPLL_FBDIV),
|
||||
.QPLL0_FBDIV_G3 (80),
|
||||
.QPLL0_INIT_CFG0 (16'h02b2),
|
||||
.QPLL0_INIT_CFG1 (8'h00),
|
||||
.QPLL0_LOCK_CFG (16'h21e8),
|
||||
.QPLL0_LOCK_CFG_G3 (16'h21e8),
|
||||
.QPLL0_LPF (10'b1111111111),
|
||||
.QPLL0_LPF_G3 (10'b0000010101),
|
||||
.QPLL0_REFCLK_DIV (QPLL_REFCLK_DIV),
|
||||
.QPLL0_SDM_CFG0 (16'b0000000000000000),
|
||||
.QPLL0_SDM_CFG1 (16'b0000000000000000),
|
||||
.QPLL0_SDM_CFG2 (16'b0000000000000000),
|
||||
.QPLL1_CFG0 (16'h321c),
|
||||
.QPLL1_CFG1 (16'h1018),
|
||||
.QPLL1_CFG1_G3 (16'h1018),
|
||||
.QPLL1_CFG2 (16'h0040),
|
||||
.QPLL1_CFG2_G3 (16'h0040),
|
||||
.QPLL1_CFG3 (16'h0120),
|
||||
.QPLL1_CFG4 (16'h0000),
|
||||
.QPLL1_CP (10'b0000011111),
|
||||
.QPLL1_CP_G3 (10'b1111111111),
|
||||
.QPLL1_FBDIV (QPLL_FBDIV),
|
||||
.QPLL1_FBDIV_G3 (80),
|
||||
.QPLL1_INIT_CFG0 (16'h02b2),
|
||||
.QPLL1_INIT_CFG1 (8'h00),
|
||||
.QPLL1_LOCK_CFG (16'h21e8),
|
||||
.QPLL1_LOCK_CFG_G3 (16'h21e8),
|
||||
.QPLL1_LPF (10'b1111111111),
|
||||
.QPLL1_LPF_G3 (10'b0000010101),
|
||||
.QPLL1_REFCLK_DIV (QPLL_REFCLK_DIV),
|
||||
.QPLL1_SDM_CFG0 (16'b0000000000000000),
|
||||
.QPLL1_SDM_CFG1 (16'b0000000000000000),
|
||||
.QPLL1_SDM_CFG2 (16'b0000000000000000),
|
||||
.RSVD_ATTR0 (16'h0000),
|
||||
.RSVD_ATTR1 (16'h0000),
|
||||
.RSVD_ATTR2 (16'h0000),
|
||||
.RSVD_ATTR3 (16'h0000),
|
||||
.RXRECCLKOUT0_SEL (2'b00),
|
||||
.RXRECCLKOUT1_SEL (2'b00),
|
||||
.SARC_EN (1'b1),
|
||||
.SARC_SEL (1'b0),
|
||||
.SDM0DATA1_0 (16'b0000000000000000),
|
||||
.SDM0DATA1_1 (9'b000000000),
|
||||
.SDM0INITSEED0_0 (16'b0000000000000000),
|
||||
.SDM0INITSEED0_1 (9'b000000000),
|
||||
.SDM0_DATA_PIN_SEL (1'b0),
|
||||
.SDM0_WIDTH_PIN_SEL (1'b0),
|
||||
.SDM1DATA1_0 (16'b0000000000000000),
|
||||
.SDM1DATA1_1 (9'b000000000),
|
||||
.SDM1INITSEED0_0 (16'b0000000000000000),
|
||||
.SDM1INITSEED0_1 (9'b000000000),
|
||||
.SDM1_DATA_PIN_SEL (1'b0),
|
||||
.SDM1_WIDTH_PIN_SEL (1'b0),
|
||||
.SIM_MODE ("FAST"),
|
||||
.SIM_RESET_SPEEDUP ("TRUE"),
|
||||
.SIM_VERSION (2))
|
||||
i_gthe3_common (
|
||||
.BGBYPASSB (1'h1),
|
||||
.BGMONITORENB (1'h1),
|
||||
.BGPDB (1'h1),
|
||||
.BGRCALOVRD (5'h1f),
|
||||
.BGRCALOVRDENB (1'h1),
|
||||
.DRPADDR (up_addr_int[8:0]),
|
||||
.DRPCLK (up_clk),
|
||||
.DRPDI (up_wdata_int),
|
||||
.DRPDO (up_rdata_s),
|
||||
.DRPEN (up_enb_int),
|
||||
.DRPRDY (up_ready_s),
|
||||
.DRPWE (up_wr_int),
|
||||
.GTGREFCLK0 (1'h0),
|
||||
.GTGREFCLK1 (1'h0),
|
||||
.GTNORTHREFCLK00 (1'h0),
|
||||
.GTNORTHREFCLK01 (1'h0),
|
||||
.GTNORTHREFCLK10 (1'h0),
|
||||
.GTNORTHREFCLK11 (1'h0),
|
||||
.GTREFCLK00 (qpll_ref_clk),
|
||||
.GTREFCLK01 (1'h0),
|
||||
.GTREFCLK10 (1'h0),
|
||||
.GTREFCLK11 (1'h0),
|
||||
.GTSOUTHREFCLK00 (1'h0),
|
||||
.GTSOUTHREFCLK01 (1'h0),
|
||||
.GTSOUTHREFCLK10 (1'h0),
|
||||
.GTSOUTHREFCLK11 (1'h0),
|
||||
.PMARSVD0 (8'h0),
|
||||
.PMARSVD1 (8'h0),
|
||||
.PMARSVDOUT0 (),
|
||||
.PMARSVDOUT1 (),
|
||||
.QPLL0CLKRSVD0 (1'h0),
|
||||
.QPLL0CLKRSVD1 (1'h0),
|
||||
.QPLL0FBCLKLOST (),
|
||||
.QPLL0LOCK (qpll2ch_locked),
|
||||
.QPLL0LOCKDETCLK (up_clk),
|
||||
.QPLL0LOCKEN (1'h1),
|
||||
.QPLL0OUTCLK (qpll2ch_clk),
|
||||
.QPLL0OUTREFCLK (qpll2ch_ref_clk),
|
||||
.QPLL0PD (1'h0),
|
||||
.QPLL0REFCLKLOST (),
|
||||
.QPLL0REFCLKSEL (3'h1),
|
||||
.QPLL0RESET (up_qpll_rst),
|
||||
.QPLL1CLKRSVD0 (1'h0),
|
||||
.QPLL1CLKRSVD1 (1'h0),
|
||||
.QPLL1FBCLKLOST (),
|
||||
.QPLL1LOCK (qpll1_locked),
|
||||
.QPLL1LOCKDETCLK (up_clk),
|
||||
.QPLL1LOCKEN (1'h1),
|
||||
.QPLL1OUTCLK (qpll1_clk),
|
||||
.QPLL1OUTREFCLK (qpll1_ref_clk),
|
||||
.QPLL1PD (~qpll_sel),
|
||||
.QPLL1REFCLKLOST (),
|
||||
.QPLL1REFCLKSEL (3'h1),
|
||||
.QPLL1RESET (up_qpll_rst),
|
||||
.QPLLDMONITOR0 (),
|
||||
.QPLLDMONITOR1 (),
|
||||
.QPLLRSVD1 (8'h0),
|
||||
.QPLLRSVD2 (5'h0),
|
||||
.QPLLRSVD3 (5'h0),
|
||||
.QPLLRSVD4 (8'h0),
|
||||
.RCALENB (1'h1),
|
||||
.REFCLKOUTMONITOR0 (),
|
||||
.REFCLKOUTMONITOR1 (),
|
||||
.RXRECCLK0_SEL (),
|
||||
.RXRECCLK1_SEL ());
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
if (XCVR_TYPE == GTHE4_TRANSCEIVERS) begin
|
||||
GTHE4_COMMON #(
|
||||
.AEN_QPLL0_FBDIV (1'b1),
|
||||
.AEN_QPLL1_FBDIV (1'b1),
|
||||
.AEN_SDM0TOGGLE (1'b0),
|
||||
.AEN_SDM1TOGGLE (1'b0),
|
||||
.A_SDM0TOGGLE (1'b0),
|
||||
.A_SDM1DATA_HIGH (9'b000000000),
|
||||
.A_SDM1DATA_LOW (16'b0000000000000000),
|
||||
.A_SDM1TOGGLE (1'b0),
|
||||
.BIAS_CFG0 (16'b0000000000000000),
|
||||
.BIAS_CFG1 (16'b0000000000000000),
|
||||
.BIAS_CFG2 (16'b0000000100100100),
|
||||
.BIAS_CFG3 (16'b0000000001000001),
|
||||
.BIAS_CFG4 (16'b0000000000010000),
|
||||
.BIAS_CFG_RSVD (16'b0000000000000000),
|
||||
.COMMON_CFG0 (16'b0000000000000000),
|
||||
.COMMON_CFG1 (16'b0000000000000000),
|
||||
.POR_CFG (POR_CFG),
|
||||
.PPF0_CFG (PPF0_CFG),
|
||||
.PPF1_CFG (PPF1_CFG),
|
||||
.QPLL0CLKOUT_RATE ("HALF"),
|
||||
.QPLL0_CFG0 (QPLL_CFG0),
|
||||
.QPLL0_CFG1 (QPLL_CFG1),
|
||||
.QPLL0_CFG1_G3 (QPLL_CFG1_G3),
|
||||
.QPLL0_CFG2 (QPLL_CFG2),
|
||||
.QPLL0_CFG2_G3 (QPLL_CFG2_G3),
|
||||
.QPLL0_CFG3 (QPLL_CFG3),
|
||||
.QPLL0_CFG4 (QPLL_CFG4),
|
||||
.QPLL0_CP (QPLL_CP),
|
||||
.QPLL0_CP_G3 (QPLL_CP_G3),
|
||||
.QPLL0_FBDIV (QPLL_FBDIV),
|
||||
.QPLL0_FBDIV_G3 (160),
|
||||
.QPLL0_INIT_CFG0 (16'b0000001010110010),
|
||||
.QPLL0_INIT_CFG1 (8'b00000000),
|
||||
.QPLL0_LOCK_CFG (16'b0010010111101000),
|
||||
.QPLL0_LOCK_CFG_G3 (16'b0010010111101000),
|
||||
.QPLL0_LPF (QPLL_LPF),
|
||||
.QPLL0_LPF_G3 (10'b0111010101),
|
||||
.QPLL0_PCI_EN (1'b0),
|
||||
.QPLL0_RATE_SW_USE_DRP (1'b1),
|
||||
.QPLL0_REFCLK_DIV (QPLL_REFCLK_DIV),
|
||||
.QPLL0_SDM_CFG0 (16'b0000000010000000),
|
||||
.QPLL0_SDM_CFG1 (16'b0000000000000000),
|
||||
.QPLL0_SDM_CFG2 (16'b0000000000000000),
|
||||
.QPLL1CLKOUT_RATE ("HALF"),
|
||||
.QPLL1_CFG0 (QPLL_CFG0),
|
||||
.QPLL1_CFG1 (QPLL_CFG1),
|
||||
.QPLL1_CFG1_G3 (QPLL_CFG1_G3),
|
||||
.QPLL1_CFG2 (QPLL_CFG2),
|
||||
.QPLL1_CFG2_G3 (QPLL_CFG2_G3),
|
||||
.QPLL1_CFG3 (QPLL_CFG3),
|
||||
.QPLL1_CFG4 (QPLL_CFG4),
|
||||
.QPLL1_CP (10'b1111111111),
|
||||
.QPLL1_CP_G3 (10'b0011111111),
|
||||
.QPLL1_FBDIV (QPLL_FBDIV),
|
||||
.QPLL1_FBDIV_G3 (80),
|
||||
.QPLL1_INIT_CFG0 (16'b0000001010110010),
|
||||
.QPLL1_INIT_CFG1 (8'b00000000),
|
||||
.QPLL1_LOCK_CFG (16'b0010010111101000),
|
||||
.QPLL1_LOCK_CFG_G3 (16'b0010010111101000),
|
||||
.QPLL1_LPF (10'b0100110101),
|
||||
.QPLL1_LPF_G3 (10'b0111010100),
|
||||
.QPLL1_PCI_EN (1'b0),
|
||||
.QPLL1_RATE_SW_USE_DRP (1'b1),
|
||||
.QPLL1_REFCLK_DIV (QPLL_REFCLK_DIV),
|
||||
.QPLL1_SDM_CFG0 (16'b0000000010000000),
|
||||
.QPLL1_SDM_CFG1 (16'b0000000000000000),
|
||||
.QPLL1_SDM_CFG2 (16'b0000000000000000),
|
||||
.RSVD_ATTR0 (16'b0000000000000000),
|
||||
.RSVD_ATTR1 (16'b0000000000000000),
|
||||
.RSVD_ATTR2 (16'b0000000000000000),
|
||||
.RSVD_ATTR3 (16'b0000000000000000),
|
||||
.RXRECCLKOUT0_SEL (2'b00),
|
||||
.RXRECCLKOUT1_SEL (2'b00),
|
||||
.SARC_ENB (1'b0),
|
||||
.SARC_SEL (1'b0),
|
||||
.SDM0INITSEED0_0 (16'b0000000100010001),
|
||||
.SDM0INITSEED0_1 (9'b000010001),
|
||||
.SDM1INITSEED0_0 (16'b0000000100010001),
|
||||
.SDM1INITSEED0_1 (9'b000010001),
|
||||
.SIM_MODE ("FAST"),
|
||||
.SIM_RESET_SPEEDUP ("TRUE"))
|
||||
i_gthe4_common (
|
||||
.BGBYPASSB (1'd1),
|
||||
.BGMONITORENB (1'd1),
|
||||
.BGPDB (1'd1),
|
||||
.BGRCALOVRD (5'b11111),
|
||||
.BGRCALOVRDENB (1'd1),
|
||||
.DRPADDR ({4'd0, up_addr_int}),
|
||||
.DRPCLK (up_clk),
|
||||
.DRPDI (up_wdata_int),
|
||||
.DRPDO (up_rdata_s),
|
||||
.DRPEN (up_enb_int),
|
||||
.DRPRDY (up_ready_s),
|
||||
.DRPWE (up_wr_int),
|
||||
.GTGREFCLK0 (1'd0),
|
||||
.GTGREFCLK1 (1'd0),
|
||||
.GTNORTHREFCLK00 (1'd0),
|
||||
.GTNORTHREFCLK01 (1'd0),
|
||||
.GTNORTHREFCLK10 (1'd0),
|
||||
.GTNORTHREFCLK11 (1'd0),
|
||||
.GTREFCLK00 (qpll_ref_clk),
|
||||
.GTREFCLK01 (qpll_ref_clk),
|
||||
.GTREFCLK10 (1'd0),
|
||||
.GTREFCLK11 (1'd0),
|
||||
.GTSOUTHREFCLK00 (1'd0),
|
||||
.GTSOUTHREFCLK01 (1'd0),
|
||||
.GTSOUTHREFCLK10 (1'd0),
|
||||
.GTSOUTHREFCLK11 (1'd0),
|
||||
.PCIERATEQPLL0 (3'd0),
|
||||
.PCIERATEQPLL1 (3'd0),
|
||||
.PMARSVD0 (8'd0),
|
||||
.PMARSVD1 (8'd0),
|
||||
.PMARSVDOUT0 (),
|
||||
.PMARSVDOUT1 (),
|
||||
.QPLL0CLKRSVD0 (1'd0),
|
||||
.QPLL0CLKRSVD1 (1'd0),
|
||||
.QPLL0FBCLKLOST (),
|
||||
.QPLL0FBDIV (8'd0),
|
||||
.QPLL0LOCK (qpll2ch_locked),
|
||||
.QPLL0LOCKDETCLK (up_clk),
|
||||
.QPLL0LOCKEN (1'd1),
|
||||
.QPLL0OUTCLK (qpll2ch_clk),
|
||||
.QPLL0OUTREFCLK (qpll2ch_ref_clk),
|
||||
.QPLL0PD (qpll_sel),
|
||||
.QPLL0REFCLKLOST (),
|
||||
.QPLL0REFCLKSEL (3'b001),
|
||||
.QPLL0RESET (up_qpll_rst),
|
||||
.QPLL1CLKRSVD0 (1'd0),
|
||||
.QPLL1CLKRSVD1 (1'd0),
|
||||
.QPLL1FBCLKLOST (),
|
||||
.QPLL1FBDIV (8'd0),
|
||||
.QPLL1LOCK (qpll1_locked),
|
||||
.QPLL1LOCKDETCLK (up_clk),
|
||||
.QPLL1LOCKEN (1'd1),
|
||||
.QPLL1OUTCLK (qpll1_clk),
|
||||
.QPLL1OUTREFCLK (qpll1_ref_clk),
|
||||
.QPLL1PD (~qpll_sel),
|
||||
.QPLL1REFCLKLOST (),
|
||||
.QPLL1REFCLKSEL (3'b001),
|
||||
.QPLL1RESET (up_qpll_rst),
|
||||
.QPLLDMONITOR0 (),
|
||||
.QPLLDMONITOR1 (),
|
||||
.QPLLRSVD1 (8'd0),
|
||||
.QPLLRSVD2 (5'd0),
|
||||
.QPLLRSVD3 (5'd0),
|
||||
.QPLLRSVD4 (8'd0),
|
||||
.RCALENB (1'd1),
|
||||
.REFCLKOUTMONITOR0 (),
|
||||
.REFCLKOUTMONITOR1 (),
|
||||
.RXRECCLK0SEL (),
|
||||
.RXRECCLK1SEL (),
|
||||
.SDM0DATA (25'd0),
|
||||
.SDM0FINALOUT (),
|
||||
.SDM0RESET (1'd0),
|
||||
.SDM0TESTDATA (),
|
||||
.SDM0TOGGLE (1'd0),
|
||||
.SDM0WIDTH (2'd0),
|
||||
.SDM1DATA (25'd0),
|
||||
.SDM1FINALOUT (),
|
||||
.SDM1RESET (1'd0),
|
||||
.SDM1TESTDATA (),
|
||||
.SDM1TOGGLE (1'd0),
|
||||
.SDM1WIDTH (2'd0),
|
||||
.TCONGPI (10'd0),
|
||||
.TCONGPO (),
|
||||
.TCONPOWERUP (1'd0),
|
||||
.TCONRESET (2'd0),
|
||||
.TCONRSVDIN1 (2'd0),
|
||||
.TCONRSVDOUT0 ());
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
if (XCVR_TYPE == GTYE4_TRANSCEIVERS) begin
|
||||
GTYE4_COMMON #(
|
||||
.AEN_QPLL0_FBDIV (1'b1),
|
||||
.AEN_QPLL1_FBDIV (1'b1),
|
||||
.AEN_SDM0TOGGLE (1'b0),
|
||||
.AEN_SDM1TOGGLE (1'b0),
|
||||
.A_SDM0TOGGLE (1'b0),
|
||||
.A_SDM1DATA_HIGH (9'b000000000),
|
||||
.A_SDM1DATA_LOW (16'b0000000000000000),
|
||||
.A_SDM1TOGGLE (1'b0),
|
||||
.BIAS_CFG0 (16'b0000000000000000),
|
||||
.BIAS_CFG1 (16'b0000000000000000),
|
||||
.BIAS_CFG2 (16'b0000000100100100),
|
||||
.BIAS_CFG3 (16'b0000000001000001),
|
||||
.BIAS_CFG4 (16'b0000000000010000),
|
||||
.BIAS_CFG_RSVD (16'b0000000000000000),
|
||||
.COMMON_CFG0 (16'b0000000000000000),
|
||||
.COMMON_CFG1 (16'b0000000000000000),
|
||||
.POR_CFG (16'b0000000000000000),
|
||||
.PPF0_CFG (PPF0_CFG),
|
||||
.PPF1_CFG (PPF1_CFG),
|
||||
.QPLL0CLKOUT_RATE ("HALF"),
|
||||
.QPLL0_CFG0 (QPLL_CFG0),
|
||||
.QPLL0_CFG1 (QPLL_CFG1),
|
||||
.QPLL0_CFG1_G3 (QPLL_CFG1_G3),
|
||||
.QPLL0_CFG2 (QPLL_CFG2),
|
||||
.QPLL0_CFG2_G3 (QPLL_CFG2_G3),
|
||||
.QPLL0_CFG3 (QPLL_CFG3),
|
||||
.QPLL0_CFG4 (QPLL_CFG4),
|
||||
.QPLL0_CP (10'b0011111111),
|
||||
.QPLL0_CP_G3 (10'b0000001111),
|
||||
.QPLL0_FBDIV (QPLL_FBDIV),
|
||||
.QPLL0_FBDIV_G3 (160),
|
||||
.QPLL0_INIT_CFG0 (16'b0000001010110010),
|
||||
.QPLL0_INIT_CFG1 (8'b00000000),
|
||||
.QPLL0_LOCK_CFG (16'b0010010111101000),
|
||||
.QPLL0_LOCK_CFG_G3 (16'b0010010111101000),
|
||||
.QPLL0_LPF (QPLL_LPF),
|
||||
.QPLL0_LPF_G3 (10'b0111010101),
|
||||
.QPLL0_PCI_EN (1'b0),
|
||||
.QPLL0_RATE_SW_USE_DRP (1'b1),
|
||||
.QPLL0_REFCLK_DIV (QPLL_REFCLK_DIV),
|
||||
.QPLL0_SDM_CFG0 (16'b0000000010000000),
|
||||
.QPLL0_SDM_CFG1 (16'b0000000000000000),
|
||||
.QPLL0_SDM_CFG2 (16'b0000000000000000),
|
||||
.QPLL1CLKOUT_RATE ("HALF"),
|
||||
.QPLL1_CFG0 (QPLL_CFG0),
|
||||
.QPLL1_CFG1 (QPLL_CFG1),
|
||||
.QPLL1_CFG1_G3 (QPLL_CFG1_G3),
|
||||
.QPLL1_CFG2 (QPLL_CFG2),
|
||||
.QPLL1_CFG2_G3 (QPLL_CFG2_G3),
|
||||
.QPLL1_CFG3 (QPLL_CFG3),
|
||||
.QPLL1_CFG4 (QPLL_CFG4),
|
||||
.QPLL1_CP (10'b0011111111),
|
||||
.QPLL1_CP_G3 (10'b0001111111),
|
||||
.QPLL1_FBDIV (QPLL_FBDIV),
|
||||
.QPLL1_FBDIV_G3 (80),
|
||||
.QPLL1_INIT_CFG0 (16'b0000001010110010),
|
||||
.QPLL1_INIT_CFG1 (8'b00000000),
|
||||
.QPLL1_LOCK_CFG (16'b0010010111101000),
|
||||
.QPLL1_LOCK_CFG_G3 (16'b0010010111101000),
|
||||
.QPLL1_LPF (10'b1000011111),
|
||||
.QPLL1_LPF_G3 (10'b0111010100),
|
||||
.QPLL1_PCI_EN (1'b0),
|
||||
.QPLL1_RATE_SW_USE_DRP (1'b1),
|
||||
.QPLL1_REFCLK_DIV (QPLL_REFCLK_DIV),
|
||||
.QPLL1_SDM_CFG0 (16'b0000000010000000),
|
||||
.QPLL1_SDM_CFG1 (16'b0000000000000000),
|
||||
.QPLL1_SDM_CFG2 (16'b0000000000000000),
|
||||
.RSVD_ATTR0 (16'b0000000000000000),
|
||||
.RSVD_ATTR1 (16'b0000000000000000),
|
||||
.RSVD_ATTR2 (16'b0000000000000000),
|
||||
.RSVD_ATTR3 (16'b0000000000000000),
|
||||
.RXRECCLKOUT0_SEL (2'b00),
|
||||
.RXRECCLKOUT1_SEL (2'b00),
|
||||
.SARC_ENB (1'b0),
|
||||
.SARC_SEL (1'b0),
|
||||
.SDM0INITSEED0_0 (16'b0000000100010001),
|
||||
.SDM0INITSEED0_1 (9'b000010001),
|
||||
.SDM1INITSEED0_0 (16'b0000000100010001),
|
||||
.SDM1INITSEED0_1 (9'b000010001),
|
||||
.SIM_MODE ("FAST"),
|
||||
.SIM_RESET_SPEEDUP ("TRUE"),
|
||||
.SIM_DEVICE ("ULTRASCALE_PLUS"),
|
||||
.UB_CFG0 (16'b0000000000000000),
|
||||
.UB_CFG1 (16'b0000000000000000),
|
||||
.UB_CFG2 (16'b0000000000000000),
|
||||
.UB_CFG3 (16'b0000000000000000),
|
||||
.UB_CFG4 (16'b0000000000000000),
|
||||
.UB_CFG5 (16'b0000010000000000),
|
||||
.UB_CFG6 (16'b0000000000000000))
|
||||
i_gtye4_common (
|
||||
.BGBYPASSB (1'b1),
|
||||
.BGMONITORENB (1'b1),
|
||||
.BGPDB (1'b1),
|
||||
.BGRCALOVRD (5'b11111),
|
||||
.BGRCALOVRDENB (1'b1),
|
||||
.DRPADDR ({4'd0, up_addr_int}),
|
||||
.DRPCLK (up_clk),
|
||||
.DRPDI (up_wdata_int),
|
||||
.DRPEN (up_enb_int),
|
||||
.DRPWE (up_wr_int),
|
||||
.GTGREFCLK0 (1'b0),
|
||||
.GTGREFCLK1 (1'b0),
|
||||
.GTNORTHREFCLK00 (1'b0),
|
||||
.GTNORTHREFCLK01 (1'b0),
|
||||
.GTNORTHREFCLK10 (1'b0),
|
||||
.GTNORTHREFCLK11 (1'b0),
|
||||
.GTREFCLK00 (qpll_ref_clk),
|
||||
.GTREFCLK01 (qpll_ref_clk),
|
||||
.GTREFCLK10 (1'b0),
|
||||
.GTREFCLK11 (1'b0),
|
||||
.GTSOUTHREFCLK00 (1'b0),
|
||||
.GTSOUTHREFCLK01 (1'b0),
|
||||
.GTSOUTHREFCLK10 (1'b0),
|
||||
.GTSOUTHREFCLK11 (1'b0),
|
||||
.PCIERATEQPLL0 (3'b0),
|
||||
.PCIERATEQPLL1 (3'b0),
|
||||
.PMARSVD0 (8'b0),
|
||||
.PMARSVD1 (8'b0),
|
||||
.QPLL0CLKRSVD0 (1'b0),
|
||||
.QPLL0CLKRSVD1 (1'b0),
|
||||
.QPLL0FBDIV (8'b0),
|
||||
.QPLL0LOCKDETCLK (up_clk),
|
||||
.QPLL0LOCKEN (1'b1),
|
||||
.QPLL0PD (qpll_sel),
|
||||
.QPLL0REFCLKSEL (3'b1),
|
||||
.QPLL0RESET (up_qpll_rst),
|
||||
.QPLL1CLKRSVD0 (1'b0),
|
||||
.QPLL1CLKRSVD1 (1'b0),
|
||||
.QPLL1FBDIV (8'b0),
|
||||
.QPLL1LOCKDETCLK (up_clk),
|
||||
.QPLL1LOCKEN (1'b1),
|
||||
.QPLL1PD (~qpll_sel),
|
||||
.QPLL1REFCLKSEL (3'b1),
|
||||
.QPLL1RESET (up_qpll_rst),
|
||||
.QPLLRSVD1 (8'b0),
|
||||
.QPLLRSVD2 (5'b0),
|
||||
.QPLLRSVD3 (5'b0),
|
||||
.QPLLRSVD4 (8'b0),
|
||||
.RCALENB (1'b1),
|
||||
.SDM0DATA (25'b0),
|
||||
.SDM0RESET (1'b0),
|
||||
.SDM0TOGGLE (1'b0),
|
||||
.SDM0WIDTH (2'b0),
|
||||
.SDM1DATA (25'b0),
|
||||
.SDM1RESET (1'b0),
|
||||
.SDM1TOGGLE (1'b0),
|
||||
.SDM1WIDTH (2'b0),
|
||||
.UBCFGSTREAMEN (1'b0),
|
||||
.UBDO (16'b0),
|
||||
.UBDRDY (1'b0),
|
||||
.UBENABLE (1'b0),
|
||||
.UBGPI (2'b0),
|
||||
.UBINTR (2'b0),
|
||||
.UBIOLMBRST (1'b0),
|
||||
.UBMBRST (1'b0),
|
||||
.UBMDMCAPTURE (1'b0),
|
||||
.UBMDMDBGRST (1'b0),
|
||||
.UBMDMDBGUPDATE (1'b0),
|
||||
.UBMDMREGEN (4'b0),
|
||||
.UBMDMSHIFT (1'b0),
|
||||
.UBMDMSYSRST (1'b0),
|
||||
.UBMDMTCK (1'b0),
|
||||
.UBMDMTDI (1'b0),
|
||||
.DRPDO ( up_rdata_s),
|
||||
.DRPRDY ( up_ready_s),
|
||||
.PMARSVDOUT0 (),
|
||||
.PMARSVDOUT1 (),
|
||||
.QPLL0FBCLKLOST (),
|
||||
.QPLL0LOCK ( qpll2ch_locked),
|
||||
.QPLL0OUTCLK ( qpll2ch_clk),
|
||||
.QPLL0OUTREFCLK ( qpll2ch_ref_clk),
|
||||
.QPLL0REFCLKLOST (),
|
||||
.QPLL1FBCLKLOST (),
|
||||
.QPLL1LOCK ( qpll1_locked),
|
||||
.QPLL1OUTCLK ( qpll1_clk),
|
||||
.QPLL1OUTREFCLK ( qpll1_ref_clk),
|
||||
.QPLL1REFCLKLOST (),
|
||||
.QPLLDMONITOR0 (),
|
||||
.QPLLDMONITOR1 (),
|
||||
.REFCLKOUTMONITOR0 (),
|
||||
.REFCLKOUTMONITOR1 (),
|
||||
.RXRECCLK0SEL (),
|
||||
.RXRECCLK1SEL (),
|
||||
.SDM0FINALOUT (),
|
||||
.SDM0TESTDATA (),
|
||||
.SDM1FINALOUT (),
|
||||
.SDM1TESTDATA (),
|
||||
.UBDADDR (),
|
||||
.UBDEN (),
|
||||
.UBDI (),
|
||||
.UBDWE (),
|
||||
.UBMDMTDO (),
|
||||
.UBRSVDOUT (),
|
||||
.UBTXUART ());
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user