initial commit, add dds_par module
This commit is contained in:
@@ -0,0 +1,70 @@
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 01/14/2024 03:49:29 PM
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// Design Name:
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// Module Name: tb_addr_to_wave
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module tb_addr_to_wave;
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localparam PHASE_WIDTH = 12;
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localparam WAVE_WIDTH = 12;
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// ports
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reg clk = 1'b0;
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reg rst = 1'b1;
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reg [PHASE_WIDTH-1 : 0] phase = 'b0;
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wire [WAVE_WIDTH-1 : 0] cos_wave, sin_wave;
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// module instantiation
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addr_to_wave
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#(
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.PHASE_WIDTH (PHASE_WIDTH),
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.WAVE_WIDTH (WAVE_WIDTH )
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) u_addr_to_wave
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(
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// clock & reset
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.clk (clk ),
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.rst (rst ),
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.phase (phase ),
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.cos_wave (cos_wave ),
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.sin_wave (sin_wave )
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);
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// stimulus
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always @(posedge clk) begin
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if (rst) begin
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phase = 'b0;
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end
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else begin
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phase <= phase + 1'b1;
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end
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end
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initial begin
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rst = 1'b1;
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#102;
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rst = 1'b0;
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end
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always #5 clk = ~clk;
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endmodule
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@@ -0,0 +1,123 @@
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 01/14/2024 08:11:00 PM
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// Design Name:
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// Module Name: tb_dds_par
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module tb_dds_par;
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localparam PHASE_WIDTH = 16;
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localparam WAVE_WIDTH = 16;
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localparam PARALLEL_NUM = 7;
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// ports
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wire clk;
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reg clk_fast = 1'b0;
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reg rst = 1'b1;
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reg rst_fast = 1'b1;
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reg [PHASE_WIDTH-1 : 0] phase_inc = 'b0;
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wire [WAVE_WIDTH*PARALLEL_NUM-1 : 0] cos_wave, sin_wave;
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// module instantiation
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dds_par
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#(
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.PHASE_WIDTH (PHASE_WIDTH ),
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.WAVE_WIDTH (WAVE_WIDTH ),
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.PARALLEL_NUM (PARALLEL_NUM )
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) u_dds_par
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(
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// clock & reset
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.clk (clk ),
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.rst (rst ),
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.phase_inc (phase_inc ),
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.cos_wave (cos_wave ),
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.sin_wave (sin_wave )
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);
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// stimulus
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initial begin
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rst = 1'b1;
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rst_fast = 1'b1;
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#102;
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rst_fast = 1'b0;
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#302;
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rst = 1'b0;
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#1000
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phase_inc = 16'd1029;
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end
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always #5 clk_fast = ~clk_fast;
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if (PARALLEL_NUM > 1) begin
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reg [$clog2(PARALLEL_NUM)-1 : 0] par_cnt = 'b0;
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always @(posedge clk_fast) begin
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if (rst_fast) begin
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par_cnt <= 'b0;
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end
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else begin
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par_cnt <= (par_cnt == PARALLEL_NUM-1) ? 'b0 : par_cnt + 1'b1;
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end
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end
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assign clk = par_cnt[$clog2(PARALLEL_NUM)-1];
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// parallel to serial
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reg [WAVE_WIDTH*PARALLEL_NUM-1 : 0] cos_wave_buf = 'b0;
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reg [WAVE_WIDTH*PARALLEL_NUM-1 : 0] sin_wave_buf = 'b0;
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reg [WAVE_WIDTH-1 : 0] cos_wave_ser = 'b0;
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reg [WAVE_WIDTH-1 : 0] sin_wave_ser = 'b0;
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always @(posedge clk_fast) begin
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if (rst_fast) begin
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cos_wave_buf <= 'b0;
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sin_wave_buf <= 'b0;
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cos_wave_ser <= 'b0;
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sin_wave_ser <= 'b0;
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end
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else begin
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if (par_cnt == PARALLEL_NUM-1) begin
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cos_wave_buf <= cos_wave;
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sin_wave_buf <= sin_wave;
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end
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else begin
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cos_wave_buf <= cos_wave_buf;
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sin_wave_buf <= sin_wave_buf;
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end
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cos_wave_ser <= cos_wave_buf[WAVE_WIDTH*par_cnt +: WAVE_WIDTH];
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sin_wave_ser <= sin_wave_buf[WAVE_WIDTH*par_cnt +: WAVE_WIDTH];
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end
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end
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end
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else begin
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assign clk = clk_fast;
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wire [WAVE_WIDTH-1 : 0] cos_wave_ser;
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wire [WAVE_WIDTH-1 : 0] sin_wave_ser;
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assign cos_wave_ser = cos_wave;
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assign sin_wave_ser = sin_wave;
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end
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endmodule
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+16391
File diff suppressed because it is too large
Load Diff
+273
@@ -0,0 +1,273 @@
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{
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"schema": "xilinx.com:schema:json_instance:1.0",
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"ip_inst": {
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"xci_name": "cos_16384_16b",
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"component_reference": "xilinx.com:ip:blk_mem_gen:8.4",
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"ip_revision": "7",
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"gen_directory": "../../../../dds_par.gen/sources_1/ip/cos_16384_16b",
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"parameters": {
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"component_parameters": {
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"Component_Name": [ { "value": "cos_16384_16b", "resolve_type": "user", "usage": "all" } ],
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"Interface_Type": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ],
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"AXI_Type": [ { "value": "AXI4_Full", "resolve_type": "user", "usage": "all" } ],
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||||
"AXI_Slave_Type": [ { "value": "Memory_Slave", "resolve_type": "user", "usage": "all" } ],
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"Use_AXI_ID": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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||||
"AXI_ID_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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||||
"Memory_Type": [ { "value": "Dual_Port_ROM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
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||||
"PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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||||
"Enable_32bit_Address": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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||||
"ecctype": [ { "value": "No_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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||||
"ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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||||
"softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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||||
"EN_SLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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||||
"EN_DEEPSLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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||||
"EN_SHUTDOWN_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"EN_ECC_PIPE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"RD_ADDR_CHNG_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"RD_ADDR_CHNG_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Use_Error_Injection_Pins": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Error_Injection_Type": [ { "value": "Single_Bit_Error_Injection", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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||||
"Use_Byte_Write_Enable": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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||||
"Byte_Size": [ { "value": "9", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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||||
"Algorithm": [ { "value": "Minimum_Area", "resolve_type": "user", "usage": "all" } ],
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||||
"Primitive": [ { "value": "8kx2", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Assume_Synchronous_Clk": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Write_Width_A": [ { "value": "15", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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||||
"Write_Depth_A": [ { "value": "16384", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Read_Width_A": [ { "value": "15", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Operating_Mode_A": [ { "value": "WRITE_FIRST", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_A": [ { "value": "Always_Enabled", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Write_Width_B": [ { "value": "15", "resolve_type": "user", "usage": "all" } ],
|
||||
"Read_Width_B": [ { "value": "15", "resolve_type": "user", "usage": "all" } ],
|
||||
"Operating_Mode_B": [ { "value": "WRITE_FIRST", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_B": [ { "value": "Always_Enabled", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_PortA_Output_of_Memory_Primitives": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Register_PortA_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Use_REGCEA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Register_PortB_Output_of_Memory_Primitives": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Register_PortB_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Use_REGCEB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"register_porta_input_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"register_portb_output_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Pipeline_Stages": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Load_Init_File": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Coe_File": [ { "value": "../coe/cos_16384_16b.coe", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Fill_Remaining_Memory_Locations": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Remaining_Memory_Locations": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Use_RSTA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Reset_Memory_Latch_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Reset_Priority_A": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Output_Reset_Value_A": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Use_RSTB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Reset_Memory_Latch_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Reset_Priority_B": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Output_Reset_Value_B": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Reset_Type": [ { "value": "SYNC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Additional_Inputs_for_Power_Estimation": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Port_A_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Port_A_Write_Rate": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Port_B_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Port_B_Write_Rate": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Port_A_Enable_Rate": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Port_B_Enable_Rate": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Collision_Warnings": [ { "value": "ALL", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Disable_Collision_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Disable_Out_of_Range_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"use_bram_block": [ { "value": "Stand_Alone", "resolve_type": "user", "usage": "all" } ],
|
||||
"MEM_FILE": [ { "value": "no_mem_loaded", "resolve_type": "user", "usage": "all" } ],
|
||||
"CTRL_ECC_ALGO": [ { "value": "NONE", "resolve_type": "user", "usage": "all" } ],
|
||||
"EN_SAFETY_CKT": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"READ_LATENCY_A": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"READ_LATENCY_B": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_XDEVICEFAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_ELABORATION_DIR": [ { "value": "./", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_INTERFACE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_SLAVE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_BRAM_BLOCK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_32BIT_ADDRESS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CTRL_ECC_ALGO": [ { "value": "NONE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_HAS_AXI_ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_ID_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MEM_TYPE": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_BYTE_SIZE": [ { "value": "9", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ALGORITHM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRIM_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_LOAD_INIT_FILE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INIT_FILE_NAME": [ { "value": "cos_16384_16b.mif", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_INIT_FILE": [ { "value": "cos_16384_16b.mem", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_HAS_RSTA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RST_PRIORITY_A": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_RSTRAM_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INITA_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_HAS_ENA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_REGCEA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_BYTE_WEA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WEA_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WRITE_MODE_A": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_WRITE_WIDTH_A": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_READ_WIDTH_A": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WRITE_DEPTH_A": [ { "value": "16384", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_READ_DEPTH_A": [ { "value": "16384", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ADDRA_WIDTH": [ { "value": "14", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_RSTB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RST_PRIORITY_B": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_RSTRAM_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INITB_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_HAS_ENB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_REGCEB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_BYTE_WEB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WEB_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WRITE_MODE_B": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_WRITE_WIDTH_B": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_READ_WIDTH_B": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WRITE_DEPTH_B": [ { "value": "16384", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_READ_DEPTH_B": [ { "value": "16384", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ADDRB_WIDTH": [ { "value": "14", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_MEM_OUTPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_MEM_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_MUX_OUTPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_MUX_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MUX_PIPELINE_STAGES": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_SOFTECC_INPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_SOFTECC_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_SOFTECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_ECC_PIPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_READ_LATENCY_A": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_READ_LATENCY_B": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_INJECTERR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SIM_COLLISION_CHECK": [ { "value": "ALL", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_COMMON_CLK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DISABLE_WARN_BHV_COLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_SLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_URAM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_RDADDRA_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_RDADDRB_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_DEEPSLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_SHUTDOWN_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_SAFETY_CKT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DISABLE_WARN_BHV_RANGE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_COUNT_36K_BRAM": [ { "value": "7", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_COUNT_18K_BRAM": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_EST_POWER_SUMMARY": [ { "value": "Estimated Power for IP : 13.394793 mW", "resolve_type": "generated", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu48dr" } ],
|
||||
"PACKAGE": [ { "value": "fsvg1517" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "7" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../dds_par.gen/sources_1/ip/cos_16384_16b" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"clka": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"addra": [ { "direction": "in", "size_left": "13", "size_right": "0", "driver_value": "0" } ],
|
||||
"douta": [ { "direction": "out", "size_left": "14", "size_right": "0" } ],
|
||||
"clkb": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"addrb": [ { "direction": "in", "size_left": "13", "size_right": "0", "driver_value": "0" } ],
|
||||
"doutb": [ { "direction": "out", "size_left": "14", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"CLK.ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_aresetn", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"RST.ARESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"BRAM_PORTA": {
|
||||
"vlnv": "xilinx.com:interface:bram:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"MEM_SIZE": [ { "value": "8192", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_ECC": [ { "value": "NONE", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MASTER_TYPE": [ { "value": "OTHER", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ADDR": [ { "physical_name": "addra" } ],
|
||||
"CLK": [ { "physical_name": "clka" } ],
|
||||
"DOUT": [ { "physical_name": "douta" } ]
|
||||
}
|
||||
},
|
||||
"BRAM_PORTB": {
|
||||
"vlnv": "xilinx.com:interface:bram:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"MEM_SIZE": [ { "value": "8192", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_ECC": [ { "value": "NONE", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MASTER_TYPE": [ { "value": "OTHER", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ADDR": [ { "physical_name": "addrb" } ],
|
||||
"CLK": [ { "physical_name": "clkb" } ],
|
||||
"DOUT": [ { "physical_name": "doutb" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S_1": {
|
||||
"address_blocks": {
|
||||
"Mem0": {
|
||||
"base_address": "0",
|
||||
"range": "4096",
|
||||
"usage": "memory",
|
||||
"access": "read-write",
|
||||
"parameters": {
|
||||
"OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
|
||||
"OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,199 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
// _ _ ____
|
||||
// | | ___ ___| |__ / ___| __ _ ___
|
||||
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||
//
|
||||
// Create Date: 2022/03/23 11:36:49
|
||||
// Design Name:
|
||||
// Module Name: addr_to_wave
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description: This module generates look-up-table-based sine/cosine wave,
|
||||
// with 1/4 cycles of cosine wave.
|
||||
// Parameter:
|
||||
// PHASE_WIDTH: Bit width of input phase address.
|
||||
// WAVE_WIDTH: Bit width of output sine/cosine wave.
|
||||
// Total latency: 4 clock cycles, including 1 clock cycle for rom read
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// 2024/01/14 - Josh:
|
||||
// 1. 修改 ROM 的宽度和深度为 16 bit，后续修改 IP 时需要同时修改本文件的 localparam。
|
||||
// 2. 输入输出改为可调位宽，但是模块内部仍按照 IP 核的位宽进行运算。
|
||||
// Additional Comments: The code below generates sine and cosine wave by
|
||||
// circularly reading 1/4 cycle of cosine data from the LUT based on the phase
|
||||
// address.
|
||||
//
|
||||
// -- --
|
||||
// --- --- --
|
||||
// -- -- ---
|
||||
// - - --
|
||||
// - - -
|
||||
// - - ----> -
|
||||
// - -
|
||||
// - - addr(cos): -->, <--, -->, <--
|
||||
// -- -- data(cos): + , - , - , +
|
||||
// --- --- addr(sin): <--, -->, <--, -->
|
||||
// ---- data(sin): + , + , - , -
|
||||
//
|
||||
// one cycle of cosine wave 1/4 cycle of cosine wave
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module addr_to_wave
|
||||
#(
|
||||
parameter PHASE_WIDTH = 16,
|
||||
parameter WAVE_WIDTH = 16
|
||||
)
|
||||
(
|
||||
// clock & reset
|
||||
input clk ,
|
||||
input rst ,
|
||||
|
||||
input [PHASE_WIDTH-1 : 0] phase ,
|
||||
|
||||
output [WAVE_WIDTH-1 : 0] cos_wave,
|
||||
output [WAVE_WIDTH-1 : 0] sin_wave
|
||||
);
|
||||
|
||||
integer i;
|
||||
|
||||
localparam ADDR_WIDTH = 16;
|
||||
localparam DATA_WIDTH = 16;
|
||||
localparam ROM_ADDR_WIDTH = ADDR_WIDTH - 2; // 1/4 cycle is stored
|
||||
localparam ROM_DATA_WIDTH = DATA_WIDTH - 1; // only positive data
|
||||
localparam ROM_MAX_INDEX = 2**ROM_ADDR_WIDTH-1;
|
||||
localparam DELAY = 3;
|
||||
|
||||
// mapping phase address to local format
|
||||
wire [ADDR_WIDTH-1 : 0] phase_addr;
|
||||
|
||||
if (PHASE_WIDTH >= ADDR_WIDTH) begin
|
||||
assign phase_addr = phase[PHASE_WIDTH-1 -: ADDR_WIDTH];
|
||||
end
|
||||
else begin
|
||||
assign phase_addr = {phase,{(ADDR_WIDTH-PHASE_WIDTH){1'b0}}};
|
||||
end
|
||||
|
||||
|
||||
// d1: buffer/stabilize input address
|
||||
// d2: phase segment decision
|
||||
// d3: wait for lut output data - [cos_lut_dout] & [sin_lut_dout]
|
||||
reg [ADDR_WIDTH-1 : 0] phase_addr_d [1 : DELAY];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
for (i = 1; i <= DELAY ; i = i + 1) begin
|
||||
phase_addr_d[i] <= 'b0;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
phase_addr_d[1] <= phase_addr;
|
||||
|
||||
for (i = 2; i <= DELAY ; i = i + 1) begin
|
||||
phase_addr_d[i] <= phase_addr_d[i-1];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// Generate cosine and sine address based on current phase segment
|
||||
reg [ROM_ADDR_WIDTH-1 : 0] cos_addr = 'b0;
|
||||
reg [ROM_ADDR_WIDTH-1 : 0] sin_addr = 'b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cos_addr <= 'b0;
|
||||
sin_addr <= 'b0;
|
||||
end
|
||||
else begin
|
||||
case (phase_addr_d[1][ADDR_WIDTH-1 -: 2])
|
||||
2'b00, 2'b10: begin
|
||||
cos_addr <= phase_addr_d[1];
|
||||
sin_addr <= ROM_MAX_INDEX - phase_addr_d[1];
|
||||
end
|
||||
2'b01, 2'b11: begin
|
||||
cos_addr <= ROM_MAX_INDEX - phase_addr_d[1];
|
||||
sin_addr <= phase_addr_d[1];
|
||||
end
|
||||
default: begin
|
||||
cos_addr <= 'b0;
|
||||
sin_addr <= 'b0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// Read 1/4 cycle of cosine data from BRAM. The Primitives Output Register and
|
||||
// the the Core Output Register are enabled, to provide better delay and latency
|
||||
// performance, so the output latency of both ports have reached 3 clock cycles.
|
||||
wire [ROM_DATA_WIDTH-1 : 0] cos_lut_dout;
|
||||
wire [ROM_DATA_WIDTH-1 : 0] sin_lut_dout;
|
||||
|
||||
cos_16384_16b u_cos_16384_16b
|
||||
(
|
||||
.clka (clk ), // input wire clka
|
||||
.addra (cos_addr ), // input wire [13 : 0] addra
|
||||
.douta (cos_lut_dout ), // output wire [14 : 0] douta
|
||||
.clkb (clk ), // input wire clkb
|
||||
.addrb (sin_addr ), // input wire [13 : 0] addrb
|
||||
.doutb (sin_lut_dout ) // output wire [14 : 0] doutb
|
||||
);
|
||||
|
||||
// Correct the sign of output data (above or below zero).
|
||||
reg signed [DATA_WIDTH-1 : 0] cos_dout;
|
||||
reg signed [DATA_WIDTH-1 : 0] sin_dout;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cos_dout <= 'b0;
|
||||
sin_dout <= 'b0;
|
||||
end
|
||||
else begin
|
||||
case (phase_addr_d[DELAY][ADDR_WIDTH-1 -: 2])
|
||||
2'b00: begin
|
||||
cos_dout <= cos_lut_dout;
|
||||
sin_dout <= sin_lut_dout;
|
||||
end
|
||||
2'b01: begin
|
||||
cos_dout <= -cos_lut_dout;
|
||||
sin_dout <= sin_lut_dout;
|
||||
end
|
||||
2'b10: begin
|
||||
cos_dout <= -cos_lut_dout;
|
||||
sin_dout <= -sin_lut_dout;
|
||||
end
|
||||
2'b11: begin
|
||||
cos_dout <= cos_lut_dout;
|
||||
sin_dout <= -sin_lut_dout;
|
||||
end
|
||||
default: begin
|
||||
cos_dout <= 'b0;
|
||||
sin_dout <= 'b0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// Output data to port
|
||||
/* FIXME: The truncation should be done by rounding operation, to avoid extra
|
||||
* DC component.
|
||||
*/
|
||||
if (WAVE_WIDTH <= DATA_WIDTH) begin
|
||||
assign cos_wave = cos_dout[DATA_WIDTH-1 -: WAVE_WIDTH];
|
||||
assign sin_wave = sin_dout[DATA_WIDTH-1 -: WAVE_WIDTH];
|
||||
end
|
||||
else begin
|
||||
assign cos_wave = {cos_dout,{(WAVE_WIDTH-DATA_WIDTH){1'b0}}};
|
||||
assign sin_wave = {sin_dout,{(WAVE_WIDTH-DATA_WIDTH){1'b0}}};
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,175 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
// _ _ ____
|
||||
// | | ___ ___| |__ / ___| __ _ ___
|
||||
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||
//
|
||||
// Create Date: 01/14/2024 02:50:34 PM
|
||||
// Design Name:
|
||||
// Module Name: dds_par
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description: This module generates parallel sine/cosine wave with continuous
|
||||
// phase, which can be used as polyphase adjustable carrier wave.
|
||||
// Parameter:
|
||||
// PHASE_WIDTH: Bit width of input phase address.
|
||||
// WAVE_WIDTH: Bit width of output sine/cosine wave.
|
||||
// PARALLEL_NUM: Number of parallel paths. The optimal wave is generated when
|
||||
// this number is power of 2, however the module should work fine with any
|
||||
// number of parallel paths.
|
||||
// Data format:
|
||||
// cos_wave/sin_wave: Suppose the samples are s = [s0, s1, ..., sN], then
|
||||
// cos_wave/sin_wave = {sN, ..., s1, s0}
|
||||
// Total latency: [PARALLEL_NUM+6] clock cycles, including 4 clock cycles for
|
||||
// addr_to_wave
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module dds_par
|
||||
#(
|
||||
parameter PHASE_WIDTH = 16,
|
||||
parameter WAVE_WIDTH = 16,
|
||||
parameter PARALLEL_NUM = 8
|
||||
)
|
||||
(
|
||||
input clk,
|
||||
input rst,
|
||||
|
||||
input [PHASE_WIDTH-1 : 0] phase_inc,
|
||||
|
||||
output [WAVE_WIDTH*PARALLEL_NUM-1 : 0] cos_wave,
|
||||
output [WAVE_WIDTH*PARALLEL_NUM-1 : 0] sin_wave
|
||||
);
|
||||
|
||||
localparam PARALLEL_NUM_LOG = $clog2(PARALLEL_NUM);
|
||||
localparam PHASE_CONFIG_DELAY = PARALLEL_NUM + 1;
|
||||
|
||||
genvar m;
|
||||
integer i;
|
||||
|
||||
// buffer
|
||||
reg [PHASE_WIDTH-1 : 0] phase_inc_d [1:2];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
for (i = 1; i <= 2 ; i = i + 1) begin
|
||||
phase_inc_d[i] <= 'b0;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
phase_inc_d[1] <= phase_inc;
|
||||
phase_inc_d[2] <= phase_inc_d[1];
|
||||
end
|
||||
end
|
||||
|
||||
// phase increment change identification
|
||||
reg phase_config_flag [0:PHASE_CONFIG_DELAY-1];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
for (i = 0; i < PHASE_CONFIG_DELAY; i = i + 1) begin
|
||||
phase_config_flag[i] <= 'b0;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
phase_config_flag[0] <= (phase_inc_d[2] != phase_inc_d[1]) ? 1'b1 : 'b0;
|
||||
for (i = 1; i < PHASE_CONFIG_DELAY; i = i + 1) begin
|
||||
phase_config_flag[i] <= phase_config_flag[i-1];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// offset counter
|
||||
reg [$clog2(PARALLEL_NUM)-1 : 0] phase_config_cnt = 'b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
phase_config_cnt <= 'b0;
|
||||
end
|
||||
else if (phase_config_flag[0]) begin
|
||||
phase_config_cnt <= phase_config_cnt + 1'b1;
|
||||
end
|
||||
else begin
|
||||
phase_config_cnt <= (phase_config_cnt == 'b0) ? 'b0 : phase_config_cnt + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
// phase offset generation based on new phase increment
|
||||
reg [PHASE_WIDTH-1 : 0] phase_off [0 : PARALLEL_NUM-1];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
for (i = 0; i < PARALLEL_NUM; i = i + 1) begin
|
||||
phase_off[i] <= 'b0;
|
||||
end
|
||||
end
|
||||
else if (phase_config_cnt != 'b0) begin
|
||||
phase_off[phase_config_cnt] <= phase_off[phase_config_cnt-1] + phase_inc_d[2];
|
||||
end
|
||||
end
|
||||
|
||||
// phase generation
|
||||
reg [PHASE_WIDTH-1 : 0] phase [0 : PARALLEL_NUM-1];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
for (i = 0; i < PARALLEL_NUM; i = i + 1) begin
|
||||
phase[i] <= 'b0;
|
||||
end
|
||||
end
|
||||
else if (phase_config_flag[PHASE_CONFIG_DELAY-1]) begin
|
||||
for (i = 0; i < PARALLEL_NUM; i = i + 1) begin
|
||||
phase[i] <= phase_off[i];
|
||||
end
|
||||
end
|
||||
else begin
|
||||
for (i = 0; i < PARALLEL_NUM; i = i + 1) begin
|
||||
phase[i] <= phase[i] + (phase_inc << PARALLEL_NUM_LOG);
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// phase to wave
|
||||
wire [WAVE_WIDTH-1 : 0] cos_wave_par [0 : PARALLEL_NUM-1];
|
||||
wire [WAVE_WIDTH-1 : 0] sin_wave_par [0 : PARALLEL_NUM-1];
|
||||
|
||||
generate
|
||||
for (m = 0; m < PARALLEL_NUM; m = m + 1) begin: phase_to_wave
|
||||
|
||||
addr_to_wave
|
||||
#(
|
||||
.PHASE_WIDTH (PHASE_WIDTH),
|
||||
.WAVE_WIDTH (WAVE_WIDTH )
|
||||
) u_addr_to_wave
|
||||
(
|
||||
// clock & reset
|
||||
.clk (clk ),
|
||||
.rst (rst ),
|
||||
|
||||
.phase (phase[m] ),
|
||||
|
||||
.cos_wave (cos_wave_par[m]),
|
||||
.sin_wave (sin_wave_par[m])
|
||||
);
|
||||
|
||||
// output to port
|
||||
assign cos_wave[WAVE_WIDTH*m +: WAVE_WIDTH] = cos_wave_par[m];
|
||||
assign sin_wave[WAVE_WIDTH*m +: WAVE_WIDTH] = sin_wave_par[m];
|
||||
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,292 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
|
||||
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/Workspace/vivado-git-new/modules/xczu48dr-fsvg1517-2-i/dds_par/dds_par.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="a90265fba4f44c3cae46ab12aecd7053"/>
|
||||
<Option Name="Part" Val="xczu48dr-fsvg1517-2-i"/>
|
||||
<Option Name="CompiledLibDir" Val="$PPRDIR/../../../../../Tools/XilCompLib/model/2023.2"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PPRDIR/../../../../../Tools/XilCompLib/model/2023.2"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PPRDIR/../../../../../Tools/XilCompLib/vcs/2023.2"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorVersionXsim" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
|
||||
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
|
||||
<Option Name="SimulatorVersionRiviera" Val="2022.10"/>
|
||||
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
|
||||
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
|
||||
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="EnableResourceEstimation" Val="FALSE"/>
|
||||
<Option Name="SimCompileState" Val="TRUE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="106"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="3"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="9"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="4"/>
|
||||
<Option Name="WTModelSimExportSim" Val="4"/>
|
||||
<Option Name="WTQuestaExportSim" Val="4"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="4"/>
|
||||
<Option Name="WTRivieraExportSim" Val="4"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="4"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
||||
<Option Name="ClassicSocBoot" Val="FALSE"/>
|
||||
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="32">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/new/addr_to_wave.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/dds_par.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/ip/coe/cos_16384_16b.coe">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="dds_par"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||
<File Path="$PSRCDIR/sim_1/new/tb_dds_par.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sim_1/new/tb_addr_to_wave.v">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="tb_dds_par"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||
<Option Name="PamDesignTestbench" Val=""/>
|
||||
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
||||
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
<Option Name="vcs.compile.vlogan.more_options" Val="-v2005 -kdb"/>
|
||||
<Option Name="vcs.elaborate.vcs.more_options" Val="-debug_access+all"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="cos_16384_16b" Type="BlockSrcs" RelSrcDir="$PSRCDIR/cos_16384_16b" RelGenDir="$PGENDIR/cos_16384_16b">
|
||||
<File Path="$PSRCDIR/sources_1/ip/cos_16384_16b/cos_16384_16b.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="cos_16384_16b"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="21">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="cos_16384_16b_synth_1" Type="Ft3:Synth" SrcSet="cos_16384_16b" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="cos_16384_16b" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/cos_16384_16b_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/cos_16384_16b_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/cos_16384_16b_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="cos_16384_16b_impl_1" Type="Ft2:EntireDesign" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="cos_16384_16b" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="cos_16384_16b_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/cos_16384_16b_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/cos_16384_16b_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
</Project>
|
||||
Reference in New Issue
Block a user