initial commit, add dds_par module
This commit is contained in:
+16391
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+273
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{
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"schema": "xilinx.com:schema:json_instance:1.0",
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"ip_inst": {
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"xci_name": "cos_16384_16b",
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"component_reference": "xilinx.com:ip:blk_mem_gen:8.4",
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"ip_revision": "7",
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"gen_directory": "../../../../dds_par.gen/sources_1/ip/cos_16384_16b",
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"parameters": {
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"component_parameters": {
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"Component_Name": [ { "value": "cos_16384_16b", "resolve_type": "user", "usage": "all" } ],
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"Interface_Type": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ],
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"AXI_Type": [ { "value": "AXI4_Full", "resolve_type": "user", "usage": "all" } ],
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"AXI_Slave_Type": [ { "value": "Memory_Slave", "resolve_type": "user", "usage": "all" } ],
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"Use_AXI_ID": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"AXI_ID_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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"Memory_Type": [ { "value": "Dual_Port_ROM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
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"PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"Enable_32bit_Address": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"ecctype": [ { "value": "No_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"EN_SLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"EN_DEEPSLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"EN_SHUTDOWN_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"EN_ECC_PIPE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"RD_ADDR_CHNG_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"RD_ADDR_CHNG_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"Use_Error_Injection_Pins": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"Error_Injection_Type": [ { "value": "Single_Bit_Error_Injection", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"Use_Byte_Write_Enable": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"Byte_Size": [ { "value": "9", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"Algorithm": [ { "value": "Minimum_Area", "resolve_type": "user", "usage": "all" } ],
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"Primitive": [ { "value": "8kx2", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"Assume_Synchronous_Clk": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"Write_Width_A": [ { "value": "15", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"Write_Depth_A": [ { "value": "16384", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"Read_Width_A": [ { "value": "15", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"Operating_Mode_A": [ { "value": "WRITE_FIRST", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"Enable_A": [ { "value": "Always_Enabled", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
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"Write_Width_B": [ { "value": "15", "resolve_type": "user", "usage": "all" } ],
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"Read_Width_B": [ { "value": "15", "resolve_type": "user", "usage": "all" } ],
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"Operating_Mode_B": [ { "value": "WRITE_FIRST", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"Enable_B": [ { "value": "Always_Enabled", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
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"Register_PortA_Output_of_Memory_Primitives": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"Register_PortA_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"Use_REGCEA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"Register_PortB_Output_of_Memory_Primitives": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"Register_PortB_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"Use_REGCEB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"register_porta_input_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"register_portb_output_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"Pipeline_Stages": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"Load_Init_File": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"Coe_File": [ { "value": "../coe/cos_16384_16b.coe", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
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"Fill_Remaining_Memory_Locations": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"Remaining_Memory_Locations": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"Use_RSTA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"Reset_Memory_Latch_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"Reset_Priority_A": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"Output_Reset_Value_A": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"Use_RSTB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"Reset_Memory_Latch_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"Reset_Priority_B": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"Output_Reset_Value_B": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"Reset_Type": [ { "value": "SYNC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"Additional_Inputs_for_Power_Estimation": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"Port_A_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"Port_A_Write_Rate": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"Port_B_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"Port_B_Write_Rate": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"Port_A_Enable_Rate": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"Port_B_Enable_Rate": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"Collision_Warnings": [ { "value": "ALL", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"Disable_Collision_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"Disable_Out_of_Range_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"use_bram_block": [ { "value": "Stand_Alone", "resolve_type": "user", "usage": "all" } ],
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"MEM_FILE": [ { "value": "no_mem_loaded", "resolve_type": "user", "usage": "all" } ],
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"CTRL_ECC_ALGO": [ { "value": "NONE", "resolve_type": "user", "usage": "all" } ],
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"EN_SAFETY_CKT": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"READ_LATENCY_A": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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"READ_LATENCY_B": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ]
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},
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"model_parameters": {
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"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
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"C_XDEVICEFAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
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"C_ELABORATION_DIR": [ { "value": "./", "resolve_type": "generated", "usage": "all" } ],
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"C_INTERFACE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_AXI_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_AXI_SLAVE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_USE_BRAM_BLOCK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_ENABLE_32BIT_ADDRESS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_CTRL_ECC_ALGO": [ { "value": "NONE", "resolve_type": "generated", "usage": "all" } ],
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"C_HAS_AXI_ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_AXI_ID_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_MEM_TYPE": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_BYTE_SIZE": [ { "value": "9", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_ALGORITHM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_PRIM_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_LOAD_INIT_FILE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_INIT_FILE_NAME": [ { "value": "cos_16384_16b.mif", "resolve_type": "generated", "usage": "all" } ],
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"C_INIT_FILE": [ { "value": "cos_16384_16b.mem", "resolve_type": "generated", "usage": "all" } ],
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"C_USE_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
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"C_HAS_RSTA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_RST_PRIORITY_A": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
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"C_RSTRAM_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_INITA_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
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"C_HAS_ENA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_HAS_REGCEA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_USE_BYTE_WEA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_WEA_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_WRITE_MODE_A": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ],
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"C_WRITE_WIDTH_A": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_READ_WIDTH_A": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_WRITE_DEPTH_A": [ { "value": "16384", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_READ_DEPTH_A": [ { "value": "16384", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_ADDRA_WIDTH": [ { "value": "14", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_HAS_RSTB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_RST_PRIORITY_B": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
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"C_RSTRAM_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_INITB_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
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"C_HAS_ENB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_HAS_REGCEB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||
"C_USE_BYTE_WEB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_WEB_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_WRITE_MODE_B": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ],
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"C_WRITE_WIDTH_B": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_READ_WIDTH_B": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_WRITE_DEPTH_B": [ { "value": "16384", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_READ_DEPTH_B": [ { "value": "16384", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_ADDRB_WIDTH": [ { "value": "14", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||
"C_HAS_MEM_OUTPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||
"C_HAS_MEM_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||
"C_HAS_MUX_OUTPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||
"C_HAS_MUX_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||
"C_MUX_PIPELINE_STAGES": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||
"C_HAS_SOFTECC_INPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||
"C_HAS_SOFTECC_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||
"C_USE_SOFTECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||
"C_USE_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||
"C_EN_ECC_PIPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_READ_LATENCY_A": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_READ_LATENCY_B": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_INJECTERR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SIM_COLLISION_CHECK": [ { "value": "ALL", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_COMMON_CLK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DISABLE_WARN_BHV_COLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_SLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_URAM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_RDADDRA_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_RDADDRB_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_DEEPSLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_SHUTDOWN_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_SAFETY_CKT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DISABLE_WARN_BHV_RANGE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_COUNT_36K_BRAM": [ { "value": "7", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_COUNT_18K_BRAM": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_EST_POWER_SUMMARY": [ { "value": "Estimated Power for IP : 13.394793 mW", "resolve_type": "generated", "usage": "all" } ]
|
||||
},
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||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu48dr" } ],
|
||||
"PACKAGE": [ { "value": "fsvg1517" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "7" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../dds_par.gen/sources_1/ip/cos_16384_16b" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"clka": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"addra": [ { "direction": "in", "size_left": "13", "size_right": "0", "driver_value": "0" } ],
|
||||
"douta": [ { "direction": "out", "size_left": "14", "size_right": "0" } ],
|
||||
"clkb": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"addrb": [ { "direction": "in", "size_left": "13", "size_right": "0", "driver_value": "0" } ],
|
||||
"doutb": [ { "direction": "out", "size_left": "14", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"CLK.ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_aresetn", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"RST.ARESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"BRAM_PORTA": {
|
||||
"vlnv": "xilinx.com:interface:bram:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"MEM_SIZE": [ { "value": "8192", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_ECC": [ { "value": "NONE", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MASTER_TYPE": [ { "value": "OTHER", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ADDR": [ { "physical_name": "addra" } ],
|
||||
"CLK": [ { "physical_name": "clka" } ],
|
||||
"DOUT": [ { "physical_name": "douta" } ]
|
||||
}
|
||||
},
|
||||
"BRAM_PORTB": {
|
||||
"vlnv": "xilinx.com:interface:bram:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"MEM_SIZE": [ { "value": "8192", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_ECC": [ { "value": "NONE", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MASTER_TYPE": [ { "value": "OTHER", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ADDR": [ { "physical_name": "addrb" } ],
|
||||
"CLK": [ { "physical_name": "clkb" } ],
|
||||
"DOUT": [ { "physical_name": "doutb" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S_1": {
|
||||
"address_blocks": {
|
||||
"Mem0": {
|
||||
"base_address": "0",
|
||||
"range": "4096",
|
||||
"usage": "memory",
|
||||
"access": "read-write",
|
||||
"parameters": {
|
||||
"OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
|
||||
"OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,199 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
// _ _ ____
|
||||
// | | ___ ___| |__ / ___| __ _ ___
|
||||
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||
//
|
||||
// Create Date: 2022/03/23 11:36:49
|
||||
// Design Name:
|
||||
// Module Name: addr_to_wave
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description: This module generates look-up-table-based sine/cosine wave,
|
||||
// with 1/4 cycles of cosine wave.
|
||||
// Parameter:
|
||||
// PHASE_WIDTH: Bit width of input phase address.
|
||||
// WAVE_WIDTH: Bit width of output sine/cosine wave.
|
||||
// Total latency: 4 clock cycles, including 1 clock cycle for rom read
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// 2024/01/14 - Josh:
|
||||
// 1. 修改 ROM 的宽度和深度为 16 bit，后续修改 IP 时需要同时修改本文件的 localparam。
|
||||
// 2. 输入输出改为可调位宽，但是模块内部仍按照 IP 核的位宽进行运算。
|
||||
// Additional Comments: The code below generates sine and cosine wave by
|
||||
// circularly reading 1/4 cycle of cosine data from the LUT based on the phase
|
||||
// address.
|
||||
//
|
||||
// -- --
|
||||
// --- --- --
|
||||
// -- -- ---
|
||||
// - - --
|
||||
// - - -
|
||||
// - - ----> -
|
||||
// - -
|
||||
// - - addr(cos): -->, <--, -->, <--
|
||||
// -- -- data(cos): + , - , - , +
|
||||
// --- --- addr(sin): <--, -->, <--, -->
|
||||
// ---- data(sin): + , + , - , -
|
||||
//
|
||||
// one cycle of cosine wave 1/4 cycle of cosine wave
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module addr_to_wave
|
||||
#(
|
||||
parameter PHASE_WIDTH = 16,
|
||||
parameter WAVE_WIDTH = 16
|
||||
)
|
||||
(
|
||||
// clock & reset
|
||||
input clk ,
|
||||
input rst ,
|
||||
|
||||
input [PHASE_WIDTH-1 : 0] phase ,
|
||||
|
||||
output [WAVE_WIDTH-1 : 0] cos_wave,
|
||||
output [WAVE_WIDTH-1 : 0] sin_wave
|
||||
);
|
||||
|
||||
integer i;
|
||||
|
||||
localparam ADDR_WIDTH = 16;
|
||||
localparam DATA_WIDTH = 16;
|
||||
localparam ROM_ADDR_WIDTH = ADDR_WIDTH - 2; // 1/4 cycle is stored
|
||||
localparam ROM_DATA_WIDTH = DATA_WIDTH - 1; // only positive data
|
||||
localparam ROM_MAX_INDEX = 2**ROM_ADDR_WIDTH-1;
|
||||
localparam DELAY = 3;
|
||||
|
||||
// mapping phase address to local format
|
||||
wire [ADDR_WIDTH-1 : 0] phase_addr;
|
||||
|
||||
if (PHASE_WIDTH >= ADDR_WIDTH) begin
|
||||
assign phase_addr = phase[PHASE_WIDTH-1 -: ADDR_WIDTH];
|
||||
end
|
||||
else begin
|
||||
assign phase_addr = {phase,{(ADDR_WIDTH-PHASE_WIDTH){1'b0}}};
|
||||
end
|
||||
|
||||
|
||||
// d1: buffer/stabilize input address
|
||||
// d2: phase segment decision
|
||||
// d3: wait for lut output data - [cos_lut_dout] & [sin_lut_dout]
|
||||
reg [ADDR_WIDTH-1 : 0] phase_addr_d [1 : DELAY];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
for (i = 1; i <= DELAY ; i = i + 1) begin
|
||||
phase_addr_d[i] <= 'b0;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
phase_addr_d[1] <= phase_addr;
|
||||
|
||||
for (i = 2; i <= DELAY ; i = i + 1) begin
|
||||
phase_addr_d[i] <= phase_addr_d[i-1];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// Generate cosine and sine address based on current phase segment
|
||||
reg [ROM_ADDR_WIDTH-1 : 0] cos_addr = 'b0;
|
||||
reg [ROM_ADDR_WIDTH-1 : 0] sin_addr = 'b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cos_addr <= 'b0;
|
||||
sin_addr <= 'b0;
|
||||
end
|
||||
else begin
|
||||
case (phase_addr_d[1][ADDR_WIDTH-1 -: 2])
|
||||
2'b00, 2'b10: begin
|
||||
cos_addr <= phase_addr_d[1];
|
||||
sin_addr <= ROM_MAX_INDEX - phase_addr_d[1];
|
||||
end
|
||||
2'b01, 2'b11: begin
|
||||
cos_addr <= ROM_MAX_INDEX - phase_addr_d[1];
|
||||
sin_addr <= phase_addr_d[1];
|
||||
end
|
||||
default: begin
|
||||
cos_addr <= 'b0;
|
||||
sin_addr <= 'b0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// Read 1/4 cycle of cosine data from BRAM. The Primitives Output Register and
|
||||
// the the Core Output Register are enabled, to provide better delay and latency
|
||||
// performance, so the output latency of both ports have reached 3 clock cycles.
|
||||
wire [ROM_DATA_WIDTH-1 : 0] cos_lut_dout;
|
||||
wire [ROM_DATA_WIDTH-1 : 0] sin_lut_dout;
|
||||
|
||||
cos_16384_16b u_cos_16384_16b
|
||||
(
|
||||
.clka (clk ), // input wire clka
|
||||
.addra (cos_addr ), // input wire [13 : 0] addra
|
||||
.douta (cos_lut_dout ), // output wire [14 : 0] douta
|
||||
.clkb (clk ), // input wire clkb
|
||||
.addrb (sin_addr ), // input wire [13 : 0] addrb
|
||||
.doutb (sin_lut_dout ) // output wire [14 : 0] doutb
|
||||
);
|
||||
|
||||
// Correct the sign of output data (above or below zero).
|
||||
reg signed [DATA_WIDTH-1 : 0] cos_dout;
|
||||
reg signed [DATA_WIDTH-1 : 0] sin_dout;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cos_dout <= 'b0;
|
||||
sin_dout <= 'b0;
|
||||
end
|
||||
else begin
|
||||
case (phase_addr_d[DELAY][ADDR_WIDTH-1 -: 2])
|
||||
2'b00: begin
|
||||
cos_dout <= cos_lut_dout;
|
||||
sin_dout <= sin_lut_dout;
|
||||
end
|
||||
2'b01: begin
|
||||
cos_dout <= -cos_lut_dout;
|
||||
sin_dout <= sin_lut_dout;
|
||||
end
|
||||
2'b10: begin
|
||||
cos_dout <= -cos_lut_dout;
|
||||
sin_dout <= -sin_lut_dout;
|
||||
end
|
||||
2'b11: begin
|
||||
cos_dout <= cos_lut_dout;
|
||||
sin_dout <= -sin_lut_dout;
|
||||
end
|
||||
default: begin
|
||||
cos_dout <= 'b0;
|
||||
sin_dout <= 'b0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// Output data to port
|
||||
/* FIXME: The truncation should be done by rounding operation, to avoid extra
|
||||
* DC component.
|
||||
*/
|
||||
if (WAVE_WIDTH <= DATA_WIDTH) begin
|
||||
assign cos_wave = cos_dout[DATA_WIDTH-1 -: WAVE_WIDTH];
|
||||
assign sin_wave = sin_dout[DATA_WIDTH-1 -: WAVE_WIDTH];
|
||||
end
|
||||
else begin
|
||||
assign cos_wave = {cos_dout,{(WAVE_WIDTH-DATA_WIDTH){1'b0}}};
|
||||
assign sin_wave = {sin_dout,{(WAVE_WIDTH-DATA_WIDTH){1'b0}}};
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,175 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
// _ _ ____
|
||||
// | | ___ ___| |__ / ___| __ _ ___
|
||||
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||
//
|
||||
// Create Date: 01/14/2024 02:50:34 PM
|
||||
// Design Name:
|
||||
// Module Name: dds_par
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description: This module generates parallel sine/cosine wave with continuous
|
||||
// phase, which can be used as polyphase adjustable carrier wave.
|
||||
// Parameter:
|
||||
// PHASE_WIDTH: Bit width of input phase address.
|
||||
// WAVE_WIDTH: Bit width of output sine/cosine wave.
|
||||
// PARALLEL_NUM: Number of parallel paths. The optimal wave is generated when
|
||||
// this number is power of 2, however the module should work fine with any
|
||||
// number of parallel paths.
|
||||
// Data format:
|
||||
// cos_wave/sin_wave: Suppose the samples are s = [s0, s1, ..., sN], then
|
||||
// cos_wave/sin_wave = {sN, ..., s1, s0}
|
||||
// Total latency: [PARALLEL_NUM+6] clock cycles, including 4 clock cycles for
|
||||
// addr_to_wave
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module dds_par
|
||||
#(
|
||||
parameter PHASE_WIDTH = 16,
|
||||
parameter WAVE_WIDTH = 16,
|
||||
parameter PARALLEL_NUM = 8
|
||||
)
|
||||
(
|
||||
input clk,
|
||||
input rst,
|
||||
|
||||
input [PHASE_WIDTH-1 : 0] phase_inc,
|
||||
|
||||
output [WAVE_WIDTH*PARALLEL_NUM-1 : 0] cos_wave,
|
||||
output [WAVE_WIDTH*PARALLEL_NUM-1 : 0] sin_wave
|
||||
);
|
||||
|
||||
localparam PARALLEL_NUM_LOG = $clog2(PARALLEL_NUM);
|
||||
localparam PHASE_CONFIG_DELAY = PARALLEL_NUM + 1;
|
||||
|
||||
genvar m;
|
||||
integer i;
|
||||
|
||||
// buffer
|
||||
reg [PHASE_WIDTH-1 : 0] phase_inc_d [1:2];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
for (i = 1; i <= 2 ; i = i + 1) begin
|
||||
phase_inc_d[i] <= 'b0;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
phase_inc_d[1] <= phase_inc;
|
||||
phase_inc_d[2] <= phase_inc_d[1];
|
||||
end
|
||||
end
|
||||
|
||||
// phase increment change identification
|
||||
reg phase_config_flag [0:PHASE_CONFIG_DELAY-1];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
for (i = 0; i < PHASE_CONFIG_DELAY; i = i + 1) begin
|
||||
phase_config_flag[i] <= 'b0;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
phase_config_flag[0] <= (phase_inc_d[2] != phase_inc_d[1]) ? 1'b1 : 'b0;
|
||||
for (i = 1; i < PHASE_CONFIG_DELAY; i = i + 1) begin
|
||||
phase_config_flag[i] <= phase_config_flag[i-1];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// offset counter
|
||||
reg [$clog2(PARALLEL_NUM)-1 : 0] phase_config_cnt = 'b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
phase_config_cnt <= 'b0;
|
||||
end
|
||||
else if (phase_config_flag[0]) begin
|
||||
phase_config_cnt <= phase_config_cnt + 1'b1;
|
||||
end
|
||||
else begin
|
||||
phase_config_cnt <= (phase_config_cnt == 'b0) ? 'b0 : phase_config_cnt + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
// phase offset generation based on new phase increment
|
||||
reg [PHASE_WIDTH-1 : 0] phase_off [0 : PARALLEL_NUM-1];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
for (i = 0; i < PARALLEL_NUM; i = i + 1) begin
|
||||
phase_off[i] <= 'b0;
|
||||
end
|
||||
end
|
||||
else if (phase_config_cnt != 'b0) begin
|
||||
phase_off[phase_config_cnt] <= phase_off[phase_config_cnt-1] + phase_inc_d[2];
|
||||
end
|
||||
end
|
||||
|
||||
// phase generation
|
||||
reg [PHASE_WIDTH-1 : 0] phase [0 : PARALLEL_NUM-1];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
for (i = 0; i < PARALLEL_NUM; i = i + 1) begin
|
||||
phase[i] <= 'b0;
|
||||
end
|
||||
end
|
||||
else if (phase_config_flag[PHASE_CONFIG_DELAY-1]) begin
|
||||
for (i = 0; i < PARALLEL_NUM; i = i + 1) begin
|
||||
phase[i] <= phase_off[i];
|
||||
end
|
||||
end
|
||||
else begin
|
||||
for (i = 0; i < PARALLEL_NUM; i = i + 1) begin
|
||||
phase[i] <= phase[i] + (phase_inc << PARALLEL_NUM_LOG);
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// phase to wave
|
||||
wire [WAVE_WIDTH-1 : 0] cos_wave_par [0 : PARALLEL_NUM-1];
|
||||
wire [WAVE_WIDTH-1 : 0] sin_wave_par [0 : PARALLEL_NUM-1];
|
||||
|
||||
generate
|
||||
for (m = 0; m < PARALLEL_NUM; m = m + 1) begin: phase_to_wave
|
||||
|
||||
addr_to_wave
|
||||
#(
|
||||
.PHASE_WIDTH (PHASE_WIDTH),
|
||||
.WAVE_WIDTH (WAVE_WIDTH )
|
||||
) u_addr_to_wave
|
||||
(
|
||||
// clock & reset
|
||||
.clk (clk ),
|
||||
.rst (rst ),
|
||||
|
||||
.phase (phase[m] ),
|
||||
|
||||
.cos_wave (cos_wave_par[m]),
|
||||
.sin_wave (sin_wave_par[m])
|
||||
);
|
||||
|
||||
// output to port
|
||||
assign cos_wave[WAVE_WIDTH*m +: WAVE_WIDTH] = cos_wave_par[m];
|
||||
assign sin_wave[WAVE_WIDTH*m +: WAVE_WIDTH] = sin_wave_par[m];
|
||||
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user