add dj_47dr_lmx vivado project
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version https://git-lfs.github.com/spec/v1
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oid sha256:6d03716e09c569dced4c3bc9492138d5eed6eafe7102eb15ace592a00ce69bfb
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size 34437472
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set_property -dict {PACKAGE_PIN F14 IOSTANDARD LVPECL } [get_ports pl_refclk_p ] ;# PL_CLK_P
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set_property -dict {PACKAGE_PIN F10 IOSTANDARD LVPECL } [get_ports pl_sysref_p ] ;# PL_SYSREF_P
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set_property -dict {PACKAGE_PIN B13 IOSTANDARD LVCMOS33} [get_ports lmk_spi_sck ] ;# LMK_SPI_SCK
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set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVCMOS33} [get_ports lmk_spi_cs ] ;# LMK_SPI_CS
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set_property -dict {PACKAGE_PIN C14 IOSTANDARD LVCMOS33} [get_ports lmk_spi_mosi ] ;# LMK_SPI_SDI
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set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS33} [get_ports lmk_spi_miso ] ;# LMK_SPI_SDO
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set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVCMOS33} [get_ports lmx_adc_spi_sck ] ;# LMX_RF_ADC_SCK
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set_property -dict {PACKAGE_PIN K14 IOSTANDARD LVCMOS33} [get_ports lmx_adc_spi_cs ] ;# LMX_RF_ADC_CS
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set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS33} [get_ports lmx_adc_spi_mosi ] ;# LMX_RF_ADC_SDI
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set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS33} [get_ports lmx_adc_spi_miso ] ;# LMX_RF_ADC_SDO
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set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS33} [get_ports lmx_dac_spi_sck ] ;# LMX_RF_DAC_CLK
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set_property -dict {PACKAGE_PIN G13 IOSTANDARD LVCMOS33} [get_ports lmx_dac_spi_cs ] ;# LMX_RF_DAC_CS
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set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS33} [get_ports lmx_dac_spi_mosi ] ;# LMX_RF_DAC_SDI
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set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports lmx_dac_spi_miso ] ;# LMX_RF_DAC_SDO
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# Route HDGC clock through BUFG to adjacent CMT
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets u_system_bd_wrapper/system_bd_i/mts_clk_gen/util_ds_buf_pl_clk/U0/USE_IBUFDS.GEN_IBUFDS[0].IBUFDS_I/O]
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+304
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{
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"schema": "xilinx.com:schema:json_instance:1.0",
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"ip_inst": {
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"xci_name": "system_bd_auto_pc_0",
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"cell_name": "ps8_0_axi_periph/s00_couplers/auto_pc",
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"component_reference": "xilinx.com:ip:axi_protocol_converter:2.1",
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"ip_revision": "31",
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"gen_directory": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_auto_pc_0",
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"parameters": {
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"component_parameters": {
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"SI_PROTOCOL": [ { "value": "AXI4", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
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"MI_PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
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"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
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"TRANSLATION_MODE": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"ADDR_WIDTH": [ { "value": "40", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"DATA_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"ID_WIDTH": [ { "value": "16", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"AWUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"ARUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"RUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"WUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"BUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"Component_Name": [ { "value": "system_bd_auto_pc_0", "resolve_type": "user", "usage": "all" } ]
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},
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"model_parameters": {
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"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
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"C_M_AXI_PROTOCOL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_S_AXI_PROTOCOL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_IGNORE_ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_AXI_ID_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_AXI_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_AXI_SUPPORTS_WRITE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_AXI_SUPPORTS_READ": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_AXI_SUPPORTS_USER_SIGNALS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_AXI_AWUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_AXI_ARUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_AXI_WUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_AXI_RUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_AXI_BUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_TRANSLATION_MODE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ]
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},
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"project_parameters": {
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"ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
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"BASE_BOARD_PART": [ { "value": "" } ],
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"BOARD_CONNECTIONS": [ { "value": "" } ],
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"DEVICE": [ { "value": "xczu47dr" } ],
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"NEXTGEN_VERSAL": [ { "value": "0" } ],
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"PACKAGE": [ { "value": "ffve1156" } ],
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"PREFHDL": [ { "value": "VERILOG" } ],
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"SILICON_REVISION": [ { "value": "" } ],
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"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
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"SPEEDGRADE": [ { "value": "-2" } ],
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"STATIC_POWER": [ { "value": "" } ],
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"TEMPERATURE_GRADE": [ { "value": "I" } ]
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},
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"runtime_parameters": {
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"IPCONTEXT": [ { "value": "IP_Integrator" } ],
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"IPREVISION": [ { "value": "31" } ],
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"MANAGED": [ { "value": "TRUE" } ],
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"OUTPUTDIR": [ { "value": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_auto_pc_0" } ],
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"SELECTEDSIMMODEL": [ { "value": "rtl" } ],
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"SHAREDDIR": [ { "value": "../../ipshared" } ],
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"SWVERSION": [ { "value": "2024.1" } ],
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"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
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}
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},
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"boundary": {
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"ports": {
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"aclk": [ { "direction": "in" } ],
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"aresetn": [ { "direction": "in" } ],
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"s_axi_awid": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0x0000" } ],
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"s_axi_awaddr": [ { "direction": "in", "size_left": "39", "size_right": "0", "driver_value": "0x0000000000" } ],
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"s_axi_awlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0x00" } ],
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"s_axi_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
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"s_axi_awburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x1" } ],
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"s_axi_awlock": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
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"s_axi_awcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
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"s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
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"s_axi_awregion": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
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"s_axi_awqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
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"s_axi_awvalid": [ { "direction": "in", "driver_value": "0x0" } ],
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"s_axi_awready": [ { "direction": "out" } ],
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"s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ],
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"s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0xF" } ],
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"s_axi_wlast": [ { "direction": "in", "driver_value": "0x1" } ],
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"s_axi_wvalid": [ { "direction": "in", "driver_value": "0x0" } ],
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"s_axi_wready": [ { "direction": "out" } ],
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"s_axi_bid": [ { "direction": "out", "size_left": "15", "size_right": "0" } ],
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"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
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"s_axi_bvalid": [ { "direction": "out" } ],
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"s_axi_bready": [ { "direction": "in", "driver_value": "0x0" } ],
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"s_axi_arid": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0x0000" } ],
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"s_axi_araddr": [ { "direction": "in", "size_left": "39", "size_right": "0", "driver_value": "0x0000000000" } ],
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"s_axi_arlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0x00" } ],
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"s_axi_arsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
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"s_axi_arburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x1" } ],
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"s_axi_arlock": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
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"s_axi_arcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
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"s_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
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"s_axi_arregion": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
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"s_axi_arqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
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"s_axi_arvalid": [ { "direction": "in", "driver_value": "0x0" } ],
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"s_axi_arready": [ { "direction": "out" } ],
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"s_axi_rid": [ { "direction": "out", "size_left": "15", "size_right": "0" } ],
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"s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
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"s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
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"s_axi_rlast": [ { "direction": "out" } ],
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"s_axi_rvalid": [ { "direction": "out" } ],
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"s_axi_rready": [ { "direction": "in", "driver_value": "0x0" } ],
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"m_axi_awaddr": [ { "direction": "out", "size_left": "39", "size_right": "0" } ],
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"m_axi_awprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
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"m_axi_awvalid": [ { "direction": "out" } ],
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"m_axi_awready": [ { "direction": "in", "driver_value": "0x0" } ],
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"m_axi_wdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
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"m_axi_wstrb": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
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"m_axi_wvalid": [ { "direction": "out" } ],
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"m_axi_wready": [ { "direction": "in", "driver_value": "0x0" } ],
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"m_axi_bresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
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"m_axi_bvalid": [ { "direction": "in", "driver_value": "0x0" } ],
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"m_axi_bready": [ { "direction": "out" } ],
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"m_axi_araddr": [ { "direction": "out", "size_left": "39", "size_right": "0" } ],
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"m_axi_arprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
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"m_axi_arvalid": [ { "direction": "out" } ],
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"m_axi_arready": [ { "direction": "in", "driver_value": "0x0" } ],
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"m_axi_rdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ],
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"m_axi_rresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
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"m_axi_rvalid": [ { "direction": "in", "driver_value": "0x0" } ],
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"m_axi_rready": [ { "direction": "out" } ]
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},
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"interfaces": {
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"S_AXI": {
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"vlnv": "xilinx.com:interface:aximm:1.0",
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"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
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"mode": "slave",
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"parameters": {
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"DATA_WIDTH": [ { "value": "32", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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"PROTOCOL": [ { "value": "AXI4", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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"FREQ_HZ": [ { "value": "96968727", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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"ID_WIDTH": [ { "value": "16", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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"ADDR_WIDTH": [ { "value": "40", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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"AWUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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"ARUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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"WUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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"RUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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"BUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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||||
"HAS_BURST": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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||||
"HAS_LOCK": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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"HAS_PROT": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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||||
"HAS_CACHE": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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||||
"HAS_QOS": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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||||
"HAS_REGION": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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||||
"HAS_WSTRB": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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||||
"HAS_BRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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||||
"HAS_RRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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||||
"SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "256", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_zynq_ultra_ps_e_0_1_pl_clk0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "4", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "4", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWID": [ { "physical_name": "s_axi_awid" } ],
|
||||
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
|
||||
"AWLEN": [ { "physical_name": "s_axi_awlen" } ],
|
||||
"AWSIZE": [ { "physical_name": "s_axi_awsize" } ],
|
||||
"AWBURST": [ { "physical_name": "s_axi_awburst" } ],
|
||||
"AWLOCK": [ { "physical_name": "s_axi_awlock" } ],
|
||||
"AWCACHE": [ { "physical_name": "s_axi_awcache" } ],
|
||||
"AWPROT": [ { "physical_name": "s_axi_awprot" } ],
|
||||
"AWREGION": [ { "physical_name": "s_axi_awregion" } ],
|
||||
"AWQOS": [ { "physical_name": "s_axi_awqos" } ],
|
||||
"AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
|
||||
"AWREADY": [ { "physical_name": "s_axi_awready" } ],
|
||||
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
|
||||
"WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
|
||||
"WLAST": [ { "physical_name": "s_axi_wlast" } ],
|
||||
"WVALID": [ { "physical_name": "s_axi_wvalid" } ],
|
||||
"WREADY": [ { "physical_name": "s_axi_wready" } ],
|
||||
"BID": [ { "physical_name": "s_axi_bid" } ],
|
||||
"BRESP": [ { "physical_name": "s_axi_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
|
||||
"BREADY": [ { "physical_name": "s_axi_bready" } ],
|
||||
"ARID": [ { "physical_name": "s_axi_arid" } ],
|
||||
"ARADDR": [ { "physical_name": "s_axi_araddr" } ],
|
||||
"ARLEN": [ { "physical_name": "s_axi_arlen" } ],
|
||||
"ARSIZE": [ { "physical_name": "s_axi_arsize" } ],
|
||||
"ARBURST": [ { "physical_name": "s_axi_arburst" } ],
|
||||
"ARLOCK": [ { "physical_name": "s_axi_arlock" } ],
|
||||
"ARCACHE": [ { "physical_name": "s_axi_arcache" } ],
|
||||
"ARPROT": [ { "physical_name": "s_axi_arprot" } ],
|
||||
"ARREGION": [ { "physical_name": "s_axi_arregion" } ],
|
||||
"ARQOS": [ { "physical_name": "s_axi_arqos" } ],
|
||||
"ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
|
||||
"ARREADY": [ { "physical_name": "s_axi_arready" } ],
|
||||
"RID": [ { "physical_name": "s_axi_rid" } ],
|
||||
"RDATA": [ { "physical_name": "s_axi_rdata" } ],
|
||||
"RRESP": [ { "physical_name": "s_axi_rresp" } ],
|
||||
"RLAST": [ { "physical_name": "s_axi_rlast" } ],
|
||||
"RVALID": [ { "physical_name": "s_axi_rvalid" } ],
|
||||
"RREADY": [ { "physical_name": "s_axi_rready" } ]
|
||||
}
|
||||
},
|
||||
"M_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "96968727", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "40", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_zynq_ultra_ps_e_0_1_pl_clk0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "4", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "4", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "m_axi_awaddr" } ],
|
||||
"AWPROT": [ { "physical_name": "m_axi_awprot" } ],
|
||||
"AWVALID": [ { "physical_name": "m_axi_awvalid" } ],
|
||||
"AWREADY": [ { "physical_name": "m_axi_awready" } ],
|
||||
"WDATA": [ { "physical_name": "m_axi_wdata" } ],
|
||||
"WSTRB": [ { "physical_name": "m_axi_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "m_axi_wvalid" } ],
|
||||
"WREADY": [ { "physical_name": "m_axi_wready" } ],
|
||||
"BRESP": [ { "physical_name": "m_axi_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "m_axi_bvalid" } ],
|
||||
"BREADY": [ { "physical_name": "m_axi_bready" } ],
|
||||
"ARADDR": [ { "physical_name": "m_axi_araddr" } ],
|
||||
"ARPROT": [ { "physical_name": "m_axi_arprot" } ],
|
||||
"ARVALID": [ { "physical_name": "m_axi_arvalid" } ],
|
||||
"ARREADY": [ { "physical_name": "m_axi_arready" } ],
|
||||
"RDATA": [ { "physical_name": "m_axi_rdata" } ],
|
||||
"RRESP": [ { "physical_name": "m_axi_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "m_axi_rvalid" } ],
|
||||
"RREADY": [ { "physical_name": "m_axi_rready" } ]
|
||||
}
|
||||
},
|
||||
"CLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXI:M_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "96968727", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_zynq_ultra_ps_e_0_1_pl_clk0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
},
|
||||
"RST": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+294
@@ -0,0 +1,294 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_bd_axi_spi_engine_0_0",
|
||||
"cell_name": "axi_spi_engine/axi_spi_engine",
|
||||
"component_reference": "analog.com:user:axi_spi_engine:1.0",
|
||||
"ip_revision": "1",
|
||||
"gen_directory": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"CMD_FIFO_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SYNC_FIFO_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SDO_FIFO_ADDRESS_WIDTH": [ { "value": "5", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SDI_FIFO_ADDRESS_WIDTH": [ { "value": "5", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MM_IF_TYPE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ASYNC_SPI_CLK": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"NUM_OFFLOAD": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"OFFLOAD0_CMD_MEM_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"OFFLOAD0_SDO_MEM_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ID": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_OF_SDI": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CFG_INFO_0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CFG_INFO_1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CFG_INFO_2": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CFG_INFO_3": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "system_bd_axi_spi_engine_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"CMD_FIFO_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"SYNC_FIFO_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"SDO_FIFO_ADDRESS_WIDTH": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"SDI_FIFO_ADDRESS_WIDTH": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"MM_IF_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"ASYNC_SPI_CLK": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"NUM_OFFLOAD": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"OFFLOAD0_CMD_MEM_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"OFFLOAD0_SDO_MEM_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"NUM_OF_SDI": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"CFG_INFO_0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"CFG_INFO_1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"CFG_INFO_2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"CFG_INFO_3": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu47dr" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffve1156" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "1" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axi_aclk": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_aresetn": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_awvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_awaddr": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awready": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wready": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"s_axi_bvalid": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_bready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_arvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_araddr": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arready": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"s_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_rvalid": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"s_axi_rready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"irq": [ { "direction": "out" } ],
|
||||
"spi_clk": [ { "direction": "in" } ],
|
||||
"spi_resetn": [ { "direction": "out" } ],
|
||||
"cmd_ready": [ { "direction": "in" } ],
|
||||
"cmd_valid": [ { "direction": "out" } ],
|
||||
"cmd_data": [ { "direction": "out", "size_left": "15", "size_right": "0" } ],
|
||||
"sdo_data_ready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"sdo_data_valid": [ { "direction": "out" } ],
|
||||
"sdo_data": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
|
||||
"sdi_data_ready": [ { "direction": "out" } ],
|
||||
"sdi_data_valid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"sdi_data": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
"sync_ready": [ { "direction": "out" } ],
|
||||
"sync_valid": [ { "direction": "in" } ],
|
||||
"sync_data": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"s_axi": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "s_axi",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "96968727", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "16", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_zynq_ultra_ps_e_0_1_pl_clk0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
|
||||
"AWPROT": [ { "physical_name": "s_axi_awprot" } ],
|
||||
"AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
|
||||
"AWREADY": [ { "physical_name": "s_axi_awready" } ],
|
||||
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
|
||||
"WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "s_axi_wvalid" } ],
|
||||
"WREADY": [ { "physical_name": "s_axi_wready" } ],
|
||||
"BRESP": [ { "physical_name": "s_axi_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
|
||||
"BREADY": [ { "physical_name": "s_axi_bready" } ],
|
||||
"ARADDR": [ { "physical_name": "s_axi_araddr" } ],
|
||||
"ARPROT": [ { "physical_name": "s_axi_arprot" } ],
|
||||
"ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
|
||||
"ARREADY": [ { "physical_name": "s_axi_arready" } ],
|
||||
"RDATA": [ { "physical_name": "s_axi_rdata" } ],
|
||||
"RRESP": [ { "physical_name": "s_axi_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "s_axi_rvalid" } ],
|
||||
"RREADY": [ { "physical_name": "s_axi_rready" } ]
|
||||
}
|
||||
},
|
||||
"s_axi_aclk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "s_axi", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axi_aclk" } ]
|
||||
}
|
||||
},
|
||||
"s_axi_aresetn": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axi_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"spi_engine_ctrl": {
|
||||
"vlnv": "analog.com:interface:spi_engine_ctrl:1.0",
|
||||
"abstraction_type": "analog.com:interface:spi_engine_ctrl_rtl:1.0",
|
||||
"mode": "master",
|
||||
"port_maps": {
|
||||
"cmd_ready": [ { "physical_name": "cmd_ready" } ],
|
||||
"cmd_valid": [ { "physical_name": "cmd_valid" } ],
|
||||
"cmd_data": [ { "physical_name": "cmd_data" } ],
|
||||
"sdo_ready": [ { "physical_name": "sdo_data_ready" } ],
|
||||
"sdo_valid": [ { "physical_name": "sdo_data_valid" } ],
|
||||
"sdo_data": [ { "physical_name": "sdo_data" } ],
|
||||
"sdi_ready": [ { "physical_name": "sdi_data_ready" } ],
|
||||
"sdi_valid": [ { "physical_name": "sdi_data_valid" } ],
|
||||
"sdi_data": [ { "physical_name": "sdi_data" } ],
|
||||
"sync_ready": [ { "physical_name": "sync_ready" } ],
|
||||
"sync_valid": [ { "physical_name": "sync_valid" } ],
|
||||
"sync_data": [ { "physical_name": "sync_data" } ]
|
||||
}
|
||||
},
|
||||
"spi_engine_ctrl_signal_clock": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "spi_engine_ctrl", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "spi_resetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "96968727", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_zynq_ultra_ps_e_0_1_pl_clk0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "spi_clk" } ]
|
||||
}
|
||||
},
|
||||
"spi_engine_ctrl_signal_reset": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "spi_resetn" } ]
|
||||
}
|
||||
},
|
||||
"spi_engine_offload_ctrl0_s_axi_signal_clock": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "spi_engine_offload_ctrl0:s_axi", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "96968727", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_zynq_ultra_ps_e_0_1_pl_clk0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axi_aclk" } ]
|
||||
}
|
||||
},
|
||||
"spi_engine_offload_ctrl0_s_axi_signal_reset": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axi_aresetn" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"s_axi": {
|
||||
"address_blocks": {
|
||||
"axi_lite": {
|
||||
"base_address": "0",
|
||||
"range": "65536"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+658
@@ -0,0 +1,658 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_bd_clk_wiz_0_0",
|
||||
"cell_name": "mts_clk_gen/clk_wiz_pl_clk",
|
||||
"component_reference": "xilinx.com:ip:clk_wiz:6.0",
|
||||
"ip_revision": "14",
|
||||
"gen_directory": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_clk_wiz_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "system_bd_clk_wiz_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"ENABLE_CLOCK_MONITOR": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ENABLE_USER_CLOCK0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ENABLE_USER_CLOCK1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ENABLE_USER_CLOCK2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ENABLE_USER_CLOCK3": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Enable_PLL0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Enable_PLL1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PRECISION": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
|
||||
"PRIMTYPE_SEL": [ { "value": "mmcm_adv", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLOCK_MGR_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_FREQ_SYNTH": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_SPREAD_SPECTRUM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_PHASE_ALIGNMENT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_MIN_POWER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_DYN_PHASE_SHIFT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_DYN_RECONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "user", "usage": "all" } ],
|
||||
"PRIM_IN_FREQ": [ { "value": "245.76", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "user", "usage": "all" } ],
|
||||
"PHASESHIFT_MODE": [ { "value": "LATENCY", "resolve_type": "user", "usage": "all" } ],
|
||||
"IN_JITTER_UNITS": [ { "value": "Units_UI", "resolve_type": "user", "usage": "all" } ],
|
||||
"RELATIVE_INCLK": [ { "value": "REL_PRIMARY", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_INCLK_SWITCHOVER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"SECONDARY_IN_FREQ": [ { "value": "100.000", "value_permission": "bd_and_user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "user", "usage": "all" } ],
|
||||
"SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
|
||||
"JITTER_OPTIONS": [ { "value": "UI", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKIN1_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKIN2_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKIN1_JITTER_PS": [ { "value": "40.69", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT2_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT3_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT4_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT5_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT6_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT7_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"NUM_OUT_CLKS": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLK_OUT1_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_OUT2_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_OUT3_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_OUT4_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_OUT5_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_OUT6_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_OUT7_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "user", "usage": "all" } ],
|
||||
"DADDR_PORT": [ { "value": "daddr", "resolve_type": "user", "usage": "all" } ],
|
||||
"DCLK_PORT": [ { "value": "dclk", "resolve_type": "user", "usage": "all" } ],
|
||||
"DRDY_PORT": [ { "value": "drdy", "resolve_type": "user", "usage": "all" } ],
|
||||
"DWE_PORT": [ { "value": "dwe", "resolve_type": "user", "usage": "all" } ],
|
||||
"DIN_PORT": [ { "value": "din", "resolve_type": "user", "usage": "all" } ],
|
||||
"DOUT_PORT": [ { "value": "dout", "resolve_type": "user", "usage": "all" } ],
|
||||
"DEN_PORT": [ { "value": "den", "resolve_type": "user", "usage": "all" } ],
|
||||
"PSCLK_PORT": [ { "value": "psclk", "resolve_type": "user", "usage": "all" } ],
|
||||
"PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ],
|
||||
"PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ],
|
||||
"PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "245.76", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"USE_MAX_I_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_MIN_O_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT1_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT2_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT3_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT4_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT5_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT6_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT7_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ],
|
||||
"FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "user", "usage": "all" } ],
|
||||
"PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "user", "usage": "all" } ],
|
||||
"SUMMARY_STRINGS": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_LOCKED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CALC_DONE": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_RESET": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_POWER_DOWN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_STATUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_FREEZE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_CLK_VALID": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_INCLK_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_CLKFB_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"RESET_PORT": [ { "value": "reset", "resolve_type": "user", "usage": "all" } ],
|
||||
"LOCKED_PORT": [ { "value": "locked", "resolve_type": "user", "usage": "all" } ],
|
||||
"POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "user", "usage": "all" } ],
|
||||
"STATUS_PORT": [ { "value": "STATUS", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "user", "usage": "all" } ],
|
||||
"INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "user", "usage": "all" } ],
|
||||
"SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "user", "usage": "all" } ],
|
||||
"SS_MOD_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
|
||||
"MMCM_DIVCLK_DIVIDE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
|
||||
"MMCM_CLKFBOUT_MULT_F": [ { "value": "4.875", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKIN1_PERIOD": [ { "value": "4.069", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_COMPENSATION": [ { "value": "AUTO", "resolve_type": "user", "usage": "all" } ],
|
||||
"MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT0_DIVIDE_F": [ { "value": "4.875", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"OVERRIDE_PLL": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"PLL_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
|
||||
"PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
|
||||
"PLL_CLKFBOUT_MULT": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "user", "usage": "all" } ],
|
||||
"PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKIN_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "user", "usage": "all" } ],
|
||||
"PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"RESET_TYPE": [ { "value": "ACTIVE_HIGH", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_SAFE_CLOCK_STARTUP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_CLOCK_SEQUENCING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"DIFF_CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"DIFF_CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
|
||||
"RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"ENABLE_CDDC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "user", "usage": "all" } ],
|
||||
"CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "user", "usage": "all" } ],
|
||||
"ENABLE_CLKOUTPHY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_JITTER": [ { "value": "85.228", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_PHASE_ERROR": [ { "value": "77.902", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT2_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT2_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT3_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT3_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT4_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT4_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT5_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT5_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT6_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT6_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT7_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT7_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"INPUT_MODE": [ { "value": "frequency", "resolve_type": "user", "usage": "all" } ],
|
||||
"INTERFACE_SELECTION": [ { "value": "Enable_AXI", "resolve_type": "user", "usage": "all" } ],
|
||||
"AXI_DRP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"PHASE_DUTY_CONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_CLKOUT2_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_ENABLE_CLOCK_MONITOR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_USER_CLOCK0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_USER_CLOCK1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_USER_CLOCK2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_USER_CLOCK3": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_Enable_PLL0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_Enable_PLL1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PRECISION": [ { "value": "1", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT4_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT5_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT6_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT7_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_CLKOUT1_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_CLKOUT2_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_CLKOUT3_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_CLKOUT4_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"c_component_name": [ { "value": "system_bd_clk_wiz_0_0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_FREQ_SYNTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_PHASE_ALIGNMENT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_MIN_POWER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_MIN_O_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_MAX_I_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_DYN_PHASE_SHIFT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_INCLK_SWITCHOVER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_DYN_RECONFIG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_SPREAD_SPECTRUM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_FAST_SIMULATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRIMTYPE_SEL": [ { "value": "AUTO", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_CLK_VALID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRIM_IN_FREQ": [ { "value": "245.76", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PHASESHIFT_MODE": [ { "value": "LATENCY", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_RESET": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RESET_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_LOCKED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_INCLK_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_CLKFB_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_POWER_DOWN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_STATUS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_FREEZE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_OUT_CLKS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_INCLK_SUM_ROW0": [ { "value": "Input Clock Freq (MHz) Input Jitter (UI)", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_INCLK_SUM_ROW1": [ { "value": "__primary__________245.76____________0.010", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_INCLK_SUM_ROW2": [ { "value": "no_secondary_input_clock ", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW0A": [ { "value": " Output Output Phase Duty Cycle Pk-to-Pk Phase", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW0B": [ { "value": " Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__245.76000______0.000______50.0_______85.228_____77.902", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW2": [ { "value": "no_CLK_OUT2_output", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW3": [ { "value": "no_CLK_OUT3_output", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW4": [ { "value": "no_CLK_OUT4_output", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW5": [ { "value": "no_CLK_OUT5_output", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW6": [ { "value": "no_CLK_OUT6_output", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW7": [ { "value": "no_CLK_OUT7_output", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "245.76", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT1_OUT_FREQ": [ { "value": "245.76000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT5_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT6_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT7_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT7_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT1_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT5_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT6_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT7_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_USE_SAFE_CLOCK_STARTUP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_CLOCK_SEQUENCING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_NOTES": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKFBOUT_MULT_F": [ { "value": "4.875", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKIN1_PERIOD": [ { "value": "4.069", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT4_CASCADE": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"C_MMCM_CLOCK_HOLD": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"C_MMCM_COMPENSATION": [ { "value": "AUTO", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_STARTUP_WAIT": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "4.875", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLL_NOTES": [ { "value": "No notes", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLL_CLKFBOUT_MULT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKIN_PERIOD": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLOCK_MGR_TYPE": [ { "value": "NA", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OVERRIDE_MMCM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OVERRIDE_PLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_RESET_PORT": [ { "value": "reset", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_LOCKED_PORT": [ { "value": "locked", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DADDR_PORT": [ { "value": "daddr", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DCLK_PORT": [ { "value": "dclk", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DRDY_PORT": [ { "value": "drdy", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DWE_PORT": [ { "value": "dwe", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIN_PORT": [ { "value": "din", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DOUT_PORT": [ { "value": "dout", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DEN_PORT": [ { "value": "den", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PSCLK_PORT": [ { "value": "psclk", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PSEN_PORT": [ { "value": "psen", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PSDONE_PORT": [ { "value": "psdone", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_STATUS_PORT": [ { "value": "STATUS", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKIN1_JITTER_PS": [ { "value": "40.69", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SS_MOD_PERIOD": [ { "value": "4000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_HAS_CDDC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUTPHY_MODE": [ { "value": "VCO", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_ENABLE_CLKOUTPHY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INTERFACE_SELECTION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_ADDR_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_POWER_REG": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT0_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT0_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT1_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT1_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT2_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT2_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT3_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT3_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT4_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT4_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT5_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT5_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT6_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT6_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFBOUT_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFBOUT_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVCLK": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_LOCK_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_LOCK_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_LOCK_3": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_FILTER_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_FILTER_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE1_AUTO": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE2_AUTO": [ { "value": "0.20512820512820512", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE3_AUTO": [ { "value": "0.20512820512820512", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE4_AUTO": [ { "value": "0.20512820512820512", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE5_AUTO": [ { "value": "0.20512820512820512", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE6_AUTO": [ { "value": "0.20512820512820512", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE7_AUTO": [ { "value": "0.20512820512820512", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLLBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLLBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLLBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLLBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLLBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV5": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV6": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV7": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT0_ACTUAL_FREQ": [ { "value": "245.76000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT1_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT2_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT3_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT4_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT5_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT6_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_M_MAX": [ { "value": "128.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_M_MIN": [ { "value": "2.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_D_MAX": [ { "value": "93.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_D_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_O_MAX": [ { "value": "128.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_O_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_VCO_MIN": [ { "value": "800.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_VCO_MAX": [ { "value": "1600.000", "resolve_type": "generated", "format": "float", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu47dr" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffve1156" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "14" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_clk_wiz_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"clk_in1": [ { "direction": "in" } ],
|
||||
"clk_out1": [ { "direction": "out" } ],
|
||||
"locked": [ { "direction": "out" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"clock_CLK_IN1": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "245760000", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_util_ds_buf_0_0_IBUF_OUT", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BOARD.ASSOCIATED_PARAM": [ { "value": "CLK_IN1_BOARD_INTERFACE", "value_permission": "bd", "usage": "all", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK_IN1": [ { "physical_name": "clk_in1" } ]
|
||||
}
|
||||
},
|
||||
"clock_CLK_OUT1": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "245760000", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_clk_wiz_0_0_clk_out1", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK_OUT1": [ { "physical_name": "clk_out1" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+353
@@ -0,0 +1,353 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_bd_ps8_0_axi_periph_0",
|
||||
"cell_name": "ps8_0_axi_periph",
|
||||
"component_reference": "xilinx.com:ip:axi_interconnect:2.1",
|
||||
"ip_revision": "32",
|
||||
"gen_directory": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_ps8_0_axi_periph_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"NUM_SI": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_MI": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"STRATEGY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ENABLE_ADVANCED_OPTIONS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ENABLE_PROTOCOL_CHECKERS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"XBAR_DATA_WIDTH": [ { "value": "32", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCHK_WAITS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCHK_MAX_RD_BURSTS": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCHK_MAX_WR_BURSTS": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
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+196
@@ -0,0 +1,196 @@
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||||
"C_EXT_RST_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AUX_RST_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EXT_RESET_HIGH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AUX_RESET_HIGH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_BUS_RST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_PERP_RST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_INTERCONNECT_ARESETN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_PERP_ARESETN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu47dr" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffve1156" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "15" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_rst_ps8_0_96M_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"slowest_sync_clk": [ { "direction": "in" } ],
|
||||
"ext_reset_in": [ { "direction": "in" } ],
|
||||
"aux_reset_in": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"mb_debug_sys_rst": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"dcm_locked": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"mb_reset": [ { "direction": "out", "driver_value": "0x0" } ],
|
||||
"bus_struct_reset": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"peripheral_reset": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"interconnect_aresetn": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "1" } ],
|
||||
"peripheral_aresetn": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "1" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"clock": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_RESET": [ { "value": "mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "96968727", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_zynq_ultra_ps_e_0_1_pl_clk0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "slowest_sync_clk" } ]
|
||||
}
|
||||
},
|
||||
"ext_reset": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"BOARD.ASSOCIATED_PARAM": [ { "value": "RESET_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "ext_reset_in" } ]
|
||||
}
|
||||
},
|
||||
"aux_reset": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aux_reset_in" } ]
|
||||
}
|
||||
},
|
||||
"dbg_reset": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "mb_debug_sys_rst" } ]
|
||||
}
|
||||
},
|
||||
"mb_rst": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"TYPE": [ { "value": "PROCESSOR", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "mb_reset" } ]
|
||||
}
|
||||
},
|
||||
"bus_struct_reset": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"TYPE": [ { "value": "INTERCONNECT", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "bus_struct_reset" } ]
|
||||
}
|
||||
},
|
||||
"interconnect_low_rst": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"TYPE": [ { "value": "INTERCONNECT", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "interconnect_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"peripheral_high_rst": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"TYPE": [ { "value": "PERIPHERAL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "peripheral_reset" } ]
|
||||
}
|
||||
},
|
||||
"peripheral_low_rst": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"TYPE": [ { "value": "PERIPHERAL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "peripheral_aresetn" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+176
@@ -0,0 +1,176 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_bd_spi_engine_execution_0_0",
|
||||
"cell_name": "axi_spi_engine/spi_engine_execution",
|
||||
"component_reference": "analog.com:user:spi_engine_execution:1.0",
|
||||
"ip_revision": "1",
|
||||
"gen_directory": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"NUM_OF_CS": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DEFAULT_SPI_CFG": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DEFAULT_CLK_DIV": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_OF_SDI": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SDO_DEFAULT": [ { "value": "\"0\"", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"ECHO_SCLK": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"SDI_DELAY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "system_bd_spi_engine_execution_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"NUM_OF_CS": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"DEFAULT_SPI_CFG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"DEFAULT_CLK_DIV": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"NUM_OF_SDI": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"SDO_DEFAULT": [ { "value": "\"0\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"ECHO_SCLK": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"SDI_DELAY": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu47dr" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffve1156" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "1" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"clk": [ { "direction": "in" } ],
|
||||
"resetn": [ { "direction": "in" } ],
|
||||
"active": [ { "direction": "out" } ],
|
||||
"cmd_ready": [ { "direction": "out" } ],
|
||||
"cmd_valid": [ { "direction": "in" } ],
|
||||
"cmd": [ { "direction": "in", "size_left": "15", "size_right": "0" } ],
|
||||
"sdo_data_valid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"sdo_data_ready": [ { "direction": "out" } ],
|
||||
"sdo_data": [ { "direction": "in", "size_left": "7", "size_right": "0" } ],
|
||||
"sdi_data_ready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"sdi_data_valid": [ { "direction": "out" } ],
|
||||
"sdi_data": [ { "direction": "out", "size_left": "23", "size_right": "0" } ],
|
||||
"sync_ready": [ { "direction": "in" } ],
|
||||
"sync_valid": [ { "direction": "out" } ],
|
||||
"sync": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
|
||||
"sclk": [ { "direction": "out" } ],
|
||||
"sdo": [ { "direction": "out" } ],
|
||||
"sdo_t": [ { "direction": "out" } ],
|
||||
"sdi": [ { "direction": "in", "size_left": "2", "size_right": "0" } ],
|
||||
"cs": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"three_wire": [ { "direction": "out" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"ctrl": {
|
||||
"vlnv": "analog.com:interface:spi_engine_ctrl:1.0",
|
||||
"abstraction_type": "analog.com:interface:spi_engine_ctrl_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"port_maps": {
|
||||
"cmd_ready": [ { "physical_name": "cmd_ready" } ],
|
||||
"cmd_valid": [ { "physical_name": "cmd_valid" } ],
|
||||
"cmd_data": [ { "physical_name": "cmd" } ],
|
||||
"sdo_ready": [ { "physical_name": "sdo_data_ready" } ],
|
||||
"sdo_valid": [ { "physical_name": "sdo_data_valid" } ],
|
||||
"sdo_data": [ { "physical_name": "sdo_data" } ],
|
||||
"sdi_ready": [ { "physical_name": "sdi_data_ready" } ],
|
||||
"sdi_valid": [ { "physical_name": "sdi_data_valid" } ],
|
||||
"sdi_data": [ { "physical_name": "sdi_data" } ],
|
||||
"sync_ready": [ { "physical_name": "sync_ready" } ],
|
||||
"sync_valid": [ { "physical_name": "sync_valid" } ],
|
||||
"sync_data": [ { "physical_name": "sync" } ]
|
||||
}
|
||||
},
|
||||
"ctrl_signal_clock": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "ctrl", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "resetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "clk" } ]
|
||||
}
|
||||
},
|
||||
"ctrl_signal_reset": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "resetn" } ]
|
||||
}
|
||||
},
|
||||
"spi": {
|
||||
"vlnv": "analog.com:interface:spi_engine:1.0",
|
||||
"abstraction_type": "analog.com:interface:spi_engine_rtl:1.0",
|
||||
"mode": "master",
|
||||
"port_maps": {
|
||||
"sclk": [ { "physical_name": "sclk" } ],
|
||||
"sdi": [ { "physical_name": "sdi" } ],
|
||||
"sdo": [ { "physical_name": "sdo" } ],
|
||||
"sdo_t": [ { "physical_name": "sdo_t" } ],
|
||||
"three_wire": [ { "physical_name": "three_wire" } ],
|
||||
"cs": [ { "physical_name": "cs" } ]
|
||||
}
|
||||
},
|
||||
"spi_signal_clock": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "spi", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "resetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "96968727", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_zynq_ultra_ps_e_0_1_pl_clk0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "clk" } ]
|
||||
}
|
||||
},
|
||||
"spi_signal_reset": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "resetn" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+3911
File diff suppressed because it is too large
Load Diff
+3117
File diff suppressed because it is too large
Load Diff
+99
@@ -0,0 +1,99 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_bd_util_ds_buf_0_0",
|
||||
"cell_name": "mts_clk_gen/util_ds_buf_pl_clk",
|
||||
"component_reference": "xilinx.com:ip:util_ds_buf:2.2",
|
||||
"ip_revision": "32",
|
||||
"gen_directory": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_util_ds_buf_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"C_SIZE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_BUF_TYPE": [ { "value": "IBUFDS", "resolve_type": "user", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "system_bd_util_ds_buf_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"BOARD_PARAMETER": [ { "value": " ", "resolve_type": "user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "156250000", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"DIFF_CLK_IN_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_BUFGCE_DIV": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_BUFG_GT_SYNC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"C_OBUFDS_GTE5_ADV": [ { "value": "\"00\"", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"C_REFCLK_ICNTL_TX": [ { "value": "\"00000\"", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_BUF_TYPE": [ { "value": "IBUFDS", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SIZE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_BUFGCE_DIV": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_BUFG_GT_SYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SIM_DEVICE": [ { "value": "VERSAL_AI_CORE_ES1", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OBUFDS_GTE5_ADV": [ { "value": "\"00\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_REFCLK_ICNTL_TX": [ { "value": "\"00000\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu47dr" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffve1156" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "32" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_util_ds_buf_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"IBUF_DS_P": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"IBUF_DS_N": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"IBUF_OUT": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"CLK_IN_D": {
|
||||
"vlnv": "xilinx.com:interface:diff_clock:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:diff_clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"BOARD.ASSOCIATED_PARAM": [ { "value": "DIFF_CLK_IN_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"CAN_DEBUG": [ { "value": "false", "value_permission": "bd", "resolve_type": "generated", "format": "bool", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "245760000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK_P": [ { "physical_name": "IBUF_DS_P" } ],
|
||||
"CLK_N": [ { "physical_name": "IBUF_DS_N" } ]
|
||||
}
|
||||
},
|
||||
"IBUF_OUT": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "245760000", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_util_ds_buf_0_0_IBUF_OUT", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "IBUF_OUT" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+102
@@ -0,0 +1,102 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_bd_util_ds_buf_0_1",
|
||||
"cell_name": "mts_clk_gen/util_bufg_pl_clk",
|
||||
"component_reference": "xilinx.com:ip:util_ds_buf:2.2",
|
||||
"ip_revision": "32",
|
||||
"gen_directory": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_util_ds_buf_0_1",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"C_SIZE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_BUF_TYPE": [ { "value": "BUFG", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "system_bd_util_ds_buf_0_1", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"BOARD_PARAMETER": [ { "value": " ", "resolve_type": "user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "156250000", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"DIFF_CLK_IN_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_BUFGCE_DIV": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_BUFG_GT_SYNC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"C_OBUFDS_GTE5_ADV": [ { "value": "\"00\"", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"C_REFCLK_ICNTL_TX": [ { "value": "\"00000\"", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_BUF_TYPE": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SIZE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_BUFGCE_DIV": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_BUFG_GT_SYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SIM_DEVICE": [ { "value": "VERSAL_AI_CORE_ES1", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OBUFDS_GTE5_ADV": [ { "value": "\"00\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_REFCLK_ICNTL_TX": [ { "value": "\"00000\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu47dr" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffve1156" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "32" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_util_ds_buf_0_1" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"BUFG_I": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"BUFG_O": [ { "direction": "out", "size_left": "0", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"BUFG_I": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "245760000", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_util_ds_buf_0_0_IBUF_OUT", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "BUFG_I" } ]
|
||||
}
|
||||
},
|
||||
"BUFG_O": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "245760000", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_util_ds_buf_0_0_IBUF_OUT", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "BUFG_O" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+99
@@ -0,0 +1,99 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_bd_util_ds_buf_1_0",
|
||||
"cell_name": "mts_clk_gen/util_ds_buf_pl_sysref",
|
||||
"component_reference": "xilinx.com:ip:util_ds_buf:2.2",
|
||||
"ip_revision": "32",
|
||||
"gen_directory": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_util_ds_buf_1_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"C_SIZE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_BUF_TYPE": [ { "value": "IBUFDS", "resolve_type": "user", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "system_bd_util_ds_buf_1_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"BOARD_PARAMETER": [ { "value": " ", "resolve_type": "user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "156250000", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"DIFF_CLK_IN_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_BUFGCE_DIV": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_BUFG_GT_SYNC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"C_OBUFDS_GTE5_ADV": [ { "value": "\"00\"", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"C_REFCLK_ICNTL_TX": [ { "value": "\"00000\"", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_BUF_TYPE": [ { "value": "IBUFDS", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SIZE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_BUFGCE_DIV": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_BUFG_GT_SYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SIM_DEVICE": [ { "value": "VERSAL_AI_CORE_ES1", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OBUFDS_GTE5_ADV": [ { "value": "\"00\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_REFCLK_ICNTL_TX": [ { "value": "\"00000\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu47dr" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffve1156" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "32" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_util_ds_buf_1_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"IBUF_DS_P": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"IBUF_DS_N": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"IBUF_OUT": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"CLK_IN_D": {
|
||||
"vlnv": "xilinx.com:interface:diff_clock:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:diff_clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"BOARD.ASSOCIATED_PARAM": [ { "value": "DIFF_CLK_IN_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"CAN_DEBUG": [ { "value": "false", "value_permission": "bd", "resolve_type": "generated", "format": "bool", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK_P": [ { "physical_name": "IBUF_DS_P" } ],
|
||||
"CLK_N": [ { "physical_name": "IBUF_DS_N" } ]
|
||||
}
|
||||
},
|
||||
"IBUF_OUT": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_util_ds_buf_1_0_IBUF_OUT", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "IBUF_OUT" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+1523
File diff suppressed because it is too large
Load Diff
+308
@@ -0,0 +1,308 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_bd_xlconcat_0_0",
|
||||
"cell_name": "xlconcat_0",
|
||||
"component_reference": "xilinx.com:ip:xlconcat:2.1",
|
||||
"ip_revision": "6",
|
||||
"gen_directory": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_xlconcat_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "system_bd_xlconcat_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"NUM_PORTS": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN0_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN1_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN2_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN3_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN4_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN5_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN6_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN7_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN8_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN9_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN10_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN11_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN12_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN13_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN14_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN15_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN16_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN17_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN18_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN19_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN20_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN21_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN22_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN23_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN24_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN25_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN26_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN27_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN28_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN29_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN30_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN31_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN32_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN33_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN34_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN35_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN36_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN37_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN38_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN39_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN40_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN41_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN42_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN43_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN44_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN45_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN46_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN47_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN48_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN49_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN50_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN51_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN52_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN53_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN54_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN55_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN56_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN57_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN58_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN59_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN60_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN61_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN62_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN63_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN64_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN65_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN66_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN67_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN68_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN69_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
+50
@@ -0,0 +1,50 @@
|
||||
{
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
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|
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|
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|
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|
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|
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|
||||
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|
||||
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|
||||
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|
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|
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|
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|
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|
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|
||||
+126
@@ -0,0 +1,126 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_bd_xpm_cdc_gen_0_0",
|
||||
"cell_name": "mts_clk_gen/xpm_cdc_gen_pl_sysref",
|
||||
"component_reference": "xilinx.com:ip:xpm_cdc_gen:1.0",
|
||||
"ip_revision": "4",
|
||||
"gen_directory": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_xpm_cdc_gen_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
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|
||||
"SRC_CLK_PERIOD": [ { "value": "5000", "resolve_type": "user", "usage": "all" } ],
|
||||
"DEST_CLK_PERIOD": [ { "value": "2500", "resolve_type": "user", "usage": "all" } ],
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"SIM_LOSSLESS_GRAY_CHK": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"Component_Name": [ { "value": "system_bd_xpm_cdc_gen_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"RST_ACTIVE_HIGH": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ]
|
||||
},
|
||||
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|
||||
"ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
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|
||||
},
|
||||
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|
||||
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|
||||
"IPREVISION": [ { "value": "4" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_xpm_cdc_gen_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"src_clk": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"dest_clk": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"src_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "1" } ],
|
||||
"dest_out": [ { "direction": "out", "size_left": "0", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
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|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "245760000", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
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|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "dest_clk" } ]
|
||||
}
|
||||
},
|
||||
"src_signal_clock": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "200000000", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
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|
||||
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|
||||
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|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "src_clk" } ]
|
||||
}
|
||||
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|
||||
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|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+126
@@ -0,0 +1,126 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_bd_xpm_cdc_gen_pl_sysref_0",
|
||||
"cell_name": "mts_clk_gen/xpm_cdc_gen_mts_sysref",
|
||||
"component_reference": "xilinx.com:ip:xpm_cdc_gen:1.0",
|
||||
"ip_revision": "4",
|
||||
"gen_directory": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_xpm_cdc_gen_pl_sysref_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"SRC_INPUT_REG": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"SIM_LOSSLESS_GRAY_CHK": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"DEST_EXT_HSK": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"REG_OUTPUT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"RST_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"INIT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"SRC_SYNC_FF": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"RST_ACTIVE_HIGH": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "system_bd_xpm_cdc_gen_pl_sysref_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_CDC_TYPE": [ { "value": "6", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"SRC_CLK_PERIOD": [ { "value": "5000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"DEST_CLK_PERIOD": [ { "value": "2500", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"SIM_ASSERT_CHK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"DEST_SYNC_FF": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"INIT_SYNC_FF": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"SRC_INPUT_REG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"REG_OUTPUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"SIM_LOSSLESS_GRAY_CHK": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"SRC_SYNC_FF": [ { "value": "4", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"DEST_EXT_HSK": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"RST_USED": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"INIT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"RST_ACTIVE_HIGH": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu47dr" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffve1156" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "4" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_xpm_cdc_gen_pl_sysref_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"src_clk": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"dest_clk": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"src_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "1" } ],
|
||||
"dest_out": [ { "direction": "out", "size_left": "0", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"dest_signal_clock": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "245760000", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_clk_wiz_0_0_clk_out1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "dest_clk" } ]
|
||||
}
|
||||
},
|
||||
"src_signal_clock": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "200000000", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "src_clk" } ]
|
||||
}
|
||||
},
|
||||
"RST": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+2045
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,249 @@
|
||||
{
|
||||
"graphjs": {
|
||||
"version": "1.0",
|
||||
"keys": [
|
||||
{
|
||||
"abrv": "VH",
|
||||
"name": "vert_hid",
|
||||
"type": "int",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "VM",
|
||||
"name": "vert_name",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "VT",
|
||||
"name": "vert_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BA",
|
||||
"name": "base_addr",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "HA",
|
||||
"name": "high_addr",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BP",
|
||||
"name": "base_param",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "HP",
|
||||
"name": "high_param",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MA",
|
||||
"name": "master_addrspace",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MX",
|
||||
"name": "master_instance",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MI",
|
||||
"name": "master_interface",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MS",
|
||||
"name": "master_segment",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MV",
|
||||
"name": "master_vlnv",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SX",
|
||||
"name": "slave_instance",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SI",
|
||||
"name": "slave_interface",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MM",
|
||||
"name": "slave_memmap",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SS",
|
||||
"name": "slave_segment",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SV",
|
||||
"name": "slave_vlnv",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "TM",
|
||||
"name": "memory_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "TU",
|
||||
"name": "usage_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "LT",
|
||||
"name": "lock_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BT",
|
||||
"name": "boot_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "EH",
|
||||
"name": "edge_hid",
|
||||
"type": "int",
|
||||
"for": "edge"
|
||||
}
|
||||
],
|
||||
"vertice_type_order": [
|
||||
{
|
||||
"abrv": "BC",
|
||||
"desc": "Block Container"
|
||||
},
|
||||
{
|
||||
"abrv": "PR",
|
||||
"desc": "Parital Reference"
|
||||
},
|
||||
{
|
||||
"abrv": "VR",
|
||||
"desc": "Variant"
|
||||
},
|
||||
{
|
||||
"abrv": "PM",
|
||||
"desc": "Variant Permutations"
|
||||
},
|
||||
{
|
||||
"abrv": "CX",
|
||||
"desc": "Boundary Connection"
|
||||
},
|
||||
{
|
||||
"abrv": "AC",
|
||||
"desc": "Assignment Coordinate"
|
||||
},
|
||||
{
|
||||
"abrv": "ACE",
|
||||
"desc": "Excluded Assign Coordinate"
|
||||
},
|
||||
{
|
||||
"abrv": "APX",
|
||||
"desc": "Boundary Aperture"
|
||||
},
|
||||
{
|
||||
"abrv": "CIP",
|
||||
"desc": "High level Processing System"
|
||||
}
|
||||
],
|
||||
"vertices": {
|
||||
"V0": {
|
||||
"VM": "system_bd",
|
||||
"VT": "BC"
|
||||
},
|
||||
"V1": {
|
||||
"VH": "2",
|
||||
"VM": "system_bd",
|
||||
"VT": "VR"
|
||||
},
|
||||
"V2": {
|
||||
"VH": "2",
|
||||
"VT": "PM",
|
||||
"TU": "active"
|
||||
},
|
||||
"V3": {
|
||||
"VT": "AC",
|
||||
"BA": "0x0080000000",
|
||||
"HA": "0x008000FFFF",
|
||||
"BP": "C_BASEADDR",
|
||||
"HP": "C_HIGHADDR",
|
||||
"MA": "Data",
|
||||
"MX": "/zynq_ultra_ps_e",
|
||||
"MI": "M_AXI_HPM0_LPD",
|
||||
"MS": "SEG_axi_spi_engine_axi_lite",
|
||||
"MV": "xilinx.com:ip:zynq_ultra_ps_e:3.5",
|
||||
"SX": "/axi_spi_engine/axi_spi_engine",
|
||||
"SI": "s_axi",
|
||||
"SS": "axi_lite",
|
||||
"SV": "analog.com:user:axi_spi_engine:1.0",
|
||||
"TM": "both",
|
||||
"TU": "register"
|
||||
},
|
||||
"V4": {
|
||||
"VT": "AC",
|
||||
"BA": "0x0080040000",
|
||||
"HA": "0x008007FFFF",
|
||||
"BP": "C_BASEADDR",
|
||||
"HP": "C_HIGHADDR",
|
||||
"MA": "Data",
|
||||
"MX": "/zynq_ultra_ps_e",
|
||||
"MI": "M_AXI_HPM0_LPD",
|
||||
"MS": "SEG_usp_rf_data_converter_Reg",
|
||||
"MV": "xilinx.com:ip:zynq_ultra_ps_e:3.5",
|
||||
"SX": "/usp_rf_data_converter",
|
||||
"SI": "s_axi",
|
||||
"SS": "Reg",
|
||||
"SV": "xilinx.com:ip:usp_rf_data_converter:2.6",
|
||||
"TM": "both",
|
||||
"TU": "register"
|
||||
}
|
||||
},
|
||||
"edges": [
|
||||
{
|
||||
"src": "V0",
|
||||
"trg": "V1"
|
||||
},
|
||||
{
|
||||
"src": "V1",
|
||||
"trg": "V2"
|
||||
},
|
||||
{
|
||||
"src": "V3",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
},
|
||||
{
|
||||
"src": "V4",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
}
|
||||
]
|
||||
}
|
||||
}
|
||||
+34
@@ -0,0 +1,34 @@
|
||||
{
|
||||
"ActiveEmotionalView":"Default View",
|
||||
"Default View_ScaleFactor":"1.0",
|
||||
"Default View_TopLeft":"-360,-198",
|
||||
"ExpandedHierarchyInLayout":"",
|
||||
"guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS
|
||||
# -string -flagsOSRD
|
||||
preplace port pl_clk -pg 1 -lvl 0 -x 0 -y 70 -defaultsOSRD
|
||||
preplace port pl_sysref -pg 1 -lvl 0 -x 0 -y 240 -defaultsOSRD
|
||||
preplace port port-id_sys_rstn -pg 1 -lvl 5 -x 1060 -y 80 -defaultsOSRD
|
||||
preplace port port-id_sys_clk -pg 1 -lvl 5 -x 1060 -y 60 -defaultsOSRD
|
||||
preplace portBus mts_sysref -pg 1 -lvl 5 -x 1060 -y 170 -defaultsOSRD
|
||||
preplace inst util_ds_buf_pl_clk -pg 1 -lvl 1 -x 150 -y 70 -defaultsOSRD
|
||||
preplace inst util_bufg_pl_clk -pg 1 -lvl 2 -x 410 -y 70 -defaultsOSRD -resize 220 88
|
||||
preplace inst util_ds_buf_pl_sysref -pg 1 -lvl 2 -x 410 -y 240 -defaultsOSRD -resize 220 88
|
||||
preplace inst clk_wiz_pl_clk -pg 1 -lvl 3 -x 670 -y 70 -defaultsOSRD
|
||||
preplace inst xpm_cdc_gen_pl_sysref -pg 1 -lvl 3 -x 670 -y 220 -defaultsOSRD
|
||||
preplace inst xpm_cdc_gen_mts_sysref -pg 1 -lvl 4 -x 910 -y 160 -defaultsOSRD -resize 200 116
|
||||
preplace inst xlconstant_0 -pg 1 -lvl 2 -x 410 -y 350 -defaultsOSRD
|
||||
preplace netloc util_ds_buf_pl_clk_IBUF_OUT 1 1 1 NJ 70
|
||||
preplace netloc util_bufg_pl_clk_BUFG_O 1 2 1 540 70n
|
||||
preplace netloc xlconstant_0_dout 1 2 2 550 140 NJ
|
||||
preplace netloc util_ds_buf_pl_sysref_IBUF_OUT 1 2 1 NJ 240
|
||||
preplace netloc xpm_cdc_gen_pl_sysref_dest_out 1 3 1 790 180n
|
||||
preplace netloc xpm_cdc_gen_mts_sysref_dest_out 1 4 1 1030J 160n
|
||||
preplace netloc clk_wiz_pl_clk_locked 1 3 2 NJ 80 N
|
||||
preplace netloc clk_wiz_pl_clk_clk_out1 1 3 2 790 60 NJ
|
||||
preplace netloc Conn1 1 0 1 NJ 70
|
||||
preplace netloc Conn2 1 0 2 NJ 240 NJ
|
||||
levelinfo -pg 1 0 150 410 670 910 1060
|
||||
pagesize -pg 1 -db -bbox -sgen -120 0 1230 410
|
||||
"
|
||||
}
|
||||
|
||||
+34
@@ -0,0 +1,34 @@
|
||||
{
|
||||
"ActiveEmotionalView":"Default View",
|
||||
"Default View_ScaleFactor":"1.0",
|
||||
"Default View_TopLeft":"-360,-198",
|
||||
"ExpandedHierarchyInLayout":"",
|
||||
"guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS
|
||||
# -string -flagsOSRD
|
||||
preplace port pl_clk -pg 1 -lvl 0 -x 0 -y 70 -defaultsOSRD
|
||||
preplace port pl_sysref -pg 1 -lvl 0 -x 0 -y 240 -defaultsOSRD
|
||||
preplace port port-id_sys_rstn -pg 1 -lvl 5 -x 1060 -y 80 -defaultsOSRD
|
||||
preplace port port-id_sys_clk -pg 1 -lvl 5 -x 1060 -y 60 -defaultsOSRD
|
||||
preplace portBus mts_sysref -pg 1 -lvl 5 -x 1060 -y 170 -defaultsOSRD
|
||||
preplace inst util_ds_buf_pl_clk -pg 1 -lvl 1 -x 150 -y 70 -defaultsOSRD
|
||||
preplace inst util_bufg_pl_clk -pg 1 -lvl 2 -x 410 -y 70 -defaultsOSRD -resize 220 88
|
||||
preplace inst util_ds_buf_pl_sysref -pg 1 -lvl 2 -x 410 -y 240 -defaultsOSRD -resize 220 88
|
||||
preplace inst clk_wiz_pl_clk -pg 1 -lvl 3 -x 670 -y 70 -defaultsOSRD
|
||||
preplace inst xpm_cdc_gen_pl_sysref -pg 1 -lvl 3 -x 670 -y 220 -defaultsOSRD
|
||||
preplace inst xpm_cdc_gen_mts_sysref -pg 1 -lvl 4 -x 910 -y 160 -defaultsOSRD -resize 200 116
|
||||
preplace inst xlconstant_0 -pg 1 -lvl 2 -x 410 -y 350 -defaultsOSRD
|
||||
preplace netloc util_ds_buf_pl_clk_IBUF_OUT 1 1 1 NJ 70
|
||||
preplace netloc util_bufg_pl_clk_BUFG_O 1 2 1 540 70n
|
||||
preplace netloc xlconstant_0_dout 1 2 2 550 140 NJ
|
||||
preplace netloc util_ds_buf_pl_sysref_IBUF_OUT 1 2 1 NJ 240
|
||||
preplace netloc xpm_cdc_gen_pl_sysref_dest_out 1 3 1 790 180n
|
||||
preplace netloc xpm_cdc_gen_mts_sysref_dest_out 1 4 1 1030J 160n
|
||||
preplace netloc clk_wiz_pl_clk_locked 1 3 2 NJ 80 N
|
||||
preplace netloc clk_wiz_pl_clk_clk_out1 1 3 2 790 60 NJ
|
||||
preplace netloc Conn1 1 0 1 NJ 70
|
||||
preplace netloc Conn2 1 0 2 NJ 240 NJ
|
||||
levelinfo -pg 1 0 150 410 670 910 1060
|
||||
pagesize -pg 1 -db -bbox -sgen -120 0 1230 410
|
||||
"
|
||||
}
|
||||
|
||||
+180
@@ -0,0 +1,180 @@
|
||||
{
|
||||
"ActiveEmotionalView":"Default View",
|
||||
"Default View_ScaleFactor":"0.872851",
|
||||
"Default View_TopLeft":"416,27",
|
||||
"ExpandedHierarchyInLayout":"",
|
||||
"guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS
|
||||
# -string -flagsOSRD
|
||||
preplace port spi -pg 1 -lvl 4 -x 1380 -y 330 -defaultsOSRD
|
||||
preplace port pl_clk -pg 1 -lvl 0 -x 0 -y 1450 -defaultsOSRD
|
||||
preplace port pl_sysref -pg 1 -lvl 0 -x 0 -y 1470 -defaultsOSRD
|
||||
preplace port adc2_clk -pg 1 -lvl 0 -x 0 -y 700 -defaultsOSRD
|
||||
preplace port dac2_clk -pg 1 -lvl 0 -x 0 -y 720 -defaultsOSRD
|
||||
preplace port m00_axis -pg 1 -lvl 4 -x 1380 -y 590 -defaultsOSRD
|
||||
preplace port m01_axis -pg 1 -lvl 4 -x 1380 -y 610 -defaultsOSRD
|
||||
preplace port m02_axis -pg 1 -lvl 4 -x 1380 -y 630 -defaultsOSRD
|
||||
preplace port m03_axis -pg 1 -lvl 4 -x 1380 -y 650 -defaultsOSRD
|
||||
preplace port m10_axis -pg 1 -lvl 4 -x 1380 -y 670 -defaultsOSRD
|
||||
preplace port m11_axis -pg 1 -lvl 4 -x 1380 -y 690 -defaultsOSRD
|
||||
preplace port m12_axis -pg 1 -lvl 4 -x 1380 -y 710 -defaultsOSRD
|
||||
preplace port m13_axis -pg 1 -lvl 4 -x 1380 -y 730 -defaultsOSRD
|
||||
preplace port m20_axis -pg 1 -lvl 4 -x 1380 -y 750 -defaultsOSRD
|
||||
preplace port m21_axis -pg 1 -lvl 4 -x 1380 -y 770 -defaultsOSRD
|
||||
preplace port m22_axis -pg 1 -lvl 4 -x 1380 -y 790 -defaultsOSRD
|
||||
preplace port m23_axis -pg 1 -lvl 4 -x 1380 -y 810 -defaultsOSRD
|
||||
preplace port m30_axis -pg 1 -lvl 4 -x 1380 -y 830 -defaultsOSRD
|
||||
preplace port m31_axis -pg 1 -lvl 4 -x 1380 -y 850 -defaultsOSRD
|
||||
preplace port m32_axis -pg 1 -lvl 4 -x 1380 -y 870 -defaultsOSRD
|
||||
preplace port m33_axis -pg 1 -lvl 4 -x 1380 -y 890 -defaultsOSRD
|
||||
preplace port s00_axis -pg 1 -lvl 0 -x 0 -y 540 -defaultsOSRD
|
||||
preplace port s02_axis -pg 1 -lvl 0 -x 0 -y 560 -defaultsOSRD
|
||||
preplace port s10_axis -pg 1 -lvl 0 -x 0 -y 580 -defaultsOSRD
|
||||
preplace port s12_axis -pg 1 -lvl 0 -x 0 -y 600 -defaultsOSRD
|
||||
preplace port s20_axis -pg 1 -lvl 0 -x 0 -y 620 -defaultsOSRD
|
||||
preplace port s22_axis -pg 1 -lvl 0 -x 0 -y 640 -defaultsOSRD
|
||||
preplace port s30_axis -pg 1 -lvl 0 -x 0 -y 660 -defaultsOSRD
|
||||
preplace port s32_axis -pg 1 -lvl 0 -x 0 -y 680 -defaultsOSRD
|
||||
preplace port sysref_in -pg 1 -lvl 0 -x 0 -y 900 -defaultsOSRD
|
||||
preplace port vin0_01 -pg 1 -lvl 0 -x 0 -y 740 -defaultsOSRD
|
||||
preplace port vin0_23 -pg 1 -lvl 0 -x 0 -y 760 -defaultsOSRD
|
||||
preplace port vin1_01 -pg 1 -lvl 0 -x 0 -y 780 -defaultsOSRD
|
||||
preplace port vin1_23 -pg 1 -lvl 0 -x 0 -y 800 -defaultsOSRD
|
||||
preplace port vin2_01 -pg 1 -lvl 0 -x 0 -y 820 -defaultsOSRD
|
||||
preplace port vin2_23 -pg 1 -lvl 0 -x 0 -y 840 -defaultsOSRD
|
||||
preplace port vin3_01 -pg 1 -lvl 0 -x 0 -y 860 -defaultsOSRD
|
||||
preplace port vin3_23 -pg 1 -lvl 0 -x 0 -y 880 -defaultsOSRD
|
||||
preplace port vout00 -pg 1 -lvl 4 -x 1380 -y 910 -defaultsOSRD
|
||||
preplace port vout02 -pg 1 -lvl 4 -x 1380 -y 930 -defaultsOSRD
|
||||
preplace port vout10 -pg 1 -lvl 4 -x 1380 -y 950 -defaultsOSRD
|
||||
preplace port vout12 -pg 1 -lvl 4 -x 1380 -y 970 -defaultsOSRD
|
||||
preplace port vout20 -pg 1 -lvl 4 -x 1380 -y 990 -defaultsOSRD
|
||||
preplace port vout22 -pg 1 -lvl 4 -x 1380 -y 1010 -defaultsOSRD
|
||||
preplace port vout30 -pg 1 -lvl 4 -x 1380 -y 1030 -defaultsOSRD
|
||||
preplace port vout32 -pg 1 -lvl 4 -x 1380 -y 1050 -defaultsOSRD
|
||||
preplace port port-id_spi_active -pg 1 -lvl 4 -x 1380 -y 350 -defaultsOSRD
|
||||
preplace port port-id_sys_rstn -pg 1 -lvl 4 -x 1380 -y 1460 -defaultsOSRD
|
||||
preplace port port-id_sys_clk -pg 1 -lvl 4 -x 1380 -y 1480 -defaultsOSRD
|
||||
preplace port port-id_ps_clk0 -pg 1 -lvl 4 -x 1380 -y 540 -defaultsOSRD
|
||||
preplace port port-id_clk_adc0 -pg 1 -lvl 4 -x 1380 -y 1070 -defaultsOSRD
|
||||
preplace port port-id_clk_adc1 -pg 1 -lvl 4 -x 1380 -y 1090 -defaultsOSRD
|
||||
preplace port port-id_clk_adc2 -pg 1 -lvl 4 -x 1380 -y 1110 -defaultsOSRD
|
||||
preplace port port-id_clk_adc3 -pg 1 -lvl 4 -x 1380 -y 1130 -defaultsOSRD
|
||||
preplace port port-id_clk_dac0 -pg 1 -lvl 4 -x 1380 -y 1150 -defaultsOSRD
|
||||
preplace port port-id_clk_dac1 -pg 1 -lvl 4 -x 1380 -y 1170 -defaultsOSRD
|
||||
preplace port port-id_clk_dac2 -pg 1 -lvl 4 -x 1380 -y 1190 -defaultsOSRD
|
||||
preplace port port-id_clk_dac3 -pg 1 -lvl 4 -x 1380 -y 1210 -defaultsOSRD
|
||||
preplace port port-id_m0_axis_aclk -pg 1 -lvl 0 -x 0 -y 1020 -defaultsOSRD
|
||||
preplace port port-id_m0_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1000 -defaultsOSRD
|
||||
preplace port port-id_m1_axis_aclk -pg 1 -lvl 0 -x 0 -y 1060 -defaultsOSRD
|
||||
preplace port port-id_m1_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1040 -defaultsOSRD
|
||||
preplace port port-id_m2_axis_aclk -pg 1 -lvl 0 -x 0 -y 1100 -defaultsOSRD
|
||||
preplace port port-id_m2_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1080 -defaultsOSRD
|
||||
preplace port port-id_m3_axis_aclk -pg 1 -lvl 0 -x 0 -y 1140 -defaultsOSRD
|
||||
preplace port port-id_m3_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1120 -defaultsOSRD
|
||||
preplace port port-id_s0_axis_aclk -pg 1 -lvl 0 -x 0 -y 1180 -defaultsOSRD
|
||||
preplace port port-id_s0_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1160 -defaultsOSRD
|
||||
preplace port port-id_s1_axis_aclk -pg 1 -lvl 0 -x 0 -y 1220 -defaultsOSRD
|
||||
preplace port port-id_s1_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1200 -defaultsOSRD
|
||||
preplace port port-id_s2_axis_aclk -pg 1 -lvl 0 -x 0 -y 1260 -defaultsOSRD
|
||||
preplace port port-id_s2_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1240 -defaultsOSRD
|
||||
preplace port port-id_s3_axis_aclk -pg 1 -lvl 0 -x 0 -y 1300 -defaultsOSRD
|
||||
preplace port port-id_s3_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1280 -defaultsOSRD
|
||||
preplace inst usp_rf_data_converter -pg 1 -lvl 1 -x 360 -y 910 -defaultsOSRD
|
||||
preplace inst axi_spi_engine -pg 1 -lvl 2 -x 880 -y 350 -defaultsOSRD
|
||||
preplace inst ps8_0_axi_periph -pg 1 -lvl 1 -x 360 -y 340 -defaultsOSRD
|
||||
preplace inst rst_ps8_0_96M -pg 1 -lvl 2 -x 880 -y 170 -defaultsOSRD
|
||||
preplace inst mts_clk_gen -pg 1 -lvl 1 -x 360 -y 1460 -defaultsOSRD
|
||||
preplace inst xlconcat_0 -pg 1 -lvl 2 -x 880 -y 470 -defaultsOSRD -orient R180
|
||||
preplace inst zynq_ultra_ps_e -pg 1 -lvl 1 -x 360 -y 110 -defaultsOSRD
|
||||
preplace inst system_ila_0 -pg 1 -lvl 3 -x 1200 -y 280 -defaultsOSRD
|
||||
preplace netloc adi_spi_engine_active_0 1 2 2 1060 360 1340
|
||||
preplace netloc adi_spi_engine_irq 1 2 1 1060 370n
|
||||
preplace netloc m0_axis_aclk_0_1 1 0 1 NJ 1020
|
||||
preplace netloc m0_axis_aresetn_0_1 1 0 1 NJ 1000
|
||||
preplace netloc m1_axis_aclk_0_1 1 0 1 NJ 1060
|
||||
preplace netloc m1_axis_aresetn_0_1 1 0 1 NJ 1040
|
||||
preplace netloc m2_axis_aclk_0_1 1 0 1 NJ 1100
|
||||
preplace netloc m2_axis_aresetn_0_1 1 0 1 NJ 1080
|
||||
preplace netloc m3_axis_aclk_0_1 1 0 1 NJ 1140
|
||||
preplace netloc m3_axis_aresetn_0_1 1 0 1 NJ 1120
|
||||
preplace netloc mts_sysref_gen_clk_out1_0 1 1 3 N 1460 NJ 1460 N
|
||||
preplace netloc mts_sysref_gen_locked_0 1 1 3 N 1480 NJ 1480 N
|
||||
preplace netloc mts_sysref_gen_mts_sysref 1 0 2 20 1380 670
|
||||
preplace netloc rst_ps8_0_96M_peripheral_aresetn 1 0 3 40 1360 700J 270 1060
|
||||
preplace netloc s0_axis_aclk_0_1 1 0 1 NJ 1180
|
||||
preplace netloc s0_axis_aresetn_0_1 1 0 1 NJ 1160
|
||||
preplace netloc s1_axis_aclk_0_1 1 0 1 NJ 1220
|
||||
preplace netloc s1_axis_aresetn_0_1 1 0 1 NJ 1200
|
||||
preplace netloc s2_axis_aclk_0_1 1 0 1 NJ 1260
|
||||
preplace netloc s2_axis_aresetn_0_1 1 0 1 NJ 1240
|
||||
preplace netloc s3_axis_aclk_0_1 1 0 1 NJ 1300
|
||||
preplace netloc s3_axis_aresetn_0_1 1 0 1 N 1280
|
||||
preplace netloc usp_rf_data_converter_clk_adc0 1 1 3 N 1070 NJ 1070 N
|
||||
preplace netloc usp_rf_data_converter_clk_adc1 1 1 3 N 1090 NJ 1090 N
|
||||
preplace netloc usp_rf_data_converter_clk_adc2 1 1 3 N 1110 NJ 1110 N
|
||||
preplace netloc usp_rf_data_converter_clk_adc3 1 1 3 N 1130 NJ 1130 N
|
||||
preplace netloc usp_rf_data_converter_clk_dac0 1 1 3 N 1150 NJ 1150 N
|
||||
preplace netloc usp_rf_data_converter_clk_dac1 1 1 3 N 1170 NJ 1170 N
|
||||
preplace netloc usp_rf_data_converter_clk_dac2 1 1 3 N 1190 NJ 1190 N
|
||||
preplace netloc usp_rf_data_converter_clk_dac3 1 1 3 N 1210 NJ 1210 N
|
||||
preplace netloc usp_rf_data_converter_irq 1 1 2 N 1230 1060
|
||||
preplace netloc xlconcat_0_dout 1 0 2 20 10 680J
|
||||
preplace netloc zynq_ultra_ps_e_pl_clk0 1 0 4 30 1370 690J 70 1070J 210 1330
|
||||
preplace netloc zynq_ultra_ps_e_pl_resetn0 1 1 1 670 110n
|
||||
preplace netloc adi_spi_engine_spi_0 1 2 2 1080 350 1320
|
||||
preplace netloc pl_clk_0_1 1 0 1 N 1450
|
||||
preplace netloc pl_sysref_0_1 1 0 1 N 1470
|
||||
preplace netloc ps8_0_axi_periph_M00_AXI 1 1 1 NJ 330
|
||||
preplace netloc ps8_0_axi_periph_M01_AXI 1 0 2 50 200 670J
|
||||
preplace netloc s00_axis_0_1 1 0 1 NJ 540
|
||||
preplace netloc s02_axis_0_1 1 0 1 NJ 560
|
||||
preplace netloc s10_axis_0_1 1 0 1 NJ 580
|
||||
preplace netloc s12_axis_0_1 1 0 1 NJ 600
|
||||
preplace netloc s20_axis_0_1 1 0 1 NJ 620
|
||||
preplace netloc s22_axis_0_1 1 0 1 NJ 640
|
||||
preplace netloc s30_axis_0_1 1 0 1 NJ 660
|
||||
preplace netloc s32_axis_0_1 1 0 1 NJ 680
|
||||
preplace netloc sysref_in_0_1 1 0 1 NJ 900
|
||||
preplace netloc usp_rf_data_converter_m00_axis 1 1 3 N 590 NJ 590 N
|
||||
preplace netloc usp_rf_data_converter_m01_axis 1 1 3 N 610 NJ 610 N
|
||||
preplace netloc usp_rf_data_converter_m02_axis 1 1 3 N 630 NJ 630 N
|
||||
preplace netloc usp_rf_data_converter_m03_axis 1 1 3 N 650 NJ 650 N
|
||||
preplace netloc usp_rf_data_converter_m10_axis 1 1 3 N 670 NJ 670 N
|
||||
preplace netloc usp_rf_data_converter_m11_axis 1 1 3 N 690 NJ 690 N
|
||||
preplace netloc usp_rf_data_converter_m12_axis 1 1 3 N 710 NJ 710 N
|
||||
preplace netloc usp_rf_data_converter_m13_axis 1 1 3 N 730 NJ 730 N
|
||||
preplace netloc usp_rf_data_converter_m20_axis 1 1 3 N 750 NJ 750 N
|
||||
preplace netloc usp_rf_data_converter_m21_axis 1 1 3 N 770 NJ 770 N
|
||||
preplace netloc usp_rf_data_converter_m22_axis 1 1 3 N 790 NJ 790 N
|
||||
preplace netloc usp_rf_data_converter_m23_axis 1 1 3 N 810 NJ 810 N
|
||||
preplace netloc usp_rf_data_converter_m30_axis 1 1 3 N 830 NJ 830 N
|
||||
preplace netloc usp_rf_data_converter_m31_axis 1 1 3 N 850 NJ 850 N
|
||||
preplace netloc usp_rf_data_converter_m32_axis 1 1 3 N 870 NJ 870 N
|
||||
preplace netloc usp_rf_data_converter_m33_axis 1 1 3 N 890 NJ 890 N
|
||||
preplace netloc usp_rf_data_converter_vout00 1 1 3 N 910 NJ 910 N
|
||||
preplace netloc usp_rf_data_converter_vout02 1 1 3 N 930 NJ 930 N
|
||||
preplace netloc usp_rf_data_converter_vout10 1 1 3 N 950 NJ 950 N
|
||||
preplace netloc usp_rf_data_converter_vout12 1 1 3 N 970 NJ 970 N
|
||||
preplace netloc usp_rf_data_converter_vout20 1 1 3 N 990 NJ 990 N
|
||||
preplace netloc usp_rf_data_converter_vout22 1 1 3 N 1010 NJ 1010 N
|
||||
preplace netloc usp_rf_data_converter_vout30 1 1 3 N 1030 NJ 1030 N
|
||||
preplace netloc usp_rf_data_converter_vout32 1 1 3 N 1050 NJ 1050 N
|
||||
preplace netloc vin0_01_0_1 1 0 1 NJ 740
|
||||
preplace netloc vin0_23_0_1 1 0 1 NJ 760
|
||||
preplace netloc vin1_01_0_1 1 0 1 NJ 780
|
||||
preplace netloc vin1_23_0_1 1 0 1 NJ 800
|
||||
preplace netloc vin2_01_0_1 1 0 1 NJ 820
|
||||
preplace netloc vin2_23_0_1 1 0 1 NJ 840
|
||||
preplace netloc vin3_01_0_1 1 0 1 NJ 860
|
||||
preplace netloc vin3_23_0_1 1 0 1 NJ 880
|
||||
preplace netloc zynq_ultra_ps_e_M_AXI_HPM0_LPD 1 0 2 40 20 670
|
||||
preplace netloc adc2_clk_1 1 0 1 N 700
|
||||
preplace netloc dac2_clk_1 1 0 1 N 720
|
||||
levelinfo -pg 1 0 360 880 1200 1380
|
||||
pagesize -pg 1 -db -bbox -sgen -170 0 1860 1610
|
||||
"
|
||||
}
|
||||
{
|
||||
"da_axi4_cnt":"4",
|
||||
"da_board_cnt":"1"
|
||||
}
|
||||
+28
@@ -0,0 +1,28 @@
|
||||
{
|
||||
"ActiveEmotionalView":"Default View",
|
||||
"Default View_ScaleFactor":"1.0",
|
||||
"Default View_TopLeft":"-578,-657",
|
||||
"ExpandedHierarchyInLayout":"",
|
||||
"guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS
|
||||
# -string -flagsOSRD
|
||||
preplace port s_axi -pg 1 -lvl 0 -x 0 -y -270 -defaultsOSRD
|
||||
preplace port spi -pg 1 -lvl 3 -x 730 -y -250 -defaultsOSRD
|
||||
preplace port port-id_s_axi_aclk -pg 1 -lvl 0 -x 0 -y -250 -defaultsOSRD
|
||||
preplace port port-id_s_axi_aresetn -pg 1 -lvl 0 -x 0 -y -230 -defaultsOSRD
|
||||
preplace port port-id_active -pg 1 -lvl 3 -x 730 -y -230 -defaultsOSRD
|
||||
preplace port port-id_irq -pg 1 -lvl 3 -x 730 -y -320 -defaultsOSRD
|
||||
preplace inst axi_spi_engine -pg 1 -lvl 1 -x 340 -y -240 -defaultsOSRD
|
||||
preplace inst spi_engine_execution -pg 1 -lvl 2 -x 600 -y -240 -defaultsOSRD
|
||||
preplace netloc axi_spi_engine_irq 1 1 2 480J -320 NJ
|
||||
preplace netloc axi_spi_engine_spi_resetn 1 1 1 N -220
|
||||
preplace netloc s_axi_aclk_0_1 1 0 2 200 -150 490J
|
||||
preplace netloc s_axi_aresetn_1 1 0 1 NJ -230
|
||||
preplace netloc spi_engine_execution_active 1 2 1 NJ -230
|
||||
preplace netloc Conn1 1 0 1 NJ -270
|
||||
preplace netloc Conn2 1 2 1 NJ -250
|
||||
preplace netloc axi_spi_engine_spi_engine_ctrl 1 1 1 N -260
|
||||
levelinfo -pg 1 0 340 600 730
|
||||
pagesize -pg 1 -db -bbox -sgen -150 -630 830 180
|
||||
"
|
||||
}
|
||||
0
|
||||
+26
@@ -0,0 +1,26 @@
|
||||
{
|
||||
"ActiveEmotionalView":"Default View",
|
||||
"Default View_ScaleFactor":"1.0",
|
||||
"Default View_TopLeft":"-578,-657",
|
||||
"ExpandedHierarchyInLayout":"",
|
||||
"guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS
|
||||
# -string -flagsOSRD
|
||||
preplace port s_axi -pg 1 -lvl 0 -x 0 -y -270 -defaultsOSRD
|
||||
preplace port spi -pg 1 -lvl 3 -x 710 -y -250 -defaultsOSRD
|
||||
preplace port port-id_s_axi_aclk -pg 1 -lvl 0 -x 0 -y -250 -defaultsOSRD
|
||||
preplace port port-id_s_axi_aresetn -pg 1 -lvl 0 -x 0 -y -230 -defaultsOSRD
|
||||
preplace port port-id_active -pg 1 -lvl 3 -x 710 -y -230 -defaultsOSRD
|
||||
preplace inst axi_spi_engine -pg 1 -lvl 1 -x 340 -y -240 -defaultsOSRD
|
||||
preplace inst spi_engine_execution -pg 1 -lvl 2 -x 590 -y -240 -defaultsOSRD
|
||||
preplace netloc axi_spi_engine_spi_resetn 1 1 1 N -220
|
||||
preplace netloc s_axi_aclk_0_1 1 0 2 200 -150 480J
|
||||
preplace netloc spi_engine_execution_active 1 2 1 NJ -230
|
||||
preplace netloc s_axi_aresetn_1 1 0 1 NJ -230
|
||||
preplace netloc axi_spi_engine_spi_engine_ctrl 1 1 1 N -260
|
||||
preplace netloc Conn1 1 0 1 NJ -270
|
||||
preplace netloc Conn2 1 2 1 NJ -250
|
||||
levelinfo -pg 1 0 340 590 710
|
||||
pagesize -pg 1 -db -bbox -sgen -150 -630 810 180
|
||||
"
|
||||
}
|
||||
|
||||
@@ -0,0 +1,213 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "cmpy_18x8",
|
||||
"component_reference": "xilinx.com:ip:cmpy:6.0",
|
||||
"ip_revision": "24",
|
||||
"gen_directory": "../../../../dj_47dr_lmx.gen/sources_1/ip/cmpy_18x8",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "cmpy_18x8", "resolve_type": "user", "usage": "all" } ],
|
||||
"APortWidth": [ { "value": "18", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HasATLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"HasATUSER": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ATUSERWidth": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"BPortWidth": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HasBTLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"HasBTUSER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"BTUSERWidth": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MultType": [ { "value": "Use_LUTs", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"OptimizeGoal": [ { "value": "Resources", "resolve_type": "user", "usage": "all" } ],
|
||||
"FlowControl": [ { "value": "NonBlocking", "resolve_type": "user", "usage": "all" } ],
|
||||
"RoundMode": [ { "value": "Truncate", "resolve_type": "user", "usage": "all" } ],
|
||||
"OutputWidth": [ { "value": "27", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HasCTRLTLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"HasCTRLTUSER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CTRLTUSERWidth": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"OutTLASTBehv": [ { "value": "Null", "resolve_type": "user", "usage": "all" } ],
|
||||
"LatencyConfig": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
|
||||
"MinimumLatency": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ARESETN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_VERBOSITY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_XDEVICEFAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_XDEVICE": [ { "value": "xczu47dr", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_A_WIDTH": [ { "value": "18", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_B_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OUT_WIDTH": [ { "value": "27", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_LATENCY": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MULT_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OPTIMIZE_GOAL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"HAS_NEGATE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"SINGLE_OUTPUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"ROUND": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"USE_DSP_CASCADES": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_THROTTLE_SCHEME": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_ACLKEN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_ARESETN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_S_AXIS_A_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_S_AXIS_A_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_S_AXIS_B_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_S_AXIS_B_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_S_AXIS_CTRL_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_S_AXIS_CTRL_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_TLAST_RESOLUTION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXIS_A_TDATA_WIDTH": [ { "value": "48", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXIS_A_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXIS_B_TDATA_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXIS_B_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXIS_CTRL_TDATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXIS_CTRL_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXIS_DOUT_TDATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXIS_DOUT_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu47dr" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffve1156" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "24" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../dj_47dr_lmx.gen/sources_1/ip/cmpy_18x8" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_a_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_a_tdata": [ { "direction": "in", "size_left": "47", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axis_b_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_b_tdata": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
|
||||
"m_axis_dout_tvalid": [ { "direction": "out", "driver_value": "0x0" } ],
|
||||
"m_axis_dout_tdata": [ { "direction": "out", "size_left": "63", "size_right": "0", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"M_AXIS_DOUT": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "8", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_dout_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_dout_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"aclk_intf": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS_CTRL:S_AXIS_B:S_AXIS_A:M_AXIS_DOUT", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_CLKEN": [ { "value": "aclken", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "10000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
},
|
||||
"aresetn_intf": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"aclken_intf": {
|
||||
"vlnv": "xilinx.com:signal:clockenable:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIS_A": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "6", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_a_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_a_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIS_B": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "2", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
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@@ -0,0 +1,358 @@
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|
||||
"s_axis_config_tdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"m_axis_data_tvalid": [ { "direction": "out", "driver_value": "0x0" } ],
|
||||
"m_axis_data_tdata": [ { "direction": "out", "size_left": "15", "size_right": "0", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"event_pinc_invalid_intf": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"event_poff_invalid_intf": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"event_phase_in_invalid_intf": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"event_s_phase_tlast_missing_intf": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"event_s_phase_tlast_unexpected_intf": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"event_s_phase_chanid_incorrect_intf": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"event_s_config_tlast_missing_intf": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"event_s_config_tlast_unexpected_intf": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"aclk_intf": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXIS_PHASE:S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_PHASE", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_CLKEN": [ { "value": "aclken", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
},
|
||||
"aresetn_intf": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"aclken_intf": {
|
||||
"vlnv": "xilinx.com:signal:clockenable:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS_DATA": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "2", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_data_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_data_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIS_CONFIG": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_config_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_config_tvalid" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,254 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "hop_rom",
|
||||
"component_reference": "xilinx.com:ip:blk_mem_gen:8.4",
|
||||
"ip_revision": "8",
|
||||
"gen_directory": "../../../../dj_47dr_lmx.gen/sources_1/ip/hop_rom",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "hop_rom", "resolve_type": "user", "usage": "all" } ],
|
||||
"Interface_Type": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ],
|
||||
"AXI_Type": [ { "value": "AXI4_Full", "resolve_type": "user", "usage": "all" } ],
|
||||
"AXI_Slave_Type": [ { "value": "Memory_Slave", "resolve_type": "user", "usage": "all" } ],
|
||||
"Use_AXI_ID": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"AXI_ID_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Memory_Type": [ { "value": "Single_Port_ROM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_32bit_Address": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ecctype": [ { "value": "No_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"EN_SLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"EN_DEEPSLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"EN_SHUTDOWN_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"EN_ECC_PIPE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"RD_ADDR_CHNG_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"RD_ADDR_CHNG_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Use_Error_Injection_Pins": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Error_Injection_Type": [ { "value": "Single_Bit_Error_Injection", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Use_Byte_Write_Enable": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Byte_Size": [ { "value": "9", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Algorithm": [ { "value": "Minimum_Area", "resolve_type": "user", "usage": "all" } ],
|
||||
"Primitive": [ { "value": "8kx2", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Assume_Synchronous_Clk": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Write_Width_A": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Write_Depth_A": [ { "value": "256", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Read_Width_A": [ { "value": "32", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Operating_Mode_A": [ { "value": "WRITE_FIRST", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_A": [ { "value": "Always_Enabled", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Write_Width_B": [ { "value": "32", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Read_Width_B": [ { "value": "32", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Operating_Mode_B": [ { "value": "WRITE_FIRST", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_B": [ { "value": "Always_Enabled", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Register_PortA_Output_of_Memory_Primitives": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Register_PortA_Output_of_Memory_Core": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Use_REGCEA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Register_PortB_Output_of_Memory_Primitives": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Register_PortB_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Use_REGCEB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"register_porta_input_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"register_portb_output_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Pipeline_Stages": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Load_Init_File": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Coe_File": [ { "value": "../sweep_freq.coe", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Fill_Remaining_Memory_Locations": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Remaining_Memory_Locations": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Use_RSTA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Reset_Memory_Latch_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Reset_Priority_A": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Output_Reset_Value_A": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Use_RSTB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Reset_Memory_Latch_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Reset_Priority_B": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Output_Reset_Value_B": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Reset_Type": [ { "value": "SYNC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
"MEM_FILE": [ { "value": "no_mem_loaded", "resolve_type": "user", "usage": "all" } ],
|
||||
"CTRL_ECC_ALGO": [ { "value": "NONE", "resolve_type": "user", "usage": "all" } ],
|
||||
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|
||||
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|
||||
"READ_LATENCY_B": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_XDEVICEFAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_ELABORATION_DIR": [ { "value": "./", "resolve_type": "generated", "usage": "all" } ],
|
||||
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|
||||
"C_AXI_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_SLAVE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_BRAM_BLOCK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_32BIT_ADDRESS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CTRL_ECC_ALGO": [ { "value": "NONE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_HAS_AXI_ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_ID_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MEM_TYPE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_BYTE_SIZE": [ { "value": "9", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ALGORITHM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRIM_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_LOAD_INIT_FILE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INIT_FILE_NAME": [ { "value": "hop_rom.mif", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_INIT_FILE": [ { "value": "hop_rom.mem", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_HAS_RSTA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RST_PRIORITY_A": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_RSTRAM_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INITA_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_HAS_ENA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_REGCEA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_BYTE_WEA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WEA_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WRITE_MODE_A": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_WRITE_WIDTH_A": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_READ_WIDTH_A": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WRITE_DEPTH_A": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_READ_DEPTH_A": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ADDRA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_RSTB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RST_PRIORITY_B": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_RSTRAM_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INITB_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_HAS_ENB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_REGCEB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_BYTE_WEB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WEB_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WRITE_MODE_B": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_WRITE_WIDTH_B": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_READ_WIDTH_B": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WRITE_DEPTH_B": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_READ_DEPTH_B": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ADDRB_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_MEM_OUTPUT_REGS_A": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_MEM_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_MUX_OUTPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_MUX_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MUX_PIPELINE_STAGES": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_SOFTECC_INPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_SOFTECC_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_SOFTECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_ECC_PIPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_READ_LATENCY_A": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_READ_LATENCY_B": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_INJECTERR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SIM_COLLISION_CHECK": [ { "value": "ALL", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_COMMON_CLK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DISABLE_WARN_BHV_COLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_SLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_URAM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_RDADDRA_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_RDADDRB_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_DEEPSLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_SHUTDOWN_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_SAFETY_CKT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DISABLE_WARN_BHV_RANGE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_COUNT_36K_BRAM": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_COUNT_18K_BRAM": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_EST_POWER_SUMMARY": [ { "value": "Estimated Power for IP : 3.163063 mW", "resolve_type": "generated", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu47dr" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffve1156" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "8" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../dj_47dr_lmx.gen/sources_1/ip/hop_rom" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"clka": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"addra": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
"douta": [ { "direction": "out", "size_left": "31", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"CLK.ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_aresetn", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"RST.ARESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"BRAM_PORTA": {
|
||||
"vlnv": "xilinx.com:interface:bram:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"MEM_ADDRESS_MODE": [ { "value": "BYTE_ADDRESS", "resolve_type": "user", "usage": "all" } ],
|
||||
"MEM_SIZE": [ { "value": "8192", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_ECC": [ { "value": "NONE", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MASTER_TYPE": [ { "value": "OTHER", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ADDR": [ { "physical_name": "addra" } ],
|
||||
"CLK": [ { "physical_name": "clka" } ],
|
||||
"DOUT": [ { "physical_name": "douta" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S_1": {
|
||||
"address_blocks": {
|
||||
"Mem0": {
|
||||
"base_address": "0",
|
||||
"range": "4096",
|
||||
"usage": "memory",
|
||||
"access": "read-write",
|
||||
"parameters": {
|
||||
"OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
|
||||
"OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,771 @@
|
||||
RADIX = 10;
|
||||
COEFDATA =
|
||||
-47,
|
||||
-30,
|
||||
-13,
|
||||
4,
|
||||
21,
|
||||
38,
|
||||
56,
|
||||
73,
|
||||
89,
|
||||
106,
|
||||
122,
|
||||
138,
|
||||
153,
|
||||
168,
|
||||
182,
|
||||
196,
|
||||
209,
|
||||
221,
|
||||
232,
|
||||
243,
|
||||
252,
|
||||
261,
|
||||
268,
|
||||
275,
|
||||
281,
|
||||
285,
|
||||
289,
|
||||
291,
|
||||
292,
|
||||
292,
|
||||
291,
|
||||
288,
|
||||
285,
|
||||
280,
|
||||
274,
|
||||
267,
|
||||
259,
|
||||
249,
|
||||
239,
|
||||
228,
|
||||
215,
|
||||
202,
|
||||
187,
|
||||
172,
|
||||
156,
|
||||
139,
|
||||
122,
|
||||
104,
|
||||
85,
|
||||
66,
|
||||
46,
|
||||
26,
|
||||
5,
|
||||
-15,
|
||||
-36,
|
||||
-56,
|
||||
-77,
|
||||
-98,
|
||||
-118,
|
||||
-138,
|
||||
-158,
|
||||
-177,
|
||||
-195,
|
||||
-213,
|
||||
-231,
|
||||
-247,
|
||||
-263,
|
||||
-277,
|
||||
-291,
|
||||
-303,
|
||||
-314,
|
||||
-325,
|
||||
-333,
|
||||
-341,
|
||||
-347,
|
||||
-351,
|
||||
-354,
|
||||
-356,
|
||||
-356,
|
||||
-354,
|
||||
-351,
|
||||
-346,
|
||||
-340,
|
||||
-332,
|
||||
-322,
|
||||
-311,
|
||||
-298,
|
||||
-284,
|
||||
-268,
|
||||
-250,
|
||||
-231,
|
||||
-211,
|
||||
-189,
|
||||
-166,
|
||||
-142,
|
||||
-117,
|
||||
-90,
|
||||
-63,
|
||||
-35,
|
||||
-6,
|
||||
24,
|
||||
54,
|
||||
85,
|
||||
116,
|
||||
147,
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{
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"parameters": {
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"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"event_s_data_tlast_unexpected_intf": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"event_s_data_chanid_incorrect_intf": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"event_s_config_tlast_missing_intf": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"event_s_config_tlast_unexpected_intf": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"event_s_reload_tlast_missing_intf": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"event_s_reload_tlast_unexpected_intf": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"aclk_intf": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_DATA:S_AXIS_RELOAD", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_CLKEN": [ { "value": "aclken", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
},
|
||||
"aresetn_intf": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"aclken_intf": {
|
||||
"vlnv": "xilinx.com:signal:clockenable:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIS_DATA": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_data_tdata" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_data_tready" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_data_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS_DATA": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "3", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
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|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
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|
||||
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|
||||
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|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_data_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_data_tvalid" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,258 @@
|
||||
MEMORY_INITIALIZATION_RADIX = 10;
|
||||
MEMORY_INITIALIZATION_VECTOR =
|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
1709565413,
|
||||
1726408422,
|
||||
1743251431,
|
||||
1760094440,
|
||||
1776937449,
|
||||
1793780458,
|
||||
1810623467,
|
||||
1827466476,
|
||||
1844309485,
|
||||
1861152494,
|
||||
1877995503,
|
||||
1894838512,
|
||||
1911681521,
|
||||
1928524530,
|
||||
1945367539,
|
||||
1962210548,
|
||||
1979053557,
|
||||
1995896566,
|
||||
2012739575,
|
||||
2029582584,
|
||||
2046425593,
|
||||
2063268602,
|
||||
2080111611,
|
||||
2096954620,
|
||||
2113797629,
|
||||
2130640638,
|
||||
2147483647;
|
||||
+1632
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,710 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 03/15/2022 08:34:01 PM
|
||||
// Design Name:
|
||||
// Module Name: system_top
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module system_top
|
||||
(
|
||||
// *************************************************************************
|
||||
// *************************** Clocks and SYSREF ***************************
|
||||
// *************************************************************************
|
||||
// adc clock
|
||||
input adc1_clk_in_p ,
|
||||
input adc1_clk_in_n ,
|
||||
input adc2_clk_in_p ,
|
||||
input adc2_clk_in_n ,
|
||||
// dac clock
|
||||
input dac0_clk_in_p ,
|
||||
input dac0_clk_in_n ,
|
||||
input dac2_clk_in_p ,
|
||||
input dac2_clk_in_n ,
|
||||
// sysref for rf
|
||||
input rf_sysref_p ,
|
||||
input rf_sysref_n ,
|
||||
// sysref for pl
|
||||
input pl_sysref_p ,
|
||||
input pl_sysref_n ,
|
||||
// fpga clock
|
||||
input pl_refclk_p ,
|
||||
input pl_refclk_n ,
|
||||
// *************************************************************************
|
||||
// ******************************** RF-DAC *********************************
|
||||
// *************************************************************************
|
||||
input adc0_01_in_p ,
|
||||
input adc0_01_in_n ,
|
||||
input adc0_23_in_p ,
|
||||
input adc0_23_in_n ,
|
||||
input adc1_01_in_p ,
|
||||
input adc1_01_in_n ,
|
||||
input adc1_23_in_p ,
|
||||
input adc1_23_in_n ,
|
||||
input adc2_01_in_p ,
|
||||
input adc2_01_in_n ,
|
||||
input adc2_23_in_p ,
|
||||
input adc2_23_in_n ,
|
||||
input adc3_01_in_p ,
|
||||
input adc3_01_in_n ,
|
||||
input adc3_23_in_p ,
|
||||
input adc3_23_in_n ,
|
||||
// *************************************************************************
|
||||
// ******************************** RF-DAC *********************************
|
||||
// *************************************************************************
|
||||
output dac00_out_p ,
|
||||
output dac00_out_n ,
|
||||
output dac02_out_p ,
|
||||
output dac02_out_n ,
|
||||
output dac10_out_p ,
|
||||
output dac10_out_n ,
|
||||
output dac12_out_p ,
|
||||
output dac12_out_n ,
|
||||
output dac20_out_p ,
|
||||
output dac20_out_n ,
|
||||
output dac22_out_p ,
|
||||
output dac22_out_n ,
|
||||
output dac30_out_p ,
|
||||
output dac30_out_n ,
|
||||
output dac32_out_p ,
|
||||
output dac32_out_n ,
|
||||
// *************************************************************************
|
||||
// ***************************** SPI Interface *****************************
|
||||
// *************************************************************************
|
||||
// lmk04828
|
||||
output lmk_spi_sck ,
|
||||
output lmk_spi_cs ,
|
||||
inout lmk_spi_mosi ,
|
||||
input lmk_spi_miso ,
|
||||
// lmx2594-adc
|
||||
output lmx_adc_spi_sck ,
|
||||
output lmx_adc_spi_cs ,
|
||||
inout lmx_adc_spi_mosi ,
|
||||
input lmx_adc_spi_miso ,
|
||||
// lmx2594-dac
|
||||
output lmx_dac_spi_sck ,
|
||||
output lmx_dac_spi_cs ,
|
||||
inout lmx_dac_spi_mosi ,
|
||||
input lmx_dac_spi_miso
|
||||
);
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//////////////////////////// Block Design Interface ////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
wire ps_clk0;
|
||||
wire sys_clk;
|
||||
wire sys_rstn;
|
||||
|
||||
// spi interface
|
||||
wire spi_sclk ;
|
||||
wire [2:0] spi_cs ;
|
||||
wire [2:0] spi_sdi ;
|
||||
wire spi_sdo ;
|
||||
wire spi_sdo_t ;
|
||||
wire spi_three_wire;
|
||||
wire spi_active ;
|
||||
|
||||
assign lmk_spi_sck = spi_sclk;
|
||||
assign lmk_spi_cs = spi_cs[0];
|
||||
assign spi_sdi[0] = spi_three_wire ? lmk_spi_mosi : lmk_spi_miso;
|
||||
assign lmk_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo;
|
||||
|
||||
assign lmx_adc_spi_sck = spi_sclk;
|
||||
assign lmx_adc_spi_cs = spi_cs[1];
|
||||
assign spi_sdi[1] = spi_three_wire ? lmx_adc_spi_mosi : lmx_adc_spi_miso;
|
||||
assign lmx_adc_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo;
|
||||
|
||||
assign lmx_dac_spi_sck = spi_sclk;
|
||||
assign lmx_dac_spi_cs = spi_cs[2];
|
||||
assign spi_sdi[2] = spi_three_wire ? lmx_dac_spi_mosi : lmx_dac_spi_miso;
|
||||
assign lmx_dac_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo;
|
||||
|
||||
// -----------------------------------------------------------------------------
|
||||
// ADC Tile & Channel Mapping (Dual RF-ADC)
|
||||
// -----------------------------------------------------------------------------
|
||||
// m00_axis adc00 adc tile 224 (adc0), channel 0
|
||||
// m01_axis adc01 adc tile 224 (adc0), channel 1
|
||||
// m02_axis adc02 adc tile 224 (adc0), channel 2
|
||||
// m03_axis adc03 adc tile 224 (adc0), channel 3
|
||||
// -----------------------------------------------------------------------------
|
||||
// m10_axis adc10 adc tile 225 (adc1), channel 0
|
||||
// m11_axis adc11 adc tile 225 (adc1), channel 1
|
||||
// m12_axis adc12 adc tile 225 (adc1), channel 2
|
||||
// m13_axis adc13 adc tile 225 (adc1), channel 3
|
||||
// -----------------------------------------------------------------------------
|
||||
// m20_axis adc20 adc tile 226 (adc2), channel 0
|
||||
// m21_axis adc21 adc tile 226 (adc2), channel 1
|
||||
// m22_axis adc22 adc tile 226 (adc2), channel 2
|
||||
// m23_axis adc23 adc tile 226 (adc2), channel 3
|
||||
// -----------------------------------------------------------------------------
|
||||
// m30_axis adc30 adc tile 227 (adc3), channel 0
|
||||
// m31_axis adc31 adc tile 227 (adc3), channel 1
|
||||
// m32_axis adc32 adc tile 227 (adc3), channel 2
|
||||
// m33_axis adc33 adc tile 227 (adc3), channel 3
|
||||
// -----------------------------------------------------------------------------
|
||||
// Note:
|
||||
// 1) If digital output data is set to real, only channel 0/2 is enabled; if
|
||||
// digital output data is set to i/q, both channel 0/2 and 1/3 are enabled,
|
||||
// since i/q data are transferred in different channels.
|
||||
// 2) When modify the following wire definition, **ONLY** change the data width.
|
||||
// The extra definition will be optimized automatically.
|
||||
// -----------------------------------------------------------------------------
|
||||
wire [15:0] adc00_data, adc01_data;
|
||||
wire adc00_data_ready, adc01_data_ready;
|
||||
wire adc00_data_valid, adc01_data_valid;
|
||||
|
||||
wire [15:0] adc02_data, adc03_data;
|
||||
wire adc02_data_ready, adc03_data_ready;
|
||||
wire adc02_data_valid, adc03_data_valid;
|
||||
|
||||
wire [15:0] adc10_data, adc11_data;
|
||||
wire adc10_data_ready, adc11_data_ready;
|
||||
wire adc10_data_valid, adc11_data_valid;
|
||||
|
||||
wire [15:0] adc12_data, adc13_data;
|
||||
wire adc12_data_ready, adc13_data_ready;
|
||||
wire adc12_data_valid, adc13_data_valid;
|
||||
|
||||
wire [15:0] adc20_data, adc21_data;
|
||||
wire adc20_data_ready, adc21_data_ready;
|
||||
wire adc20_data_valid, adc21_data_valid;
|
||||
|
||||
wire [15:0] adc22_data, adc23_data;
|
||||
wire adc22_data_ready, adc23_data_ready;
|
||||
wire adc22_data_valid, adc23_data_valid;
|
||||
|
||||
wire [15:0] adc30_data, adc31_data;
|
||||
wire adc30_data_ready, adc31_data_ready;
|
||||
wire adc30_data_valid, adc31_data_valid;
|
||||
|
||||
wire [15:0] adc32_data, adc33_data;
|
||||
wire adc32_data_ready, adc33_data_ready;
|
||||
wire adc32_data_valid, adc33_data_valid;
|
||||
|
||||
// -----------------------------------------------------------------------------
|
||||
// DAC Tile & Channel Mapping (Dual RF-DAC)
|
||||
// -----------------------------------------------------------------------------
|
||||
// s00_axis dac00 dac tile 228 (dac0), channel 0
|
||||
// s01_axis dac00 dac tile 228 (dac0), channel 1
|
||||
// s02_axis dac02 dac tile 228 (dac0), channel 2
|
||||
// s03_axis dac02 dac tile 228 (dac0), channel 3
|
||||
// -----------------------------------------------------------------------------
|
||||
// s10_axis dac10 dac tile 229 (dac1), channel 0
|
||||
// s11_axis dac10 dac tile 229 (dac1), channel 1
|
||||
// s12_axis dac12 dac tile 229 (dac1), channel 2
|
||||
// s13_axis dac12 dac tile 229 (dac1), channel 3
|
||||
// -----------------------------------------------------------------------------
|
||||
// s20_axis dac20 dac tile 230 (dac2), channel 0
|
||||
// s21_axis dac20 dac tile 230 (dac2), channel 1
|
||||
// s22_axis dac22 dac tile 230 (dac2), channel 2
|
||||
// s23_axis dac22 dac tile 230 (dac2), channel 3
|
||||
// -----------------------------------------------------------------------------
|
||||
// s30_axis dac30 dac tile 231 (dac3), channel 0
|
||||
// s31_axis dac30 dac tile 231 (dac3), channel 1
|
||||
// s32_axis dac32 dac tile 231 (dac3), channel 2
|
||||
// s33_axis dac32 dac tile 231 (dac3), channel 3
|
||||
// -----------------------------------------------------------------------------
|
||||
// Note:
|
||||
// 1) In most single-band cases, only channel 0/2 is enabled since i/q data are
|
||||
// transferred in one signle channel; when multi-band is used, multiple digital
|
||||
// channel may be enabled.
|
||||
// 2) When modify the following wire definition, **ONLY** change the data width.
|
||||
// The extra definition will be optimized automatically.
|
||||
// -----------------------------------------------------------------------------
|
||||
wire [31:0] dac00_data, dac01_data;
|
||||
wire dac00_data_ready, dac01_data_ready;
|
||||
wire dac00_data_valid, dac01_data_valid;
|
||||
|
||||
wire [31:0] dac02_data, dac03_data;
|
||||
wire dac02_data_ready, dac03_data_ready;
|
||||
wire dac02_data_valid, dac03_data_valid;
|
||||
|
||||
wire [31:0] dac10_data, dac11_data;
|
||||
wire dac10_data_ready, dac11_data_ready;
|
||||
wire dac10_data_valid, dac11_data_valid;
|
||||
|
||||
wire [31:0] dac12_data, dac13_data;
|
||||
wire dac12_data_ready, dac13_data_ready;
|
||||
wire dac12_data_valid, dac13_data_valid;
|
||||
|
||||
wire [31:0] dac20_data, dac21_data;
|
||||
wire dac20_data_ready, dac21_data_ready;
|
||||
wire dac20_data_valid, dac21_data_valid;
|
||||
|
||||
wire [31:0] dac22_data, dac23_data;
|
||||
wire dac22_data_ready, dac23_data_ready;
|
||||
wire dac22_data_valid, dac23_data_valid;
|
||||
|
||||
wire [31:0] dac30_data, dac31_data;
|
||||
wire dac30_data_ready, dac31_data_ready;
|
||||
wire dac30_data_valid, dac31_data_valid;
|
||||
|
||||
wire [31:0] dac32_data, dac33_data;
|
||||
wire dac32_data_ready, dac33_data_ready;
|
||||
wire dac32_data_valid, dac33_data_valid;
|
||||
|
||||
system_bd_wrapper u_system_bd_wrapper
|
||||
(
|
||||
// *************************************************************************
|
||||
// ********************* PL SYSREF & Reference Clocks **********************
|
||||
// *************************************************************************
|
||||
.ps_clk0 (ps_clk0 ),
|
||||
|
||||
.pl_clk_clk_p (pl_refclk_p ),
|
||||
.pl_clk_clk_n (pl_refclk_n ),
|
||||
|
||||
.pl_sysref_clk_p (pl_sysref_p ),
|
||||
.pl_sysref_clk_n (pl_sysref_n ),
|
||||
|
||||
.sys_clk (sys_clk ),
|
||||
.sys_rstn (sys_rstn ),
|
||||
|
||||
// *************************************************************************
|
||||
// ********************* RF SYSREF & Reference Clocks **********************
|
||||
// *************************************************************************
|
||||
.spi_sclk (spi_sclk ),
|
||||
.spi_cs (spi_cs ),
|
||||
.spi_sdi (spi_sdi ),
|
||||
.spi_sdo (spi_sdo ),
|
||||
.spi_sdo_t (spi_sdo_t ),
|
||||
.spi_three_wire (spi_three_wire ),
|
||||
.spi_active (spi_active ),
|
||||
|
||||
// *************************************************************************
|
||||
// ********************* RF SYSREF & Reference Clocks **********************
|
||||
// *************************************************************************
|
||||
// rf sysref
|
||||
.sysref_in_diff_p (rf_sysref_p ), // input sysref_in_diff_p
|
||||
.sysref_in_diff_n (rf_sysref_n ), // input sysref_in_diff_n
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// RF ADC Reference Clocks Mapping
|
||||
// -------------------------------------------------------------------------
|
||||
// adc0_clk_clk adc tile 224 (adc0) ref clock input, nc on borad
|
||||
// adc1_clk_clk adc tile 225 (adc1) ref clock input, from lmk04828
|
||||
// adc2_clk_clk adc tile 226 (adc2) ref clock input, from sma
|
||||
// adc3_clk_clk adc tile 227 (adc3) ref clock input, nc on borad
|
||||
// clk_adc0 adc tile 224 (adc0) clock output
|
||||
// clk_adc1 adc tile 225 (adc1) clock output
|
||||
// clk_adc2 adc tile 226 (adc2) clock output
|
||||
// clk_adc3 adc tile 227 (adc3) clock output
|
||||
// -------------------------------------------------------------------------
|
||||
// Note:
|
||||
// When modify the following wire connections, **ONLY** uncomment the needed
|
||||
// ports and comment the not-needed ones.
|
||||
// -------------------------------------------------------------------------
|
||||
// .adc1_clk_clk_p (adc1_clk_in_p ), // input adc1_clk_clk_p
|
||||
// .adc1_clk_clk_n (adc1_clk_in_n ), // input adc1_clk_clk_n
|
||||
.adc2_clk_clk_p (adc2_clk_in_p ), // input adc2_clk_clk_p
|
||||
.adc2_clk_clk_n (adc2_clk_in_n ), // input adc2_clk_clk_n
|
||||
.clk_adc0 ( ), // output clk_adc0
|
||||
.clk_adc1 ( ), // output clk_adc1
|
||||
.clk_adc2 ( ), // output clk_adc2
|
||||
.clk_adc3 ( ), // output clk_adc3
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// RF DAC Reference Clocks Mapping
|
||||
// -------------------------------------------------------------------------
|
||||
// dac0_clk_clk dac tile 228 (dac0) ref clock input, from lmk04828
|
||||
// dac1_clk_clk dac tile 229 (dac1) ref clock input, none for zu48dr
|
||||
// dac2_clk_clk dac tile 230 (dac2) ref clock input, from sma
|
||||
// dac3_clk_clk dac tile 231 (dac3) ref clock input, none for zu48dr
|
||||
// clk_dac0 dac tile 228 (dac0) clock output
|
||||
// clk_dac1 dac tile 229 (dac1) clock output
|
||||
// clk_dac2 dac tile 230 (dac2) clock output
|
||||
// clk_dac3 dac tile 231 (dac3) clock output
|
||||
// -------------------------------------------------------------------------
|
||||
// Note:
|
||||
// When modify the following wire connections, **ONLY** uncomment the needed
|
||||
// ports and comment the not-needed ones.
|
||||
// -------------------------------------------------------------------------
|
||||
// .dac0_clk_clk_p (dac0_clk_in_p ), // input dac0_clk_clk_p
|
||||
// .dac0_clk_clk_n (dac0_clk_in_n ), // input dac0_clk_clk_n
|
||||
.dac2_clk_clk_p (dac2_clk_in_p ), // input dac2_clk_clk_p
|
||||
.dac2_clk_clk_n (dac2_clk_in_n ), // input dac2_clk_clk_n
|
||||
.clk_dac0 ( ), // output clk_dac0
|
||||
.clk_dac1 ( ), // output clk_dac1
|
||||
.clk_dac2 ( ), // output clk_dac2
|
||||
.clk_dac3 ( ), // output clk_dac3
|
||||
|
||||
// *************************************************************************
|
||||
// *********** RF-ADC Tile 224 (adc0) Digital & Analog Interface ***********
|
||||
// *************************************************************************
|
||||
// fabric clock (axi4-stream clock)
|
||||
.m0_axis_aclk (sys_clk ), // input m0_axis_aclk
|
||||
.m0_axis_aresetn (sys_rstn ), // input m0_axis_aresetn
|
||||
|
||||
// channel 0 data
|
||||
.m00_axis_tdata (adc00_data ), // output [15:0]m00_axis_tdata
|
||||
.m00_axis_tready (adc00_data_ready ), // input m00_axis_tready
|
||||
.m00_axis_tvalid (adc00_data_valid ), // output m00_axis_tvalid
|
||||
// channel 1 data
|
||||
.m01_axis_tdata (adc01_data ), // output [15:0]m01_axis_tdata
|
||||
.m01_axis_tready (adc01_data_ready ), // input m01_axis_tready
|
||||
.m01_axis_tvalid (adc01_data_valid ), // output m01_axis_tvalid
|
||||
// analog input signal, J3 on board
|
||||
.vin0_01_v_p (adc0_01_in_p ), // input vin0_01_v_p
|
||||
.vin0_01_v_n (adc0_01_in_n ), // input vin0_01_v_n
|
||||
|
||||
// channel 2 data
|
||||
.m02_axis_tdata (adc02_data ), // output [15:0]m02_axis_tdata
|
||||
.m02_axis_tready (adc02_data_ready ), // input m02_axis_tready
|
||||
.m02_axis_tvalid (adc02_data_valid ), // output m02_axis_tvalid
|
||||
// channel 3 data
|
||||
.m03_axis_tdata (adc03_data ), // output [15:0]m03_axis_tdata
|
||||
.m03_axis_tready (adc03_data_ready ), // input m03_axis_tready
|
||||
.m03_axis_tvalid (adc03_data_valid ), // output m03_axis_tvalid
|
||||
// analog input signal, J5 on board
|
||||
.vin0_23_v_p (adc0_23_in_p ), // input vin0_23_v_p
|
||||
.vin0_23_v_n (adc0_23_in_n ), // input vin0_23_v_n
|
||||
|
||||
// *************************************************************************
|
||||
// *********** RF-ADC Tile 225 (adc1) Digital & Analog Interface ***********
|
||||
// *************************************************************************
|
||||
// fabric clock (axi4-stream clock)
|
||||
.m1_axis_aclk (sys_clk ), // input m1_axis_aclk
|
||||
.m1_axis_aresetn (sys_rstn ), // input m1_axis_aresetn
|
||||
|
||||
// channel 0 data
|
||||
.m10_axis_tdata (adc10_data ), // output [15:0]m10_axis_tdata
|
||||
.m10_axis_tready (adc10_data_ready ), // input m10_axis_tready
|
||||
.m10_axis_tvalid (adc10_data_valid ), // output m10_axis_tvalid
|
||||
// channel 1 data
|
||||
.m11_axis_tdata (adc11_data ), // output [15:0]m11_axis_tdata
|
||||
.m11_axis_tready (adc11_data_ready ), // input m11_axis_tready
|
||||
.m11_axis_tvalid (adc11_data_valid ), // output m11_axis_tvalid
|
||||
// analog input signal, J6 on board
|
||||
.vin1_01_v_p (adc1_01_in_p ), // input vin1_01_v_p
|
||||
.vin1_01_v_n (adc1_01_in_n ), // input vin1_01_v_n
|
||||
|
||||
// channel 2 data
|
||||
.m12_axis_tdata (adc12_data ), // output [15:0]m12_axis_tdata
|
||||
.m12_axis_tready (adc12_data_ready ), // input m12_axis_tready
|
||||
.m12_axis_tvalid (adc12_data_valid ), // output m12_axis_tvalid
|
||||
// channel 3 data
|
||||
.m13_axis_tdata (adc13_data ), // output [15:0]m13_axis_tdata
|
||||
.m13_axis_tready (adc13_data_ready ), // input m13_axis_tready
|
||||
.m13_axis_tvalid (adc13_data_valid ), // output m13_axis_tvalid
|
||||
// analog input signal, J7 on board
|
||||
.vin1_23_v_p (adc1_23_in_p ), // input vin1_23_v_p
|
||||
.vin1_23_v_n (adc1_23_in_n ), // input vin1_23_v_n
|
||||
|
||||
// *************************************************************************
|
||||
// *********** RF-ADC Tile 226 (adc2) Digital & Analog Interface ***********
|
||||
// *************************************************************************
|
||||
// fabric clock (axi4-stream clock)
|
||||
.m2_axis_aclk (sys_clk ), // input m2_axis_aclk
|
||||
.m2_axis_aresetn (sys_rstn ), // input m2_axis_aresetn
|
||||
|
||||
// channel 0 data
|
||||
.m20_axis_tdata (adc20_data ), // output [15:0]m20_axis_tdata
|
||||
.m20_axis_tready (adc20_data_ready ), // input m20_axis_tready
|
||||
.m20_axis_tvalid (adc20_data_valid ), // output m20_axis_tvalid
|
||||
// channel 1 data
|
||||
.m21_axis_tdata (adc21_data ), // output [15:0]m21_axis_tdata
|
||||
.m21_axis_tready (adc21_data_ready ), // input m21_axis_tready
|
||||
.m21_axis_tvalid (adc21_data_valid ), // output m21_axis_tvalid
|
||||
// analog input signal, J8 on board
|
||||
.vin2_01_v_p (adc2_01_in_p ), // input vin2_01_v_p
|
||||
.vin2_01_v_n (adc2_01_in_n ), // input vin2_01_v_n
|
||||
|
||||
// channel 2 data
|
||||
.m22_axis_tdata (adc22_data ), // output [15:0]m22_axis_tdata
|
||||
.m22_axis_tready (adc22_data_ready ), // input m22_axis_tready
|
||||
.m22_axis_tvalid (adc22_data_valid ), // output m22_axis_tvalid
|
||||
// channel 3 data
|
||||
.m23_axis_tdata (adc23_data ), // output [15:0]m23_axis_tdata
|
||||
.m23_axis_tready (adc23_data_ready ), // input m23_axis_tready
|
||||
.m23_axis_tvalid (adc23_data_valid ), // output m23_axis_tvalid
|
||||
// analog input signal, J9 on board
|
||||
.vin2_23_v_p (adc2_23_in_p ), // input vin2_23_v_p
|
||||
.vin2_23_v_n (adc2_23_in_n ), // input vin2_23_v_n
|
||||
|
||||
// *************************************************************************
|
||||
// *********** RF-ADC Tile 227 (adc3) Digital & Analog Interface ***********
|
||||
// *************************************************************************
|
||||
// fabric clock (axi4-stream clock)
|
||||
.m3_axis_aclk (sys_clk ), // input m3_axis_aclk
|
||||
.m3_axis_aresetn (sys_rstn ), // input m3_axis_aresetn
|
||||
|
||||
// channel 0 data
|
||||
.m30_axis_tdata (adc30_data ), // output [15:0]m30_axis_tdata
|
||||
.m30_axis_tready (adc30_data_ready ), // input m30_axis_tready
|
||||
.m30_axis_tvalid (adc30_data_valid ), // output m30_axis_tvalid
|
||||
// channel 1 data
|
||||
.m31_axis_tdata (adc31_data ), // output [15:0]m31_axis_tdata
|
||||
.m31_axis_tready (adc31_data_ready ), // input m31_axis_tready
|
||||
.m31_axis_tvalid (adc31_data_valid ), // output m31_axis_tvalid
|
||||
// analog input signal, J10 on board
|
||||
.vin3_01_v_p (adc3_01_in_p ), // input vin3_01_v_p
|
||||
.vin3_01_v_n (adc3_01_in_n ), // input vin3_01_v_n
|
||||
|
||||
// channel 2 data
|
||||
.m32_axis_tdata (adc32_data ), // output [15:0]m32_axis_tdata
|
||||
.m32_axis_tready (adc32_data_ready ), // input m32_axis_tready
|
||||
.m32_axis_tvalid (adc32_data_valid ), // output m32_axis_tvalid
|
||||
// channel 3 data
|
||||
.m33_axis_tdata (adc33_data ), // output [15:0]m33_axis_tdata
|
||||
.m33_axis_tready (adc33_data_ready ), // input m33_axis_tready
|
||||
.m33_axis_tvalid (adc33_data_valid ), // output m33_axis_tvalid
|
||||
// analog input signal, J12 on board
|
||||
.vin3_23_v_p (adc3_23_in_p ), // input vin3_23_v_p
|
||||
.vin3_23_v_n (adc3_23_in_n ), // input vin3_23_v_n
|
||||
|
||||
// *************************************************************************
|
||||
// *********** RF-DAC Tile 228 (dac0) Digital & Analog Interface ***********
|
||||
// *************************************************************************
|
||||
// fabric clock (axi4-stream clock)
|
||||
.s0_axis_aclk (sys_clk ), // input s0_axis_aclk
|
||||
.s0_axis_aresetn (sys_rstn ), // input s0_axis_aresetn
|
||||
|
||||
// channel 0 data
|
||||
.s00_axis_tdata (dac00_data ), // input [31:0]s00_axis_tdata
|
||||
.s00_axis_tready (dac00_data_ready ), // output s00_axis_tready
|
||||
.s00_axis_tvalid (dac00_data_valid ), // input s00_axis_tvalid
|
||||
// channel 1 data
|
||||
// .s01_axis_tdata (dac01_data ), // input [31:0]s01_axis_tdata
|
||||
// .s01_axis_tready (dac01_data_ready ), // output s01_axis_tready
|
||||
// .s01_axis_tvalid (dac01_data_valid ), // input s01_axis_tvalid
|
||||
// analog output signal, J14 on board
|
||||
.vout00_v_p (dac00_out_p ), // output vout00_v_p
|
||||
.vout00_v_n (dac00_out_n ), // output vout00_v_n
|
||||
|
||||
// channel 2 data
|
||||
.s02_axis_tdata (dac02_data ), // input [31:0]s02_axis_tdata
|
||||
.s02_axis_tready (dac02_data_ready ), // output s02_axis_tready
|
||||
.s02_axis_tvalid (dac02_data_valid ), // input s02_axis_tvalid
|
||||
// channel 3 data
|
||||
// .s03_axis_tdata (dac03_data ), // input [31:0]s03_axis_tdata
|
||||
// .s03_axis_tready (dac03_data_ready ), // output s03_axis_tready
|
||||
// .s03_axis_tvalid (dac03_data_valid ), // input s03_axis_tvalid
|
||||
// analog output signal, J16 on board
|
||||
.vout02_v_p (dac02_out_p ), // output vout02_v_p
|
||||
.vout02_v_n (dac02_out_n ), // output vout02_v_n
|
||||
|
||||
// *************************************************************************
|
||||
// *********** RF-DAC Tile 229 (dac1) Digital & Analog Interface ***********
|
||||
// *************************************************************************
|
||||
// fabric clock (axi4-stream clock)
|
||||
.s1_axis_aclk (sys_clk ), // input s1_axis_aclk
|
||||
.s1_axis_aresetn (sys_rstn ), // input s1_axis_aresetn
|
||||
|
||||
// channel 0 data
|
||||
.s10_axis_tdata (dac10_data ), // input [31:0]s10_axis_tdata
|
||||
.s10_axis_tready (dac10_data_ready ), // output s10_axis_tready
|
||||
.s10_axis_tvalid (dac10_data_valid ), // input s10_axis_tvalid
|
||||
// channel 1 data
|
||||
// .s11_axis_tdata (dac11_data ), // input [31:0]s11_axis_tdata
|
||||
// .s11_axis_tready (dac11_data_ready ), // output s11_axis_tready
|
||||
// .s11_axis_tvalid (dac11_data_valid ), // input s11_axis_tvalid
|
||||
// analog output signal, J17 on board
|
||||
.vout10_v_p (dac10_out_p ), // output vout10_v_p
|
||||
.vout10_v_n (dac10_out_n ), // output vout10_v_n
|
||||
|
||||
// channel 2 data
|
||||
.s12_axis_tdata (dac12_data ), // input [31:0]s12_axis_tdata
|
||||
.s12_axis_tready (dac12_data_ready ), // output s12_axis_tready
|
||||
.s12_axis_tvalid (dac12_data_valid ), // input s12_axis_tvalid
|
||||
// channel 3 data
|
||||
// .s13_axis_tdata (dac13_data ), // input [31:0]s13_axis_tdata
|
||||
// .s13_axis_tready (dac13_data_ready ), // output s13_axis_tready
|
||||
// .s13_axis_tvalid (dac13_data_valid ), // input s13_axis_tvalid
|
||||
// analog output signal, J18 on board
|
||||
.vout12_v_p (dac12_out_p ), // output vout12_v_p
|
||||
.vout12_v_n (dac12_out_n ), // output vout12_v_n
|
||||
|
||||
// *************************************************************************
|
||||
// *********** RF-DAC Tile 230 (dac2) Digital & Analog Interface ***********
|
||||
// *************************************************************************
|
||||
// fabric clock (axi4-stream clock)
|
||||
.s2_axis_aclk (sys_clk ), // input s2_axis_aclk
|
||||
.s2_axis_aresetn (sys_rstn ), // input s2_axis_aresetn
|
||||
|
||||
// channel 0 data
|
||||
.s20_axis_tdata (dac20_data ), // input [31:0]s20_axis_tdata
|
||||
.s20_axis_tready (dac20_data_ready ), // output s20_axis_tready
|
||||
.s20_axis_tvalid (dac20_data_valid ), // input s20_axis_tvalid
|
||||
// channel 1 data
|
||||
// .s21_axis_tdata (dac21_data ), // input [31:0]s21_axis_tdata
|
||||
// .s21_axis_tready (dac21_data_ready ), // output s21_axis_tready
|
||||
// .s21_axis_tvalid (dac21_data_valid ), // input s21_axis_tvalid
|
||||
// analog output signal, J19 on board
|
||||
.vout20_v_p (dac20_out_p ), // output vout20_v_p
|
||||
.vout20_v_n (dac20_out_n ), // output vout20_v_n
|
||||
|
||||
// channel 2 data
|
||||
.s22_axis_tdata (dac22_data ), // input [31:0]s22_axis_tdata
|
||||
.s22_axis_tready (dac22_data_ready ), // output s22_axis_tready
|
||||
.s22_axis_tvalid (dac22_data_valid ), // input s22_axis_tvalid
|
||||
// channel 3 data
|
||||
// .s23_axis_tdata (dac23_data ), // input [31:0]s23_axis_tdata
|
||||
// .s23_axis_tready (dac23_data_ready ), // output s23_axis_tready
|
||||
// .s23_axis_tvalid (dac23_data_valid ), // input s23_axis_tvalid
|
||||
// analog output signal, J20 on board
|
||||
.vout22_v_p (dac22_out_p ), // output vout22_v_p
|
||||
.vout22_v_n (dac22_out_n ), // output vout22_v_n
|
||||
|
||||
// *************************************************************************
|
||||
// *********** RF-DAC Tile 231 (dac3) Digital & Analog Interface ***********
|
||||
// *************************************************************************
|
||||
// fabric clock (axi4-stream clock)
|
||||
.s3_axis_aclk (sys_clk ), // input s3_axis_aclk
|
||||
.s3_axis_aresetn (sys_rstn ), // input s3_axis_aresetn
|
||||
|
||||
// channel 0 data
|
||||
.s30_axis_tdata (dac30_data ), // input [31:0]s30_axis_tdata
|
||||
.s30_axis_tready (dac30_data_ready ), // output s30_axis_tready
|
||||
.s30_axis_tvalid (dac30_data_valid ), // input s30_axis_tvalid
|
||||
// channel 1 data
|
||||
// .s31_axis_tdata (dac31_data ), // input [31:0]s31_axis_tdata
|
||||
// .s31_axis_tready (dac31_data_ready ), // output s31_axis_tready
|
||||
// .s31_axis_tvalid (dac31_data_valid ), // input s31_axis_tvalid
|
||||
// analog output signal, J21 on board
|
||||
.vout30_v_p (dac30_out_p ), // output vout30_v_p
|
||||
.vout30_v_n (dac30_out_n ), // output vout30_v_n
|
||||
|
||||
// channel 2 data
|
||||
.s32_axis_tdata (dac32_data ), // input [31:0]s32_axis_tdata
|
||||
.s32_axis_tready (dac32_data_ready ), // output s32_axis_tready
|
||||
.s32_axis_tvalid (dac32_data_valid ), // input s32_axis_tvalid
|
||||
// channel 3 data
|
||||
// .s33_axis_tdata (dac33_data ), // input [31:0]s33_axis_tdata
|
||||
// .s33_axis_tready (dac33_data_ready ), // output s33_axis_tready
|
||||
// .s33_axis_tvalid (dac33_data_valid ), // input s33_axis_tvalid
|
||||
// analog output signal, J23 on board
|
||||
.vout32_v_p (dac32_out_p ), // output vout32_v_p
|
||||
.vout32_v_n (dac32_out_n ) // output vout32_v_n
|
||||
);
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
////////////////////////////////// Tx Signal ///////////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// tx signal mapping
|
||||
wire [15:0] tx_data_i, tx_data_q;
|
||||
|
||||
assign dac00_data = {tx_data_q, tx_data_i};
|
||||
assign dac02_data = {tx_data_q, tx_data_i};
|
||||
assign dac10_data = {tx_data_q, tx_data_i};
|
||||
assign dac12_data = {tx_data_q, tx_data_i};
|
||||
assign dac20_data = {tx_data_q, tx_data_i};
|
||||
assign dac22_data = {tx_data_q, tx_data_i};
|
||||
assign dac30_data = {tx_data_q, tx_data_i};
|
||||
assign dac32_data = {tx_data_q, tx_data_i};
|
||||
|
||||
// transimitter logic
|
||||
wire [ 1:0] waveform_sel;
|
||||
wire sweep_on ;
|
||||
wire [31:0] freq_set ;
|
||||
wire [ 1:0] iq_sel ;
|
||||
wire [ 3:0] bb_rshift ;
|
||||
|
||||
tx_qpsk #(
|
||||
.DATA_WIDTH (16),
|
||||
.BIT_DATA (1024'b0000000100100010000011001001101000010010101000011110101110101101101100000000110000011011001100001010110101110001101111110001000111100111101101101000000010100001011010101000111110111100100101100000100110010001010001101101110000001111000111011111110010000110001011011101000011010101100111100101101100100000100010010011000000101100010100111011001110001011111101010001011101101011000011001101101010000011101001111010011010100100111000001111100111001101111010001010101101111100001001110100011101011111011010010000100001010010101100011100111111101100001000110100111001001111000011011101100011000111101111101001001010000001101000110010111010010110100010001011001101001010010001100001110110111100000101110010101110011101110111001100111010101110111101100101000100110110001000011100101111100101001100110010101010011111100110001101011110011010110100110001001011100001011110101010101111111101000001010100101111000101011110111010100110111001000111000111111111100000001110000111111011100010011111000110011111010110010110010010010000000001),
|
||||
.BIT_DATA_LEN (1024),
|
||||
.CLK_FREQ (245_760_000)
|
||||
) u_tx_qpsk
|
||||
(
|
||||
.clk (sys_clk ), // input clk
|
||||
.rst (~sys_rstn ), // input rst
|
||||
.tx_data_i (tx_data_i ), // output [15:0] tx_data_i
|
||||
.tx_data_q (tx_data_q ), // output [15:0] tx_data_q
|
||||
// debug ports
|
||||
.waveform_sel (waveform_sel[1:0] ), // input [ 1:0] waveform_sel
|
||||
.sweep_on (sweep_on ), // input sweep_on
|
||||
.freq_set (freq_set ), // input [31:0] freq_set
|
||||
.iq_sel (iq_sel ), // input [ 1:0] iq_sel
|
||||
.bb_rshift (bb_rshift ) // input [ 3:0] bb_rshift
|
||||
);
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
////////////////////////////////// Rx Signal ///////////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// rx signal mapping
|
||||
wire [15:0] rx_ch1_i, rx_ch1_q;
|
||||
wire [15:0] rx_ch2_i, rx_ch2_q;
|
||||
wire [15:0] rx_ch3_i, rx_ch3_q;
|
||||
wire [15:0] rx_ch4_i, rx_ch4_q;
|
||||
wire [15:0] rx_ch5_i, rx_ch5_q;
|
||||
wire [15:0] rx_ch6_i, rx_ch6_q;
|
||||
wire [15:0] rx_ch7_i, rx_ch7_q;
|
||||
wire [15:0] rx_ch8_i, rx_ch8_q;
|
||||
|
||||
assign rx_ch1_i = adc00_data;
|
||||
assign rx_ch1_q = adc01_data;
|
||||
assign rx_ch2_i = adc02_data;
|
||||
assign rx_ch2_q = adc03_data;
|
||||
assign rx_ch3_i = adc10_data;
|
||||
assign rx_ch3_q = adc11_data;
|
||||
assign rx_ch4_i = adc12_data;
|
||||
assign rx_ch4_q = adc13_data;
|
||||
assign rx_ch5_i = adc20_data;
|
||||
assign rx_ch5_q = adc21_data;
|
||||
assign rx_ch6_i = adc22_data;
|
||||
assign rx_ch6_q = adc23_data;
|
||||
assign rx_ch7_i = adc30_data;
|
||||
assign rx_ch7_q = adc31_data;
|
||||
assign rx_ch8_i = adc32_data;
|
||||
assign rx_ch8_q = adc33_data;
|
||||
|
||||
// receiver logic
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//////////////////////////////// ILAs and VIOs /////////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
ila_adc u_ila_adc
|
||||
(
|
||||
.clk (sys_clk ), // input wire clk
|
||||
.probe0 (rx_ch1_i ), // input wire [15:0] probe0
|
||||
.probe1 (rx_ch1_q ), // input wire [15:0] probe1
|
||||
.probe2 (rx_ch2_i ), // input wire [15:0] probe2
|
||||
.probe3 (rx_ch2_q ), // input wire [15:0] probe3
|
||||
.probe4 (rx_ch3_i ), // input wire [15:0] probe4
|
||||
.probe5 (rx_ch3_q ), // input wire [15:0] probe5
|
||||
.probe6 (rx_ch4_i ), // input wire [15:0] probe6
|
||||
.probe7 (rx_ch4_q ), // input wire [15:0] probe7
|
||||
.probe8 (rx_ch5_i ), // input wire [15:0] probe8
|
||||
.probe9 (rx_ch5_q ), // input wire [15:0] probe9
|
||||
.probe10(rx_ch6_i ), // input wire [15:0] probe10
|
||||
.probe11(rx_ch6_q ), // input wire [15:0] probe11
|
||||
.probe12(rx_ch7_i ), // input wire [15:0] probe12
|
||||
.probe13(rx_ch7_q ), // input wire [15:0] probe13
|
||||
.probe14(rx_ch8_i ), // input wire [15:0] probe14
|
||||
.probe15(rx_ch8_q ) // input wire [15:0] probe15
|
||||
);
|
||||
|
||||
ila_dac u_ila_dac
|
||||
(
|
||||
.clk (sys_clk ), // input wire clk
|
||||
.probe0 (tx_data_i ), // input wire [15:0] probe0
|
||||
.probe1 (tx_data_q ) // input wire [15:0] probe1
|
||||
);
|
||||
|
||||
vio_manual_ctrl u_vio_manual_ctrl
|
||||
(
|
||||
.clk (sys_clk ), // input wire clk
|
||||
.probe_out0 (waveform_sel[1:0] ), // output wire [1 : 0] probe_out0
|
||||
.probe_out1 (sweep_on ), // output wire [0 : 0] probe_out1
|
||||
.probe_out2 (freq_set[31:0] ), // output wire [31 : 0] probe_out2
|
||||
.probe_out3 (iq_sel[1:0] ), // output wire [1 : 0] probe_out3
|
||||
.probe_out4 (bb_rshift[3:0] ) // output wire [3 : 0] probe_out4
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,539 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
// _ _ ____
|
||||
// | | ___ ___| |__ / ___| __ _ ___
|
||||
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||
//
|
||||
// Create Date: 2022/03/23 20:17:56
|
||||
// Last Modified Date: 2023/03/10 15:41
|
||||
// Design Name:
|
||||
// Module Name: tx_qpsk
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// 20230228-1541 - 修改不扫频、无基带频偏时 [baseband_i/q] 的数据输出，原来从
|
||||
// 乘法器引出，会导致频率为 0 时输出数据错误，现在直接从基带数据引出。
|
||||
// 20230310-1542 - 增加输入参数，发送数据更改为直接由参数输入，发送方波改为 8
|
||||
// 倍过采样，发送双音信号中 1MHz 信号的频率控制字可以根据参数中的时钟频率计
|
||||
// 算得出。
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module tx_qpsk
|
||||
#(
|
||||
parameter DATA_WIDTH = 12, // need to be <= 16
|
||||
parameter BIT_DATA = 128'b00000011000010100011110010001011001110101001111101000011100010010011011010110111101100011010010111011100110010101011111110000001, // inverse pseudorandom bit sequence, [0,flip(PRSB7)]
|
||||
parameter BIT_DATA_LEN = 128,
|
||||
parameter SQUARE_INTERP = 8,
|
||||
parameter CLK_FREQ = 245760000 // in Hertz
|
||||
)
|
||||
(
|
||||
input clk ,
|
||||
input rst ,
|
||||
output [DATA_WIDTH-1:0] tx_data_i ,
|
||||
output [DATA_WIDTH-1:0] tx_data_q ,
|
||||
// debug ports
|
||||
input [ 1:0] waveform_sel ,
|
||||
input sweep_on ,
|
||||
input [31:0] freq_set ,
|
||||
input [ 1:0] iq_sel ,
|
||||
input [ 3:0] bb_rshift
|
||||
);
|
||||
|
||||
localparam RCOS_INTERP = 64;
|
||||
localparam INTERP = (RCOS_INTERP > SQUARE_INTERP) ? RCOS_INTERP : SQUARE_INTERP;
|
||||
localparam FREQ_WORD_1M = 64'd2**64'd32*64'd1000000/CLK_FREQ;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
///////////////////////////////// Data Counter /////////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// symbol & interpolation counter
|
||||
reg [$clog2(INTERP*BIT_DATA_LEN)-1 : 0] cnt = 'b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cnt <= 'b0;
|
||||
end
|
||||
else begin
|
||||
cnt <= (cnt == INTERP*BIT_DATA_LEN - 1) ? 'b0 : cnt + 16'b1;
|
||||
end
|
||||
end
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
////////////////////// Root-Rasied Cosine Shaping Filter ///////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// address
|
||||
reg [$clog2(BIT_DATA_LEN)-1 : 0] hrc_data_addr_i = 'b0;
|
||||
reg [$clog2(BIT_DATA_LEN)-1 : 0] hrc_data_addr_q = 'b1;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
hrc_data_addr_i <= 'b0;
|
||||
hrc_data_addr_q <= 'b1;
|
||||
end
|
||||
else begin
|
||||
hrc_data_addr_i <= {cnt[$clog2(RCOS_INTERP) +: ($clog2(BIT_DATA_LEN)-1)],1'b0};
|
||||
hrc_data_addr_q <= {cnt[$clog2(RCOS_INTERP) +: ($clog2(BIT_DATA_LEN)-1)],1'b1};
|
||||
end
|
||||
end
|
||||
|
||||
// bit data
|
||||
reg hrc_data_i = 'b0;
|
||||
reg hrc_data_q = 'b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
hrc_data_i <= 'b0;
|
||||
hrc_data_q <= 'b0;
|
||||
end
|
||||
else begin
|
||||
hrc_data_i <= BIT_DATA[hrc_data_addr_i];
|
||||
hrc_data_q <= BIT_DATA[hrc_data_addr_q];
|
||||
end
|
||||
end
|
||||
|
||||
// polarization
|
||||
wire [ 7:0] hrc_data_polar_i;
|
||||
wire [ 7:0] hrc_data_polar_q;
|
||||
|
||||
assign hrc_data_polar_i = {{7{hrc_data_i}},1'b1};
|
||||
assign hrc_data_polar_q = {{7{hrc_data_q}},1'b1};
|
||||
|
||||
// root raised cosine shaping-filter
|
||||
wire [23:0] hrc_wave_i;
|
||||
wire [23:0] hrc_wave_q;
|
||||
|
||||
hrc_64_12_025 u_hrc_i (
|
||||
.aclk (clk ), // input wire aclk
|
||||
.s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid
|
||||
.s_axis_data_tready ( ), // output wire s_axis_data_tready
|
||||
.s_axis_data_tdata (hrc_data_polar_i ), // input wire [7 : 0] s_axis_data_tdata
|
||||
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
|
||||
.m_axis_data_tdata (hrc_wave_i ) // output wire [23 : 0] m_axis_data_tdata
|
||||
);
|
||||
|
||||
hrc_64_12_025 u_hrc_q (
|
||||
.aclk (clk ), // input wire aclk
|
||||
.s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid
|
||||
.s_axis_data_tready ( ), // output wire s_axis_data_tready
|
||||
.s_axis_data_tdata (hrc_data_polar_q ), // input wire [7 : 0] s_axis_data_tdata
|
||||
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
|
||||
.m_axis_data_tdata (hrc_wave_q ) // output wire [23 : 0] m_axis_data_tdata
|
||||
);
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//////////////////////////// Square Shaping Filter /////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// address
|
||||
reg [$clog2(BIT_DATA_LEN)-1 : 0] hsq_data_addr = 'b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
hsq_data_addr <= 'b0;
|
||||
end
|
||||
else
|
||||
hsq_data_addr <= {cnt[$clog2(SQUARE_INTERP) +: $clog2(BIT_DATA_LEN)]};
|
||||
end
|
||||
|
||||
// bit data
|
||||
reg hsq_data = 'b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
hsq_data <= 'b0;
|
||||
end
|
||||
else begin
|
||||
hsq_data <= BIT_DATA[hsq_data_addr];
|
||||
end
|
||||
end
|
||||
|
||||
// square shaping-filter
|
||||
reg [17:0] hsq_wave_i ='b0;
|
||||
reg [17:0] hsq_wave_q ='b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
hsq_wave_i <= 'b0;
|
||||
hsq_wave_q <= 'b0;
|
||||
end
|
||||
else begin
|
||||
hsq_wave_i <= hsq_data ? 18'b01_1111_1111_1111_1111 : 18'b10_0000_0000_0000_0001;
|
||||
hsq_wave_q <= hsq_data ? 18'b10_0000_0000_0000_0001 : 18'b01_1111_1111_1111_1111;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/////////////////////////////// Two Tone Siganl ////////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// cosine wave with freq of 1 MHz
|
||||
wire signed [7:0] cos_1m;
|
||||
wire signed [7:0] sin_1m;
|
||||
|
||||
dds_32b_8b u_dds_1m
|
||||
(
|
||||
.aclk (clk ), // input wire aclk
|
||||
.s_axis_config_tvalid (1'b1 ), // input wire s_axis_config_tvalid
|
||||
.s_axis_config_tdata (FREQ_WORD_1M[31:0] ), // input wire [31 : 0] s_axis_config_tdata
|
||||
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
|
||||
.m_axis_data_tdata ({sin_1m,cos_1m} ) // output wire [15 : 0] m_axis_data_tdata
|
||||
);
|
||||
|
||||
// two-tone signal
|
||||
reg signed [16:0] two_tone_wave_i = 'b0;
|
||||
reg signed [16:0] two_tone_wave_q = 'b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
two_tone_wave_i <= 'b0;
|
||||
two_tone_wave_q <= 'b0;
|
||||
end
|
||||
else begin
|
||||
two_tone_wave_i <= 17'b0_0111_1111_1111_1111 + {cos_1m[7],cos_1m,8'd0};
|
||||
two_tone_wave_q <= 17'b0 + {sin_1m[7],sin_1m,8'd0};
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
///////////////////// Waveform Selection & Hopping Control /////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// baseband signal select
|
||||
reg [17:0] baseband_sel_i = 'b0;
|
||||
reg [17:0] baseband_sel_q = 'b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
baseband_sel_i <= 'b0;
|
||||
baseband_sel_q <= 'b0;
|
||||
end
|
||||
else begin
|
||||
case (waveform_sel[1:0])
|
||||
2'd0: begin
|
||||
baseband_sel_i <= {hrc_wave_i[16:0],1'b0};
|
||||
baseband_sel_q <= {hrc_wave_q[16:0],1'b0};
|
||||
end
|
||||
2'd1: begin
|
||||
baseband_sel_i <= hsq_wave_i[17:0];
|
||||
baseband_sel_q <= hsq_wave_q[17:0];
|
||||
end
|
||||
2'd2: begin
|
||||
baseband_sel_i <= 18'b01_1111_1111_1111_1111;
|
||||
baseband_sel_q <= 18'b0;
|
||||
end
|
||||
2'd3: begin
|
||||
baseband_sel_i <= {two_tone_wave_i[16:0],1'b0};
|
||||
baseband_sel_q <= {two_tone_wave_q[16:0],1'b0};
|
||||
end
|
||||
default: begin
|
||||
baseband_sel_i <= {hrc_wave_i[16:0],1'b0};
|
||||
baseband_sel_q <= {hrc_wave_q[16:0],1'b0};
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// hopping control, 3750hop/s
|
||||
reg [23:0] sweep_rom_addr = 'b0;
|
||||
wire [31:0] freq_sweep;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
sweep_rom_addr <= 'b0;
|
||||
end
|
||||
else if (sweep_on) begin
|
||||
sweep_rom_addr <= sweep_rom_addr + 24'b1;
|
||||
end
|
||||
else begin
|
||||
sweep_rom_addr <= 'b0;
|
||||
end
|
||||
end
|
||||
|
||||
hop_rom u_sweep_rom
|
||||
(
|
||||
.clka (clk ), // input wire clka
|
||||
.addra (sweep_rom_addr[23:16] ), // input wire [7 : 0] addra
|
||||
.douta (freq_sweep ) // output wire [31 : 0] douta
|
||||
);
|
||||
|
||||
// choose the actual frequency word
|
||||
reg [31:0] freq_word = 'b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
freq_word <= 'b0;
|
||||
end
|
||||
else if (sweep_on) begin
|
||||
// frequency sweep
|
||||
freq_word <= freq_sweep;
|
||||
end
|
||||
else begin
|
||||
// normal operation
|
||||
freq_word <= freq_set;
|
||||
end
|
||||
end
|
||||
|
||||
// baseband frequency shift carrier generation
|
||||
wire [ 7:0] cos_dds;
|
||||
wire [ 7:0] sin_dds;
|
||||
reg [ 7:0] cos = 'b0;
|
||||
reg [ 7:0] sin = 'b0;
|
||||
|
||||
dds_32b_8b u_dds_bb_shift (
|
||||
.aclk (clk ), // input wire aclk
|
||||
.s_axis_config_tvalid (~rst ), // input wire s_axis_config_tvalid
|
||||
.s_axis_config_tdata (freq_word ), // input wire [31 : 0] s_axis_config_tdata
|
||||
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
|
||||
.m_axis_data_tdata ({sin_dds,cos_dds}) // output wire [31 : 0] m_axis_data_tdata
|
||||
);
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cos <= 'b0;
|
||||
sin <= 'b0;
|
||||
end
|
||||
else if (freq_word == 'b0) begin
|
||||
// to make sure the carriers stay at the right position when freq = 0
|
||||
cos <= 8'b0111_1111;
|
||||
sin <= 8'b0111_1111;
|
||||
end
|
||||
else begin
|
||||
cos <= cos_dds;
|
||||
sin <= sin_dds;
|
||||
end
|
||||
end
|
||||
|
||||
// baseband frequency shift modulation
|
||||
wire [47:0] mod_cmpy_a;
|
||||
wire [15:0] mod_cmpy_b;
|
||||
wire [63:0] mod_cmpy_out;
|
||||
|
||||
wire [26:0] baseband_mult_i;
|
||||
wire [26:0] baseband_mult_q;
|
||||
|
||||
assign mod_cmpy_a = {6'b0,baseband_sel_q,6'b0,baseband_sel_i};
|
||||
assign mod_cmpy_b = {-sin,cos};
|
||||
|
||||
assign baseband_mult_i = mod_cmpy_out[58:32];
|
||||
assign baseband_mult_q = mod_cmpy_out[26: 0];
|
||||
|
||||
cmpy_18x8 u_cmpy_18x8
|
||||
(
|
||||
.aclk (clk ), // input wire aclk
|
||||
.s_axis_a_tvalid (1'b1 ), // input wire s_axis_a_tvalid
|
||||
.s_axis_a_tdata (mod_cmpy_a ), // input wire [47 : 0] s_axis_a_tdata
|
||||
.s_axis_b_tvalid (1'b1 ), // input wire s_axis_b_tvalid
|
||||
.s_axis_b_tdata (mod_cmpy_b ), // input wire [15 : 0] s_axis_b_tdata
|
||||
.m_axis_dout_tvalid ( ), // output wire m_axis_dout_tvalid
|
||||
.m_axis_dout_tdata (mod_cmpy_out ) // output wire [63 : 0] m_axis_dout_tdata
|
||||
);
|
||||
|
||||
// truncate to 16-bit
|
||||
reg signed [15:0] baseband_i = 'b0;
|
||||
reg signed [15:0] baseband_q = 'b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
baseband_i <= 'b0;
|
||||
baseband_q <= 'b0;
|
||||
end
|
||||
else begin
|
||||
case (waveform_sel[1:0])
|
||||
2'd0: begin
|
||||
// scale rasied-cosine-shaped bpsk signal by 1.125 or 1.625
|
||||
baseband_i <= (sweep_on == 0 && freq_set == 0) ? (baseband_sel_i[17 -: 16] + {{3{baseband_sel_i[17]}},baseband_sel_i[17 -: 13]}) : (baseband_mult_i[25:10] + {baseband_mult_i[25],baseband_mult_i[25:11]} + {{3{baseband_mult_i[25]}},baseband_mult_i[25:13]});
|
||||
baseband_q <= (sweep_on == 0 && freq_set == 0) ? (baseband_sel_q[17 -: 16] + {{3{baseband_sel_q[17]}},baseband_sel_q[17 -: 13]}) : (baseband_mult_q[25:10] + {baseband_mult_q[25],baseband_mult_q[25:11]} + {{3{baseband_mult_q[25]}},baseband_mult_q[25:13]});
|
||||
end
|
||||
2'd1: begin
|
||||
baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : (baseband_mult_i[25:10] + {{2{baseband_mult_i[25]}},baseband_mult_i[25:12]});
|
||||
baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : (baseband_mult_q[25:10] + {{2{baseband_mult_q[25]}},baseband_mult_q[25:12]});
|
||||
end
|
||||
2'd2: begin
|
||||
baseband_i <= baseband_mult_i[24:9];
|
||||
baseband_q <= baseband_mult_q[24:9];
|
||||
end
|
||||
2'd3: begin
|
||||
baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : baseband_mult_i[24:9];
|
||||
baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : baseband_mult_q[24:9];
|
||||
end
|
||||
default: begin
|
||||
// scale rasied-cosine-shaped bpsk signal by 1.125
|
||||
baseband_i <= baseband_mult_i[25:10] + {{3{baseband_mult_i[25]}},baseband_mult_i[25:13]};
|
||||
baseband_q <= baseband_mult_q[25:10] + {{3{baseband_mult_q[25]}},baseband_mult_q[25:13]};
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// iq selection & baseband right shift
|
||||
reg signed [15:0] baseband_data_i = 'b0;
|
||||
reg signed [15:0] baseband_data_q = 'b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
baseband_data_i <= 'b0;
|
||||
baseband_data_q <= 'b0;
|
||||
end
|
||||
else begin
|
||||
// inphase selection
|
||||
if (iq_sel[1]) begin
|
||||
baseband_data_i <= baseband_i >>> bb_rshift;
|
||||
end
|
||||
else begin
|
||||
baseband_data_i <= 'b0;
|
||||
end
|
||||
// quadrature selection
|
||||
if (iq_sel[0]) begin
|
||||
baseband_data_q <= baseband_q >>> bb_rshift;
|
||||
end
|
||||
else begin
|
||||
baseband_data_q <= 'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// output data to ports
|
||||
assign tx_data_i = baseband_data_i[15 -: DATA_WIDTH];
|
||||
assign tx_data_q = baseband_data_q[15 -: DATA_WIDTH];
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2020/12/08 12:43:46
|
||||
// Design Name:
|
||||
// Module Name: tb_tx_qpsk
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
// module tb_tx_qpsk;
|
||||
|
||||
// reg clk = 1'b0 ;
|
||||
// reg rst = 1'b1 ;
|
||||
// reg tx_on = 1'b1 ;
|
||||
// reg [31:0] freq_set ;
|
||||
// reg [ 1:0] waveform_sel = 2'b00;
|
||||
// reg [ 1:0] iq_sel = 2'b11 ;
|
||||
// wire [11:0] tx_data_i ;
|
||||
// wire [11:0] tx_data_q ;
|
||||
// reg [ 3:0] bb_rshift = 5'b0 ;
|
||||
|
||||
// tx_qpsk u_tx_qpsk
|
||||
// (
|
||||
// .clk (clk ),
|
||||
// .rst (rst ),
|
||||
// .tx_data_i (tx_data_i ),
|
||||
// .tx_data_q (tx_data_q ),
|
||||
// .waveform_sel (waveform_sel ),
|
||||
// .sweep_on (1'b0 ),
|
||||
// // .freq_set (32'd447392426 ),
|
||||
// .freq_set (32'd0 ),
|
||||
// .iq_sel (iq_sel ),
|
||||
// .bb_rshift (bb_rshift )
|
||||
// );
|
||||
|
||||
// initial begin
|
||||
// #102
|
||||
// rst = 1'b0;
|
||||
// // freq_set = 32'd873813333;
|
||||
// // waveform_sel = 2'b00;
|
||||
// // bb_rshift = 5'd0;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd1;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd2;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd3;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd4;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd5;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd6;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd7;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd8;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd9;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd14;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd15;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd16;
|
||||
// // freq_set = 32'd0;
|
||||
// // func_sel = 3'b010;
|
||||
// // #7777
|
||||
// // freq_set = 32'd536870912;
|
||||
// // func_sel = 3'b100;
|
||||
// // #7777
|
||||
// // freq_set = 32'd0;
|
||||
// // func_sel = 3'b100;
|
||||
// // #7777
|
||||
// // freq_set = 32'd536870912;
|
||||
// // func_sel = 3'b010;
|
||||
// // #7777
|
||||
// // freq_set = 32'd0;
|
||||
// // func_sel = 3'b010;
|
||||
// // freq_set = 32'd536870912;
|
||||
// // iq_sel = 2'b00;
|
||||
// // #7777
|
||||
// // freq_set = 32'd536870912;
|
||||
// // iq_sel = 2'b01;
|
||||
// // #7777
|
||||
// // freq_set = 32'd536870912;
|
||||
// // iq_sel = 2'b10;
|
||||
// // #7777
|
||||
// // freq_set = 32'd536870912;
|
||||
// // iq_sel = 2'b11;
|
||||
// end
|
||||
|
||||
// always #5 clk = ~clk;
|
||||
|
||||
// // integer i;
|
||||
// // integer w_file;
|
||||
|
||||
// // initial begin
|
||||
// // w_file = $fopen("D:\\qpsk_josh.txt","w");
|
||||
// // for (i = 0; i <= 35000; i = i + 1) begin
|
||||
// // wait(clk);
|
||||
// // #10;
|
||||
// // $fdisplay(w_file,"%d %d",$signed(tx_data_i),
|
||||
// // $signed(tx_data_q));
|
||||
// // if (i == 35000) begin
|
||||
// // $fclose(w_file);
|
||||
// // $stop;
|
||||
// // end
|
||||
// // end
|
||||
// // end
|
||||
|
||||
// endmodule
|
||||
@@ -0,0 +1,3 @@
|
||||
version https://git-lfs.github.com/spec/v1
|
||||
oid sha256:82bfa605a6f34744f7bca24fe9ce2486403b42574d5588533ada7d4a4b4912b6
|
||||
size 250882
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,3 @@
|
||||
version https://git-lfs.github.com/spec/v1
|
||||
oid sha256:5770774e3c603f731a26905379ca1afd27fae0f231ddbd21b6cfff073bf9646f
|
||||
size 2378340
|
||||
Reference in New Issue
Block a user