update ad9361 mapping

cmos mode works fine, but the timing of lvds mode needs more test

modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sim_1/new/tb_ad9361_trx_cmos_dual.v

@@ -0,0 +1,109 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 09/27/2024 04:42:03 PM
+// Design Name:
+// Module Name: tb_ad9361_trx_cmos_dual
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module tb_ad9361_trx_cmos_dual;
+
+reg clk_2x_in = 'b0;
+reg clk_in_rst = 'b0;
+reg data_clk = 'b0;
+reg data_clk_rst = 'b0;
+reg [11:0] tx_ch1_i = 'b0;
+reg [11:0] tx_ch1_q = 'b0;
+reg [11:0] tx_ch2_i = 'b0;
+reg [11:0] tx_ch2_q = 'b0;
+wire [11:0] rx_ch1_i;
+wire [11:0] rx_ch1_q;
+wire [11:0] rx_ch2_i;
+wire [11:0] rx_ch2_q;
+
+wire clk_out;
+wire tx_frame;
+wire [11:0] tx_data;
+
+ad9361_tx_map_cmos_dual dut_tx
+(
+    .clk_2x_in      (clk_2x_in      ),
+    .clk_in_rst     (clk_in_rst     ),
+
+    .tx_data_clk    (data_clk       ),
+    .tx_data_clk_rst(data_clk_rst   ),
+
+    .tx_ch1_i       (tx_ch1_i       ),
+    .tx_ch1_q       (tx_ch1_q       ),
+    .tx_ch2_i       (tx_ch2_i       ),
+    .tx_ch2_q       (tx_ch2_q       ),
+
+    .clk_out        (clk_out        ),
+    .tx_frame       (tx_frame       ),
+    .tx_data        (tx_data        )
+);
+
+ad9361_rx_map_cmos_dual dut_rx
+(
+    .clk_2x_in      (clk_2x_in      ),
+    .clk_in_rst     (clk_in_rst     ),
+
+    .rx_data_clk    (data_clk       ), // sync to output data
+    .rx_data_clk_rst(data_clk_rst   ),
+
+    .rx_fifo_rst    (1'b0           ),  // async fifo reset
+
+    .rx_frame       (tx_frame       ),
+    .rx_data        (tx_data        ),
+
+    .rx_ch1_i       (rx_ch1_i       ),
+    .rx_ch1_q       (rx_ch1_q       ),
+    .rx_ch2_i       (rx_ch2_i       ),
+    .rx_ch2_q       (rx_ch2_q       )
+);
+
+initial begin
+    clk_in_rst = 1'b1;
+    data_clk_rst = 1'b1;
+    #102
+    clk_in_rst = 'b0;
+    #333
+    data_clk_rst = 'b0;
+end
+
+always #20 clk_2x_in = ~clk_2x_in;
+
+always @(posedge clk_2x_in) begin
+    #7 data_clk <= ~data_clk;
+end
+
+always @(posedge data_clk) begin
+    if (data_clk_rst) begin
+        tx_ch1_i <= 'b0;
+        tx_ch1_q <= 'b0;
+        tx_ch2_i <= 'b0;
+        tx_ch2_q <= 'b0;
+    end
+    else begin
+        tx_ch1_i <= tx_ch1_i + 3'd1;
+        tx_ch1_q <= tx_ch1_q + 3'd2;
+        tx_ch2_i <= tx_ch2_i + 3'd3;
+        tx_ch2_q <= tx_ch2_q + 3'd4;
+    end
+end
+
+endmodule

modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sim_1/new/tb_ad9361_trx_cmos_single.v

@@ -0,0 +1,94 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 09/27/2024 04:34:43 PM
+// Design Name:
+// Module Name: tb_ad9361_trx_cmos_single
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module tb_ad9361_trx_cmos_single;
+
+reg clk_in = 'b0;
+reg clk_in_rst = 'b0;
+wire data_clk;
+reg data_clk_rst = 'b0;
+reg [11:0] tx_data_i = 'b0;
+reg [11:0] tx_data_q = 'b0;
+wire [11:0] rx_data_i;
+wire [11:0] rx_data_q;
+
+wire clk_out;
+wire tx_frame;
+wire [11:0] tx_data;
+
+ad9361_tx_map_cmos_single dut_tx
+(
+    .clk_in         (clk_in         ),
+    .clk_in_rst     (clk_in_rst     ),
+
+    .tx_data_clk    (data_clk       ),
+    .tx_data_clk_rst(data_clk_rst   ),
+
+    .tx_data_i      (tx_data_i      ),
+    .tx_data_q      (tx_data_q      ),
+
+    .clk_out        (clk_out        ),
+    .tx_frame       (tx_frame       ),
+    .tx_data        (tx_data        )
+);
+
+ad9361_rx_map_cmos_single dut_rx
+(
+    .clk_in         (clk_in         ),
+    .clk_in_rst     (clk_in_rst     ),
+
+    .rx_data_clk    (data_clk       ),
+    .rx_data_clk_rst(data_clk_rst   ),
+
+    .rx_fifo_rst    (1'b0           ),
+
+    .rx_frame       (tx_frame       ),
+    .rx_data        (tx_data        ),
+
+    .rx_data_i      (rx_data_i      ),
+    .rx_data_q      (rx_data_q      )
+);
+
+initial begin
+    clk_in_rst = 1'b1;
+    data_clk_rst = 1'b1;
+    #102
+    clk_in_rst = 'b0;
+    #333
+    data_clk_rst = 'b0;
+end
+
+always #20 clk_in = ~clk_in;
+assign #7 data_clk = clk_in;
+
+always @(posedge data_clk) begin
+    if (data_clk_rst) begin
+        tx_data_i <= 'b0;
+        tx_data_q <= 'b0;
+    end
+    else begin
+        tx_data_i <= tx_data_i + 2'd1;
+        tx_data_q <= tx_data_q + 2'd2;
+    end
+end
+
+endmodule

modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sim_1/new/tb_ad9361_trx_lvds_dual.v

@@ -0,0 +1,123 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 09/27/2024 05:23:01 PM
+// Design Name:
+// Module Name: tb_ad9361_trx_lvds_dual
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module tb_ad9361_trx_lvds_dual;
+
+reg clk_4x_in = 'b0;
+reg clk_in_rst = 'b0;
+reg data_clk = 'b0;
+reg data_clk_rst = 'b0;
+reg [11:0] tx_ch1_i = 'b0;
+reg [11:0] tx_ch1_q = 'b0;
+reg [11:0] tx_ch2_i = 'b0;
+reg [11:0] tx_ch2_q = 'b0;
+wire [11:0] rx_ch1_i;
+wire [11:0] rx_ch1_q;
+wire [11:0] rx_ch2_i;
+wire [11:0] rx_ch2_q;
+
+wire clk_out_p;
+wire clk_out_n;
+wire tx_frame_p;
+wire tx_frame_n;
+wire [5:0] tx_data_p;
+wire [5:0] tx_data_n;
+
+ad9361_tx_map_lvds_dual dut_tx
+(
+    .clk_4x_in      (clk_4x_in      ),
+    .clk_in_rst     (clk_in_rst     ),
+
+    .tx_data_clk    (data_clk       ),
+    .tx_data_clk_rst(data_clk_rst   ),
+
+    .tx_ch1_i       (tx_ch1_i       ),
+    .tx_ch1_q       (tx_ch1_q       ),
+    .tx_ch2_i       (tx_ch2_i       ),
+    .tx_ch2_q       (tx_ch2_q       ),
+
+    .clk_out_p      (clk_out_p      ),
+    .clk_out_n      (clk_out_n      ),
+    .tx_frame_p     (tx_frame_p     ),
+    .tx_frame_n     (tx_frame_n     ),
+    .tx_data_p      (tx_data_p      ),
+    .tx_data_n      (tx_data_n      )
+);
+
+ad9361_rx_map_lvds_dual dut_rx
+(
+    .clk_4x_in      (clk_4x_in      ),
+    .clk_in_rst     (clk_in_rst     ),
+
+    .rx_data_clk    (data_clk       ),
+    .rx_data_clk_rst(data_clk_rst   ),
+
+    .rx_fifo_rst    (1'b0           ),
+
+    .rx_frame_p     (tx_frame_p     ),
+    .rx_frame_n     (tx_frame_n     ),
+    .rx_data_p      (tx_data_p      ),
+    .rx_data_n      (tx_data_n      ),
+
+    .rx_ch1_i       (rx_ch1_i       ),
+    .rx_ch1_q       (rx_ch1_q       ),
+    .rx_ch2_i       (rx_ch2_i       ),
+    .rx_ch2_q       (rx_ch2_q       )
+);
+
+initial begin
+    clk_in_rst = 1'b1;
+    data_clk_rst = 1'b1;
+    #102
+    clk_in_rst = 'b0;
+    #333
+    data_clk_rst = 'b0;
+end
+
+reg clk_2x_in = 'b0;
+
+always #40 clk_4x_in = ~clk_4x_in;
+
+always @(posedge clk_4x_in) begin
+    clk_2x_in <= ~clk_2x_in;
+end
+
+always @(posedge clk_2x_in) begin
+    #7 data_clk <= ~data_clk;
+end
+
+always @(posedge data_clk) begin
+    if (data_clk_rst) begin
+        tx_ch1_i <= 'b0;
+        tx_ch1_q <= 'b0;
+        tx_ch2_i <= 'b0;
+        tx_ch2_q <= 'b0;
+    end
+    else begin
+        tx_ch1_i <= tx_ch1_i + 3'd1;
+        tx_ch1_q <= tx_ch1_q + 3'd2;
+        tx_ch2_i <= tx_ch2_i + 3'd3;
+        tx_ch2_q <= tx_ch2_q + 3'd4;
+    end
+end
+
+endmodule

modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sim_1/new/tb_ad9361_trx_lvds_single.v

@@ -0,0 +1,105 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 09/27/2024 03:43:52 PM
+// Design Name:
+// Module Name: tb_ad9361_trx_lvds_single
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module tb_ad9361_trx_lvds_single;
+
+reg clk_2x_in = 'b0;
+reg clk_in_rst = 'b0;
+reg data_clk = 'b0;
+reg data_clk_rst = 'b0;
+reg [11:0] tx_data_i = 'b0;
+reg [11:0] tx_data_q = 'b0;
+wire [11:0] rx_data_i;
+wire [11:0] rx_data_q;
+
+wire clk_out_p;
+wire clk_out_n;
+wire tx_frame_p;
+wire tx_frame_n;
+wire [5:0] tx_data_p;
+wire [5:0] tx_data_n;
+
+ad9361_tx_map_lvds_single dut_tx
+(
+    .clk_2x_in      (clk_2x_in      ),
+    .clk_in_rst     (clk_in_rst     ),
+
+    .tx_data_clk    (data_clk       ),
+    .tx_data_clk_rst(data_clk_rst   ),
+
+    .tx_data_i      (tx_data_i      ),
+    .tx_data_q      (tx_data_q      ),
+
+    .clk_out_p      (clk_out_p      ),
+    .clk_out_n      (clk_out_n      ),
+    .tx_frame_p     (tx_frame_p     ),
+    .tx_frame_n     (tx_frame_n     ),
+    .tx_data_p      (tx_data_p      ),
+    .tx_data_n      (tx_data_n      )
+);
+
+ad9361_rx_map_lvds_single dut_rx
+(
+    .clk_2x_in      (clk_2x_in      ),
+    .clk_in_rst     (clk_in_rst     ),
+
+    .rx_data_clk    (data_clk       ),
+    .rx_data_clk_rst(data_clk_rst   ),
+
+    .rx_fifo_rst    (1'b0           ),
+
+    .rx_frame_p     (tx_frame_p     ),
+    .rx_frame_n     (tx_frame_n     ),
+    .rx_data_p      (tx_data_p      ),
+    .rx_data_n      (tx_data_n      ),
+
+    .rx_data_i      (rx_data_i      ),
+    .rx_data_q      (rx_data_q      )
+);
+
+initial begin
+    clk_in_rst = 1'b1;
+    data_clk_rst = 1'b1;
+    #102
+    clk_in_rst = 'b0;
+    #333
+    data_clk_rst = 'b0;
+end
+
+always #20 clk_2x_in = ~clk_2x_in;
+
+always @(posedge clk_2x_in) begin
+    #7 data_clk <= ~data_clk;
+end
+
+always @(posedge data_clk) begin
+    if (data_clk_rst) begin
+        tx_data_i <= 'b0;
+        tx_data_q <= 'b0;
+    end
+    else begin
+        tx_data_i <= tx_data_i + 2'd1;
+        tx_data_q <= tx_data_q + 2'd2;
+    end
+end
+
+endmodule

modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_cmos_dual.v

@@ -45,13 +45,14 @@ module ad9361_rx_map_cmos_dual
     output  [11:0]  rx_ch2_q
 );
 
-genvar          m;
+genvar mm;
 
 // rx data
-wire [11:0] rx_data_i, rx_data_q;
+wire [11:0] rx_data_pos;
+wire [11:0] rx_data_neg;
 
 generate
-for (m=0; m<12; m=m+1) begin : rx_data_iddr
+for (mm = 0; mm < 12; mm = mm + 1) begin
 
 IDDR #(
     .DDR_CLK_EDGE   ("SAME_EDGE"    ),
@@ -63,17 +64,17 @@ IDDR #(
     .R              (1'b0           ),
     .S              (1'b0           ),
     .C              (clk_2x_in      ),
-    .D              (rx_data[m]     ),
+    .D              (rx_data[mm]    ),
-    .Q1             (rx_data_q[m]   ),
+    .Q1             (rx_data_pos[mm]),
-    .Q2             (rx_data_i[m]   )
+    .Q2             (rx_data_neg[mm])
 );
 
 end
 endgenerate
 
 // rx frame
-wire        rx_frame_i;
+wire rx_frame_pos;
-wire        rx_frame_q;
+wire rx_frame_neg;
 
 IDDR #(
     .DDR_CLK_EDGE   ("SAME_EDGE"    ),
@@ -86,8 +87,8 @@ IDDR #(
     .S              (1'b0           ),
     .C              (clk_2x_in      ),
     .D              (rx_frame       ),
-    .Q1             (rx_frame_q     ),
+    .Q1             (rx_frame_pos   ),
-    .Q2             (rx_frame_i     )
+    .Q2             (rx_frame_neg   )
 );
 
 // divide rx_data to dual channel
@@ -96,7 +97,7 @@ reg     [11:0]  rx1_data_q = 'b0;
 reg [11:0] rx2_data_i = 'b0;
 reg [11:0] rx2_data_q = 'b0;
 
-wire            rx_fifo_wr_en;
+reg rx_fifo_wr_en = 'b0;
 reg rx_fifo_rd_en = 'b0;
 
 wire rx_fifo_empty_1;
@@ -104,31 +105,34 @@ wire            rx_fifo_empty_2;
 wire rx_fifo_empty_3;
 wire rx_fifo_empty_4;
 
-assign rx_fifo_wr_en = rx_frame_i; // align data & write enable
-
 always @ (posedge clk_2x_in) begin
     if (clk_in_rst) begin
         rx1_data_i <= 'b0;
-        rx2_data_i <= 'b0;
-    end
-    else if(rx_frame_i) begin
-        rx1_data_i <= rx_data_i;
-    end
-    else begin
-        rx2_data_i <= rx_data_i;
-    end
-end
-
-always @ (posedge clk_2x_in) begin
-    if (clk_in_rst) begin
         rx1_data_q <= 'b0;
+        rx2_data_i <= 'b0;
         rx2_data_q <= 'b0;
+        rx_fifo_wr_en <= 'b0;
     end
-    else if(rx_frame_q) begin
+    else if({rx_frame_neg,rx_frame_pos} == 2'b11) begin
-        rx1_data_q <= rx_data_q;
+        rx1_data_i <= rx_data_neg;
+        rx1_data_q <= rx_data_pos;
+        rx2_data_i <= rx2_data_i;
+        rx2_data_q <= rx2_data_q;
+        rx_fifo_wr_en <= 'b0;
+    end
+    else if({rx_frame_neg,rx_frame_pos} == 2'b00) begin
+        rx1_data_i <= rx1_data_i;
+        rx1_data_q <= rx1_data_q;
+        rx2_data_i <= rx_data_neg;
+        rx2_data_q <= rx_data_pos;
+        rx_fifo_wr_en <= 'b1;
     end
     else begin
-        rx2_data_q <= rx_data_q;
+        rx1_data_i <= 'd1234; // error
+        rx1_data_q <= 'd4321; // error
+        rx2_data_i <= 'd5678; // error
+        rx2_data_q <= 'd8765; // error
+        rx_fifo_wr_en <= 'b0;
     end
 end
 
@@ -143,7 +147,7 @@ end
 
 ad9361_fifo u_rx_fifo_ch1_i
 (
-    .rst        (rx_fifo_rst    ), // input wire rst
+    .rst        (clk_in_rst || rx_fifo_rst  ), // input wire rst
     .wr_clk     (clk_2x_in                  ), // input wire wr_clk
     .rd_clk     (rx_data_clk                ), // input wire rd_clk
     .din        (rx1_data_i                 ), // input wire [11 : 0] din
@@ -151,12 +155,12 @@ ad9361_fifo u_rx_fifo_ch1_i
     .rd_en      (rx_fifo_rd_en              ), // input wire rd_en
     .dout       (rx_ch1_i                   ), // output wire [11 : 0] dout
     .full       (                           ), // output wire full
-    .empty      (rx_fifo_empty_1)  // output wire empty
+    .empty      (rx_fifo_empty_1            )  // output wire empty
 );
 
 ad9361_fifo u_rx_fifo_ch1_q
 (
-    .rst        (rx_fifo_rst    ), // input wire rst
+    .rst        (clk_in_rst || rx_fifo_rst  ), // input wire rst
     .wr_clk     (clk_2x_in                  ), // input wire wr_clk
     .rd_clk     (rx_data_clk                ), // input wire rd_clk
     .din        (rx1_data_q                 ), // input wire [11 : 0] din
@@ -164,12 +168,12 @@ ad9361_fifo u_rx_fifo_ch1_q
     .rd_en      (rx_fifo_rd_en              ), // input wire rd_en
     .dout       (rx_ch1_q                   ), // output wire [11 : 0] dout
     .full       (                           ), // output wire full
-    .empty      (rx_fifo_empty_2)  // output wire empty
+    .empty      (rx_fifo_empty_2            )  // output wire empty
 );
 
 ad9361_fifo u_rx_fifo_ch2_i
 (
-    .rst        (rx_fifo_rst    ), // input wire rst
+    .rst        (clk_in_rst || rx_fifo_rst  ), // input wire rst
     .wr_clk     (clk_2x_in                  ), // input wire wr_clk
     .rd_clk     (rx_data_clk                ), // input wire rd_clk
     .din        (rx2_data_i                 ), // input wire [11 : 0] din
@@ -177,12 +181,12 @@ ad9361_fifo u_rx_fifo_ch2_i
     .rd_en      (rx_fifo_rd_en              ), // input wire rd_en
     .dout       (rx_ch2_i                   ), // output wire [11 : 0] dout
     .full       (                           ), // output wire full
-    .empty      (rx_fifo_empty_3)  // output wire empty
+    .empty      (rx_fifo_empty_3            )  // output wire empty
 );
 
 ad9361_fifo u_rx_fifo_ch2_q
 (
-    .rst        (rx_fifo_rst    ), // input wire rst
+    .rst        (clk_in_rst || rx_fifo_rst  ), // input wire rst
     .wr_clk     (clk_2x_in                  ), // input wire wr_clk
     .rd_clk     (rx_data_clk                ), // input wire rd_clk
     .din        (rx2_data_q                 ), // input wire [11 : 0] din
@@ -190,7 +194,7 @@ ad9361_fifo u_rx_fifo_ch2_q
     .rd_en      (rx_fifo_rd_en              ), // input wire rd_en
     .dout       (rx_ch2_q                   ), // output wire [11 : 0] dout
     .full       (                           ), // output wire full
-    .empty      (rx_fifo_empty_4)  // output wire empty
+    .empty      (rx_fifo_empty_4            )  // output wire empty
 );
 
 endmodule

modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_cmos_single.v

@@ -43,32 +43,71 @@ module ad9361_rx_map_cmos_single
     output  [11:0]  rx_data_q
 );
 
-genvar          m;
+genvar mm;
 
-// rx data
+// rx data from port
-wire [11:0] rx_raw_i, rx_raw_q;
+wire [11:0] rx_data_pos;
+wire [11:0] rx_data_neg;
 
 generate
-for (m=0; m<12; m=m+1) begin : rx_data_iddr
+for (mm = 0; mm < 12; mm = mm + 1) begin : rx_data_iddr
-
 IDDR #(
-    .DDR_CLK_EDGE   ("SAME_EDGE"    ),
+    .DDR_CLK_EDGE   ("SAME_EDGE"    ), // "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED"
-    .INIT_Q1        (1'b0           ),
+    .INIT_Q1        (1'b0           ), // Initial value of Q1: 1'b0 or 1'b1
-    .INIT_Q2        (1'b0           ),
+    .INIT_Q2        (1'b0           ), // Initial value of Q2: 1'b0 or 1'b1
-    .SRTYPE         ("ASYNC"        )
+    .SRTYPE         ("ASYNC"        )  // Set/Reset type: "SYNC" or "ASYNC"
 ) i_rx_data_iddr (
-    .CE             (1'b1           ),
+    .CE             (1'b1           ), // 1-bit clock enable input
-    .R              (1'b0           ),
+    .R              (1'b0           ), // 1-bit reset
-    .S              (1'b0           ),
+    .S              (1'b0           ), // 1-bit set
-    .C              (clk_in         ),
+    .C              (clk_in         ), // 1-bit clock input
-    .D              (rx_data[m]     ),
+    .D              (rx_data[mm]    ), // 1-bit DDR data input
-    .Q1             (rx_raw_q[m]    ),
+    .Q1             (rx_data_pos[mm]), // 1-bit output for positive edge of clock
-    .Q2             (rx_raw_i[m]    )
+    .Q2             (rx_data_neg[mm])  // 1-bit output for negative edge of clock
 );
 
 end
 endgenerate
 
+// rx frame from port
+wire rx_frame_pos;
+wire rx_frame_neg;
+
+IDDR #(
+    .DDR_CLK_EDGE   ("SAME_EDGE"    ), // "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED"
+    .INIT_Q1        (1'b0           ), // Initial value of Q1: 1'b0 or 1'b1
+    .INIT_Q2        (1'b0           ), // Initial value of Q2: 1'b0 or 1'b1
+    .SRTYPE         ("ASYNC"        )  // Set/Reset type: "SYNC" or "ASYNC"
+) i_rx_frame_iddr (
+    .CE             (1'b1           ), // 1-bit clock enable input
+    .R              (1'b0           ), // 1-bit reset
+    .S              (1'b0           ), // 1-bit set
+    .C              (clk_in         ), // 1-bit clock input
+    .D              (rx_frame       ), // 1-bit DDR data input
+    .Q1             (rx_frame_pos   ), // 1-bit output for positive edge of clock
+    .Q2             (rx_frame_neg   )  // 1-bit output for negative edge of clock
+);
+
+// rx data
+reg [11:0] rx_fifo_i = 'b0;
+reg [11:0] rx_fifo_q = 'b0;
+
+always @(posedge clk_in) begin
+    if (clk_in_rst) begin
+        rx_fifo_i <= 'b0;
+        rx_fifo_q <= 'b0;
+    end
+    else begin
+        if ({rx_frame_neg,rx_frame_pos} == 2'b10) begin
+            rx_fifo_i <= rx_data_neg;
+            rx_fifo_q <= rx_data_pos;
+        end
+        else begin
+            rx_fifo_i <= 'd1234; // error
+            rx_fifo_q <= 'd4321; // error
+        end
+    end
+end
 
 // divide rx_data to dual channel
 reg             rx_fifo_wr_en = 1'b0;
@@ -97,28 +136,28 @@ end
 
 ad9361_fifo u_rx_fifo_i
 (
-    .rst        (rx_fifo_rst    ), // input wire rst
+    .rst        (clk_in_rst || rx_fifo_rst  ), // input wire rst
     .wr_clk     (clk_in                     ), // input wire wr_clk
     .rd_clk     (rx_data_clk                ), // input wire rd_clk
-    .din        (rx_raw_i       ), // input wire [11 : 0] din
+    .din        (rx_fifo_i                  ), // input wire [11 : 0] din
     .wr_en      (rx_fifo_wr_en              ), // input wire wr_en
     .rd_en      (rx_fifo_rd_en              ), // input wire rd_en
     .dout       (rx_data_i                  ), // output wire [11 : 0] dout
     .full       (                           ), // output wire full
-    .empty      (rx_fifo_empty_1)  // output wire empty
+    .empty      (rx_fifo_empty_1            )  // output wire empty
 );
 
 ad9361_fifo u_rx_fifo_q
 (
-    .rst        (rx_fifo_rst    ), // input wire rst
+    .rst        (clk_in_rst || rx_fifo_rst  ), // input wire rst
     .wr_clk     (clk_in                     ), // input wire wr_clk
     .rd_clk     (rx_data_clk                ), // input wire rd_clk
-    .din        (rx_raw_q       ), // input wire [11 : 0] din
+    .din        (rx_fifo_q                  ), // input wire [11 : 0] din
     .wr_en      (rx_fifo_wr_en              ), // input wire wr_en
     .rd_en      (rx_fifo_rd_en              ), // input wire rd_en
     .dout       (rx_data_q                  ), // output wire [11 : 0] dout
     .full       (                           ), // output wire full
-    .empty      (rx_fifo_empty_2)  // output wire empty
+    .empty      (rx_fifo_empty_2            )  // output wire empty
 );
 
 endmodule

modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_lvds_dual.v

@@ -8,10 +8,9 @@
 // | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
 //  \___/ \___/|___/_| |_|  \____|\__,_|\___/
 //
-// Create Date: 2022/07/01 17:37:27
+// Create Date: 09/27/2024 04:49:13 PM
-// Last Modified Date: 2023/03/06 10:54
 // Design Name:
-// Module Name: ad9361_rx_mapping_dual
+// Module Name: ad9361_rx_map_lvds_dual
 // Project Name:
 // Target Devices:
 // Tool Versions:
@@ -47,155 +46,84 @@ module ad9361_rx_map_lvds_dual
     output  [11:0]  rx_ch2_q
 );
 
-genvar          m;
+genvar mm;
 
-// rx data
+// rx data from port
 wire [5:0] rx_data;
-wire [5:0] rx_data_i, rx_data_q;
+wire [5:0] rx_data_pos;
+wire [5:0] rx_data_neg;
 
 generate
-for (m=0; m<6; m=m+1) begin : rx_data_iddr
+for (mm = 0; mm < 6; mm = mm + 1) begin
 
 IBUFDS #(
-    .DIFF_TERM  ("TRUE"         )
+    .DIFF_TERM  ("TRUE"         )  // Differential Termination
-) u_ibufds_rx_data
+) u_rx_data_ibufds
 (
-    .I          (rx_data_p[m]   ),
+    .I          (rx_data_p[mm]  ), // Diff_p buffer input (connect directly to top-level port)
-    .IB         (rx_data_n[m]   ),
+    .IB         (rx_data_n[mm]  ), // Diff_n buffer input (connect directly to top-level port)
-    .O          (rx_data[m]     )
+    .O          (rx_data[mm]    )  // Buffer output
 );
 
 IDDR #(
-    .DDR_CLK_EDGE   ("SAME_EDGE"    ),
+    .DDR_CLK_EDGE   ("SAME_EDGE"    ), // "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED"
-    .INIT_Q1        (1'b0           ),
+    .INIT_Q1        (1'b0           ), // Initial value of Q1: 1'b0 or 1'b1
-    .INIT_Q2        (1'b0           ),
+    .INIT_Q2        (1'b0           ), // Initial value of Q2: 1'b0 or 1'b1
-    .SRTYPE         ("ASYNC"        )
+    .SRTYPE         ("ASYNC"        )  // Set/Reset type: "SYNC" or "ASYNC"
-) u_rx_data_iddr (
+) i_rx_data_iddr (
-    .CE             (1'b1           ), // clock enable
+    .CE             (1'b1           ), // 1-bit clock enable input
-    .R              (1'b0           ), // iddr reset
+    .R              (1'b0           ), // 1-bit reset
-    .S              (1'b0           ), // iddr set
+    .S              (1'b0           ), // 1-bit set
-    .C              (clk_4x_in      ), // iddr clock
+    .C              (clk_4x_in      ), // 1-bit clock input
-    .D              (rx_data[m]     ), // ddr data
+    .D              (rx_data[mm]    ), // 1-bit DDR data input
-    .Q1             (rx_data_q[m]   ), // sdr data at rising edge
+    .Q1             (rx_data_pos[mm]), // 1-bit output for positive edge of clock
-    .Q2             (rx_data_i[m]   )  // sdr data at falling edge
+    .Q2             (rx_data_neg[mm])  // 1-bit output for negative edge of clock
 );
 
 end
 endgenerate
 
-// rx frame
+// rx frame from port
 wire rx_frame;
-wire            rx_frame_i;
+wire rx_frame_pos;
-wire            rx_frame_q;
+wire rx_frame_neg;
 
 IBUFDS #(
-    .DIFF_TERM  ("TRUE"     )
+    .DIFF_TERM  ("TRUE"     )  // Differential Termination
-) u_ibufds_rx_frame
+) u_rx_frame_ibufds
 (
-    .I          (rx_frame_p ),
+    .I          (rx_frame_p ), // Diff_p buffer input (connect directly to top-level port)
-    .IB         (rx_frame_n ),
+    .IB         (rx_frame_n ), // Diff_n buffer input (connect directly to top-level port)
-    .O          (rx_frame   )
+    .O          (rx_frame   )  // Buffer output
 );
 
 IDDR #(
-    .DDR_CLK_EDGE   ("SAME_EDGE"    ),
+    .DDR_CLK_EDGE   ("SAME_EDGE"    ), // "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED"
-    .INIT_Q1        (1'b0           ),
+    .INIT_Q1        (1'b0           ), // Initial value of Q1: 1'b0 or 1'b1
-    .INIT_Q2        (1'b0           ),
+    .INIT_Q2        (1'b0           ), // Initial value of Q2: 1'b0 or 1'b1
-    .SRTYPE         ("ASYNC"        )
+    .SRTYPE         ("ASYNC"        )  // Set/Reset type: "SYNC" or "ASYNC"
-) u_rx_frame_iddr (
+) i_rx_frame_iddr (
-    .CE             (1'b1           ), // clock enable
+    .CE             (1'b1           ), // 1-bit clock enable input
-    .R              (1'b0           ), // iddr reset
+    .R              (1'b0           ), // 1-bit reset
-    .S              (1'b0           ), // iddr set
+    .S              (1'b0           ), // 1-bit set
-    .C              (clk_4x_in      ), // iddr clock
+    .C              (clk_4x_in      ), // 1-bit clock input
-    .D              (rx_frame       ), // ddr data
+    .D              (rx_frame       ), // 1-bit DDR data input
-    .Q1             (rx_frame_q     ), // sdr data at rising edge
+    .Q1             (rx_frame_pos   ), // 1-bit output for positive edge of clock
-    .Q2             (rx_frame_i     )  // sdr data at falling edge
+    .Q2             (rx_frame_neg   )  // 1-bit output for negative edge of clock
 );
 
 // unpack rx frame & data
-reg             rx_frame_i_d1   = 'b0;
+reg rx_frame_pos_d = 'b0;
-reg     [ 5:0]  rx_data_i_d1    = 'b0;
+reg rx_frame_neg_d = 'b0;
-reg     [ 5:0]  rx_data_q_d1    = 'b0;
-reg             rx_flag         = 'b0; // rx frame rising edge indicator
-reg     [ 1:0]  rx_cnt          = 'b0; // unpack stage counter
 
-always @(posedge clk_4x_in) begin
+reg [11:0] rx_fifo_ch1_i = 'b0;
-    // wait for [rx_flag]
+reg [11:0] rx_fifo_ch1_q = 'b0;
-    rx_frame_i_d1 <= rx_frame_i;
+reg [11:0] rx_fifo_ch2_i = 'b0;
-     rx_data_i_d1 <=  rx_data_i;
+reg [11:0] rx_fifo_ch2_q = 'b0;
-     rx_data_q_d1 <=  rx_data_q;
-end
 
-always @(posedge clk_4x_in) begin
+reg rx_fifo_wr_en = 'b0;
-    if (clk_in_rst) begin
+reg rx_fifo_rd_en = 'b0;
-        rx_flag <= 'b0;
-    end
-    else if (~rx_frame_i_d1 & rx_frame_i) begin
-        // assert when rising edge of rx frame is detected
-        rx_flag <= 'b1;
-    end
-    else begin
-        rx_flag <= rx_flag;
-    end
-end
 
-always @(posedge clk_4x_in) begin
-    if (clk_in_rst) begin
-        rx_cnt <= 'b0;
-    end
-    else begin
-        rx_cnt <= (rx_flag) ? rx_cnt + 1'b1 : rx_cnt;
-    end
-end
-
-reg     [11:0]  rx1_data_i = 'b0;
-reg     [11:0]  rx1_data_q = 'b0;
-reg     [11:0]  rx2_data_i = 'b0;
-reg     [11:0]  rx2_data_q = 'b0;
-
-always @(posedge clk_4x_in) begin
-    if (clk_in_rst) begin
-        rx1_data_i <= 'b0;
-        rx1_data_q <= 'b0;
-        rx2_data_i <= 'b0;
-        rx2_data_q <= 'b0;
-    end
-    else begin
-        case (rx_cnt)
-            3'd0: begin
-                // 1st clock cycle: upper 6-bit of rx ch1 inphase/quadrature data
-                rx1_data_i[11:6] <= rx_data_i_d1;
-                rx1_data_q[11:6] <= rx_data_q_d1;
-            end
-            3'd1: begin
-                // 2nd clock cycle: lower 6-bit of rx ch1 inphase/quadrature data
-                rx1_data_i[ 5:0] <= rx_data_i_d1;
-                rx1_data_q[ 5:0] <= rx_data_q_d1;
-            end
-            3'd2: begin
-                // 3rd clock cycle: upper 6-bit of rx ch2 inphase/quadrature data
-                rx2_data_i[11:6] <= rx_data_i_d1;
-                rx2_data_q[11:6] <= rx_data_q_d1;
-            end
-            3'd3: begin
-                // 4th clock cycle: lower 6-bit of rx ch2 inphase/quadrature data
-                rx2_data_i[ 5:0] <= rx_data_i_d1;
-                rx2_data_q[ 5:0] <= rx_data_q_d1;
-            end
-            default: begin
-                rx1_data_i <= 'b0;
-                rx1_data_q <= 'b0;
-                rx2_data_i <= 'b0;
-                rx2_data_q <= 'b0;
-            end
-        endcase
-    end
-end
-
-// write fifo when rx1/2_data_i/q are all prepared with 192MHz clock
-// read fifo at every clock cycle with 48MHz clock
-reg fifo_wr_en = 'b0;
-reg fifo_rd_en = 'b0;
 wire rx_fifo_empty_1;
 wire rx_fifo_empty_2;
 wire rx_fifo_empty_3;
@@ -203,75 +131,122 @@ wire rx_fifo_empty_4;
 
 always @(posedge clk_4x_in) begin
     if (clk_in_rst) begin
-        fifo_wr_en <= 'b0;
+        rx_frame_pos_d <= 'b0;
-    end
+        rx_frame_neg_d <= 'b0;
-    else if (rx_cnt == 2'd3) begin
-        fifo_wr_en <= 1'b1;
     end
     else begin
-        fifo_wr_en <= 'b0;
+        rx_frame_pos_d <= rx_frame_pos;
+        rx_frame_neg_d <= rx_frame_neg;
     end
 end
 
-always @(posedge rx_data_clk) begin
+always @(posedge clk_4x_in) begin
-    if (rx_data_clk_rst) begin
+    if (clk_in_rst) begin
-        fifo_rd_en <= 1'b0;
+        rx_fifo_ch1_i <= 'b0;
+        rx_fifo_ch1_q <= 'b0;
+        rx_fifo_ch2_i <= 'b0;
+        rx_fifo_ch2_q <= 'b0;
+        rx_fifo_wr_en <= 'b0;
     end
     else begin
-        fifo_rd_en <= &{~rx_fifo_empty_1, ~rx_fifo_empty_2, ~rx_fifo_empty_3, ~rx_fifo_empty_4};
+        case ({rx_frame_neg_d,rx_frame_pos_d,rx_frame_neg,rx_frame_pos})
+            4'b0011: begin
+                rx_fifo_ch1_i[11:6] <= rx_data_neg;
+                rx_fifo_ch1_q[11:6] <= rx_data_pos;
+                rx_fifo_ch2_i <= rx_fifo_ch2_i;
+                rx_fifo_ch2_q <= rx_fifo_ch2_q;
+                rx_fifo_wr_en <= 'b0;
+            end
+            4'b1111: begin
+                rx_fifo_ch1_i[5:0] <= rx_data_neg;
+                rx_fifo_ch1_q[5:0] <= rx_data_pos;
+                rx_fifo_ch2_i <= rx_fifo_ch2_i;
+                rx_fifo_ch2_q <= rx_fifo_ch2_q;
+                rx_fifo_wr_en <= 'b0;
+            end
+            4'b1100: begin
+                rx_fifo_ch1_i <= rx_fifo_ch1_i;
+                rx_fifo_ch1_q <= rx_fifo_ch1_q;
+                rx_fifo_ch2_i[11:6] <= rx_data_neg;
+                rx_fifo_ch2_q[11:6] <= rx_data_pos;
+                rx_fifo_wr_en <= 'b0;
+            end
+            4'b0000: begin
+                rx_fifo_ch1_i <= rx_fifo_ch1_i;
+                rx_fifo_ch1_q <= rx_fifo_ch1_q;
+                rx_fifo_ch2_i[5:0] <= rx_data_neg;
+                rx_fifo_ch2_q[5:0] <= rx_data_pos;
+                rx_fifo_wr_en <= 1'b1;
+            end
+            default: begin
+                rx_fifo_ch1_i <= 'd1234; // error
+                rx_fifo_ch1_q <= 'd4321; // error
+                rx_fifo_ch2_i <= 'd5678; // error
+                rx_fifo_ch2_q <= 'd8765; // error
+                rx_fifo_wr_en <= 'b0;
+            end
+        endcase
+    end
+end
+always @(posedge rx_data_clk) begin
+    if (rx_data_clk_rst) begin
+        rx_fifo_rd_en <= 'b0;
+    end
+    else begin
+        rx_fifo_rd_en <= &{~rx_fifo_empty_1, ~rx_fifo_empty_2,~rx_fifo_empty_3, ~rx_fifo_empty_4};
     end
 end
 
 ad9361_fifo u_rx_fifo_ch1_i
 (
-    .rst        (rx_fifo_rst    ), // input wire rst
+    .rst        (clk_in_rst || rx_fifo_rst  ), // input wire rst
     .wr_clk     (clk_4x_in                  ), // input wire wr_clk
     .rd_clk     (rx_data_clk                ), // input wire rd_clk
-    .din        (rx1_data_i     ), // input wire [11 : 0] din
+    .din        (rx_fifo_ch1_i              ), // input wire [11 : 0] din
-    .wr_en      (fifo_wr_en     ), // input wire wr_en
+    .wr_en      (rx_fifo_wr_en              ), // input wire wr_en
-    .rd_en      (fifo_rd_en     ), // input wire rd_en
+    .rd_en      (rx_fifo_rd_en              ), // input wire rd_en
     .dout       (rx_ch1_i                   ), // output wire [11 : 0] dout
     .full       (                           ), // output wire full
-    .empty      (rx_fifo_empty_1)  // output wire empty
+    .empty      (rx_fifo_empty_1            )  // output wire empty
 );
 
 ad9361_fifo u_rx_fifo_ch1_q
 (
-    .rst        (rx_fifo_rst    ), // input wire rst
+    .rst        (clk_in_rst || rx_fifo_rst  ), // input wire rst
     .wr_clk     (clk_4x_in                  ), // input wire wr_clk
     .rd_clk     (rx_data_clk                ), // input wire rd_clk
-    .din        (rx1_data_q     ), // input wire [11 : 0] din
+    .din        (rx_fifo_ch1_q              ), // input wire [11 : 0] din
-    .wr_en      (fifo_wr_en     ), // input wire wr_en
+    .wr_en      (rx_fifo_wr_en              ), // input wire wr_en
-    .rd_en      (fifo_rd_en     ), // input wire rd_en
+    .rd_en      (rx_fifo_rd_en              ), // input wire rd_en
     .dout       (rx_ch1_q                   ), // output wire [11 : 0] dout
     .full       (                           ), // output wire full
-    .empty      (rx_fifo_empty_2)  // output wire empty
+    .empty      (rx_fifo_empty_2            )  // output wire empty
 );
 
 ad9361_fifo u_rx_fifo_ch2_i
 (
-    .rst        (rx_fifo_rst    ), // input wire rst
+    .rst        (clk_in_rst || rx_fifo_rst  ), // input wire rst
     .wr_clk     (clk_4x_in                  ), // input wire wr_clk
     .rd_clk     (rx_data_clk                ), // input wire rd_clk
-    .din        (rx2_data_i     ), // input wire [11 : 0] din
+    .din        (rx_fifo_ch2_i              ), // input wire [11 : 0] din
-    .wr_en      (fifo_wr_en     ), // input wire wr_en
+    .wr_en      (rx_fifo_wr_en              ), // input wire wr_en
-    .rd_en      (fifo_rd_en     ), // input wire rd_en
+    .rd_en      (rx_fifo_rd_en              ), // input wire rd_en
     .dout       (rx_ch2_i                   ), // output wire [11 : 0] dout
     .full       (                           ), // output wire full
-    .empty      (rx_fifo_empty_3)  // output wire empty
+    .empty      (rx_fifo_empty_3            )  // output wire empty
 );
 
 ad9361_fifo u_rx_fifo_ch2_q
 (
-    .rst        (rx_fifo_rst    ), // input wire rst
+    .rst        (clk_in_rst || rx_fifo_rst  ), // input wire rst
     .wr_clk     (clk_4x_in                  ), // input wire wr_clk
     .rd_clk     (rx_data_clk                ), // input wire rd_clk
-    .din        (rx2_data_q     ), // input wire [11 : 0] din
+    .din        (rx_fifo_ch2_q              ), // input wire [11 : 0] din
-    .wr_en      (fifo_wr_en     ), // input wire wr_en
+    .wr_en      (rx_fifo_wr_en              ), // input wire wr_en
-    .rd_en      (fifo_rd_en     ), // input wire rd_en
+    .rd_en      (rx_fifo_rd_en              ), // input wire rd_en
     .dout       (rx_ch2_q                   ), // output wire [11 : 0] dout
     .full       (                           ), // output wire full
-    .empty      (rx_fifo_empty_4)  // output wire empty
+    .empty      (rx_fifo_empty_4            )  // output wire empty
 );
 
 endmodule

modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_lvds_single.v

@@ -0,0 +1,182 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//      _           _        ____
+//     | | ___  ___| |__    / ___| __ _  ___
+//  _  | |/ _ \/ __| '_ \  | |  _ / _` |/ _ \
+// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
+//  \___/ \___/|___/_| |_|  \____|\__,_|\___/
+//
+// Create Date: 2022/07/01 17:37:27
+// Last Modified Date: 2023/03/03 13:01
+// Design Name:
+// Module Name: ad9361_rx_map_lvds_single
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module ad9361_rx_map_lvds_single
+(
+    input           clk_2x_in       ,
+    input           clk_in_rst      ,
+
+    input           rx_data_clk     ,
+    input           rx_data_clk_rst ,
+
+    input           rx_fifo_rst     ,
+
+    input           rx_frame_p      ,
+    input           rx_frame_n      ,
+    input   [ 5:0]  rx_data_p       ,
+    input   [ 5:0]  rx_data_n       ,
+
+    output  [11:0]  rx_data_i       ,
+    output  [11:0]  rx_data_q
+);
+
+genvar mm;
+
+// rx data from port
+wire [5:0] rx_data;
+wire [5:0] rx_data_pos;
+wire [5:0] rx_data_neg;
+
+generate
+for (mm = 0; mm < 6; mm = mm + 1) begin
+
+IBUFDS #(
+    .DIFF_TERM  ("TRUE"         )  // Differential Termination
+) u_rx_data_ibufds
+(
+    .I          (rx_data_p[mm]  ), // Diff_p buffer input (connect directly to top-level port)
+    .IB         (rx_data_n[mm]  ), // Diff_n buffer input (connect directly to top-level port)
+    .O          (rx_data[mm]    )  // Buffer output
+);
+
+IDDR #(
+    .DDR_CLK_EDGE   ("SAME_EDGE"    ), // "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED"
+    .INIT_Q1        (1'b0           ), // Initial value of Q1: 1'b0 or 1'b1
+    .INIT_Q2        (1'b0           ), // Initial value of Q2: 1'b0 or 1'b1
+    .SRTYPE         ("ASYNC"        )  // Set/Reset type: "SYNC" or "ASYNC"
+) i_rx_data_iddr (
+    .CE             (1'b1           ), // 1-bit clock enable input
+    .R              (1'b0           ), // 1-bit reset
+    .S              (1'b0           ), // 1-bit set
+    .C              (clk_2x_in      ), // 1-bit clock input
+    .D              (rx_data[mm]    ), // 1-bit DDR data input
+    .Q1             (rx_data_pos[mm]), // 1-bit output for positive edge of clock
+    .Q2             (rx_data_neg[mm])  // 1-bit output for negative edge of clock
+);
+
+end
+endgenerate
+
+// rx frame from port
+wire rx_frame;
+wire rx_frame_pos;
+wire rx_frame_neg;
+
+IBUFDS #(
+    .DIFF_TERM  ("TRUE"     )  // Differential Termination
+) u_rx_frame_ibufds
+(
+    .I          (rx_frame_p ), // Diff_p buffer input (connect directly to top-level port)
+    .IB         (rx_frame_n ), // Diff_n buffer input (connect directly to top-level port)
+    .O          (rx_frame   )  // Buffer output
+);
+
+IDDR #(
+    .DDR_CLK_EDGE   ("SAME_EDGE"    ), // "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED"
+    .INIT_Q1        (1'b0           ), // Initial value of Q1: 1'b0 or 1'b1
+    .INIT_Q2        (1'b0           ), // Initial value of Q2: 1'b0 or 1'b1
+    .SRTYPE         ("ASYNC"        )  // Set/Reset type: "SYNC" or "ASYNC"
+) i_rx_frame_iddr (
+    .CE             (1'b1           ), // 1-bit clock enable input
+    .R              (1'b0           ), // 1-bit reset
+    .S              (1'b0           ), // 1-bit set
+    .C              (clk_2x_in      ), // 1-bit clock input
+    .D              (rx_frame       ), // 1-bit DDR data input
+    .Q1             (rx_frame_pos   ), // 1-bit output for positive edge of clock
+    .Q2             (rx_frame_neg   )  // 1-bit output for negative edge of clock
+);
+
+// unpack rx frame & data
+reg [11:0] rx_fifo_i = 'b0;
+reg [11:0] rx_fifo_q = 'b0;
+reg rx_fifo_wr_en = 'b0;
+reg rx_fifo_rd_en = 'b0;
+wire rx_fifo_empty_1;
+wire rx_fifo_empty_2;
+
+always @(posedge clk_2x_in) begin
+    if (clk_in_rst) begin
+        rx_fifo_i <= 'b0;
+        rx_fifo_q <= 'b0;
+        rx_fifo_wr_en <= 'b0;
+    end
+    else begin
+        if ({rx_frame_neg,rx_frame_pos} == 2'b11) begin
+            rx_fifo_i[11:6] <= rx_data_neg;
+            rx_fifo_q[11:6] <= rx_data_pos;
+            rx_fifo_wr_en <= 'b0;
+        end
+        else if ({rx_frame_neg,rx_frame_pos} == 2'b00) begin
+            rx_fifo_i[5:0] <= rx_data_neg;
+            rx_fifo_q[5:0] <= rx_data_pos;
+            rx_fifo_wr_en <= 1'b1;
+        end
+        else begin
+            rx_fifo_i <= 'd1234; // error
+            rx_fifo_q <= 'd4321; // error
+            rx_fifo_wr_en <= 'b0;
+        end
+    end
+end
+
+always @(posedge rx_data_clk) begin
+    if (rx_data_clk_rst) begin
+        rx_fifo_rd_en <= 'b0;
+    end
+    else begin
+        rx_fifo_rd_en <= &{~rx_fifo_empty_1, ~rx_fifo_empty_2};
+    end
+end
+
+ad9361_fifo u_rx_fifo_i
+(
+    .rst        (clk_in_rst || rx_fifo_rst  ), // input wire rst
+    .wr_clk     (clk_2x_in                  ), // input wire wr_clk
+    .rd_clk     (rx_data_clk                ), // input wire rd_clk
+    .din        (rx_fifo_i                  ), // input wire [11 : 0] din
+    .wr_en      (rx_fifo_wr_en              ), // input wire wr_en
+    .rd_en      (1'b1                       ), // input wire rd_en
+    .dout       (rx_data_i                  ), // output wire [11 : 0] dout
+    .full       (                           ), // output wire full
+    .empty      (rx_fifo_empty_1            )  // output wire empty
+);
+
+ad9361_fifo u_rx_fifo_q
+(
+    .rst        (clk_in_rst || rx_fifo_rst  ), // input wire rst
+    .wr_clk     (clk_2x_in                  ), // input wire wr_clk
+    .rd_clk     (rx_data_clk                ), // input wire rd_clk
+    .din        (rx_fifo_q                  ), // input wire [11 : 0] din
+    .wr_en      (rx_fifo_wr_en              ), // input wire wr_en
+    .rd_en      (rx_fifo_rd_en              ), // input wire rd_en
+    .dout       (rx_data_q                  ), // output wire [11 : 0] dout
+    .full       (                           ), // output wire full
+    .empty      (rx_fifo_empty_2            )  // output wire empty
+);
+
+endmodule

modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_cmos_dual.v

@@ -9,7 +9,7 @@
 //  \___/ \___/|___/_| |_|  \____|\__,_|\___/
 //
 // Create Date: 2022/07/01 16:39:19
-// Last Modified Date: 2023/03/06 11:45
+// Last Modified Date: 2024/09/27 16:22
 // Design Name:
 // Module Name: ad9361_tx_map_cmos_dual
 // Project Name:
@@ -44,21 +44,31 @@ module ad9361_tx_map_cmos_dual
     output  [11:0]  tx_data
 );
 
-genvar m;
+genvar mm;
 
 // input data fifo
-reg rx_fifo_rd_en = 'b0;
+reg tx_fifo_rd_en = 'b0;
 wire [11:0] tx_fifo_ch1_i;
 wire [11:0] tx_fifo_ch1_q;
 wire [11:0] tx_fifo_ch2_i;
 wire [11:0] tx_fifo_ch2_q;
 
+wire rx_fifo_empty_1;
+wire rx_fifo_empty_2;
+wire rx_fifo_empty_3;
+wire rx_fifo_empty_4;
+
 always @(posedge clk_2x_in) begin
     if (clk_in_rst) begin
-        rx_fifo_rd_en <= 'b0;
+        tx_fifo_rd_en <= 'b0;
     end
     else begin
-        rx_fifo_rd_en <= ~rx_fifo_rd_en;
+        if (&{~rx_fifo_empty_1, ~rx_fifo_empty_2, ~rx_fifo_empty_3, ~rx_fifo_empty_4}) begin
+            tx_fifo_rd_en <= ~tx_fifo_rd_en;
+        end
+        else begin
+            tx_fifo_rd_en <= 'b0;
+        end
     end
 end
 
@@ -69,10 +79,10 @@ ad9361_fifo u_tx_fifo_ch1_i
     .rd_clk     (clk_2x_in      ), // input wire rd_clk
     .din        (tx_ch1_i       ), // input wire [11 : 0] din
     .wr_en      (1'b1           ), // input wire wr_en
-    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
+    .rd_en      (tx_fifo_rd_en  ), // input wire rd_en
     .dout       (tx_fifo_ch1_i  ), // output wire [11 : 0] dout
     .full       (               ), // output wire full
-    .empty      (               )  // output wire empty
+    .empty      (rx_fifo_empty_1)  // output wire empty
 );
 
 ad9361_fifo u_tx_fifo_ch1_q
@@ -82,10 +92,10 @@ ad9361_fifo u_tx_fifo_ch1_q
     .rd_clk     (clk_2x_in      ), // input wire rd_clk
     .din        (tx_ch1_q       ), // input wire [11 : 0] din
     .wr_en      (1'b1           ), // input wire wr_en
-    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
+    .rd_en      (tx_fifo_rd_en  ), // input wire rd_en
     .dout       (tx_fifo_ch1_q  ), // output wire [11 : 0] dout
     .full       (               ), // output wire full
-    .empty      (               )  // output wire empty
+    .empty      (rx_fifo_empty_2)  // output wire empty
 );
 
 ad9361_fifo u_tx_fifo_ch2_i
@@ -95,10 +105,10 @@ ad9361_fifo u_tx_fifo_ch2_i
     .rd_clk     (clk_2x_in      ), // input wire rd_clk
     .din        (tx_ch2_i       ), // input wire [11 : 0] din
     .wr_en      (1'b1           ), // input wire wr_en
-    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
+    .rd_en      (tx_fifo_rd_en  ), // input wire rd_en
     .dout       (tx_fifo_ch2_i  ), // output wire [11 : 0] dout
     .full       (               ), // output wire full
-    .empty      (               )  // output wire empty
+    .empty      (rx_fifo_empty_3)  // output wire empty
 );
 
 ad9361_fifo u_tx_fifo_ch2_q
@@ -108,10 +118,10 @@ ad9361_fifo u_tx_fifo_ch2_q
     .rd_clk     (clk_2x_in      ), // input wire rd_clk
     .din        (tx_ch2_q       ), // input wire [11 : 0] din
     .wr_en      (1'b1           ), // input wire wr_en
-    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
+    .rd_en      (tx_fifo_rd_en  ), // input wire rd_en
     .dout       (tx_fifo_ch2_q  ), // output wire [11 : 0] dout
     .full       (               ), // output wire full
-    .empty      (               )  // output wire empty
+    .empty      (rx_fifo_empty_4)  // output wire empty
 );
 
 // frame and data control
@@ -127,7 +137,7 @@ always @(posedge clk_2x_in) begin
         tx_data_i <= 'b0;
         tx_data_q <= 'b0;
     end
-    else if (rx_fifo_rd_en == 1'b0) begin
+    else if (tx_fifo_rd_en == 1'b0) begin
         tx_frame_i <= 1'b1;
         tx_frame_q <= 1'b1;
         tx_data_i <= tx_fifo_ch1_i;
@@ -159,10 +169,10 @@ ODDR #(
     .Q              (tx_frame       )
 );
 
-// output tx data to port
 generate
-for (m=0; m<12; m=m+1) begin: tx_data_oddr
+for (mm = 0; mm < 12; mm = mm + 1) begin
 
+// output tx data to port
 ODDR #(
     .DDR_CLK_EDGE   ("SAME_EDGE"   ),
     .INIT           (1'b0          ),
@@ -172,9 +182,9 @@ ODDR #(
     .R              (1'b0          ),
     .S              (1'b0          ),
     .C              (clk_2x_in     ),
-    .D1             (tx_data_i[m]  ),
+    .D1             (tx_data_i[mm] ),
-    .D2             (tx_data_q[m]  ),
+    .D2             (tx_data_q[mm] ),
-    .Q              (tx_data[m]    )
+    .Q              (tx_data[mm]   )
 );
 
 end

modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_cmos_single.v

@@ -41,7 +41,7 @@ module ad9361_tx_map_cmos_single
     output  [11:0]  tx_data
 );
 
-genvar m;
+genvar mm;
 
 // inout data fifo
 wire [11:0] tx_fifo_i;
@@ -82,35 +82,35 @@ assign clk_out = clk_in;
 
 // output tx frame to port
 ODDR #(
-    .DDR_CLK_EDGE   ("SAME_EDGE"    ),
+    .DDR_CLK_EDGE   ("SAME_EDGE"    ), // "OPPOSITE_EDGE" or "SAME_EDGE"
-    .INIT           (1'b0           ),
+    .INIT           (1'b0           ), // Initial value of Q: 1'b0 or 1'b1
-    .SRTYPE         ("ASYNC"        )
+    .SRTYPE         ("ASYNC"        )  // Set/Reset type: "SYNC" or "ASYNC"
 ) u_tx_frame_oddr (
-    .CE             (1'b1           ),
+    .CE             (1'b1           ), // 1-bit clock enable input
-    .R              (1'b0           ),
+    .R              (1'b0           ), // 1-bit reset
-    .S              (1'b0           ),
+    .S              (1'b0           ), // 1-bit set
-    .C              (clk_in         ),
+    .C              (clk_in         ), // 1-bit clock input
-    .D1             (tx_frame_i     ),
+    .D1             (tx_frame_i     ), // 1-bit data input (positive edge)
-    .D2             (tx_frame_q     ),
+    .D2             (tx_frame_q     ), // 1-bit data input (negative edge)
-    .Q              (tx_frame       )
+    .Q              (tx_frame       )  // 1-bit DDR output
 );
 
 // output tx data to port
 generate
-for (m=0; m<12; m=m+1) begin: tx_data_oddr
+for (mm = 0; mm < 12; mm = mm + 1) begin: tx_data_oddr
 
 ODDR #(
-    .DDR_CLK_EDGE   ("SAME_EDGE"   ),
+    .DDR_CLK_EDGE   ("SAME_EDGE"   ), // "OPPOSITE_EDGE" or "SAME_EDGE"
-    .INIT           (1'b0          ),
+    .INIT           (1'b0          ), // Initial value of Q: 1'b0 or 1'b1
-    .SRTYPE         ("ASYNC"       )
+    .SRTYPE         ("ASYNC"       )  // Set/Reset type: "SYNC" or "ASYNC"
 ) u_tx_data_oddr (
-    .CE             (1'b1          ),
+    .CE             (1'b1          ), // 1-bit clock enable input
-    .R              (1'b0          ),
+    .R              (1'b0          ), // 1-bit reset
-    .S              (1'b0          ),
+    .S              (1'b0          ), // 1-bit set
-    .C              (clk_in        ),
+    .C              (clk_in        ), // 1-bit clock input
-    .D1             (tx_fifo_i[m]  ),
+    .D1             (tx_fifo_i[mm] ), // 1-bit data input (positive edge)
-    .D2             (tx_fifo_q[m]  ),
+    .D2             (tx_fifo_q[mm] ), // 1-bit data input (negative edge)
-    .Q              (tx_data[m]    )
+    .Q              (tx_data[mm]   )  // 1-bit DDR output
 );
 
 end

modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_lvds_dual.v

@@ -8,8 +8,7 @@
 // | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
 //  \___/ \___/|___/_| |_|  \____|\__,_|\___/
 //
-// Create Date: 2023/03/05 23:21:27
+// Create Date: 09/27/2024 03:26:45 PM
-// Last Modified Date: 2023/03/06 11:01
 // Design Name:
 // Module Name: ad9361_tx_map_lvds_dual
 // Project Name:
@@ -47,34 +46,41 @@ module ad9361_tx_map_lvds_dual
     output  [ 5:0]  tx_data_n
 );
 
-genvar m;
+genvar mm;
 
 // input data fifo
-reg [1:0] tx_control_cnt = 'b0;
+reg [1:0] tx_fifo_rd_en_cnt = 'b0;
-reg rx_fifo_rd_en = 'b0;
+reg tx_fifo_rd_en = 'b0;
 wire [11:0] tx_fifo_ch1_i;
 wire [11:0] tx_fifo_ch1_q;
 wire [11:0] tx_fifo_ch2_i;
 wire [11:0] tx_fifo_ch2_q;
 
+wire rx_fifo_empty_1;
+wire rx_fifo_empty_2;
+wire rx_fifo_empty_3;
+wire rx_fifo_empty_4;
+
 always @(posedge clk_4x_in) begin
     if (clk_in_rst) begin
-        tx_control_cnt <= 'b0;
+        tx_fifo_rd_en_cnt <= 'b0;
     end
     else begin
-        tx_control_cnt <= tx_control_cnt + 1'b1;
+        tx_fifo_rd_en_cnt <= tx_fifo_rd_en_cnt + 1'b1;
     end
 end
 
 always @(posedge clk_4x_in) begin
     if (clk_in_rst) begin
-        rx_fifo_rd_en <= 'b0;
+        tx_fifo_rd_en <= 'b0;
-    end
-    else if (tx_control_cnt == 2'd2) begin
-        rx_fifo_rd_en <= 1'b1;
     end
     else begin
-        rx_fifo_rd_en <= 'b0;
+        if (&{~rx_fifo_empty_1, ~rx_fifo_empty_2, ~rx_fifo_empty_3, ~rx_fifo_empty_4}) begin
+            tx_fifo_rd_en <= (tx_fifo_rd_en_cnt == 2'd3) ? 1'b1 : 'b0;
+        end
+        else begin
+            tx_fifo_rd_en <= 'b0;
+        end
     end
 end
 
@@ -85,10 +91,10 @@ ad9361_fifo u_tx_fifo_ch1_i
     .rd_clk     (clk_4x_in      ), // input wire rd_clk
     .din        (tx_ch1_i       ), // input wire [11 : 0] din
     .wr_en      (1'b1           ), // input wire wr_en
-    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
+    .rd_en      (tx_fifo_rd_en  ), // input wire rd_en
     .dout       (tx_fifo_ch1_i  ), // output wire [11 : 0] dout
     .full       (               ), // output wire full
-    .empty      (               )  // output wire empty
+    .empty      (rx_fifo_empty_1)  // output wire empty
 );
 
 ad9361_fifo u_tx_fifo_ch1_q
@@ -98,10 +104,10 @@ ad9361_fifo u_tx_fifo_ch1_q
     .rd_clk     (clk_4x_in      ), // input wire rd_clk
     .din        (tx_ch1_q       ), // input wire [11 : 0] din
     .wr_en      (1'b1           ), // input wire wr_en
-    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
+    .rd_en      (tx_fifo_rd_en  ), // input wire rd_en
     .dout       (tx_fifo_ch1_q  ), // output wire [11 : 0] dout
     .full       (               ), // output wire full
-    .empty      (               )  // output wire empty
+    .empty      (rx_fifo_empty_2)  // output wire empty
 );
 
 ad9361_fifo u_tx_fifo_ch2_i
@@ -111,10 +117,10 @@ ad9361_fifo u_tx_fifo_ch2_i
     .rd_clk     (clk_4x_in      ), // input wire rd_clk
     .din        (tx_ch2_i       ), // input wire [11 : 0] din
     .wr_en      (1'b1           ), // input wire wr_en
-    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
+    .rd_en      (tx_fifo_rd_en  ), // input wire rd_en
     .dout       (tx_fifo_ch2_i  ), // output wire [11 : 0] dout
     .full       (               ), // output wire full
-    .empty      (               )  // output wire empty
+    .empty      (rx_fifo_empty_3)  // output wire empty
 );
 
 ad9361_fifo u_tx_fifo_ch2_q
@@ -124,57 +130,56 @@ ad9361_fifo u_tx_fifo_ch2_q
     .rd_clk     (clk_4x_in      ), // input wire rd_clk
     .din        (tx_ch2_q       ), // input wire [11 : 0] din
     .wr_en      (1'b1           ), // input wire wr_en
-    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
+    .rd_en      (tx_fifo_rd_en  ), // input wire rd_en
     .dout       (tx_fifo_ch2_q  ), // output wire [11 : 0] dout
     .full       (               ), // output wire full
-    .empty      (               )  // output wire empty
+    .empty      (rx_fifo_empty_4)  // output wire empty
 );
 
-
 // frame and data control
-reg tx_frame_r = 'b0; // rising edge data
+reg tx_frame_i = 'b0;
-reg tx_frame_f = 'b0; // falling edge data
+reg tx_frame_q = 'b0;
-reg [5:0] tx_data_r = 'b0;
+reg [5:0] tx_buf_i = 'b0;
-reg [5:0] tx_data_f = 'b0;
+reg [5:0] tx_buf_q = 'b0;
 
 always @(posedge clk_4x_in) begin
     if (clk_in_rst) begin
-        tx_frame_r <= 'b0;
+        tx_frame_i <= 'b0;
-        tx_frame_f <= 'b0;
+        tx_frame_q <= 'b0;
-        tx_data_r <= 'b0;
+        tx_buf_i <= 'b0;
-        tx_data_f <= 'b0;
+        tx_buf_q <= 'b0;
     end
     else begin
-        case (tx_control_cnt)
+        case (tx_fifo_rd_en_cnt)
             2'd0: begin
-                tx_frame_r <= 1'b1;
+                tx_frame_i <= 1'b1;
-                tx_frame_f <= 1'b1;
+                tx_frame_q <= 1'b1;
-                tx_data_r <= tx_fifo_ch1_i[11: 6];
+                tx_buf_i <= tx_fifo_ch1_i[11:6];
-                tx_data_f <= tx_fifo_ch1_q[11: 6];
+                tx_buf_q <= tx_fifo_ch1_q[11:6];
             end
             2'd1: begin
-                tx_frame_r <= 1'b1;
+                tx_frame_i <= 1'b1;
-                tx_frame_f <= 1'b1;
+                tx_frame_q <= 1'b1;
-                tx_data_r <= tx_fifo_ch1_i[5:0];
+                tx_buf_i <= tx_fifo_ch1_i[5:0];
-                tx_data_f <= tx_fifo_ch1_q[5:0];
+                tx_buf_q <= tx_fifo_ch1_q[5:0];
             end
             2'd2: begin
-                tx_frame_r <= 1'b0;
+                tx_frame_i <= 1'b0;
-                tx_frame_f <= 1'b0;
+                tx_frame_q <= 1'b0;
-                tx_data_r <= tx_fifo_ch2_i[11:6];
+                tx_buf_i <= tx_fifo_ch2_i[11:6];
-                tx_data_f <= tx_fifo_ch2_q[11:6];
+                tx_buf_q <= tx_fifo_ch2_q[11:6];
             end
             2'd3: begin
-                tx_frame_r <= 1'b0;
+                tx_frame_i <= 1'b0;
-                tx_frame_f <= 1'b0;
+                tx_frame_q <= 1'b0;
-                tx_data_r <= tx_fifo_ch2_i[5:0];
+                tx_buf_i <= tx_fifo_ch2_i[5:0];
-                tx_data_f <= tx_fifo_ch2_q[5:0];
+                tx_buf_q <= tx_fifo_ch2_q[5:0];
             end
             default: begin
-                tx_frame_r <= 'b0;
+                tx_frame_i <= 'b0; // error
-                tx_frame_f <= 'b0;
+                tx_frame_q <= 'b0; // error
-                tx_data_r <= 'b0;
+                tx_buf_i <= 'b0; // error
-                tx_data_f <= 'b0;
+                tx_buf_q <= 'b0; // error
             end
         endcase
     end
@@ -182,9 +187,10 @@ end
 
 // output clock to port
 wire clk_out;
+
 assign clk_out = clk_4x_in;
 
-OBUFDS u_obufds_clk_out
+OBUFDS u_clk_out_obufds
 (
     .I  (clk_out    ),
     .O  (clk_out_p  ),
@@ -192,6 +198,8 @@ OBUFDS u_obufds_clk_out
 );
 
 // output tx frame to port
+wire tx_frame;
+
 ODDR #(
     .DDR_CLK_EDGE   ("SAME_EDGE"    ),
     .INIT           (1'b0           ),
@@ -201,23 +209,23 @@ ODDR #(
     .R              (1'b0           ),
     .S              (1'b0           ),
     .C              (clk_4x_in      ),
-    .D1             (tx_frame_r     ),
+    .D1             (tx_frame_i     ),
-    .D2             (tx_frame_f     ),
+    .D2             (tx_frame_q     ),
     .Q              (tx_frame       )
 );
 
-OBUFDS u_obufds_tx_frame
+OBUFDS u_tx_frame_obufds
 (
-    .I  (tx_frame   ),
+    .O  (tx_frame_p ), // Diff_p output (connect directly to top-level port)
-    .O  (tx_frame_p ),
+    .OB (tx_frame_n ), // Diff_n output (connect directly to top-level port)
-    .OB (tx_frame_n )
+    .I  (tx_frame   )  // Buffer input
 );
 
-// output tx data to port
+// ouput tx data to port
 wire [5:0] tx_data;
 
 generate
-for (m=0; m<6; m=m+1) begin: tx_data_oddr
+for (mm = 0; mm < 6; mm = mm + 1) begin
 
 ODDR #(
     .DDR_CLK_EDGE   ("SAME_EDGE"   ),
@@ -228,16 +236,16 @@ ODDR #(
     .R              (1'b0          ),
     .S              (1'b0          ),
     .C              (clk_4x_in     ),
-    .D1             (tx_data_r[m]  ),
+    .D1             (tx_buf_i[mm]  ),
-    .D2             (tx_data_f[m]  ),
+    .D2             (tx_buf_q[mm]  ),
-    .Q              (tx_data[m]    )
+    .Q              (tx_data[mm]   )
 );
 
-OBUFDS u_obufds_tx_data
+OBUFDS u_tx_data_obufds
 (
-    .I  (tx_data[m]     ),
+    .O  (tx_data_p[mm]  ), // Diff_p output (connect directly to top-level port)
-    .O  (tx_data_p[m]   ),
+    .OB (tx_data_n[mm]  ), // Diff_n output (connect directly to top-level port)
-    .OB (tx_data_n[m]   )
+    .I  (tx_data[mm]    )  // Buffer input
 );
 
 end

modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_lvds_single.v

@@ -0,0 +1,187 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 09/27/2024 03:26:45 PM
+// Design Name:
+// Module Name: ad9361_tx_map_lvds_single
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module ad9361_tx_map_lvds_single
+(
+    input           clk_2x_in       ,
+    input           clk_in_rst      ,
+
+    input           tx_data_clk     ,
+    input           tx_data_clk_rst ,
+
+    input   [11:0]  tx_data_i       ,
+    input   [11:0]  tx_data_q       ,
+
+    output          clk_out_p       ,
+    output          clk_out_n       ,
+    output          tx_frame_p      ,
+    output          tx_frame_n      ,
+    output  [ 5:0]  tx_data_p       ,
+    output  [ 5:0]  tx_data_n
+);
+
+genvar mm;
+
+// input data fifo
+reg tx_fifo_rd_en = 'b0;
+wire [11:0] tx_fifo_i;
+wire [11:0] tx_fifo_q;
+
+wire rx_fifo_empty_1;
+wire rx_fifo_empty_2;
+
+always @(posedge clk_2x_in) begin
+    if (clk_in_rst) begin
+        tx_fifo_rd_en <= 'b0;
+    end
+    else begin
+        if (&{~rx_fifo_empty_1, ~rx_fifo_empty_2}) begin
+            tx_fifo_rd_en <= ~tx_fifo_rd_en;
+        end
+        else begin
+            tx_fifo_rd_en <= 'b0;
+        end
+    end
+end
+
+ad9361_fifo u_tx_fifo_i
+(
+    .rst        (clk_in_rst     ), // input wire rst
+    .wr_clk     (tx_data_clk    ), // input wire wr_clk
+    .rd_clk     (clk_2x_in      ), // input wire rd_clk
+    .din        (tx_data_i      ), // input wire [11 : 0] din
+    .wr_en      (1'b1           ), // input wire wr_en
+    .rd_en      (tx_fifo_rd_en  ), // input wire rd_en
+    .dout       (tx_fifo_i      ), // output wire [11 : 0] dout
+    .full       (               ), // output wire full
+    .empty      (rx_fifo_empty_1)  // output wire empty
+);
+
+ad9361_fifo u_tx_fifo_q
+(
+    .rst        (clk_in_rst     ), // input wire rst
+    .wr_clk     (tx_data_clk    ), // input wire wr_clk
+    .rd_clk     (clk_2x_in      ), // input wire rd_clk
+    .din        (tx_data_q      ), // input wire [11 : 0] din
+    .wr_en      (1'b1           ), // input wire wr_en
+    .rd_en      (tx_fifo_rd_en  ), // input wire rd_en
+    .dout       (tx_fifo_q      ), // output wire [11 : 0] dout
+    .full       (               ), // output wire full
+    .empty      (rx_fifo_empty_2)  // output wire empty
+);
+
+// frame and data control
+reg tx_frame_i = 'b0;
+reg tx_frame_q = 'b0;
+reg [ 5:0] tx_buf_i = 'b0;
+reg [ 5:0] tx_buf_q = 'b0;
+
+always @(posedge clk_2x_in) begin
+    if (clk_in_rst) begin
+        tx_frame_i <= 'b0;
+        tx_frame_q <= 'b0;
+        tx_buf_i <= 'b0;
+        tx_buf_q <= 'b0;
+    end
+    else begin
+        if (tx_fifo_rd_en == 1'b0) begin
+            tx_frame_i <= 1'b1;
+            tx_frame_q <= 1'b1;
+            tx_buf_i <= tx_fifo_i[11:6];
+            tx_buf_q <= tx_fifo_q[11:6];
+        end
+        else begin
+            tx_frame_i <= 1'b0;
+            tx_frame_q <= 1'b0;
+            tx_buf_i <= tx_fifo_i[5:0];
+            tx_buf_q <= tx_fifo_q[5:0];
+        end
+    end
+end
+
+// output clock to port
+wire clk_out;
+
+assign clk_out = clk_2x_in;
+
+OBUFDS u_clk_out_obufds
+(
+    .I  (clk_out    ),
+    .O  (clk_out_p  ),
+    .OB (clk_out_n  )
+);
+
+// output tx frame to port
+wire tx_frame;
+
+ODDR #(
+    .DDR_CLK_EDGE   ("SAME_EDGE"    ),
+    .INIT           (1'b0           ),
+    .SRTYPE         ("ASYNC"        )
+) u_tx_frame_oddr (
+    .CE             (1'b1           ),
+    .R              (1'b0           ),
+    .S              (1'b0           ),
+    .C              (clk_2x_in      ),
+    .D1             (tx_frame_i     ),
+    .D2             (tx_frame_q     ),
+    .Q              (tx_frame       )
+);
+
+OBUFDS u_tx_frame_obufds
+(
+    .O  (tx_frame_p ), // Diff_p output (connect directly to top-level port)
+    .OB (tx_frame_n ), // Diff_n output (connect directly to top-level port)
+    .I  (tx_frame   )  // Buffer input
+);
+
+// ouput tx data to port
+wire [5:0] tx_data;
+
+generate
+for (mm = 0; mm < 6; mm = mm + 1) begin
+
+ODDR #(
+    .DDR_CLK_EDGE   ("SAME_EDGE"   ),
+    .INIT           (1'b0          ),
+    .SRTYPE         ("ASYNC"       )
+) u_tx_data_oddr (
+    .CE             (1'b1          ),
+    .R              (1'b0          ),
+    .S              (1'b0          ),
+    .C              (clk_2x_in     ),
+    .D1             (tx_buf_i[mm]  ),
+    .D2             (tx_buf_q[mm]  ),
+    .Q              (tx_data[mm]   )
+);
+
+OBUFDS u_tx_data_obufds
+(
+    .O  (tx_data_p[mm]  ), // Diff_p output (connect directly to top-level port)
+    .OB (tx_data_n[mm]  ), // Diff_n output (connect directly to top-level port)
+    .I  (tx_data[mm]    )  // Buffer input
+);
+
+end
+endgenerate
+
+endmodule

modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.xpr

@@ -89,13 +89,29 @@
   <FileSets Version="1" Minor="32">
     <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
       <Filter Type="Srcs"/>
-      <File Path="$PSRCDIR/sources_1/new/ad9361_rx_map_cmos_dual.v">
+      <File Path="$PSRCDIR/sources_1/new/ad9361_tx_map_lvds_single.v">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="implementation"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PSRCDIR/sources_1/new/ad9361_rx_map_lvds_single.v">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/ad9361_tx_map_lvds_dual.v">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <File Path="$PSRCDIR/sources_1/new/ad9361_rx_map_lvds_dual.v">
         <FileInfo>
           <Attr Name="AutoDisabled" Val="1"/>
@@ -104,7 +120,7 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PSRCDIR/sources_1/new/ad9361_tx_map_cmos_dual.v">
+      <File Path="$PSRCDIR/sources_1/new/ad9361_rx_map_cmos_dual.v">
         <FileInfo>
           <Attr Name="AutoDisabled" Val="1"/>
           <Attr Name="UsedIn" Val="synthesis"/>
@@ -112,7 +128,7 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PSRCDIR/sources_1/new/ad9361_tx_map_lvds_dual.v">
+      <File Path="$PSRCDIR/sources_1/new/ad9361_tx_map_cmos_dual.v">
         <FileInfo>
           <Attr Name="AutoDisabled" Val="1"/>
           <Attr Name="UsedIn" Val="synthesis"/>
@@ -138,8 +154,7 @@
       </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="ad9361_rx_map_cmos_dual"/>
+        <Option Name="TopModule" Val="ad9361_tx_map_lvds_single"/>
-        <Option Name="TopAutoSet" Val="TRUE"/>
       </Config>
     </FileSet>
     <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
@@ -150,9 +165,40 @@
     </FileSet>
     <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
       <Filter Type="Srcs"/>
+      <File Path="$PSRCDIR/sim_1/new/tb_ad9361_trx_cmos_dual.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sim_1/new/tb_ad9361_trx_lvds_single.v">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sim_1/new/tb_ad9361_trx_cmos_single.v">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sim_1/new/tb_ad9361_trx_lvds_dual.v">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="ad9361_rx_map_cmos_dual"/>
+        <Option Name="TopModule" Val="tb_ad9361_trx_cmos_dual"/>
         <Option Name="TopLib" Val="xil_defaultlib"/>
         <Option Name="TopAutoSet" Val="TRUE"/>
         <Option Name="TransportPathDelay" Val="0"/>
@@ -167,6 +213,14 @@
     </FileSet>
     <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
       <Filter Type="Utils"/>
+      <File Path="$PSRCDIR/utils_1/imports/synth_1/ad9361_rx_map_cmos_dual.dcp">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedInSteps" Val="synth_1"/>
+          <Attr Name="AutoDcp" Val="1"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="TopAutoSet" Val="TRUE"/>
       </Config>
@@ -207,7 +261,7 @@
     </Simulator>
   </Simulators>
   <Runs Version="1" Minor="22">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z100ffg900-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z100ffg900-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/ad9361_rx_map_cmos_dual.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
         <Step Id="synth_design"/>