3 Commits

Include renames

Author	SHA1	Message	Date
josh	cec690b984	add dj_47dr vitis projects, refer to readme within each project for details	2024-06-28 23:06:09 +08:00
josh	0eead518df	add dj_47dr pl project, set .dcp as large file type	2024-06-28 22:24:04 +08:00
josh	8c68cb519e	add xilinx spi examlpe with ax7020 ... refer to projects/ax7020/ax7020_spi_loopback/README.md for detailed information	2024-01-24 20:14:55 +08:00