329 lines
15 KiB
XML
329 lines
15 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<spirit:vendor>analog.com</spirit:vendor>
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<spirit:library>user</spirit:library>
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<spirit:name>ad463x_data_capture</spirit:name>
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<spirit:version>1.0</spirit:version>
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<spirit:busInterfaces>
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<spirit:busInterface>
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<spirit:name>m_axis</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
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<spirit:master/>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>TREADY</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axis_ready</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>TVALID</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axis_valid</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>TDATA</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axis_data</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>m_axis_signal_clock</spirit:name>
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<spirit:displayName>m_axis_signal_clock</spirit:displayName>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>CLK</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>clk</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>ASSOCIATED_BUSIF</spirit:name>
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<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS_SIGNAL_CLOCK.ASSOCIATED_BUSIF">m_axis</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:busInterface>
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</spirit:busInterfaces>
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<spirit:model>
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<spirit:view>
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<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
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<spirit:displayName>Synthesis</spirit:displayName>
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<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
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<spirit:language>Verilog</spirit:language>
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<spirit:modelName>ad463x_data_capture</spirit:modelName>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>viewChecksum</spirit:name>
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<spirit:value>345b66ae</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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<spirit:view>
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<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
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<spirit:displayName>Simulation</spirit:displayName>
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<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
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<spirit:language>Verilog</spirit:language>
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<spirit:modelName>ad463x_data_capture</spirit:modelName>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>viewChecksum</spirit:name>
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<spirit:value>345b66ae</spirit:value>
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</spirit:parameter>
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</spirit:view>
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<spirit:view>
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<spirit:name>xilinx_xpgui</spirit:name>
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<spirit:displayName>UI Layout</spirit:displayName>
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<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>viewChecksum</spirit:name>
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<spirit:value>b26bd2d7</spirit:value>
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</spirit:view>
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</spirit:views>
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<spirit:ports>
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<spirit:port>
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<spirit:name>clk</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>csn</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>echo_sclk</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>data_in</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:vector>
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<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) - 1)">1</spirit:left>
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<spirit:right spirit:format="long">0</spirit:right>
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</spirit:vector>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>m_axis_data</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:vector>
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<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) * spirit:decode(id('MODELPARAM_VALUE.DATA_WIDTH'))) - 1)">63</spirit:left>
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<spirit:right spirit:format="long">0</spirit:right>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>m_axis_valid</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>m_axis_ready</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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<spirit:modelParameters>
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<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
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<spirit:name>DDR_EN</spirit:name>
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<spirit:displayName>Ddr En</spirit:displayName>
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<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DDR_EN">0</spirit:value>
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</spirit:modelParameter>
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<spirit:modelParameter spirit:dataType="integer">
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<spirit:name>NUM_OF_LANES</spirit:name>
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<spirit:displayName>Num Of Lanes</spirit:displayName>
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<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NUM_OF_LANES">2</spirit:value>
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<spirit:modelParameter spirit:dataType="integer">
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<spirit:name>DATA_WIDTH</spirit:name>
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<spirit:displayName>Data Width</spirit:displayName>
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<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DATA_WIDTH">32</spirit:value>
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<spirit:fileSets>
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<spirit:fileSet>
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<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
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<spirit:file>
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<spirit:name>ad463x_data_capture.v</spirit:name>
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<spirit:fileType>verilogSource</spirit:fileType>
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<spirit:userFileType>CHECKSUM_345b66ae</spirit:userFileType>
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<spirit:fileSet>
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<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
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<spirit:name>ad463x_data_capture.v</spirit:name>
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<spirit:fileType>verilogSource</spirit:fileType>
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<spirit:fileSet>
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<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
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<spirit:file>
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<spirit:name>xgui/ad463x_data_capture_v1_0.tcl</spirit:name>
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<spirit:userFileType>CHECKSUM_b26bd2d7</spirit:userFileType>
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<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
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<spirit:description>ad463x_data_capture_v1_0</spirit:description>
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<spirit:parameters>
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<spirit:name>DDR_EN</spirit:name>
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<spirit:displayName>Ddr En</spirit:displayName>
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<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DDR_EN">0</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>NUM_OF_LANES</spirit:name>
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<spirit:displayName>Num Of Lanes</spirit:displayName>
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<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_OF_LANES">2</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>DATA_WIDTH</spirit:name>
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<spirit:displayName>Data Width</spirit:displayName>
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<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DATA_WIDTH">32</spirit:value>
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<spirit:parameter>
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<spirit:name>Component_Name</spirit:name>
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<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">ad463x_data_capture_v1_0</spirit:value>
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<spirit:vendorExtensions>
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<xilinx:taxonomy>/Analog_Devices</xilinx:taxonomy>
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<xilinx:displayName>ad463x_data_capture_v1_0</xilinx:displayName>
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<xilinx:definitionSource>package_project</xilinx:definitionSource>
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<xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
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<xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
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<xilinx:coreCreationDateTime>2024-06-06T02:52:57Z</xilinx:coreCreationDateTime>
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