67542 lines
2.8 MiB
Plaintext
67542 lines
2.8 MiB
Plaintext
<?xml version="1.0" encoding="UTF-8"?>
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<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<spirit:vendor>analog.com</spirit:vendor>
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<spirit:library>user</spirit:library>
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<spirit:name>util_adxcvr</spirit:name>
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<spirit:version>1.0</spirit:version>
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<spirit:busInterfaces>
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<spirit:busInterface>
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<spirit:name>up_clk</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>CLK</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>up_clk</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>ASSOCIATED_RESET</spirit:name>
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<spirit:value spirit:id="BUSIFPARAM_VALUE.UP_CLK.ASSOCIATED_RESET">up_rstn</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>cpll_ref_clk_0</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>CLK</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>cpll_ref_clk_0</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>ASSOCIATED_RESET</spirit:name>
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<spirit:value spirit:id="BUSIFPARAM_VALUE.CPLL_REF_CLK_0.ASSOCIATED_RESET">up_rx_rst_0:up_tx_rst_0</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>rx_out_clk_0</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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<spirit:master/>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>CLK</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>rx_out_clk_0</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>tx_out_clk_0</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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<spirit:master/>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>CLK</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>tx_out_clk_0</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>rx_clk_0</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>CLK</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>rx_clk_0</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>tx_clk_0</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>CLK</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>tx_clk_0</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>qpll_ref_clk_0</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>CLK</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>qpll_ref_clk_0</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>cpll_ref_clk_1</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>CLK</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>cpll_ref_clk_1</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>ASSOCIATED_RESET</spirit:name>
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<spirit:value spirit:id="BUSIFPARAM_VALUE.CPLL_REF_CLK_1.ASSOCIATED_RESET">up_rx_rst_1:up_tx_rst_1</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>rx_out_clk_1</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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<spirit:master/>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>CLK</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>rx_out_clk_1</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>tx_out_clk_1</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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<spirit:master/>
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<spirit:portMaps>
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<spirit:portMap>
|
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<spirit:logicalPort>
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<spirit:name>CLK</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>tx_out_clk_1</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>rx_clk_1</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
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<spirit:slave/>
|
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>CLK</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>rx_clk_1</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>tx_clk_1</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
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<spirit:slave/>
|
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>CLK</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>tx_clk_1</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>cpll_ref_clk_2</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>cpll_ref_clk_2</spirit:name>
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</spirit:physicalPort>
|
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</spirit:portMap>
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</spirit:portMaps>
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<spirit:parameters>
|
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<spirit:parameter>
|
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<spirit:name>ASSOCIATED_RESET</spirit:name>
|
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<spirit:value spirit:id="BUSIFPARAM_VALUE.CPLL_REF_CLK_2.ASSOCIATED_RESET">up_rx_rst_2:up_tx_rst_2</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
|
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</spirit:busInterface>
|
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<spirit:busInterface>
|
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<spirit:name>rx_out_clk_2</spirit:name>
|
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
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</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
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<spirit:name>rx_out_clk_2</spirit:name>
|
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</spirit:physicalPort>
|
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</spirit:portMap>
|
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</spirit:portMaps>
|
|
</spirit:busInterface>
|
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<spirit:busInterface>
|
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<spirit:name>tx_out_clk_2</spirit:name>
|
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
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<spirit:name>CLK</spirit:name>
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</spirit:logicalPort>
|
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<spirit:physicalPort>
|
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<spirit:name>tx_out_clk_2</spirit:name>
|
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</spirit:physicalPort>
|
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</spirit:portMap>
|
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</spirit:portMaps>
|
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</spirit:busInterface>
|
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<spirit:busInterface>
|
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<spirit:name>rx_clk_2</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_clk_2</spirit:name>
|
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</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_clk_2</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_clk_2</spirit:name>
|
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</spirit:physicalPort>
|
|
</spirit:portMap>
|
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</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>cpll_ref_clk_3</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cpll_ref_clk_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.CPLL_REF_CLK_3.ASSOCIATED_RESET">up_rx_rst_3:up_tx_rst_3</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_out_clk_3</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_out_clk_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_out_clk_3</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_out_clk_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_clk_3</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_clk_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_clk_3</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_clk_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>cpll_ref_clk_4</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cpll_ref_clk_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.CPLL_REF_CLK_4.ASSOCIATED_RESET">up_rx_rst_4:up_tx_rst_4</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_out_clk_4</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_out_clk_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_out_clk_4</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_out_clk_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_clk_4</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_clk_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_clk_4</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_clk_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>qpll_ref_clk_4</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>qpll_ref_clk_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>cpll_ref_clk_5</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cpll_ref_clk_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.CPLL_REF_CLK_5.ASSOCIATED_RESET">up_rx_rst_5:up_tx_rst_5</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_out_clk_5</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_out_clk_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_out_clk_5</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_out_clk_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_clk_5</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_clk_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_clk_5</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_clk_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>cpll_ref_clk_6</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cpll_ref_clk_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.CPLL_REF_CLK_6.ASSOCIATED_RESET">up_rx_rst_6:up_tx_rst_6</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_out_clk_6</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_out_clk_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_out_clk_6</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_out_clk_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_clk_6</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_clk_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_clk_6</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_clk_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>cpll_ref_clk_7</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cpll_ref_clk_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.CPLL_REF_CLK_7.ASSOCIATED_RESET">up_rx_rst_7:up_tx_rst_7</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_out_clk_7</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_out_clk_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_out_clk_7</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_out_clk_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_clk_7</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_clk_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_clk_7</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_clk_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>cpll_ref_clk_8</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cpll_ref_clk_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.CPLL_REF_CLK_8.ASSOCIATED_RESET">up_rx_rst_8:up_tx_rst_8</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_out_clk_8</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_out_clk_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_out_clk_8</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_out_clk_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_clk_8</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_clk_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
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|
|
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|
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|
|
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|
|
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|
|
<spirit:name>CLK</spirit:name>
|
|
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|
|
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|
|
<spirit:name>tx_clk_8</spirit:name>
|
|
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|
|
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|
|
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|
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|
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|
|
<spirit:name>CLK</spirit:name>
|
|
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|
|
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|
|
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|
|
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|
|
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|
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|
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|
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|
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<spirit:name>CLK</spirit:name>
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<spirit:name>CLK</spirit:name>
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<spirit:name>ASSOCIATED_RESET</spirit:name>
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<spirit:value spirit:id="BUSIFPARAM_VALUE.CPLL_REF_CLK_12.ASSOCIATED_RESET">up_rx_rst_12:up_tx_rst_12</spirit:value>
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<spirit:name>CLK</spirit:name>
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<spirit:name>rx_out_clk_12</spirit:name>
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<spirit:name>CLK</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:logicalPort>
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<spirit:name>CLK</spirit:name>
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<spirit:name>rx_clk_12</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>CLK</spirit:name>
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|
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|
<spirit:physicalPort>
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<spirit:name>tx_clk_12</spirit:name>
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|
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|
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|
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|
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<spirit:busInterface>
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<spirit:name>qpll_ref_clk_12</spirit:name>
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|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:name>CLK</spirit:name>
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|
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<spirit:name>qpll_ref_clk_12</spirit:name>
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|
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|
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|
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<spirit:name>cpll_ref_clk_13</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:name>CLK</spirit:name>
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|
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<spirit:name>cpll_ref_clk_13</spirit:name>
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|
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|
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|
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.CPLL_REF_CLK_13.ASSOCIATED_RESET">up_rx_rst_13:up_tx_rst_13</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_out_clk_13</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_out_clk_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_out_clk_13</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_out_clk_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_clk_13</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_clk_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_clk_13</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_clk_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>cpll_ref_clk_14</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cpll_ref_clk_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.CPLL_REF_CLK_14.ASSOCIATED_RESET">up_rx_rst_14:up_tx_rst_14</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_out_clk_14</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_out_clk_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_out_clk_14</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_out_clk_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_clk_14</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_clk_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_clk_14</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_clk_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>cpll_ref_clk_15</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cpll_ref_clk_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.CPLL_REF_CLK_15.ASSOCIATED_RESET">up_rx_rst_15:up_tx_rst_15</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_out_clk_15</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_out_clk_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_out_clk_15</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_out_clk_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_clk_15</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_clk_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_clk_15</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_clk_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>cpll_ref_clk_16</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cpll_ref_clk_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.CPLL_REF_CLK_16.ASSOCIATED_RESET">up_rx_rst_16:up_tx_rst_16</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_out_clk_16</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_out_clk_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_out_clk_16</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_out_clk_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_clk_16</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_clk_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_clk_16</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_clk_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>qpll_ref_clk_16</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>qpll_ref_clk_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>cpll_ref_clk_17</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cpll_ref_clk_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.CPLL_REF_CLK_17.ASSOCIATED_RESET">up_rx_rst_17:up_tx_rst_17</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_out_clk_17</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_out_clk_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_out_clk_17</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_out_clk_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_clk_17</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_clk_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
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|
|
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|
|
<spirit:name>tx_clk_17</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
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|
|
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|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_clk_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
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|
|
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|
|
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|
|
<spirit:busInterface>
|
|
<spirit:name>cpll_ref_clk_18</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
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|
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|
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|
|
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|
|
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|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cpll_ref_clk_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
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|
|
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|
|
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|
|
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|
|
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.CPLL_REF_CLK_18.ASSOCIATED_RESET">up_rx_rst_18:up_tx_rst_18</spirit:value>
|
|
</spirit:parameter>
|
|
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|
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<spirit:name>rx_out_clk_18</spirit:name>
|
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|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_out_clk_18</spirit:name>
|
|
</spirit:physicalPort>
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|
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|
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<spirit:name>CLK</spirit:name>
|
|
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|
<spirit:name>tx_out_clk_18</spirit:name>
|
|
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<spirit:name>rx_clk_18</spirit:name>
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|
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<spirit:name>CLK</spirit:name>
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|
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|
|
<spirit:name>rx_clk_18</spirit:name>
|
|
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<spirit:name>tx_clk_18</spirit:name>
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<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
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|
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<spirit:physicalPort>
|
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<spirit:name>tx_clk_18</spirit:name>
|
|
</spirit:physicalPort>
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<spirit:name>cpll_ref_clk_19</spirit:name>
|
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<spirit:name>CLK</spirit:name>
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|
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|
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<spirit:name>ASSOCIATED_RESET</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.CPLL_REF_CLK_19.ASSOCIATED_RESET">up_rx_rst_19:up_tx_rst_19</spirit:value>
|
|
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|
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<spirit:name>rx_out_clk_19</spirit:name>
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<spirit:name>CLK</spirit:name>
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<spirit:physicalPort>
|
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<spirit:name>rx_out_clk_19</spirit:name>
|
|
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<spirit:name>tx_out_clk_19</spirit:name>
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<spirit:name>CLK</spirit:name>
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|
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<spirit:name>rx_clk_19</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:name>CLK</spirit:name>
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<spirit:name>rx_clk_19</spirit:name>
|
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<spirit:name>tx_clk_19</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>CLK</spirit:name>
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|
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|
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<spirit:physicalPort>
|
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<spirit:name>tx_clk_19</spirit:name>
|
|
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|
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|
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|
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|
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<spirit:name>cpll_ref_clk_20</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:logicalPort>
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<spirit:name>CLK</spirit:name>
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<spirit:physicalPort>
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<spirit:name>cpll_ref_clk_20</spirit:name>
|
|
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|
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|
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|
|
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.CPLL_REF_CLK_20.ASSOCIATED_RESET">up_rx_rst_20:up_tx_rst_20</spirit:value>
|
|
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<spirit:logicalPort>
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<spirit:name>CLK</spirit:name>
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<spirit:name>rx_out_clk_20</spirit:name>
|
|
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|
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:logicalPort>
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<spirit:name>CLK</spirit:name>
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<spirit:name>tx_out_clk_20</spirit:name>
|
|
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|
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|
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|
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<spirit:name>rx_clk_20</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:logicalPort>
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<spirit:name>CLK</spirit:name>
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|
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<spirit:physicalPort>
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|
<spirit:name>rx_clk_20</spirit:name>
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|
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|
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<spirit:name>tx_clk_20</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:logicalPort>
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<spirit:name>CLK</spirit:name>
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|
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|
<spirit:physicalPort>
|
|
<spirit:name>tx_clk_20</spirit:name>
|
|
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|
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|
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|
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<spirit:name>qpll_ref_clk_20</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:portMap>
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<spirit:logicalPort>
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|
<spirit:name>CLK</spirit:name>
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|
</spirit:logicalPort>
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|
<spirit:physicalPort>
|
|
<spirit:name>qpll_ref_clk_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
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|
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|
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<spirit:busInterface>
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<spirit:name>cpll_ref_clk_21</spirit:name>
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|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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<spirit:portMap>
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|
<spirit:logicalPort>
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<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cpll_ref_clk_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
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|
|
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|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.CPLL_REF_CLK_21.ASSOCIATED_RESET">up_rx_rst_21:up_tx_rst_21</spirit:value>
|
|
</spirit:parameter>
|
|
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<spirit:name>rx_out_clk_21</spirit:name>
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|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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<spirit:portMap>
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|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_out_clk_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
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|
|
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|
|
<spirit:busInterface>
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|
<spirit:name>tx_out_clk_21</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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<spirit:master/>
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|
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|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_out_clk_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
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|
|
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|
|
<spirit:busInterface>
|
|
<spirit:name>rx_clk_21</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_clk_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_clk_21</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_clk_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>cpll_ref_clk_22</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cpll_ref_clk_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.CPLL_REF_CLK_22.ASSOCIATED_RESET">up_rx_rst_22:up_tx_rst_22</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
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|
|
<spirit:busInterface>
|
|
<spirit:name>rx_out_clk_22</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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|
<spirit:master/>
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|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_out_clk_22</spirit:name>
|
|
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|
|
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|
|
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|
|
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|
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|
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|
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|
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|
|
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|
|
<spirit:name>CLK</spirit:name>
|
|
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|
|
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|
|
<spirit:name>tx_out_clk_22</spirit:name>
|
|
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|
|
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|
|
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|
|
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|
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<spirit:name>rx_clk_22</spirit:name>
|
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|
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|
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|
|
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|
|
<spirit:name>CLK</spirit:name>
|
|
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|
|
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|
|
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|
|
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|
|
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|
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|
|
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<spirit:name>tx_clk_22</spirit:name>
|
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|
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|
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|
|
<spirit:name>CLK</spirit:name>
|
|
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|
|
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|
|
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|
|
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|
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<spirit:name>ASSOCIATED_RESET</spirit:name>
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<spirit:name>CLK</spirit:name>
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<spirit:name>CLK</spirit:name>
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|
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<spirit:name>CLK</spirit:name>
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|
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|
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|
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<spirit:name>ASSOCIATED_RESET</spirit:name>
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|
<spirit:value spirit:id="BUSIFPARAM_VALUE.CPLL_REF_CLK_26.ASSOCIATED_RESET">up_rx_rst_26:up_tx_rst_26</spirit:value>
|
|
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|
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<spirit:name>CLK</spirit:name>
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|
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<spirit:name>rx_out_clk_26</spirit:name>
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|
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|
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|
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:logicalPort>
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<spirit:name>CLK</spirit:name>
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|
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|
<spirit:physicalPort>
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|
<spirit:name>tx_out_clk_26</spirit:name>
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|
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|
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|
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|
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|
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<spirit:name>rx_clk_26</spirit:name>
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|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
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|
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|
|
<spirit:physicalPort>
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|
<spirit:name>rx_clk_26</spirit:name>
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|
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|
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|
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|
|
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|
<spirit:busInterface>
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<spirit:name>tx_clk_26</spirit:name>
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|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:portMap>
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<spirit:logicalPort>
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|
<spirit:name>CLK</spirit:name>
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|
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|
<spirit:physicalPort>
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|
<spirit:name>tx_clk_26</spirit:name>
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|
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|
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|
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|
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|
<spirit:name>cpll_ref_clk_27</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
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|
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|
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|
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|
|
<spirit:name>CLK</spirit:name>
|
|
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|
|
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|
|
<spirit:name>cpll_ref_clk_27</spirit:name>
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.CPLL_REF_CLK_27.ASSOCIATED_RESET">up_rx_rst_27:up_tx_rst_27</spirit:value>
|
|
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|
|
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|
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|
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|
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|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_out_clk_27</spirit:name>
|
|
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|
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|
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<spirit:name>tx_out_clk_27</spirit:name>
|
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|
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<spirit:name>CLK</spirit:name>
|
|
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|
|
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<spirit:name>rx_clk_27</spirit:name>
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<spirit:name>CLK</spirit:name>
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|
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<spirit:name>CLK</spirit:name>
|
|
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|
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<spirit:physicalPort>
|
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<spirit:name>tx_clk_27</spirit:name>
|
|
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|
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<spirit:busInterface>
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<spirit:name>cpll_ref_clk_28</spirit:name>
|
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:name>CLK</spirit:name>
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|
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<spirit:name>ASSOCIATED_RESET</spirit:name>
|
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<spirit:value spirit:id="BUSIFPARAM_VALUE.CPLL_REF_CLK_28.ASSOCIATED_RESET">up_rx_rst_28:up_tx_rst_28</spirit:value>
|
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<spirit:name>rx_out_clk_28</spirit:name>
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<spirit:name>CLK</spirit:name>
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|
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<spirit:name>tx_out_clk_28</spirit:name>
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<spirit:name>CLK</spirit:name>
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|
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<spirit:name>CLK</spirit:name>
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<spirit:name>rx_clk_28</spirit:name>
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<spirit:name>tx_clk_28</spirit:name>
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<spirit:logicalPort>
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<spirit:name>CLK</spirit:name>
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|
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<spirit:name>tx_clk_28</spirit:name>
|
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<spirit:name>qpll_ref_clk_28</spirit:name>
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<spirit:name>CLK</spirit:name>
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<spirit:name>qpll_ref_clk_28</spirit:name>
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<spirit:name>cpll_ref_clk_29</spirit:name>
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<spirit:name>CLK</spirit:name>
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<spirit:name>cpll_ref_clk_29</spirit:name>
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|
|
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.CPLL_REF_CLK_29.ASSOCIATED_RESET">up_rx_rst_29:up_tx_rst_29</spirit:value>
|
|
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<spirit:name>CLK</spirit:name>
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|
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|
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:name>CLK</spirit:name>
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<spirit:name>tx_out_clk_29</spirit:name>
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|
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<spirit:name>rx_clk_29</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:name>CLK</spirit:name>
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<spirit:name>rx_clk_29</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:name>CLK</spirit:name>
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<spirit:name>tx_clk_29</spirit:name>
|
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<spirit:name>cpll_ref_clk_30</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:logicalPort>
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<spirit:name>CLK</spirit:name>
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|
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|
<spirit:physicalPort>
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|
<spirit:name>cpll_ref_clk_30</spirit:name>
|
|
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|
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|
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|
<spirit:name>ASSOCIATED_RESET</spirit:name>
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<spirit:value spirit:id="BUSIFPARAM_VALUE.CPLL_REF_CLK_30.ASSOCIATED_RESET">up_rx_rst_30:up_tx_rst_30</spirit:value>
|
|
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|
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<spirit:name>rx_out_clk_30</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:logicalPort>
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<spirit:name>CLK</spirit:name>
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|
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<spirit:physicalPort>
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<spirit:name>rx_out_clk_30</spirit:name>
|
|
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|
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|
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<spirit:name>tx_out_clk_30</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:portMap>
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<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
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|
<spirit:physicalPort>
|
|
<spirit:name>tx_out_clk_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
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|
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|
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<spirit:name>rx_clk_30</spirit:name>
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|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMap>
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<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_clk_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
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|
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|
|
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|
<spirit:busInterface>
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|
<spirit:name>tx_clk_30</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMap>
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<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_clk_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
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|
|
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|
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<spirit:busInterface>
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<spirit:name>cpll_ref_clk_31</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>CLK</spirit:name>
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|
</spirit:logicalPort>
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|
<spirit:physicalPort>
|
|
<spirit:name>cpll_ref_clk_31</spirit:name>
|
|
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|
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|
|
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|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.CPLL_REF_CLK_31.ASSOCIATED_RESET">up_rx_rst_31:up_tx_rst_31</spirit:value>
|
|
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|
|
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<spirit:name>rx_out_clk_31</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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<spirit:master/>
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<spirit:portMap>
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|
<spirit:logicalPort>
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|
<spirit:name>CLK</spirit:name>
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|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_out_clk_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
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|
|
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|
|
<spirit:busInterface>
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|
<spirit:name>tx_out_clk_31</spirit:name>
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|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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<spirit:master/>
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<spirit:portMap>
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<spirit:logicalPort>
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|
<spirit:name>CLK</spirit:name>
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|
</spirit:logicalPort>
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|
<spirit:physicalPort>
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|
<spirit:name>tx_out_clk_31</spirit:name>
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|
</spirit:physicalPort>
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|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_cpll_rst_30</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cpll_rst_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_rx_rst_31</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_tx_rst_31</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_cpll_rst_31</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cpll_rst_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_cm_0</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_enb_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_addr_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_wr_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_wdata_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_rdata_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_ready_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_cm_0" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0) or (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0)">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_0</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_0" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_rx_0</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_pll_locked_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_user_ready_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_done_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbssel_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbscntreset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbscntreset_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbserr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbserr_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbslocked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbslocked_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus_rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_rst_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_lpm_dfe_n_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rate_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_sys_clk_sel_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_out_clk_sel_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_enb_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_addr_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wr_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wdata_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rdata_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_ready_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_rx_0" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_tx_0</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_pll_locked_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_user_ready_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_done_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbsforceerr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbsforceerr_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbssel_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_bufstatus_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_lpm_dfe_n_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rate_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_sys_clk_sel_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_out_clk_sel_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_diffctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_diffctrl_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_postcursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_postcursor_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_precursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_precursor_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_enb_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_addr_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wr_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wdata_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rdata_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_ready_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_tx_0" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_0</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_charisk_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxnotintable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_notintable_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdisperr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_disperr_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_data_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_header_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxblock_sync</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_block_sync_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.rx_0" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_0</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_charisk_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_data_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_header_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.tx_0" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_1</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_1" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_rx_1</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_pll_locked_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_user_ready_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_done_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbssel_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbscntreset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbscntreset_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbserr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbserr_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbslocked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbslocked_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus_rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_rst_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_lpm_dfe_n_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rate_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_sys_clk_sel_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_out_clk_sel_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_enb_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_addr_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wr_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wdata_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rdata_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_ready_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_rx_1" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_tx_1</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_pll_locked_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_user_ready_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_done_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbsforceerr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbsforceerr_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbssel_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_bufstatus_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_lpm_dfe_n_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rate_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_sys_clk_sel_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_out_clk_sel_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_diffctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_diffctrl_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_postcursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_postcursor_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_precursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_precursor_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_enb_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_addr_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wr_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wdata_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rdata_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_ready_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_tx_1" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_1</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_charisk_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxnotintable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_notintable_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdisperr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_disperr_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_data_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_header_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxblock_sync</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_block_sync_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.rx_1" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_1</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_charisk_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_data_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_header_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.tx_1" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_2</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_2" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_rx_2</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_pll_locked_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_user_ready_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_done_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbssel_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbscntreset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbscntreset_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbserr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbserr_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbslocked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbslocked_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus_rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_rst_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_lpm_dfe_n_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rate_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_sys_clk_sel_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_out_clk_sel_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_enb_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_addr_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wr_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wdata_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rdata_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_ready_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_rx_2" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_tx_2</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_pll_locked_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_user_ready_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_done_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbsforceerr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbsforceerr_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbssel_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_bufstatus_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_lpm_dfe_n_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rate_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_sys_clk_sel_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_out_clk_sel_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_diffctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_diffctrl_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_postcursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_postcursor_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_precursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_precursor_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_enb_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_addr_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wr_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wdata_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rdata_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_ready_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_tx_2" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_2</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_charisk_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxnotintable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_notintable_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdisperr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_disperr_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_data_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_header_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxblock_sync</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_block_sync_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.rx_2" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_2</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_charisk_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_data_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_header_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.tx_2" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_3</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_3" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_rx_3</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_pll_locked_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_user_ready_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_done_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbssel_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbscntreset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbscntreset_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbserr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbserr_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbslocked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbslocked_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus_rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_rst_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_lpm_dfe_n_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rate_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_sys_clk_sel_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_out_clk_sel_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_enb_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_addr_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wr_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wdata_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rdata_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_ready_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_rx_3" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_tx_3</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_pll_locked_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_user_ready_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_done_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbsforceerr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbsforceerr_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbssel_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_bufstatus_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_lpm_dfe_n_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rate_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_sys_clk_sel_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_out_clk_sel_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_diffctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_diffctrl_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_postcursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_postcursor_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_precursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_precursor_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_enb_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_addr_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wr_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wdata_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rdata_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_ready_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_tx_3" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_3</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_charisk_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxnotintable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_notintable_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdisperr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_disperr_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_data_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_header_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxblock_sync</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_block_sync_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.rx_3" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_3</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_charisk_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_data_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_header_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.tx_3" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_cm_4</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_enb_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_addr_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_wr_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_wdata_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_rdata_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_ready_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_cm_4" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4) or (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4)">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_4</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_4" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_rx_4</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_pll_locked_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_user_ready_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_done_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbssel_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbscntreset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbscntreset_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbserr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbserr_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbslocked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbslocked_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus_rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_rst_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_lpm_dfe_n_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rate_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_sys_clk_sel_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_out_clk_sel_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_enb_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_addr_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wr_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wdata_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rdata_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_ready_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_rx_4" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_tx_4</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_pll_locked_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_user_ready_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_done_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbsforceerr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbsforceerr_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbssel_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_bufstatus_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_lpm_dfe_n_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rate_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_sys_clk_sel_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_out_clk_sel_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_diffctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_diffctrl_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_postcursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_postcursor_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_precursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_precursor_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_enb_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_addr_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wr_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wdata_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rdata_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_ready_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_tx_4" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_4</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_charisk_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxnotintable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_notintable_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdisperr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_disperr_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_data_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_header_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxblock_sync</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_block_sync_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.rx_4" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_4</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_charisk_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_data_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_header_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.tx_4" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_5</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_5" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_rx_5</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_pll_locked_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_user_ready_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_done_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbssel_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbscntreset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbscntreset_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbserr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbserr_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbslocked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbslocked_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus_rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_rst_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_lpm_dfe_n_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rate_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_sys_clk_sel_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_out_clk_sel_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_enb_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_addr_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wr_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wdata_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rdata_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_ready_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_rx_5" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_tx_5</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_pll_locked_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_user_ready_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_done_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbsforceerr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbsforceerr_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbssel_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_bufstatus_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_lpm_dfe_n_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rate_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_sys_clk_sel_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_out_clk_sel_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_diffctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_diffctrl_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_postcursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_postcursor_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_precursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_precursor_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_enb_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_addr_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wr_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wdata_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rdata_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_ready_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_tx_5" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_5</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_charisk_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxnotintable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_notintable_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdisperr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_disperr_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_data_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_header_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxblock_sync</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_block_sync_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.rx_5" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_5</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_charisk_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_data_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_header_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.tx_5" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_6</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_6" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_rx_6</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_pll_locked_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_user_ready_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_done_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbssel_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbscntreset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbscntreset_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbserr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbserr_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbslocked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbslocked_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus_rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_rst_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_lpm_dfe_n_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rate_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_sys_clk_sel_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_out_clk_sel_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_enb_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_addr_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wr_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wdata_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rdata_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_ready_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_rx_6" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_tx_6</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_pll_locked_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_user_ready_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_done_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbsforceerr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbsforceerr_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbssel_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_bufstatus_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_lpm_dfe_n_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rate_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_sys_clk_sel_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_out_clk_sel_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_diffctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_diffctrl_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_postcursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_postcursor_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_precursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_precursor_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_enb_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_addr_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wr_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wdata_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rdata_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_ready_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_tx_6" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_6</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_charisk_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxnotintable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_notintable_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdisperr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_disperr_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_data_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_header_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxblock_sync</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_block_sync_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.rx_6" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_6</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_charisk_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_data_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_header_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.tx_6" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_7</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_7" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_rx_7</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_pll_locked_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_user_ready_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_done_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbssel_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbscntreset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbscntreset_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbserr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbserr_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbslocked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbslocked_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus_rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_rst_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_lpm_dfe_n_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rate_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_sys_clk_sel_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_out_clk_sel_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_enb_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_addr_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wr_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wdata_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rdata_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_ready_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_rx_7" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_tx_7</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_pll_locked_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_user_ready_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_done_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbsforceerr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbsforceerr_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbssel_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_bufstatus_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_lpm_dfe_n_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rate_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_sys_clk_sel_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_out_clk_sel_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_diffctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_diffctrl_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_postcursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_postcursor_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_precursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_precursor_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_enb_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_addr_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wr_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wdata_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rdata_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_ready_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_tx_7" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_7</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_charisk_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxnotintable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_notintable_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdisperr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_disperr_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_data_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_header_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxblock_sync</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_block_sync_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.rx_7" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_7</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_charisk_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_data_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_header_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.tx_7" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_cm_8</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_enb_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_addr_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_wr_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_wdata_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_rdata_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_ready_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_cm_8" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8) or (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_8</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_8" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_rx_8</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_pll_locked_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_user_ready_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_done_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbssel_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbscntreset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbscntreset_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbserr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbserr_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbslocked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbslocked_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus_rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_rst_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_lpm_dfe_n_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rate_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_sys_clk_sel_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_out_clk_sel_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_enb_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_addr_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wr_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wdata_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rdata_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_ready_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_rx_8" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_tx_8</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_pll_locked_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_user_ready_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_done_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbsforceerr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbsforceerr_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbssel_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_bufstatus_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_lpm_dfe_n_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rate_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_sys_clk_sel_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_out_clk_sel_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_diffctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_diffctrl_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_postcursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_postcursor_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_precursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_precursor_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_enb_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_addr_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wr_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wdata_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rdata_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_ready_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_tx_8" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_8</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_charisk_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxnotintable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_notintable_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdisperr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_disperr_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_data_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_header_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxblock_sync</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_block_sync_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.rx_8" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_8</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_charisk_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_data_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_header_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.tx_8" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_9</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_9" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_rx_9</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_pll_locked_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_user_ready_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_done_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbssel_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbscntreset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbscntreset_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbserr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbserr_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbslocked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbslocked_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus_rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_rst_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_lpm_dfe_n_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rate_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_sys_clk_sel_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_out_clk_sel_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_enb_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_addr_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wr_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wdata_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rdata_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_ready_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_rx_9" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_tx_9</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_pll_locked_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_user_ready_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_done_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbsforceerr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbsforceerr_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbssel_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_bufstatus_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_lpm_dfe_n_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rate_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_sys_clk_sel_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_out_clk_sel_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_diffctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_diffctrl_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_postcursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_postcursor_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_precursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_precursor_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_enb_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_addr_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wr_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wdata_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rdata_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_ready_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_tx_9" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_9</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_charisk_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxnotintable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_notintable_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdisperr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_disperr_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_data_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_header_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxblock_sync</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_block_sync_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.rx_9" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_9</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_charisk_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_data_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_header_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.tx_9" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_10</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_10" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_rx_10</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_pll_locked_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_user_ready_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_done_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbssel_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbscntreset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbscntreset_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbserr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbserr_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbslocked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbslocked_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus_rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_rst_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_lpm_dfe_n_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rate_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_sys_clk_sel_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_out_clk_sel_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_enb_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_addr_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wr_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wdata_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rdata_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_ready_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_rx_10" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_tx_10</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_pll_locked_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_user_ready_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_done_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbsforceerr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbsforceerr_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbssel_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_bufstatus_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_lpm_dfe_n_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rate_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_sys_clk_sel_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_out_clk_sel_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_diffctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_diffctrl_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_postcursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_postcursor_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_precursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_precursor_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_enb_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_addr_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wr_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wdata_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rdata_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_ready_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_tx_10" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_10</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_charisk_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxnotintable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_notintable_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdisperr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_disperr_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_data_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_header_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxblock_sync</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_block_sync_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.rx_10" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_10</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_charisk_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_data_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_header_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.tx_10" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_11</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_11" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_rx_11</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_pll_locked_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_user_ready_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_done_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbssel_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbscntreset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbscntreset_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbserr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbserr_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbslocked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbslocked_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus_rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_rst_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_lpm_dfe_n_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rate_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_sys_clk_sel_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_out_clk_sel_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_enb_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_addr_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wr_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wdata_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rdata_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_ready_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_rx_11" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_tx_11</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_pll_locked_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_user_ready_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_done_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbsforceerr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbsforceerr_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbssel_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_bufstatus_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_lpm_dfe_n_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rate_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_sys_clk_sel_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_out_clk_sel_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_diffctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_diffctrl_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_postcursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_postcursor_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_precursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_precursor_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_enb_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_addr_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wr_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wdata_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rdata_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_ready_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_tx_11" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_11</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_charisk_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxnotintable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_notintable_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdisperr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_disperr_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_data_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_header_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxblock_sync</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_block_sync_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.rx_11" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_11</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_charisk_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_data_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_header_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.tx_11" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_cm_12</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_enb_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_addr_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_wr_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_wdata_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_rdata_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_ready_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_cm_12" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12) or (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_12</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_12" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_rx_12</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_pll_locked_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_user_ready_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_done_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbssel_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbscntreset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbscntreset_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbserr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbserr_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbslocked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbslocked_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus_rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_rst_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_lpm_dfe_n_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rate_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_sys_clk_sel_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_out_clk_sel_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_enb_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_addr_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wr_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wdata_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rdata_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_ready_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_rx_12" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_tx_12</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_pll_locked_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_user_ready_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_done_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbsforceerr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbsforceerr_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbssel_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_bufstatus_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_lpm_dfe_n_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rate_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_sys_clk_sel_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_out_clk_sel_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_diffctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_diffctrl_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_postcursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_postcursor_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_precursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_precursor_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_enb_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_addr_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wr_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wdata_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rdata_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_ready_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_tx_12" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_12</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_charisk_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxnotintable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_notintable_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdisperr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_disperr_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_data_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_header_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxblock_sync</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_block_sync_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.rx_12" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_12</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_charisk_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_data_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_header_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.tx_12" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_13</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_13" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_rx_13</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_pll_locked_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_user_ready_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_done_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbssel_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbscntreset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbscntreset_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbserr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbserr_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbslocked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbslocked_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus_rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_rst_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_lpm_dfe_n_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rate_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_sys_clk_sel_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_out_clk_sel_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_enb_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_addr_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wr_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wdata_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rdata_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_ready_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_rx_13" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_tx_13</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_pll_locked_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_user_ready_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_done_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbsforceerr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbsforceerr_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbssel_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_bufstatus_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_lpm_dfe_n_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rate_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_sys_clk_sel_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_out_clk_sel_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_diffctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_diffctrl_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_postcursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_postcursor_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_precursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_precursor_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_enb_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_addr_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wr_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wdata_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rdata_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_ready_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_tx_13" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_13</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_charisk_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxnotintable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_notintable_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdisperr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_disperr_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_data_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_header_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxblock_sync</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_block_sync_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.rx_13" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_13</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_charisk_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_data_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_header_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.tx_13" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_14</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_14" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_rx_14</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_pll_locked_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_user_ready_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_done_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbssel_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbscntreset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbscntreset_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbserr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbserr_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbslocked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbslocked_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus_rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_rst_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_lpm_dfe_n_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rate_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_sys_clk_sel_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_out_clk_sel_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_enb_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_addr_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wr_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wdata_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rdata_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_ready_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_rx_14" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_tx_14</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_pll_locked_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_user_ready_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_done_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbsforceerr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbsforceerr_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbssel_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_bufstatus_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_lpm_dfe_n_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rate_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_sys_clk_sel_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_out_clk_sel_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_diffctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_diffctrl_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_postcursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_postcursor_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_precursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_precursor_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_enb_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_addr_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wr_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wdata_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rdata_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_ready_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_tx_14" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_14</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_charisk_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxnotintable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_notintable_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdisperr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_disperr_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_data_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_header_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxblock_sync</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_block_sync_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.rx_14" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_14</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_charisk_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_data_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_header_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.tx_14" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_15</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_15" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_rx_15</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_pll_locked_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_user_ready_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_done_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbssel_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbscntreset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbscntreset_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbserr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbserr_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbslocked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbslocked_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus_rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_rst_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_lpm_dfe_n_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rate_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_sys_clk_sel_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_out_clk_sel_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_enb_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_addr_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wr_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wdata_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rdata_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_ready_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_rx_15" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_tx_15</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_pll_locked_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_user_ready_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_done_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbsforceerr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbsforceerr_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbssel_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_bufstatus_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_lpm_dfe_n_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rate_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_sys_clk_sel_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_out_clk_sel_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_diffctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_diffctrl_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_postcursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_postcursor_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_precursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_precursor_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_enb_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_addr_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wr_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wdata_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rdata_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_ready_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_tx_15" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_15</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_charisk_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxnotintable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_notintable_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdisperr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_disperr_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_data_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_header_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxblock_sync</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_block_sync_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.rx_15" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_15</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_charisk_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_data_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_header_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.tx_15" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_cm_16</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_enb_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_addr_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_wr_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_wdata_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_rdata_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_ready_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_cm_16" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 16) or (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 16)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_16</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_16" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 16">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_rx_16</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_pll_locked_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_user_ready_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_done_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbssel_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbscntreset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbscntreset_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbserr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbserr_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbslocked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbslocked_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus_rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_rst_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_lpm_dfe_n_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rate_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_sys_clk_sel_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_out_clk_sel_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_enb_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_addr_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wr_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wdata_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rdata_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_ready_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_rx_16" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 16">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_tx_16</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_pll_locked_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_user_ready_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_done_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbsforceerr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbsforceerr_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbssel_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_bufstatus_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_lpm_dfe_n_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rate_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_sys_clk_sel_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_out_clk_sel_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_diffctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_diffctrl_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_postcursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_postcursor_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_precursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_precursor_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_enb_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_addr_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wr_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wdata_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rdata_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_ready_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_tx_16" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 16">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_16</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_charisk_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxnotintable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_notintable_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdisperr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_disperr_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_data_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_header_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxblock_sync</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_block_sync_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.rx_16" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 16">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_16</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_charisk_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_data_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_header_16</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.tx_16" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 16">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_17</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_17" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 17">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_rx_17</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_pll_locked_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_user_ready_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_done_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbssel_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbscntreset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbscntreset_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbserr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbserr_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbslocked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbslocked_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus_rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_rst_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_lpm_dfe_n_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rate_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_sys_clk_sel_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_out_clk_sel_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_enb_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_addr_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wr_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wdata_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rdata_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_ready_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_rx_17" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 17">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_tx_17</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_pll_locked_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_user_ready_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_done_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbsforceerr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbsforceerr_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbssel_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_bufstatus_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_lpm_dfe_n_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rate_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_sys_clk_sel_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_out_clk_sel_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_diffctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_diffctrl_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_postcursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_postcursor_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_precursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_precursor_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_enb_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_addr_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wr_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wdata_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rdata_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_ready_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_tx_17" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 17">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_17</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_charisk_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxnotintable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_notintable_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdisperr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_disperr_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_data_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_header_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxblock_sync</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_block_sync_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.rx_17" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 17">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_17</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_charisk_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_data_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_header_17</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.tx_17" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 17">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_18</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_18" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 18">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_rx_18</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_pll_locked_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_user_ready_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_done_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbssel_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbscntreset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbscntreset_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbserr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbserr_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbslocked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbslocked_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus_rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_rst_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_lpm_dfe_n_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rate_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_sys_clk_sel_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_out_clk_sel_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_enb_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_addr_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wr_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wdata_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rdata_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_ready_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_rx_18" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 18">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_tx_18</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_pll_locked_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_user_ready_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_done_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbsforceerr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbsforceerr_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbssel_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_bufstatus_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_lpm_dfe_n_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rate_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_sys_clk_sel_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_out_clk_sel_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_diffctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_diffctrl_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_postcursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_postcursor_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_precursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_precursor_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_enb_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_addr_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wr_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wdata_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rdata_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_ready_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_tx_18" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 18">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_18</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_charisk_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxnotintable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_notintable_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdisperr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_disperr_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_data_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_header_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxblock_sync</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_block_sync_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.rx_18" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 18">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_18</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_charisk_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_data_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_header_18</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.tx_18" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 18">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_19</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_19" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 19">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_rx_19</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_pll_locked_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_user_ready_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_done_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbssel_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbscntreset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbscntreset_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbserr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbserr_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbslocked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbslocked_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus_rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_rst_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_lpm_dfe_n_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rate_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_sys_clk_sel_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_out_clk_sel_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_enb_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_addr_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wr_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wdata_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rdata_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_ready_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_rx_19" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 19">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_tx_19</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_pll_locked_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_user_ready_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_done_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbsforceerr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbsforceerr_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbssel_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_bufstatus_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_lpm_dfe_n_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rate_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_sys_clk_sel_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_out_clk_sel_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_diffctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_diffctrl_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_postcursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_postcursor_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_precursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_precursor_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_enb_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_addr_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wr_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wdata_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rdata_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_ready_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_tx_19" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 19">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_19</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_charisk_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxnotintable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_notintable_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdisperr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_disperr_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_data_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_header_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxblock_sync</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_block_sync_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.rx_19" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 19">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_19</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_charisk_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_data_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_header_19</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.tx_19" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 19">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_cm_20</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_enb_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_addr_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_wr_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_wdata_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_rdata_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_ready_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_cm_20" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 20) or (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 20)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_20</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_20" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 20">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_rx_20</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_pll_locked_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_user_ready_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_done_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbssel_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbscntreset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbscntreset_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbserr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbserr_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbslocked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbslocked_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus_rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_rst_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_lpm_dfe_n_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rate_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_sys_clk_sel_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_out_clk_sel_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_enb_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_addr_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wr_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wdata_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rdata_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_ready_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_rx_20" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 20">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_tx_20</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_pll_locked_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_user_ready_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_done_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbsforceerr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbsforceerr_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbssel_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_bufstatus_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_lpm_dfe_n_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rate_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_sys_clk_sel_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_out_clk_sel_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_diffctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_diffctrl_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_postcursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_postcursor_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_precursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_precursor_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_enb_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_addr_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wr_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wdata_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rdata_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_ready_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_tx_20" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 20">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_20</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_charisk_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxnotintable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_notintable_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdisperr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_disperr_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_data_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_header_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxblock_sync</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_block_sync_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.rx_20" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 20">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_20</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_charisk_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_data_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_header_20</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.tx_20" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 20">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_21</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_21" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 21">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_rx_21</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_pll_locked_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_user_ready_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_done_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbssel_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbscntreset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbscntreset_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbserr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbserr_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbslocked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbslocked_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus_rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_rst_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_lpm_dfe_n_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rate_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_sys_clk_sel_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_out_clk_sel_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_enb_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_addr_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wr_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wdata_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rdata_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_ready_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_rx_21" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 21">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_tx_21</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_pll_locked_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_user_ready_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_done_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbsforceerr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbsforceerr_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbssel_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_bufstatus_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_lpm_dfe_n_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rate_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_sys_clk_sel_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_out_clk_sel_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_diffctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_diffctrl_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_postcursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_postcursor_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_precursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_precursor_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_enb_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_addr_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wr_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wdata_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rdata_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_ready_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_tx_21" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 21">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_21</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_charisk_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxnotintable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_notintable_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdisperr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_disperr_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_data_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_header_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxblock_sync</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_block_sync_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.rx_21" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 21">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_21</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_charisk_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_data_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_header_21</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.tx_21" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 21">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_22</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_22" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 22">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_rx_22</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_pll_locked_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_user_ready_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_done_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbssel_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbscntreset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbscntreset_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbserr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbserr_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbslocked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbslocked_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus_rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_rst_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_lpm_dfe_n_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rate_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_sys_clk_sel_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_out_clk_sel_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_enb_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_addr_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wr_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wdata_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rdata_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_ready_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_rx_22" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 22">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_tx_22</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_pll_locked_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_user_ready_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_done_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbsforceerr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbsforceerr_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbssel_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_bufstatus_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_lpm_dfe_n_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rate_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_sys_clk_sel_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_out_clk_sel_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_diffctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_diffctrl_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_postcursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_postcursor_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_precursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_precursor_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_enb_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_addr_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wr_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wdata_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rdata_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_ready_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_tx_22" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 22">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_22</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_charisk_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxnotintable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_notintable_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdisperr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_disperr_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_data_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_header_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxblock_sync</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_block_sync_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.rx_22" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 22">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_22</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_charisk_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_data_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_header_22</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.tx_22" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 22">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_23</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_23" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 23">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_rx_23</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_pll_locked_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_user_ready_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_done_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbssel_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbscntreset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbscntreset_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbserr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbserr_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbslocked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbslocked_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus_rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_rst_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_lpm_dfe_n_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rate_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_sys_clk_sel_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_out_clk_sel_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_enb_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_addr_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wr_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wdata_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rdata_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_ready_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_rx_23" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 23">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_tx_23</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_pll_locked_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_user_ready_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_done_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbsforceerr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbsforceerr_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbssel_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_bufstatus_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_lpm_dfe_n_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rate_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_sys_clk_sel_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_out_clk_sel_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_diffctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_diffctrl_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_postcursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_postcursor_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_precursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_precursor_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_enb_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_addr_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wr_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wdata_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rdata_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_ready_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_tx_23" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 23">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_23</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_charisk_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxnotintable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_notintable_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdisperr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_disperr_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_data_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_header_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxblock_sync</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_block_sync_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.rx_23" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 23">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_23</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_charisk_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_data_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_header_23</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.tx_23" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 23">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_cm_24</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_enb_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_addr_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_wr_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_wdata_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_rdata_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_ready_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_cm_24" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 24) or (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 24)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_24</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_24" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 24">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_rx_24</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_pll_locked_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_user_ready_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_done_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbssel_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbscntreset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbscntreset_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbserr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbserr_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbslocked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbslocked_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus_rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_rst_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_lpm_dfe_n_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rate_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_sys_clk_sel_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_out_clk_sel_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_enb_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_addr_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wr_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wdata_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rdata_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_ready_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_rx_24" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 24">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_tx_24</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_pll_locked_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_user_ready_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_done_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbsforceerr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbsforceerr_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbssel_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_bufstatus_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_lpm_dfe_n_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rate_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_sys_clk_sel_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_out_clk_sel_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_diffctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_diffctrl_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_postcursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_postcursor_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_precursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_precursor_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_enb_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_addr_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wr_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wdata_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rdata_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_ready_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_tx_24" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 24">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_24</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_charisk_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxnotintable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_notintable_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdisperr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_disperr_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_data_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_header_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxblock_sync</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_block_sync_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.rx_24" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 24">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_24</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_charisk_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_data_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_header_24</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.tx_24" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 24">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_25</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_25" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 25">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_rx_25</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_pll_locked_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_user_ready_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_done_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbssel_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbscntreset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbscntreset_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbserr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbserr_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbslocked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbslocked_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus_rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_rst_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_lpm_dfe_n_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rate_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_sys_clk_sel_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_out_clk_sel_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_enb_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_addr_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wr_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wdata_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rdata_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_ready_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_rx_25" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 25">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_tx_25</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_pll_locked_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_user_ready_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_done_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbsforceerr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbsforceerr_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbssel_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_bufstatus_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_lpm_dfe_n_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rate_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_sys_clk_sel_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_out_clk_sel_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_diffctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_diffctrl_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_postcursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_postcursor_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_precursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_precursor_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_enb_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_addr_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wr_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wdata_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rdata_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_ready_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_tx_25" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 25">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_25</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_charisk_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxnotintable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_notintable_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdisperr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_disperr_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_data_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_header_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxblock_sync</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_block_sync_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.rx_25" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 25">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_25</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_charisk_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_data_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_header_25</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.tx_25" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 25">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_26</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_26" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 26">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_rx_26</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_pll_locked_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_user_ready_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_done_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbssel_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbscntreset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbscntreset_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbserr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbserr_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbslocked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbslocked_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus_rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_rst_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_lpm_dfe_n_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rate_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_sys_clk_sel_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_out_clk_sel_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_enb_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_addr_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wr_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wdata_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rdata_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_ready_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_rx_26" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 26">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_tx_26</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_pll_locked_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_user_ready_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_done_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbsforceerr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbsforceerr_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbssel_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_bufstatus_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_lpm_dfe_n_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rate_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_sys_clk_sel_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_out_clk_sel_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_diffctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_diffctrl_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_postcursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_postcursor_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_precursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_precursor_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_enb_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_addr_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wr_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wdata_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rdata_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_ready_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_tx_26" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 26">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_26</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_charisk_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxnotintable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_notintable_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdisperr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_disperr_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_data_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_header_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxblock_sync</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_block_sync_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.rx_26" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 26">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_26</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_charisk_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_data_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_header_26</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.tx_26" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 26">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_27</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_27" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 27">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_rx_27</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_pll_locked_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_user_ready_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_done_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbssel_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbscntreset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbscntreset_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbserr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbserr_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbslocked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbslocked_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus_rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_rst_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_lpm_dfe_n_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rate_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_sys_clk_sel_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_out_clk_sel_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_enb_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_addr_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wr_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wdata_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rdata_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_ready_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_rx_27" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 27">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_tx_27</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_pll_locked_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_user_ready_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_done_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbsforceerr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbsforceerr_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbssel_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_bufstatus_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_lpm_dfe_n_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rate_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_sys_clk_sel_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_out_clk_sel_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_diffctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_diffctrl_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_postcursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_postcursor_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_precursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_precursor_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_enb_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_addr_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wr_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wdata_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rdata_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_ready_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_tx_27" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 27">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_27</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_charisk_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxnotintable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_notintable_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdisperr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_disperr_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_data_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_header_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxblock_sync</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_block_sync_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.rx_27" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 27">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_27</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_charisk_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_data_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_header_27</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.tx_27" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 27">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_cm_28</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_enb_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_addr_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_wr_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_wdata_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_rdata_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_ready_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_cm_28" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 28) or (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 28)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_28</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_28" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 28">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_rx_28</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_pll_locked_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_user_ready_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_done_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbssel_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbscntreset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbscntreset_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbserr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbserr_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbslocked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbslocked_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus_rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_rst_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_lpm_dfe_n_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rate_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_sys_clk_sel_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_out_clk_sel_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_enb_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_addr_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wr_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wdata_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rdata_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_ready_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_rx_28" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 28">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_tx_28</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_pll_locked_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_user_ready_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_done_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbsforceerr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbsforceerr_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbssel_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_bufstatus_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_lpm_dfe_n_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rate_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_sys_clk_sel_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_out_clk_sel_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_diffctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_diffctrl_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_postcursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_postcursor_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_precursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_precursor_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_enb_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_addr_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wr_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wdata_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rdata_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_ready_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_tx_28" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 28">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_28</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_charisk_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxnotintable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_notintable_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdisperr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_disperr_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_data_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_header_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxblock_sync</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_block_sync_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.rx_28" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 28">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_28</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_charisk_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_data_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_header_28</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.tx_28" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 28">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_29</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_29" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 29">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_rx_29</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_pll_locked_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_user_ready_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_done_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbssel_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbscntreset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbscntreset_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbserr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbserr_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbslocked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbslocked_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus_rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_rst_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_lpm_dfe_n_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rate_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_sys_clk_sel_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_out_clk_sel_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_enb_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_addr_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wr_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wdata_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rdata_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_ready_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_rx_29" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 29">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_tx_29</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_pll_locked_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_user_ready_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_done_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbsforceerr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbsforceerr_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbssel_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_bufstatus_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_lpm_dfe_n_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rate_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_sys_clk_sel_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_out_clk_sel_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_diffctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_diffctrl_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_postcursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_postcursor_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_precursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_precursor_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_enb_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_addr_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wr_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wdata_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rdata_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_ready_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_tx_29" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 29">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_29</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_charisk_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxnotintable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_notintable_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdisperr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_disperr_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_data_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_header_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxblock_sync</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_block_sync_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.rx_29" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 29">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_29</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_charisk_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_data_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_header_29</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.tx_29" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 29">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_30</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_30" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 30">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_rx_30</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_pll_locked_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_user_ready_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_done_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbssel_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbscntreset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbscntreset_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbserr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbserr_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbslocked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbslocked_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus_rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_rst_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_lpm_dfe_n_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rate_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_sys_clk_sel_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_out_clk_sel_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_enb_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_addr_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wr_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wdata_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rdata_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_ready_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_rx_30" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 30">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_tx_30</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_pll_locked_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_user_ready_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_done_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbsforceerr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbsforceerr_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbssel_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_bufstatus_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_lpm_dfe_n_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rate_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_sys_clk_sel_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_out_clk_sel_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_diffctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_diffctrl_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_postcursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_postcursor_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_precursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_precursor_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_enb_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_addr_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wr_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wdata_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rdata_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_ready_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_tx_30" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 30">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_30</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_charisk_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxnotintable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_notintable_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdisperr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_disperr_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_data_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_header_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxblock_sync</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_block_sync_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.rx_30" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 30">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_30</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_charisk_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_data_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_header_30</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.tx_30" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 30">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_31</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_31" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 31">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_rx_31</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_pll_locked_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_user_ready_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rst_done_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbssel_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbscntreset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbscntreset_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbserr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbserr_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbslocked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_prbslocked_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus_rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_bufstatus_rst_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_lpm_dfe_n_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rate_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_sys_clk_sel_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_out_clk_sel_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_enb_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_addr_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wr_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_wdata_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_rdata_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_rx_ready_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_rx_31" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 31">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_tx_31</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_pll_locked_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_user_ready_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rst_done_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbsforceerr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbsforceerr_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_prbssel_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_bufstatus_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_lpm_dfe_n_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rate_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_sys_clk_sel_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_out_clk_sel_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_diffctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_diffctrl_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_postcursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_postcursor_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_precursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_precursor_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_enb_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_addr_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wr_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_wdata_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_rdata_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_tx_ready_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_tx_31" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 31">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>rx_31</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_rx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_charisk_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxnotintable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_notintable_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdisperr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_disperr_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_data_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_header_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxblock_sync</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx_block_sync_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.rx_31" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 31">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>tx_31</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_jesd204" spirit:name="jesd204_tx_bus_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txcharisk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_charisk_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_data_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txheader</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx_header_31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.tx_31" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 31">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
</spirit:busInterfaces>
|
|
<spirit:model>
|
|
<spirit:views>
|
|
<spirit:view>
|
|
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
|
<spirit:displayName>Synthesis</spirit:displayName>
|
|
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
|
<spirit:language>Verilog</spirit:language>
|
|
<spirit:modelName>util_adxcvr</spirit:modelName>
|
|
<spirit:fileSetRef>
|
|
<spirit:localName>xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset</spirit:localName>
|
|
</spirit:fileSetRef>
|
|
<spirit:fileSetRef>
|
|
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
|
|
</spirit:fileSetRef>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>viewChecksum</spirit:name>
|
|
<spirit:value>4dc43688</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:view>
|
|
<spirit:view>
|
|
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
|
<spirit:displayName>Simulation</spirit:displayName>
|
|
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
|
<spirit:language>Verilog</spirit:language>
|
|
<spirit:modelName>util_adxcvr</spirit:modelName>
|
|
<spirit:fileSetRef>
|
|
<spirit:localName>xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset</spirit:localName>
|
|
</spirit:fileSetRef>
|
|
<spirit:fileSetRef>
|
|
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
|
</spirit:fileSetRef>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>viewChecksum</spirit:name>
|
|
<spirit:value>01045f07</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:view>
|
|
<spirit:view>
|
|
<spirit:name>xilinx_xpgui</spirit:name>
|
|
<spirit:displayName>UI Layout</spirit:displayName>
|
|
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
|
|
<spirit:fileSetRef>
|
|
<spirit:localName>xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset</spirit:localName>
|
|
</spirit:fileSetRef>
|
|
<spirit:fileSetRef>
|
|
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
|
|
</spirit:fileSetRef>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>viewChecksum</spirit:name>
|
|
<spirit:value>87390f73</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:view>
|
|
<spirit:view>
|
|
<spirit:name>xilinx_blockdiagram</spirit:name>
|
|
<spirit:displayName>Block Diagram</spirit:displayName>
|
|
<spirit:envIdentifier>:vivado.xilinx.com:block.diagram</spirit:envIdentifier>
|
|
<spirit:fileSetRef>
|
|
<spirit:localName>xilinx_blockdiagram_analog_com_user_util_cdc_1_0__ref_view_fileset</spirit:localName>
|
|
</spirit:fileSetRef>
|
|
<spirit:fileSetRef>
|
|
<spirit:localName>xilinx_blockdiagram_view_fileset</spirit:localName>
|
|
</spirit:fileSetRef>
|
|
</spirit:view>
|
|
<spirit:view>
|
|
<spirit:name>xilinx_utilityxitfiles</spirit:name>
|
|
<spirit:displayName>Utility XIT/TTCL</spirit:displayName>
|
|
<spirit:envIdentifier>:vivado.xilinx.com:xit.util</spirit:envIdentifier>
|
|
<spirit:fileSetRef>
|
|
<spirit:localName>xilinx_utilityxitfiles_view_fileset</spirit:localName>
|
|
</spirit:fileSetRef>
|
|
</spirit:view>
|
|
</spirit:views>
|
|
<spirit:ports>
|
|
<spirit:port>
|
|
<spirit:name>up_rstn</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_clk</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>qpll_ref_clk_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_prbscntreset_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_prbserr_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_prbslocked_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_bufstatus_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
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|
|
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_bufstatus_rst_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_lpm_dfe_n_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_rate_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_sys_clk_sel_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_out_clk_sel_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_enb_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_addr_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">11</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_wr_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_wdata_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_rdata_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_ready_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_pll_locked_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_rst_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.up_tx_rst_0" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_user_ready_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
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|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_rst_done_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_bufstatus_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
</spirit:vector>
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_prbsforceerr_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_prbssel_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_lpm_dfe_n_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_rate_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_sys_clk_sel_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_out_clk_sel_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
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|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
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|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_rst_done_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_prbssel_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_prbscntreset_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_prbserr_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_prbslocked_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_bufstatus_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_bufstatus_rst_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_lpm_dfe_n_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_rate_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_sys_clk_sel_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_out_clk_sel_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_enb_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_addr_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">11</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_wr_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_wdata_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_rdata_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_ready_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_pll_locked_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_rst_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.up_tx_rst_1" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_user_ready_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_rst_done_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_bufstatus_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_prbsforceerr_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_prbssel_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_lpm_dfe_n_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_rate_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
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|
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|
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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<xilinx:portInfo>
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|
<xilinx:enablement>
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<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.up_rx_rst_2" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2">true</xilinx:isEnabled>
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|
</xilinx:enablement>
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|
|
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
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|
<spirit:name>up_rx_prbssel_2</spirit:name>
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|
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|
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDefs>
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
</spirit:wireTypeDef>
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|
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_rx_prbslocked_2</spirit:name>
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|
<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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<spirit:port>
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|
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|
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|
<spirit:direction>out</spirit:direction>
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|
<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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<spirit:direction>in</spirit:direction>
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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<spirit:direction>in</spirit:direction>
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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<spirit:direction>in</spirit:direction>
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<spirit:left spirit:format="long">2</spirit:left>
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|
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<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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|
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|
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|
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|
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|
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|
<spirit:direction>in</spirit:direction>
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|
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|
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|
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|
<spirit:name>up_rx_out_clk_sel_2</spirit:name>
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|
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|
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|
<spirit:left spirit:format="long">2</spirit:left>
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|
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|
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|
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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|
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|
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|
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|
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|
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<spirit:typeName>std_logic</spirit:typeName>
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|
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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|
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<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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|
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|
|
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|
|
</spirit:driver>
|
|
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_prbssel_3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
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|
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|
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
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|
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|
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|
|
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|
|
</spirit:driver>
|
|
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_lpm_dfe_n_3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
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|
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|
|
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|
|
</spirit:driver>
|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_rate_3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
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|
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|
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
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|
|
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|
|
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|
|
</spirit:driver>
|
|
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|
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|
<spirit:port>
|
|
<spirit:name>up_tx_sys_clk_sel_3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
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|
|
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|
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|
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|
|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
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|
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|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_out_clk_sel_3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
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|
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_diffctrl_3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_postcursor_3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_precursor_3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
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|
</spirit:vector>
|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_enb_3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
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|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_addr_3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">11</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
</spirit:vector>
|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
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|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_wr_3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
|
</spirit:wireTypeDefs>
|
|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_wdata_3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
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|
</spirit:vector>
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
|
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|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
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|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_rdata_3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
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|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
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|
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|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_ready_3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
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|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>qpll_ref_clk_4</spirit:name>
|
|
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|
|
<spirit:direction>in</spirit:direction>
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|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
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</spirit:wireTypeDef>
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|
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|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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|
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</xilinx:enablement>
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|
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|
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|
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|
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.up_qpll_rst_4" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4) or (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4)">true</xilinx:isEnabled>
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</xilinx:enablement>
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|
</spirit:port>
|
|
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|
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|
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cpll_ref_clk_4" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4) or (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4)">true</xilinx:isEnabled>
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</xilinx:enablement>
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|
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|
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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<xilinx:enablement>
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<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.up_cpll_rst_4" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4) or (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4)">true</xilinx:isEnabled>
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|
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|
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|
|
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|
|
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|
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|
|
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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<xilinx:enablement>
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<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rx_4_p" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4">true</xilinx:isEnabled>
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|
</xilinx:enablement>
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|
</xilinx:portInfo>
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|
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|
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|
|
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|
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|
|
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|
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|
|
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|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
</spirit:wireTypeDef>
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|
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|
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|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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<xilinx:enablement>
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<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rx_4_n" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
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|
</spirit:vendorExtensions>
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|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rx_out_clk_4</spirit:name>
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|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
</spirit:wireTypeDef>
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|
</spirit:wireTypeDefs>
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|
</spirit:wire>
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|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
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|
<xilinx:enablement>
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|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rx_out_clk_4" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4">true</xilinx:isEnabled>
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|
</xilinx:enablement>
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|
</xilinx:portInfo>
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|
</spirit:vendorExtensions>
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|
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|
<spirit:port>
|
|
<spirit:name>rx_out_clk_div2_4</spirit:name>
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_addr_4</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">11</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_wr_4</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_wdata_4</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
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|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_rdata_4</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
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|
</spirit:vector>
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|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_ready_4</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_pll_locked_4</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_rst_4</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.up_tx_rst_4" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_user_ready_4</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_rst_done_4</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_bufstatus_4</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_prbsforceerr_4</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_prbssel_4</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_lpm_dfe_n_4</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_rate_4</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
</spirit:vector>
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
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|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_sys_clk_sel_4</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
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|
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
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|
</spirit:wireTypeDefs>
|
|
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
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|
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_out_clk_sel_4</spirit:name>
|
|
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|
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|
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|
|
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|
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|
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|
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
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|
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_diffctrl_4</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
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|
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
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|
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_postcursor_4</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
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|
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|
|
<spirit:left spirit:format="long">4</spirit:left>
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|
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|
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
|
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
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|
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|
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|
<spirit:port>
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|
<spirit:name>up_tx_precursor_4</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
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|
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|
<spirit:left spirit:format="long">4</spirit:left>
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|
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|
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
</spirit:wireTypeDefs>
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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|
</spirit:driver>
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|
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|
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|
<spirit:port>
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|
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|
|
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|
|
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|
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|
|
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
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|
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|
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|
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|
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|
<spirit:left spirit:format="long">11</spirit:left>
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|
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|
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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|
</spirit:driver>
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|
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|
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|
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|
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|
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|
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|
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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|
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|
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|
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|
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|
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|
<spirit:direction>in</spirit:direction>
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|
<spirit:left spirit:format="long">15</spirit:left>
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|
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|
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<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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|
</spirit:driver>
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|
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|
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|
<spirit:port>
|
|
<spirit:name>up_tx_rdata_4</spirit:name>
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|
<spirit:wire>
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|
<spirit:direction>out</spirit:direction>
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<spirit:left spirit:format="long">15</spirit:left>
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|
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|
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|
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<spirit:typeName>std_logic_vector</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
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|
</spirit:wireTypeDefs>
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|
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|
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|
<spirit:port>
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|
<spirit:name>up_tx_ready_4</spirit:name>
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|
<spirit:wire>
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|
<spirit:direction>out</spirit:direction>
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|
<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
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|
|
</spirit:vector>
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
</spirit:wireTypeDef>
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|
</spirit:wireTypeDefs>
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|
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|
|
</spirit:driver>
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|
|
<spirit:port>
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<spirit:name>up_rx_enb_5</spirit:name>
|
|
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|
|
<spirit:direction>in</spirit:direction>
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|
|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
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</spirit:wire>
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</spirit:port>
|
|
<spirit:port>
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|
<spirit:name>up_rx_addr_5</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">11</spirit:left>
|
|
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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<spirit:port>
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<spirit:name>up_rx_wr_5</spirit:name>
|
|
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<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDefs>
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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<spirit:port>
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<spirit:name>up_rx_wdata_5</spirit:name>
|
|
<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:left spirit:format="long">15</spirit:left>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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<spirit:driver>
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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|
</spirit:driver>
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|
<spirit:port>
|
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<spirit:name>up_rx_rdata_5</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
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|
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<spirit:left spirit:format="long">15</spirit:left>
|
|
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</spirit:vector>
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|
|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
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|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_ready_5</spirit:name>
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|
<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDefs>
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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|
</spirit:wireTypeDefs>
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_pll_locked_5</spirit:name>
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|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
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|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
</spirit:wireTypeDef>
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|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_rst_5</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
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|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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<spirit:driver>
|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
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|
</spirit:wire>
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<spirit:vendorExtensions>
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|
<xilinx:portInfo>
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|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.up_tx_rst_5" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5">true</xilinx:isEnabled>
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|
</xilinx:enablement>
|
|
</xilinx:portInfo>
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_user_ready_5</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
</spirit:wireTypeDefs>
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<spirit:driver>
|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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|
</spirit:driver>
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<spirit:port>
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<spirit:name>up_tx_rst_done_5</spirit:name>
|
|
<spirit:wire>
|
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<spirit:direction>out</spirit:direction>
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|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
</spirit:wireTypeDef>
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|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
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|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_bufstatus_5</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
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|
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|
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|
|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
</spirit:wireTypeDef>
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|
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|
|
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|
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|
|
<spirit:port>
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|
<spirit:name>up_tx_prbsforceerr_5</spirit:name>
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|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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<spirit:port>
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<spirit:name>up_tx_prbssel_5</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
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|
<spirit:left spirit:format="long">3</spirit:left>
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|
<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:name>up_tx_lpm_dfe_n_5</spirit:name>
|
|
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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|
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|
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<spirit:direction>in</spirit:direction>
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<spirit:left spirit:format="long">15</spirit:left>
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|
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_sys_clk_sel_6</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_out_clk_sel_6</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_enb_6</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_addr_6</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">11</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_wr_6</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_wdata_6</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_rdata_6</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_ready_6</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_pll_locked_6</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_rst_6</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.up_tx_rst_6" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_user_ready_6</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_rst_done_6</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_bufstatus_6</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_prbsforceerr_6</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_prbssel_6</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_lpm_dfe_n_6</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_rate_6</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_sys_clk_sel_6</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_out_clk_sel_6</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_diffctrl_6</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_postcursor_6</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_precursor_6</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_enb_6</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_addr_6</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">11</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_wr_6</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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<spirit:left spirit:format="long">15</spirit:left>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:left spirit:format="long">15</spirit:left>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:name>up_rx_ready_7</spirit:name>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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|
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|
|
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|
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|
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|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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|
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|
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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|
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|
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|
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|
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|
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|
<spirit:name>up_tx_diffctrl_8</spirit:name>
|
|
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|
<spirit:direction>in</spirit:direction>
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|
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|
<spirit:left spirit:format="long">4</spirit:left>
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|
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|
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|
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|
|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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|
|
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|
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|
|
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|
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|
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|
<spirit:port>
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|
<spirit:name>up_tx_postcursor_8</spirit:name>
|
|
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|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:left spirit:format="long">4</spirit:left>
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|
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|
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|
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|
|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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|
|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
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|
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|
<spirit:port>
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|
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|
|
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|
|
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|
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|
<spirit:left spirit:format="long">4</spirit:left>
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|
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|
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|
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|
|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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|
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|
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|
|
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|
|
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|
|
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_enb_8</spirit:name>
|
|
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|
|
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|
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|
|
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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|
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|
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|
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|
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_addr_8</spirit:name>
|
|
<spirit:wire>
|
|
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|
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|
|
<spirit:left spirit:format="long">11</spirit:left>
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|
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|
|
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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|
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|
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|
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|
|
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|
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|
|
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|
|
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|
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|
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|
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|
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|
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|
<spirit:port>
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|
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|
|
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|
<spirit:left spirit:format="long">15</spirit:left>
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|
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|
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|
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|
|
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|
|
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|
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<spirit:left spirit:format="long">15</spirit:left>
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|
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|
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|
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|
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|
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
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|
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|
|
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|
|
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|
|
<spirit:name>up_es_rdata_9</spirit:name>
|
|
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|
|
<spirit:direction>out</spirit:direction>
|
|
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|
<spirit:left spirit:format="long">15</spirit:left>
|
|
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|
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
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|
|
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|
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|
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<spirit:port>
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|
<spirit:name>up_es_ready_9</spirit:name>
|
|
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<spirit:direction>out</spirit:direction>
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
</spirit:wireTypeDef>
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|
</spirit:wireTypeDefs>
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|
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|
<spirit:port>
|
|
<spirit:name>up_es_reset_9</spirit:name>
|
|
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
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<spirit:name>up_rx_rst_9</spirit:name>
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<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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<xilinx:portInfo>
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<xilinx:enablement>
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<spirit:name>up_rx_user_ready_9</spirit:name>
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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<spirit:port>
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<spirit:name>up_rx_rst_done_9</spirit:name>
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|
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
</spirit:wireTypeDefs>
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|
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|
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<spirit:name>up_rx_prbssel_9</spirit:name>
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|
<spirit:wire>
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<spirit:direction>in</spirit:direction>
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|
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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|
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<spirit:port>
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<spirit:name>up_rx_prbscntreset_9</spirit:name>
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|
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<spirit:direction>in</spirit:direction>
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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<spirit:name>up_rx_prbserr_9</spirit:name>
|
|
<spirit:wire>
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|
<spirit:direction>out</spirit:direction>
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|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
</spirit:wireTypeDefs>
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|
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|
|
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|
|
<spirit:name>up_rx_prbslocked_9</spirit:name>
|
|
<spirit:wire>
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|
<spirit:direction>out</spirit:direction>
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
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|
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|
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_rx_bufstatus_9</spirit:name>
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|
<spirit:wire>
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|
<spirit:direction>out</spirit:direction>
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|
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|
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|
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|
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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|
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|
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|
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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|
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|
|
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|
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
|
<spirit:name>up_tx_rst_done_9</spirit:name>
|
|
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|
|
<spirit:direction>out</spirit:direction>
|
|
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|
|
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|
<spirit:typeName>std_logic</spirit:typeName>
|
|
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|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_bufstatus_9</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
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|
|
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|
|
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|
|
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_prbsforceerr_9</spirit:name>
|
|
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|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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|
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|
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|
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|
|
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|
|
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|
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|
<spirit:port>
|
|
<spirit:name>up_tx_prbssel_9</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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<spirit:name>up_tx_lpm_dfe_n_9</spirit:name>
|
|
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|
|
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|
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
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|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
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|
<spirit:port>
|
|
<spirit:name>up_tx_rate_9</spirit:name>
|
|
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|
|
<spirit:direction>in</spirit:direction>
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|
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|
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|
|
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|
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
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|
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|
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|
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|
|
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|
|
</spirit:driver>
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|
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|
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|
<spirit:port>
|
|
<spirit:name>up_tx_sys_clk_sel_9</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
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|
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|
|
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|
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
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|
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|
|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_out_clk_sel_9</spirit:name>
|
|
<spirit:wire>
|
|
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|
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|
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|
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|
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
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|
|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
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|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_diffctrl_9</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
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|
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_postcursor_9</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
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|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
</spirit:wireTypeDef>
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|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
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|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_precursor_9</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
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|
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
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|
|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_enb_9</spirit:name>
|
|
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|
|
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|
|
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|
|
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|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
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|
|
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
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|
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_addr_9</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:left spirit:format="long">11</spirit:left>
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|
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|
|
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|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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|
|
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
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|
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|
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|
|
<spirit:port>
|
|
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|
|
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|
|
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|
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|
|
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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|
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|
|
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|
<spirit:left spirit:format="long">15</spirit:left>
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|
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|
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<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
|
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<spirit:left spirit:format="long">15</spirit:left>
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|
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|
|
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|
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|
|
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|
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|
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|
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|
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|
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<spirit:name>cpll_ref_clk_10</spirit:name>
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rx_10_n" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10">false</xilinx:isEnabled>
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</xilinx:enablement>
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|
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|
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|
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<spirit:typeName>std_logic</spirit:typeName>
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|
</xilinx:enablement>
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|
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|
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|
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|
<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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|
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|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_es_wdata_10</spirit:name>
|
|
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|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
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|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
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|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_es_rdata_10</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
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|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
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|
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
</spirit:wireTypeDef>
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|
</spirit:wireTypeDefs>
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|
</spirit:wire>
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_es_ready_10</spirit:name>
|
|
<spirit:wire>
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|
<spirit:direction>out</spirit:direction>
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|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_es_reset_10</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
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|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
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|
</spirit:wireTypeDefs>
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|
<spirit:driver>
|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
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|
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_rx_pll_locked_10</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_rst_10</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.up_rx_rst_10" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_user_ready_10</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_rst_done_10</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_prbssel_10</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_prbscntreset_10</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_prbserr_10</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_prbslocked_10</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_bufstatus_10</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_rx_bufstatus_rst_10</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
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|
|
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|
|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_rx_lpm_dfe_n_10</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
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|
|
</spirit:wireTypeDefs>
|
|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
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|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_rate_10</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
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|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_sys_clk_sel_10</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
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|
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
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|
|
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|
|
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|
|
</spirit:wireTypeDefs>
|
|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
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|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_out_clk_sel_10</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
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|
|
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|
|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
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|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_enb_10</spirit:name>
|
|
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|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
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|
|
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
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|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_rx_addr_10</spirit:name>
|
|
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|
|
<spirit:direction>in</spirit:direction>
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|
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|
|
<spirit:left spirit:format="long">11</spirit:left>
|
|
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|
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|
|
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|
|
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|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
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|
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|
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|
|
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|
|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
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|
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|
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|
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|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
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|
|
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|
|
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|
|
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|
|
<spirit:name>up_rx_wdata_10</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
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|
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|
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|
|
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|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
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|
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|
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|
|
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|
|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
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|
|
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|
|
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|
|
<spirit:name>up_rx_rdata_10</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
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|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
</spirit:vector>
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_ready_10</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
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|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_pll_locked_10</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_rst_10</spirit:name>
|
|
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|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
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|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
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|
|
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|
|
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|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.up_tx_rst_10" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10">false</xilinx:isEnabled>
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|
</xilinx:enablement>
|
|
</xilinx:portInfo>
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|
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|
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|
|
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|
|
<spirit:name>up_tx_user_ready_10</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
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|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_rst_done_10</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_bufstatus_10</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
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|
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|
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
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|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_prbsforceerr_10</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
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|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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|
</spirit:driver>
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|
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|
<spirit:port>
|
|
<spirit:name>up_tx_prbssel_10</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_lpm_dfe_n_10</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_rate_10</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
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|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_sys_clk_sel_10</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_out_clk_sel_10</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
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|
</spirit:vector>
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_diffctrl_10</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_postcursor_10</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_precursor_10</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
</spirit:vector>
|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
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|
|
</spirit:wireTypeDefs>
|
|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_enb_10</spirit:name>
|
|
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|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
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|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
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|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_addr_10</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:left spirit:format="long">11</spirit:left>
|
|
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|
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|
|
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|
|
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|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
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|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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|
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|
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|
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
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|
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|
|
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
|
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|
|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
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|
|
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|
|
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|
|
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|
|
<spirit:name>up_tx_rdata_10</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
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|
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|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
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|
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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|
|
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|
|
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|
|
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|
|
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|
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|
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|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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|
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|
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|
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|
|
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|
|
<spirit:name>cpll_ref_clk_11</spirit:name>
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|
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|
<spirit:typeName>std_logic</spirit:typeName>
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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|
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|
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|
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|
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|
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|
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|
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|
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<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rx_11_p" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11">false</xilinx:isEnabled>
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|
</xilinx:enablement>
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|
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|
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|
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|
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|
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|
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|
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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|
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<xilinx:enablement>
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<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rx_11_n" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11">false</xilinx:isEnabled>
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|
</xilinx:enablement>
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|
</xilinx:portInfo>
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|
</spirit:vendorExtensions>
|
|
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|
|
<spirit:port>
|
|
<spirit:name>rx_out_clk_11</spirit:name>
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|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
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|
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
|
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|
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|
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|
|
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|
|
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|
|
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
|
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|
<spirit:port>
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|
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|
|
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|
|
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|
|
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:name>up_rx_out_clk_sel_12</spirit:name>
|
|
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|
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<spirit:left spirit:format="long">2</spirit:left>
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|
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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|
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_rx_enb_12</spirit:name>
|
|
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|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
</spirit:wireTypeDef>
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|
</spirit:wireTypeDefs>
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
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|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_addr_12</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">11</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
</spirit:vector>
|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_wr_12</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_wdata_12</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_rdata_12</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_ready_12</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_pll_locked_12</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_rst_12</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.up_tx_rst_12" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
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|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_user_ready_12</spirit:name>
|
|
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|
|
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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|
|
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|
|
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|
|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
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|
|
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|
|
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|
|
<spirit:port>
|
|
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|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
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|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_bufstatus_12</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
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|
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
|
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|
|
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|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_prbsforceerr_12</spirit:name>
|
|
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|
|
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|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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|
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|
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|
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|
|
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|
|
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|
|
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|
|
<spirit:port>
|
|
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|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
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|
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|
|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
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|
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|
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|
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|
|
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|
|
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|
|
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
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|
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|
|
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|
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|
|
<spirit:wire>
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|
<spirit:direction>in</spirit:direction>
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|
<spirit:left spirit:format="long">2</spirit:left>
|
|
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|
|
<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
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|
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|
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|
|
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|
|
<spirit:name>up_tx_sys_clk_sel_12</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
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|
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|
<spirit:left spirit:format="long">1</spirit:left>
|
|
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|
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|
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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|
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|
<spirit:name>up_tx_out_clk_sel_12</spirit:name>
|
|
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|
<spirit:direction>in</spirit:direction>
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|
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<spirit:left spirit:format="long">2</spirit:left>
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|
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|
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|
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<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
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|
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_diffctrl_12</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
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|
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|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
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|
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|
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
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|
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_postcursor_12</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
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|
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|
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|
|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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|
|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
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|
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_precursor_12</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:left spirit:format="long">4</spirit:left>
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|
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|
|
</spirit:vector>
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|
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|
|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
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<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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|
|
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|
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|
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|
|
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|
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|
|
<spirit:name>up_rx_bufstatus_13</spirit:name>
|
|
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|
|
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|
|
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|
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|
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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|
|
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|
|
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|
|
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|
|
<spirit:name>up_rx_bufstatus_rst_13</spirit:name>
|
|
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|
|
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|
|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
|
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|
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|
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|
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
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|
|
<spirit:port>
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|
<spirit:name>up_rx_sys_clk_sel_13</spirit:name>
|
|
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|
<spirit:direction>in</spirit:direction>
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|
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<spirit:left spirit:format="long">1</spirit:left>
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|
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_rx_out_clk_sel_13</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
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|
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|
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|
|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
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|
|
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_rx_enb_13</spirit:name>
|
|
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|
|
<spirit:direction>in</spirit:direction>
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_rx_addr_13</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">11</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
</spirit:vector>
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_rx_wr_13</spirit:name>
|
|
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|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_rx_wdata_13</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_rx_rdata_13</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
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|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
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|
</spirit:vector>
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_rx_ready_13</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_pll_locked_13</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
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|
|
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|
|
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|
|
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|
|
<spirit:port>
|
|
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|
|
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|
|
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|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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|
|
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|
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|
|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
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|
|
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|
|
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|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.up_tx_rst_13" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13">false</xilinx:isEnabled>
|
|
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|
|
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|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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|
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|
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|
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|
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|
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|
|
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|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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|
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|
|
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|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_bufstatus_13</spirit:name>
|
|
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|
|
<spirit:direction>out</spirit:direction>
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|
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|
<spirit:left spirit:format="long">1</spirit:left>
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|
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|
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|
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|
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|
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|
|
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|
|
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|
|
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|
|
<spirit:name>up_tx_prbsforceerr_13</spirit:name>
|
|
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|
|
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|
|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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|
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|
|
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|
|
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|
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|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
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|
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<spirit:typeName>std_logic_vector</spirit:typeName>
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|
|
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|
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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|
|
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|
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|
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|
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<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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|
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|
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|
|
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|
<spirit:direction>in</spirit:direction>
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|
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<spirit:left spirit:format="long">1</spirit:left>
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|
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|
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|
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<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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<spirit:name>up_tx_out_clk_sel_13</spirit:name>
|
|
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<spirit:left spirit:format="long">2</spirit:left>
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|
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|
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|
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|
|
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|
|
<spirit:name>up_tx_diffctrl_13</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
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|
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|
<spirit:left spirit:format="long">4</spirit:left>
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|
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|
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|
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<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
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|
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_postcursor_13</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
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|
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|
|
<spirit:left spirit:format="long">4</spirit:left>
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|
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|
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|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_prbserr_14</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_prbslocked_14</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_bufstatus_14</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_bufstatus_rst_14</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_lpm_dfe_n_14</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_rate_14</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_sys_clk_sel_14</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_out_clk_sel_14</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_enb_14</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_addr_14</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">11</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_wr_14</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_wdata_14</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_rdata_14</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_ready_14</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_pll_locked_14</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_rst_14</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.up_tx_rst_14" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_user_ready_14</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_rst_done_14</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_bufstatus_14</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_prbsforceerr_14</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_prbssel_14</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_lpm_dfe_n_14</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_rate_14</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_sys_clk_sel_14</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_out_clk_sel_14</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_prbssel_15</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_prbscntreset_15</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_prbserr_15</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_prbslocked_15</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_bufstatus_15</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_bufstatus_rst_15</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_lpm_dfe_n_15</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_rate_15</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_sys_clk_sel_15</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_out_clk_sel_15</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_enb_15</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_addr_15</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">11</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_wr_15</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_wdata_15</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_rdata_15</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_ready_15</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_pll_locked_15</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_rst_15</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.up_tx_rst_15" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_user_ready_15</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_rst_done_15</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_bufstatus_15</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_prbsforceerr_15</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_prbssel_15</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_lpm_dfe_n_15</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_rate_15</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_sys_clk_sel_15</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_es_enb_16</spirit:name>
|
|
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|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
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|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
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|
|
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|
|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
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|
|
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|
|
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|
|
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|
|
<spirit:name>up_es_addr_16</spirit:name>
|
|
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|
|
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|
|
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|
|
<spirit:left spirit:format="long">11</spirit:left>
|
|
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|
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|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
</spirit:wireTypeDef>
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|
</spirit:wireTypeDefs>
|
|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
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|
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_es_wr_16</spirit:name>
|
|
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|
|
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|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
</spirit:wireTypeDef>
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|
</spirit:wireTypeDefs>
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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|
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|
<spirit:port>
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|
<spirit:name>up_es_wdata_16</spirit:name>
|
|
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|
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|
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|
<spirit:left spirit:format="long">15</spirit:left>
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|
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
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|
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|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_es_rdata_16</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_es_ready_16</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_es_reset_16</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_pll_locked_16</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_rst_16</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.up_rx_rst_16" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 16">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_user_ready_16</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_rst_done_16</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_prbssel_16</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_prbscntreset_16</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
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|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_prbserr_16</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_prbslocked_16</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_rx_bufstatus_16</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
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|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
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|
|
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|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
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|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
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|
|
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|
|
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|
|
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|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
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|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
<spirit:name>up_rx_lpm_dfe_n_16</spirit:name>
|
|
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|
|
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|
|
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|
|
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|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
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|
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|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
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|
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|
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|
|
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|
|
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|
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|
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|
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|
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|
|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
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|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_rx_out_clk_sel_16</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
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|
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|
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|
|
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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|
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|
|
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|
|
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|
|
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|
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|
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|
|
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|
|
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|
|
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|
|
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|
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|
|
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|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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|
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|
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|
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|
|
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|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
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|
|
<spirit:left spirit:format="long">11</spirit:left>
|
|
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|
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|
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|
|
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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|
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|
|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
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|
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|
|
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|
|
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|
|
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|
|
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|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
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|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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|
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|
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|
|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
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|
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|
|
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
|
</spirit:wireTypeDefs>
|
|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
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|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_rdata_16</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
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|
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|
|
<spirit:left spirit:format="long">15</spirit:left>
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|
<spirit:right spirit:format="long">0</spirit:right>
|
|
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|
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<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
|
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|
|
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|
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|
<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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|
|
<spirit:name>up_tx_pll_locked_16</spirit:name>
|
|
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|
|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
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|
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|
|
<spirit:name>up_tx_rst_16</spirit:name>
|
|
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|
<spirit:direction>in</spirit:direction>
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:name>up_tx_rst_done_16</spirit:name>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
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|
<spirit:port>
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|
<spirit:name>up_tx_bufstatus_16</spirit:name>
|
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<spirit:direction>out</spirit:direction>
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
</spirit:wireTypeDef>
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|
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|
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_prbsforceerr_16</spirit:name>
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|
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<spirit:direction>in</spirit:direction>
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:name>up_tx_prbssel_16</spirit:name>
|
|
<spirit:wire>
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|
<spirit:direction>in</spirit:direction>
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|
<spirit:left spirit:format="long">3</spirit:left>
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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<spirit:name>up_tx_lpm_dfe_n_16</spirit:name>
|
|
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<spirit:direction>in</spirit:direction>
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|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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|
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|
|
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|
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|
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|
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|
|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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|
|
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|
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|
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|
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|
|
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|
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|
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|
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|
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|
|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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|
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|
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|
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|
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|
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|
|
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|
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|
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|
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|
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|
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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|
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|
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|
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|
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|
<spirit:left spirit:format="long">4</spirit:left>
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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<spirit:typeName>std_logic</spirit:typeName>
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<xilinx:portInfo>
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|
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|
|
<spirit:direction>in</spirit:direction>
|
|
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<spirit:left spirit:format="long">15</spirit:left>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:name>up_tx_pll_locked_17</spirit:name>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:name>up_tx_rst_17</spirit:name>
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<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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<xilinx:portInfo>
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<spirit:name>up_tx_user_ready_17</spirit:name>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:port>
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<spirit:name>up_tx_rst_done_17</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
</spirit:wireTypeDefs>
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|
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|
<spirit:port>
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|
<spirit:name>up_tx_bufstatus_17</spirit:name>
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|
<spirit:wire>
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|
<spirit:direction>out</spirit:direction>
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|
<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
<spirit:port>
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|
<spirit:name>up_tx_prbsforceerr_17</spirit:name>
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|
<spirit:wire>
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|
<spirit:direction>in</spirit:direction>
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:port>
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<spirit:name>up_tx_prbssel_17</spirit:name>
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|
<spirit:wire>
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|
<spirit:direction>in</spirit:direction>
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|
<spirit:left spirit:format="long">3</spirit:left>
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:name>up_tx_lpm_dfe_n_17</spirit:name>
|
|
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|
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
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<spirit:name>up_tx_rate_17</spirit:name>
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|
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|
<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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|
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|
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|
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|
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|
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|
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:name>up_es_enb_18</spirit:name>
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<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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<spirit:port>
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<spirit:name>up_es_addr_18</spirit:name>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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<spirit:port>
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<spirit:name>up_es_wdata_18</spirit:name>
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<spirit:direction>in</spirit:direction>
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<spirit:left spirit:format="long">15</spirit:left>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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<spirit:port>
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<spirit:name>up_es_rdata_18</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:left spirit:format="long">15</spirit:left>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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<spirit:port>
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<spirit:name>up_es_ready_18</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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<spirit:port>
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<spirit:name>up_es_reset_18</spirit:name>
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<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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<spirit:name>up_rx_pll_locked_18</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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<spirit:port>
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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<xilinx:portInfo>
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|
<xilinx:enablement>
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<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.up_rx_rst_18" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 18">false</xilinx:isEnabled>
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|
<spirit:typeName>std_logic</spirit:typeName>
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<spirit:wire>
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
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</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_addr_18</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">11</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_wr_18</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_wdata_18</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_rdata_18</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_ready_18</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_pll_locked_18</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_rst_18</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.up_tx_rst_18" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 18">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_user_ready_18</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_rst_done_18</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_bufstatus_18</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_prbsforceerr_18</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_prbssel_18</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_lpm_dfe_n_18</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_rate_18</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
</spirit:vector>
|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
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|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_sys_clk_sel_18</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
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|
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|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
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|
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|
|
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|
|
</spirit:wireTypeDefs>
|
|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
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|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_out_clk_sel_18</spirit:name>
|
|
<spirit:wire>
|
|
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|
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|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
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|
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|
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|
|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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|
|
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
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|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_diffctrl_18</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
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|
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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|
|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
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|
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_postcursor_18</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
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|
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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|
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|
|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
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|
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_precursor_18</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
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|
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|
|
<spirit:left spirit:format="long">4</spirit:left>
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|
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|
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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|
|
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
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|
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_enb_18</spirit:name>
|
|
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|
|
<spirit:direction>in</spirit:direction>
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|
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|
|
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|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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|
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|
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|
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|
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|
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|
|
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|
|
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|
|
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|
|
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|
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|
|
<spirit:left spirit:format="long">11</spirit:left>
|
|
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|
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|
|
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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|
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|
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|
|
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|
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|
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|
|
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|
|
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|
|
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|
|
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|
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|
|
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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|
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
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|
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|
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|
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|
|
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|
|
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|
|
<spirit:direction>in</spirit:direction>
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|
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|
<spirit:left spirit:format="long">15</spirit:left>
|
|
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|
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|
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<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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|
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|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
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|
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|
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|
|
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|
|
<spirit:name>up_tx_rdata_18</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
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|
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|
<spirit:left spirit:format="long">15</spirit:left>
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|
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|
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|
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|
<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
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|
</spirit:wireTypeDef>
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|
</spirit:wireTypeDefs>
|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_ready_18</spirit:name>
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|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
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|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
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|
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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<spirit:name>up_rx_addr_19</spirit:name>
|
|
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<spirit:left spirit:format="long">11</spirit:left>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:left spirit:format="long">15</spirit:left>
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<spirit:left spirit:format="long">15</spirit:left>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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|
</spirit:wireTypeDefs>
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<spirit:port>
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<spirit:name>up_rx_ready_19</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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<spirit:port>
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<spirit:name>up_tx_pll_locked_19</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
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<spirit:port>
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<spirit:name>up_tx_rst_19</spirit:name>
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|
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<spirit:direction>in</spirit:direction>
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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<xilinx:portInfo>
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|
<xilinx:enablement>
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|
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
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<spirit:port>
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<spirit:name>up_tx_rst_done_19</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
</spirit:wireTypeDefs>
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|
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|
<spirit:port>
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|
<spirit:name>up_tx_bufstatus_19</spirit:name>
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|
<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:left spirit:format="long">15</spirit:left>
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|
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<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_rst_done_20</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_prbssel_20</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_prbscntreset_20</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_prbserr_20</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_prbslocked_20</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_bufstatus_20</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_bufstatus_rst_20</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_lpm_dfe_n_20</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_rate_20</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_sys_clk_sel_20</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_out_clk_sel_20</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_enb_20</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_addr_20</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">11</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_wr_20</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_wdata_20</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_rdata_20</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_ready_20</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_pll_locked_20</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_rst_20</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.up_tx_rst_20" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 20">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_user_ready_20</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_rst_done_20</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_bufstatus_20</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_prbsforceerr_20</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_prbssel_20</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_lpm_dfe_n_20</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_rate_20</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
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|
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|
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|
|
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|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
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<xilinx:portInfo>
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|
<xilinx:enablement>
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|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.up_rx_rst_21" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 21">false</xilinx:isEnabled>
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|
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
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|
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|
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|
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|
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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|
<spirit:port>
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|
<spirit:name>up_rx_prbserr_21</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
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|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
</spirit:wireTypeDef>
|
|
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|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_rx_prbslocked_21</spirit:name>
|
|
<spirit:wire>
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|
<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDefs>
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|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
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|
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|
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|
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|
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|
<spirit:port>
|
|
<spirit:name>up_rx_bufstatus_21</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
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|
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|
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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|
|
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|
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|
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|
<spirit:name>up_rx_bufstatus_rst_21</spirit:name>
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|
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<spirit:direction>in</spirit:direction>
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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|
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|
<spirit:port>
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|
<spirit:name>up_rx_lpm_dfe_n_21</spirit:name>
|
|
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|
<spirit:direction>in</spirit:direction>
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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|
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|
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|
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|
<spirit:direction>in</spirit:direction>
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|
<spirit:left spirit:format="long">2</spirit:left>
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|
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|
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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|
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|
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|
|
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|
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|
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|
|
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|
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|
|
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|
<spirit:direction>in</spirit:direction>
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|
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|
<spirit:left spirit:format="long">1</spirit:left>
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|
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|
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|
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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|
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|
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|
<spirit:name>up_rx_out_clk_sel_21</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
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|
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|
<spirit:left spirit:format="long">2</spirit:left>
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|
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|
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|
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|
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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|
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|
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|
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|
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|
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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<spirit:left spirit:format="long">11</spirit:left>
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|
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|
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|
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|
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<spirit:left spirit:format="long">15</spirit:left>
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|
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<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.tx_22_n" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 22">false</xilinx:isEnabled>
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<spirit:direction>out</spirit:direction>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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|
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<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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|
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|
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|
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|
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<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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|
|
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|
|
<spirit:name>up_tx_rst_done_23</spirit:name>
|
|
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|
|
<spirit:direction>out</spirit:direction>
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|
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|
|
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|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_bufstatus_23</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
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|
|
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|
|
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|
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
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|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_prbsforceerr_23</spirit:name>
|
|
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|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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|
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|
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|
|
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|
|
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|
<spirit:port>
|
|
<spirit:name>up_tx_prbssel_23</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
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|
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|
|
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|
|
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<spirit:name>up_tx_lpm_dfe_n_23</spirit:name>
|
|
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|
|
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|
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
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|
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|
|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_rate_23</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
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|
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
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|
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|
|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_sys_clk_sel_23</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
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|
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_out_clk_sel_23</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
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|
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_diffctrl_23</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
</spirit:vector>
|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
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|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_postcursor_23</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_precursor_23</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
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|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_enb_23</spirit:name>
|
|
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|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
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|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_addr_23</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">11</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
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|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
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|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
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|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_wr_23</spirit:name>
|
|
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|
|
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|
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|
|
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|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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|
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|
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|
|
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
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|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_wdata_23</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
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|
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|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
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|
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|
|
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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|
|
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
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|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_rdata_23</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
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|
<spirit:left spirit:format="long">15</spirit:left>
|
|
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|
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|
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
|
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|
|
</spirit:wireTypeDefs>
|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_ready_23</spirit:name>
|
|
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|
|
<spirit:direction>out</spirit:direction>
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|
|
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|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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|
|
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|
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|
|
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|
|
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|
|
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|
|
<spirit:name>qpll_ref_clk_24</spirit:name>
|
|
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|
|
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|
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|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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</xilinx:enablement>
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|
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|
<spirit:typeName>std_logic</spirit:typeName>
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</xilinx:enablement>
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|
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|
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|
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cpll_ref_clk_24" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 24) or (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 24)">false</xilinx:isEnabled>
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</xilinx:enablement>
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|
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|
</xilinx:enablement>
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|
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|
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|
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|
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|
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rx_24_p" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 24">false</xilinx:isEnabled>
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|
</xilinx:enablement>
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|
</xilinx:portInfo>
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|
</spirit:vendorExtensions>
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|
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|
|
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|
|
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|
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|
|
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|
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|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_out_clk_sel_24</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_enb_24</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_addr_24</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">11</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_wr_24</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_wdata_24</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_rdata_24</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_ready_24</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_pll_locked_24</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_rst_24</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.up_tx_rst_24" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 24">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_user_ready_24</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_rst_done_24</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_bufstatus_24</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_prbsforceerr_24</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_prbssel_24</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_lpm_dfe_n_24</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_rate_24</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_sys_clk_sel_24</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_out_clk_sel_24</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_diffctrl_24</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_postcursor_24</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_precursor_24</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_enb_24</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_addr_24</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">11</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_wr_24</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_wdata_24</spirit:name>
|
|
<spirit:wire>
|
|
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</spirit:driver>
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_rx_rate_25</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
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|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_rx_sys_clk_sel_25</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
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|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
</spirit:wireTypeDef>
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|
</spirit:wireTypeDefs>
|
|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_rx_out_clk_sel_25</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
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|
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|
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
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|
<spirit:port>
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|
<spirit:name>up_rx_enb_25</spirit:name>
|
|
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|
|
<spirit:direction>in</spirit:direction>
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|
|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
</spirit:wireTypeDef>
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|
</spirit:wireTypeDefs>
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|
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
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|
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_rx_addr_25</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">11</spirit:left>
|
|
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|
</spirit:vector>
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_wr_25</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
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|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_wdata_25</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
</spirit:vector>
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|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_rdata_25</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_ready_25</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_pll_locked_25</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_rst_25</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.up_tx_rst_25" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 25">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_user_ready_25</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
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|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_rst_done_25</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_bufstatus_25</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
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|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_prbsforceerr_25</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
</spirit:wireTypeDefs>
|
|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_prbssel_25</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
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|
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|
|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
</spirit:wireTypeDefs>
|
|
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
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|
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|
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|
<spirit:port>
|
|
<spirit:name>up_tx_lpm_dfe_n_25</spirit:name>
|
|
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|
|
<spirit:direction>in</spirit:direction>
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
|
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
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|
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|
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|
|
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|
|
<spirit:name>up_tx_rate_25</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
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|
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|
<spirit:left spirit:format="long">2</spirit:left>
|
|
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|
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|
|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
|
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
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|
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_sys_clk_sel_25</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
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|
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|
<spirit:left spirit:format="long">1</spirit:left>
|
|
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|
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|
|
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
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|
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|
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|
|
<spirit:port>
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|
<spirit:name>up_tx_out_clk_sel_25</spirit:name>
|
|
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|
<spirit:direction>in</spirit:direction>
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|
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<spirit:left spirit:format="long">2</spirit:left>
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|
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|
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|
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
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|
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_diffctrl_25</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
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|
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|
<spirit:left spirit:format="long">4</spirit:left>
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|
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|
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|
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
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|
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_postcursor_25</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
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|
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|
<spirit:left spirit:format="long">4</spirit:left>
|
|
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|
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|
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|
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
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|
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|
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|
<spirit:port>
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|
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|
|
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|
|
<spirit:direction>in</spirit:direction>
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|
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|
<spirit:left spirit:format="long">4</spirit:left>
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|
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|
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|
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|
|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
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|
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|
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|
<spirit:port>
|
|
<spirit:name>up_tx_enb_25</spirit:name>
|
|
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|
|
<spirit:direction>in</spirit:direction>
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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|
</spirit:driver>
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|
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_addr_25</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
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|
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|
<spirit:left spirit:format="long">11</spirit:left>
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|
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|
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|
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<spirit:name>up_rx_bufstatus_rst_26</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_lpm_dfe_n_26</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_rate_26</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_sys_clk_sel_26</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_out_clk_sel_26</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_enb_26</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_addr_26</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">11</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_wr_26</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_wdata_26</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_rdata_26</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_ready_26</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_pll_locked_26</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_rst_26</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.up_tx_rst_26" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 26">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_user_ready_26</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_rst_done_26</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_bufstatus_26</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_prbsforceerr_26</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_prbssel_26</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_lpm_dfe_n_26</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_rate_26</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_sys_clk_sel_26</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_out_clk_sel_26</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_diffctrl_26</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_postcursor_26</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_precursor_26</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
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|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_bufstatus_27</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_bufstatus_rst_27</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_lpm_dfe_n_27</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_rate_27</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_sys_clk_sel_27</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_out_clk_sel_27</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_enb_27</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_addr_27</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">11</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_wr_27</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_wdata_27</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_rdata_27</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_ready_27</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_pll_locked_27</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_rst_27</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.up_tx_rst_27" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 27">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_user_ready_27</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_rst_done_27</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_bufstatus_27</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_prbsforceerr_27</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_prbssel_27</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_lpm_dfe_n_27</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_rate_27</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_sys_clk_sel_27</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_out_clk_sel_27</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_diffctrl_27</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_postcursor_27</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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|
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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|
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|
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|
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|
|
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|
|
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|
|
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|
|
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|
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|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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|
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|
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|
|
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|
|
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|
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|
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_user_ready_28</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_rst_done_28</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_bufstatus_28</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_prbsforceerr_28</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_prbssel_28</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_lpm_dfe_n_28</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_rate_28</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_sys_clk_sel_28</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_out_clk_sel_28</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_diffctrl_28</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_postcursor_28</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_precursor_28</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_enb_28</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_addr_28</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">11</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_wr_28</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
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|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
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|
|
</spirit:wireTypeDefs>
|
|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_wdata_28</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
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|
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|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
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|
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|
|
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|
|
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|
|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_rdata_28</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
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|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
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|
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|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
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|
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|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_tx_ready_28</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
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|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>cpll_ref_clk_29</spirit:name>
|
|
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|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
|
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|
|
</spirit:wireTypeDef>
|
|
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|
|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
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|
|
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|
</xilinx:enablement>
|
|
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|
|
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|
|
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|
|
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|
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|
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|
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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|
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|
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|
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|
|
</xilinx:enablement>
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rx_29_p" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 29">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
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|
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|
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|
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|
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|
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|
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|
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|
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|
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<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rx_29_n" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 29">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rx_out_clk_29</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
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|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
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|
|
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|
|
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|
<xilinx:enablement>
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|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rx_out_clk_29" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 29">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
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|
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:name>up_es_reset_29</spirit:name>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:name>up_rx_pll_locked_29</spirit:name>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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<spirit:port>
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<spirit:name>up_rx_rst_29</spirit:name>
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<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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<xilinx:portInfo>
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|
<xilinx:enablement>
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<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.up_rx_rst_29" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 29">false</xilinx:isEnabled>
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<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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<spirit:port>
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<spirit:name>up_rx_rst_done_29</spirit:name>
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|
<spirit:wire>
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
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|
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|
<spirit:wire>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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|
|
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|
|
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|
|
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|
|
<spirit:wire>
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|
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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<spirit:port>
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|
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|
<spirit:wire>
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|
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|
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|
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|
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|
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|
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_es_enb_30</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_es_addr_30</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">11</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_es_wr_30</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_es_wdata_30</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_es_rdata_30</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_es_ready_30</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_es_reset_30</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_pll_locked_30</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_rst_30</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.up_rx_rst_30" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 30">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_user_ready_30</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_rst_done_30</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_prbssel_30</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_prbscntreset_30</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_prbserr_30</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_prbslocked_30</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_bufstatus_30</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
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|
|
</spirit:vector>
|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_rx_bufstatus_rst_30</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
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|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
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|
|
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|
|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_rx_lpm_dfe_n_30</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
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|
|
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|
|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
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|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_rate_30</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
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|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
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|
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
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|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
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|
|
</spirit:wireTypeDefs>
|
|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_rx_sys_clk_sel_30</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
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|
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|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
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|
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|
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|
|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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|
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|
|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
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|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_rx_out_clk_sel_30</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
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|
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|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
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|
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|
|
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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|
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|
|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
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|
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|
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|
|
<spirit:port>
|
|
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|
|
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|
|
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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|
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|
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
<spirit:direction>in</spirit:direction>
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|
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|
|
<spirit:left spirit:format="long">11</spirit:left>
|
|
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|
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|
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|
|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
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|
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|
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|
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|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
<spirit:direction>in</spirit:direction>
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|
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|
|
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|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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|
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|
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|
|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
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|
|
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|
|
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|
|
<spirit:name>up_rx_wdata_30</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
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|
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|
|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_rdata_30</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
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|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
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|
<spirit:right spirit:format="long">0</spirit:right>
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|
</spirit:vector>
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|
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|
<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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|
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:name>up_tx_rst_done_30</spirit:name>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
<spirit:port>
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|
<spirit:name>up_tx_bufstatus_30</spirit:name>
|
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<spirit:direction>out</spirit:direction>
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|
<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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|
</spirit:wireTypeDef>
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|
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|
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|
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|
<spirit:port>
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|
<spirit:name>up_tx_prbsforceerr_30</spirit:name>
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|
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<spirit:direction>in</spirit:direction>
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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<spirit:name>up_tx_prbssel_30</spirit:name>
|
|
<spirit:wire>
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|
<spirit:direction>in</spirit:direction>
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<spirit:left spirit:format="long">3</spirit:left>
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
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|
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|
<spirit:port>
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<spirit:name>up_tx_lpm_dfe_n_30</spirit:name>
|
|
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|
<spirit:direction>in</spirit:direction>
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|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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|
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|
<spirit:port>
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|
<spirit:name>up_tx_rate_30</spirit:name>
|
|
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|
<spirit:direction>in</spirit:direction>
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|
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|
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|
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|
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|
|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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|
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|
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|
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|
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|
<spirit:name>up_tx_sys_clk_sel_30</spirit:name>
|
|
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|
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|
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|
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|
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|
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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|
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|
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|
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|
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|
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|
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|
|
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|
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
|
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|
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|
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|
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|
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|
|
<spirit:name>up_rx_wdata_31</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_rdata_31</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_rx_ready_31</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_pll_locked_31</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_rst_31</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.up_tx_rst_31" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 31">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_user_ready_31</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_rst_done_31</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_bufstatus_31</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_prbsforceerr_31</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_prbssel_31</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_lpm_dfe_n_31</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_rate_31</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_sys_clk_sel_31</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_out_clk_sel_31</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_diffctrl_31</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_postcursor_31</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_precursor_31</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_enb_31</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_addr_31</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">11</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_wr_31</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_wdata_31</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_rdata_31</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_tx_ready_31</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
</spirit:ports>
|
|
<spirit:modelParameters>
|
|
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
|
<spirit:name>XCVR_TYPE</spirit:name>
|
|
<spirit:displayName>Xcvr Type</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.XCVR_TYPE">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="signed">
|
|
<spirit:name>RX_LANE_RATE</spirit:name>
|
|
<spirit:displayName>Rx Lane Rate</spirit:displayName>
|
|
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RX_LANE_RATE">12.5</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="signed">
|
|
<spirit:name>TX_LANE_RATE</spirit:name>
|
|
<spirit:displayName>Tx Lane Rate</spirit:displayName>
|
|
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.TX_LANE_RATE">12.5</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>LINK_MODE</spirit:name>
|
|
<spirit:displayName>Link Mode</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.LINK_MODE">1</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>DATA_PATH_WIDTH</spirit:name>
|
|
<spirit:displayName>Data Path Width</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DATA_PATH_WIDTH" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) ? 8 : 4)">4</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>QPLL_REFCLK_DIV</spirit:name>
|
|
<spirit:displayName>Qpll Refclk Div</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.QPLL_REFCLK_DIV">1</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>QPLL_FBDIV_RATIO</spirit:name>
|
|
<spirit:displayName>Qpll Fbdiv Ratio</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.QPLL_FBDIV_RATIO">1</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>POR_CFG</spirit:name>
|
|
<spirit:displayName>Por Cfg</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.POR_CFG" spirit:bitStringLength="16">0x0006</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>PPF0_CFG</spirit:name>
|
|
<spirit:displayName>Ppf0 Cfg</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PPF0_CFG" spirit:bitStringLength="16">0x0600</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>PPF1_CFG</spirit:name>
|
|
<spirit:displayName>Ppf1 Cfg</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PPF1_CFG" spirit:bitStringLength="16">0x0600</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>QPLL_CFG</spirit:name>
|
|
<spirit:displayName>Qpll Cfg</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.QPLL_CFG" spirit:bitStringLength="27">"000011010000000000110000001"</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>QPLL_FBDIV</spirit:name>
|
|
<spirit:displayName>Qpll Fbdiv</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.QPLL_FBDIV" spirit:bitStringLength="10">"0000110000"</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>QPLL_CFG0</spirit:name>
|
|
<spirit:displayName>Qpll Cfg0</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.QPLL_CFG0" spirit:bitStringLength="16">0x331C</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>QPLL_CFG1</spirit:name>
|
|
<spirit:displayName>Qpll Cfg1</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.QPLL_CFG1" spirit:bitStringLength="16">0xD038</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>QPLL_CFG1_G3</spirit:name>
|
|
<spirit:displayName>Qpll Cfg1 G3</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.QPLL_CFG1_G3" spirit:bitStringLength="16">0xD038</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>QPLL_CFG2</spirit:name>
|
|
<spirit:displayName>Qpll Cfg2</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.QPLL_CFG2" spirit:bitStringLength="16">0x0FC0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>QPLL_CFG2_G3</spirit:name>
|
|
<spirit:displayName>Qpll Cfg2 G3</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.QPLL_CFG2_G3" spirit:bitStringLength="16">0x0FC0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>QPLL_CFG3</spirit:name>
|
|
<spirit:displayName>Qpll Cfg3</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.QPLL_CFG3" spirit:bitStringLength="16">0x0120</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>QPLL_CFG4</spirit:name>
|
|
<spirit:displayName>Qpll Cfg4</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.QPLL_CFG4" spirit:bitStringLength="16">0x0003</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>QPLL_CP_G3</spirit:name>
|
|
<spirit:displayName>Qpll Cp G3</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.QPLL_CP_G3" spirit:bitStringLength="10">"0000011111"</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>QPLL_LPF</spirit:name>
|
|
<spirit:displayName>Qpll Lpf</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.QPLL_LPF" spirit:bitStringLength="10">"0100110111"</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>QPLL_CP</spirit:name>
|
|
<spirit:displayName>Qpll Cp</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.QPLL_CP" spirit:bitStringLength="10">"0001111111"</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>CPLL_FBDIV</spirit:name>
|
|
<spirit:displayName>Cpll Fbdiv</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CPLL_FBDIV">2</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>CPLL_FBDIV_4_5</spirit:name>
|
|
<spirit:displayName>Cpll Fbdiv 4 5</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CPLL_FBDIV_4_5">5</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>CPLL_CFG0</spirit:name>
|
|
<spirit:displayName>Cpll Cfg0</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CPLL_CFG0" spirit:bitStringLength="16">0x01FA</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>CPLL_CFG1</spirit:name>
|
|
<spirit:displayName>Cpll Cfg1</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CPLL_CFG1" spirit:bitStringLength="16">0x0023</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>CPLL_CFG2</spirit:name>
|
|
<spirit:displayName>Cpll Cfg2</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CPLL_CFG2" spirit:bitStringLength="16">0x0002</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>CPLL_CFG3</spirit:name>
|
|
<spirit:displayName>Cpll Cfg3</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CPLL_CFG3" spirit:bitStringLength="16">0x0000</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>CH_HSPMUX</spirit:name>
|
|
<spirit:displayName>Ch Hspmux</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CH_HSPMUX" spirit:bitStringLength="16">0x2424</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>PREIQ_FREQ_BST</spirit:name>
|
|
<spirit:displayName>Preiq Freq Bst</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PREIQ_FREQ_BST">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>RXPI_CFG0</spirit:name>
|
|
<spirit:displayName>Rxpi Cfg0</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RXPI_CFG0" spirit:bitStringLength="16">0x0002</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>RXPI_CFG1</spirit:name>
|
|
<spirit:displayName>Rxpi Cfg1</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RXPI_CFG1" spirit:bitStringLength="16">0x0015</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>RTX_BUF_CML_CTRL</spirit:name>
|
|
<spirit:displayName>Rtx Buf Cml Ctrl</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RTX_BUF_CML_CTRL" spirit:bitStringLength="3">"011"</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>TX_NUM_OF_LANES</spirit:name>
|
|
<spirit:displayName>Tx Num Of Lanes</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.TX_NUM_OF_LANES">8</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>TX_OUT_DIV</spirit:name>
|
|
<spirit:displayName>Tx Out Div</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.TX_OUT_DIV">1</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>TX_CLK25_DIV</spirit:name>
|
|
<spirit:displayName>Tx Clk25 Div</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.TX_CLK25_DIV">20</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>TX_LANE_INVERT</spirit:name>
|
|
<spirit:displayName>Tx Lane Invert</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.TX_LANE_INVERT">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>TX_PI_BIASSET</spirit:name>
|
|
<spirit:displayName>Tx Pi Biasset</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.TX_PI_BIASSET">1</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>TXPI_CFG</spirit:name>
|
|
<spirit:displayName>Txpi Cfg</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.TXPI_CFG" spirit:bitStringLength="16">0x0054</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>A_TXDIFFCTRL</spirit:name>
|
|
<spirit:displayName>A Txdiffctrl</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.A_TXDIFFCTRL" spirit:bitStringLength="5">"10110"</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>RX_NUM_OF_LANES</spirit:name>
|
|
<spirit:displayName>Rx Num Of Lanes</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RX_NUM_OF_LANES">8</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>RX_OUT_DIV</spirit:name>
|
|
<spirit:displayName>Rx Out Div</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RX_OUT_DIV">1</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>RX_CLK25_DIV</spirit:name>
|
|
<spirit:displayName>Rx Clk25 Div</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RX_CLK25_DIV">20</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>RX_DFE_LPM_CFG</spirit:name>
|
|
<spirit:displayName>Rx Dfe Lpm Cfg</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RX_DFE_LPM_CFG" spirit:bitStringLength="16">0x0104</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>RX_PMA_CFG</spirit:name>
|
|
<spirit:displayName>Rx Pma Cfg</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RX_PMA_CFG" spirit:bitStringLength="32">0x001E7080</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>RX_CDR_CFG</spirit:name>
|
|
<spirit:displayName>Rx Cdr Cfg</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RX_CDR_CFG" spirit:bitStringLength="72">0x0B000023FF10400020</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>RXCDR_CFG0</spirit:name>
|
|
<spirit:displayName>Rxcdr Cfg0</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RXCDR_CFG0" spirit:bitStringLength="16">0x0002</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>RXCDR_CFG2</spirit:name>
|
|
<spirit:displayName>Rxcdr Cfg2</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RXCDR_CFG2" spirit:bitStringLength="16">0x0269</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>RXCDR_CFG2_GEN2</spirit:name>
|
|
<spirit:displayName>Rxcdr Cfg2 Gen2</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RXCDR_CFG2_GEN2" spirit:bitStringLength="10">"1001100101"</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>RXCDR_CFG2_GEN4</spirit:name>
|
|
<spirit:displayName>Rxcdr Cfg2 Gen4</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RXCDR_CFG2_GEN4" spirit:bitStringLength="16">0x00B4</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>RXCDR_CFG3</spirit:name>
|
|
<spirit:displayName>Rxcdr Cfg3</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RXCDR_CFG3" spirit:bitStringLength="16">0x0012</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>RXCDR_CFG3_GEN2</spirit:name>
|
|
<spirit:displayName>Rxcdr Cfg3 Gen2</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RXCDR_CFG3_GEN2" spirit:bitStringLength="6">"011010"</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>RXCDR_CFG3_GEN3</spirit:name>
|
|
<spirit:displayName>Rxcdr Cfg3 Gen3</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RXCDR_CFG3_GEN3" spirit:bitStringLength="16">0x0012</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>RXCDR_CFG3_GEN4</spirit:name>
|
|
<spirit:displayName>Rxcdr Cfg3 Gen4</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RXCDR_CFG3_GEN4" spirit:bitStringLength="16">0x0024</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>RXDFE_KH_CFG2</spirit:name>
|
|
<spirit:displayName>Rxdfe Kh Cfg2</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RXDFE_KH_CFG2" spirit:bitStringLength="16">0x0200</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>RXDFE_KH_CFG3</spirit:name>
|
|
<spirit:displayName>Rxdfe Kh Cfg3</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RXDFE_KH_CFG3" spirit:bitStringLength="16">0x4101</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>RX_WIDEMODE_CDR</spirit:name>
|
|
<spirit:displayName>Rx Widemode Cdr</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RX_WIDEMODE_CDR" spirit:bitStringLength="2">"00"</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>RX_XMODE_SEL</spirit:name>
|
|
<spirit:displayName>Rx Xmode Sel</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RX_XMODE_SEL" spirit:bitStringLength="1">"1"</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>TXDRV_FREQBAND</spirit:name>
|
|
<spirit:displayName>Txdrv Freqband</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.TXDRV_FREQBAND">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>TXFE_CFG0</spirit:name>
|
|
<spirit:displayName>Txfe Cfg0</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.TXFE_CFG0" spirit:bitStringLength="16">0x03C2</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>TXFE_CFG1</spirit:name>
|
|
<spirit:displayName>Txfe Cfg1</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.TXFE_CFG1" spirit:bitStringLength="16">0x6C00</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>TXFE_CFG2</spirit:name>
|
|
<spirit:displayName>Txfe Cfg2</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.TXFE_CFG2" spirit:bitStringLength="16">0x6C00</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>TXFE_CFG3</spirit:name>
|
|
<spirit:displayName>Txfe Cfg3</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.TXFE_CFG3" spirit:bitStringLength="16">0x6C00</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>TXPI_CFG0</spirit:name>
|
|
<spirit:displayName>Txpi Cfg0</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.TXPI_CFG0" spirit:bitStringLength="16">0x0300</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>TXPI_CFG1</spirit:name>
|
|
<spirit:displayName>Txpi Cfg1</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.TXPI_CFG1" spirit:bitStringLength="16">0x1000</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>TXSWBST_EN</spirit:name>
|
|
<spirit:displayName>Txswbst En</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.TXSWBST_EN">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>RX_LANE_INVERT</spirit:name>
|
|
<spirit:displayName>Rx Lane Invert</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RX_LANE_INVERT">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
</spirit:modelParameters>
|
|
</spirit:model>
|
|
<spirit:choices>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_74b5137e</spirit:name>
|
|
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
|
|
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_pairs_07421b06</spirit:name>
|
|
<spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
|
|
<spirit:enumeration spirit:text="GTPE2_NOT_SUPPORTED">1</spirit:enumeration>
|
|
<spirit:enumeration spirit:text="GTXE2">2</spirit:enumeration>
|
|
<spirit:enumeration spirit:text="GTHE2_NOT_SUPPORTED">3</spirit:enumeration>
|
|
<spirit:enumeration spirit:text="GTZE2_NOT_SUPPORTED">4</spirit:enumeration>
|
|
<spirit:enumeration spirit:text="GTHE3">5</spirit:enumeration>
|
|
<spirit:enumeration spirit:text="GTYE3_NOT_SUPPORTED">6</spirit:enumeration>
|
|
<spirit:enumeration spirit:text="GTRE4_NOT_SUPPORTED">7</spirit:enumeration>
|
|
<spirit:enumeration spirit:text="GTHE4">8</spirit:enumeration>
|
|
<spirit:enumeration spirit:text="GTYE4">9</spirit:enumeration>
|
|
<spirit:enumeration spirit:text="GTME4_NOT_SUPPORTED">10</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_pairs_1942b210</spirit:name>
|
|
<spirit:enumeration spirit:text="64B66B">2</spirit:enumeration>
|
|
<spirit:enumeration spirit:text="8B10B">1</spirit:enumeration>
|
|
</spirit:choice>
|
|
</spirit:choices>
|
|
<spirit:fileSets>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
|
|
<spirit:file>
|
|
<spirit:name>util_adxcvr_constr.xdc</spirit:name>
|
|
<spirit:userFileType>xdc</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>../../jesd204/jesd204_common/sync_header_align.v</spirit:name>
|
|
<spirit:fileType>verilogSource</spirit:fileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>util_adxcvr_xch.v</spirit:name>
|
|
<spirit:fileType>verilogSource</spirit:fileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>util_adxcvr_xcm.v</spirit:name>
|
|
<spirit:fileType>verilogSource</spirit:fileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>../../scripts/adi_xilinx_device_info_enc.tcl</spirit:name>
|
|
<spirit:fileType>tclSource</spirit:fileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>bd/bd.tcl</spirit:name>
|
|
<spirit:fileType>tclSource</spirit:fileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>util_adxcvr.v</spirit:name>
|
|
<spirit:fileType>verilogSource</spirit:fileType>
|
|
<spirit:userFileType>CHECKSUM_ae47eb4b</spirit:userFileType>
|
|
</spirit:file>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset</spirit:name>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:subCoreRef>
|
|
<xilinx:componentRef xilinx:vendor="analog.com" xilinx:library="user" xilinx:name="util_cdc" xilinx:version="1.0">
|
|
<xilinx:mode xilinx:name="copy_mode"/>
|
|
</xilinx:componentRef>
|
|
</xilinx:subCoreRef>
|
|
</spirit:vendorExtensions>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
|
<spirit:file>
|
|
<spirit:name>../../jesd204/jesd204_common/sync_header_align.v</spirit:name>
|
|
<spirit:fileType>verilogSource</spirit:fileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>util_adxcvr_xch.v</spirit:name>
|
|
<spirit:fileType>verilogSource</spirit:fileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>util_adxcvr_xcm.v</spirit:name>
|
|
<spirit:fileType>verilogSource</spirit:fileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>../../scripts/adi_xilinx_device_info_enc.tcl</spirit:name>
|
|
<spirit:fileType>tclSource</spirit:fileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>bd/bd.tcl</spirit:name>
|
|
<spirit:fileType>tclSource</spirit:fileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>util_adxcvr.v</spirit:name>
|
|
<spirit:fileType>verilogSource</spirit:fileType>
|
|
</spirit:file>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset</spirit:name>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:subCoreRef>
|
|
<xilinx:componentRef xilinx:vendor="analog.com" xilinx:library="user" xilinx:name="util_cdc" xilinx:version="1.0">
|
|
<xilinx:mode xilinx:name="copy_mode"/>
|
|
</xilinx:componentRef>
|
|
</xilinx:subCoreRef>
|
|
</spirit:vendorExtensions>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
|
|
<spirit:file>
|
|
<spirit:name>xgui/util_adxcvr_v1_0.tcl</spirit:name>
|
|
<spirit:fileType>tclSource</spirit:fileType>
|
|
<spirit:userFileType>CHECKSUM_fedc5936</spirit:userFileType>
|
|
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
|
|
</spirit:file>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset</spirit:name>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:subCoreRef>
|
|
<xilinx:componentRef xilinx:vendor="analog.com" xilinx:library="user" xilinx:name="util_cdc" xilinx:version="1.0"/>
|
|
</xilinx:subCoreRef>
|
|
</spirit:vendorExtensions>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_blockdiagram_view_fileset</spirit:name>
|
|
<spirit:file>
|
|
<spirit:name>bd/bd.tcl</spirit:name>
|
|
<spirit:fileType>tclSource</spirit:fileType>
|
|
</spirit:file>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_blockdiagram_analog_com_user_util_cdc_1_0__ref_view_fileset</spirit:name>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:subCoreRef>
|
|
<xilinx:componentRef xilinx:vendor="analog.com" xilinx:library="user" xilinx:name="util_cdc" xilinx:version="1.0"/>
|
|
</xilinx:subCoreRef>
|
|
</spirit:vendorExtensions>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_utilityxitfiles_view_fileset</spirit:name>
|
|
<spirit:file>
|
|
<spirit:name>gui/util_adxcvr_v1_0.gtcl</spirit:name>
|
|
<spirit:userFileType>GTCL</spirit:userFileType>
|
|
</spirit:file>
|
|
</spirit:fileSet>
|
|
</spirit:fileSets>
|
|
<spirit:description>util_adxcvr_v1_0</spirit:description>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>XCVR_TYPE</spirit:name>
|
|
<spirit:displayName>Xcvr Type</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.XCVR_TYPE" spirit:choiceRef="choice_pairs_07421b06">0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>RX_LANE_RATE</spirit:name>
|
|
<spirit:displayName>Rx Lane Rate (Gbps)</spirit:displayName>
|
|
<spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_LANE_RATE">12.5</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TX_LANE_RATE</spirit:name>
|
|
<spirit:displayName>Tx Lane Rate (Gbps)</spirit:displayName>
|
|
<spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.TX_LANE_RATE">12.5</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>LINK_MODE</spirit:name>
|
|
<spirit:displayName>Link Layer mode</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.LINK_MODE" spirit:choiceRef="choice_pairs_1942b210">1</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>DATA_PATH_WIDTH</spirit:name>
|
|
<spirit:displayName>Data Path Width</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DATA_PATH_WIDTH">4</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.DATA_PATH_WIDTH">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>QPLL_REFCLK_DIV</spirit:name>
|
|
<spirit:displayName>Qpll Refclk Div</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.QPLL_REFCLK_DIV">1</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>QPLL_FBDIV_RATIO</spirit:name>
|
|
<spirit:displayName>Qpll Fbdiv Ratio</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.QPLL_FBDIV_RATIO">1</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>POR_CFG</spirit:name>
|
|
<spirit:displayName>Por Cfg</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.POR_CFG" spirit:bitStringLength="16">0x0006</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PPF0_CFG</spirit:name>
|
|
<spirit:displayName>Ppf0 Cfg</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.PPF0_CFG" spirit:bitStringLength="16">0x0600</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PPF1_CFG</spirit:name>
|
|
<spirit:displayName>Ppf1 Cfg</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.PPF1_CFG" spirit:bitStringLength="16">0x0600</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>QPLL_CFG</spirit:name>
|
|
<spirit:displayName>Qpll Cfg</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.QPLL_CFG" spirit:bitStringLength="27">"000011010000000000110000001"</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>QPLL_FBDIV</spirit:name>
|
|
<spirit:displayName>Qpll Fbdiv</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.QPLL_FBDIV" spirit:bitStringLength="10">"0000110000"</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>QPLL_CFG0</spirit:name>
|
|
<spirit:displayName>Qpll Cfg0</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.QPLL_CFG0" spirit:bitStringLength="16">0x331C</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>QPLL_CFG1</spirit:name>
|
|
<spirit:displayName>Qpll Cfg1</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.QPLL_CFG1" spirit:bitStringLength="16">0xD038</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>QPLL_CFG1_G3</spirit:name>
|
|
<spirit:displayName>Qpll Cfg1 G3</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.QPLL_CFG1_G3" spirit:bitStringLength="16">0xD038</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>QPLL_CFG2</spirit:name>
|
|
<spirit:displayName>Qpll Cfg2</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.QPLL_CFG2" spirit:bitStringLength="16">0x0FC0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>QPLL_CFG2_G3</spirit:name>
|
|
<spirit:displayName>Qpll Cfg2 G3</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.QPLL_CFG2_G3" spirit:bitStringLength="16">0x0FC0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>QPLL_CFG3</spirit:name>
|
|
<spirit:displayName>Qpll Cfg3</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.QPLL_CFG3" spirit:bitStringLength="16">0x0120</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>QPLL_CFG4</spirit:name>
|
|
<spirit:displayName>Qpll Cfg4</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.QPLL_CFG4" spirit:bitStringLength="16">0x0003</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>QPLL_CP_G3</spirit:name>
|
|
<spirit:displayName>Qpll Cp G3</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.QPLL_CP_G3" spirit:bitStringLength="10">"0000011111"</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>QPLL_LPF</spirit:name>
|
|
<spirit:displayName>Qpll Lpf</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.QPLL_LPF" spirit:bitStringLength="10">"0100110111"</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>QPLL_CP</spirit:name>
|
|
<spirit:displayName>Qpll Cp</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.QPLL_CP" spirit:bitStringLength="10">"0001111111"</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>CPLL_FBDIV</spirit:name>
|
|
<spirit:displayName>Cpll Fbdiv</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CPLL_FBDIV">2</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>CPLL_FBDIV_4_5</spirit:name>
|
|
<spirit:displayName>Cpll Fbdiv 4 5</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CPLL_FBDIV_4_5">5</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>CPLL_CFG0</spirit:name>
|
|
<spirit:displayName>Cpll Cfg0</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.CPLL_CFG0" spirit:bitStringLength="16">0x01FA</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>CPLL_CFG1</spirit:name>
|
|
<spirit:displayName>Cpll Cfg1</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.CPLL_CFG1" spirit:bitStringLength="16">0x0023</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>CPLL_CFG2</spirit:name>
|
|
<spirit:displayName>Cpll Cfg2</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.CPLL_CFG2" spirit:bitStringLength="16">0x0002</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>CPLL_CFG3</spirit:name>
|
|
<spirit:displayName>Cpll Cfg3</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.CPLL_CFG3" spirit:bitStringLength="16">0x0000</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>CH_HSPMUX</spirit:name>
|
|
<spirit:displayName>Ch Hspmux</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.CH_HSPMUX" spirit:bitStringLength="16">0x2424</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PREIQ_FREQ_BST</spirit:name>
|
|
<spirit:displayName>Preiq Freq Bst</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PREIQ_FREQ_BST">0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>RXPI_CFG0</spirit:name>
|
|
<spirit:displayName>Rxpi Cfg0</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.RXPI_CFG0" spirit:bitStringLength="16">0x0002</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>RXPI_CFG1</spirit:name>
|
|
<spirit:displayName>Rxpi Cfg1</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.RXPI_CFG1" spirit:bitStringLength="16">0x0015</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>RTX_BUF_CML_CTRL</spirit:name>
|
|
<spirit:displayName>Rtx Buf Cml Ctrl</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.RTX_BUF_CML_CTRL" spirit:bitStringLength="3">"011"</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TX_NUM_OF_LANES</spirit:name>
|
|
<spirit:displayName>Tx Num Of Lanes</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.TX_NUM_OF_LANES">8</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TX_OUT_DIV</spirit:name>
|
|
<spirit:displayName>Tx Out Div</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.TX_OUT_DIV">1</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TX_CLK25_DIV</spirit:name>
|
|
<spirit:displayName>Tx Clk25 Div</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.TX_CLK25_DIV">20</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TX_LANE_INVERT</spirit:name>
|
|
<spirit:displayName>Tx Lane Invert</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.TX_LANE_INVERT">0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TX_PI_BIASSET</spirit:name>
|
|
<spirit:displayName>Tx Pi Biasset</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.TX_PI_BIASSET">1</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TXPI_CFG</spirit:name>
|
|
<spirit:displayName>Txpi Cfg</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.TXPI_CFG" spirit:bitStringLength="16">0x0054</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>A_TXDIFFCTRL</spirit:name>
|
|
<spirit:displayName>A Txdiffctrl</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.A_TXDIFFCTRL" spirit:bitStringLength="5">"10110"</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>RX_NUM_OF_LANES</spirit:name>
|
|
<spirit:displayName>Rx Num Of Lanes</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_NUM_OF_LANES">8</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>RX_OUT_DIV</spirit:name>
|
|
<spirit:displayName>Rx Out Div</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_OUT_DIV">1</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>RX_CLK25_DIV</spirit:name>
|
|
<spirit:displayName>Rx Clk25 Div</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CLK25_DIV">20</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>RX_DFE_LPM_CFG</spirit:name>
|
|
<spirit:displayName>Rx Dfe Lpm Cfg</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_DFE_LPM_CFG" spirit:bitStringLength="16">0x0104</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>RX_PMA_CFG</spirit:name>
|
|
<spirit:displayName>Rx Pma Cfg</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_PMA_CFG" spirit:bitStringLength="32">0x001E7080</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>RX_CDR_CFG</spirit:name>
|
|
<spirit:displayName>Rx Cdr Cfg</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CDR_CFG" spirit:bitStringLength="72">0x0B000023FF10400020</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>RXCDR_CFG0</spirit:name>
|
|
<spirit:displayName>Rxcdr Cfg0</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.RXCDR_CFG0" spirit:bitStringLength="16">0x0002</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>RXCDR_CFG2</spirit:name>
|
|
<spirit:displayName>Rxcdr Cfg2</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.RXCDR_CFG2" spirit:bitStringLength="16">0x0269</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>RXCDR_CFG2_GEN2</spirit:name>
|
|
<spirit:displayName>Rxcdr Cfg2 Gen2</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.RXCDR_CFG2_GEN2" spirit:bitStringLength="10">"1001100101"</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>RXCDR_CFG2_GEN4</spirit:name>
|
|
<spirit:displayName>Rxcdr Cfg2 Gen4</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.RXCDR_CFG2_GEN4" spirit:bitStringLength="16">0x00B4</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>RXCDR_CFG3</spirit:name>
|
|
<spirit:displayName>Rxcdr Cfg3</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.RXCDR_CFG3" spirit:bitStringLength="16">0x0012</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>RXCDR_CFG3_GEN2</spirit:name>
|
|
<spirit:displayName>Rxcdr Cfg3 Gen2</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.RXCDR_CFG3_GEN2" spirit:bitStringLength="6">"011010"</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>RXCDR_CFG3_GEN3</spirit:name>
|
|
<spirit:displayName>Rxcdr Cfg3 Gen3</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.RXCDR_CFG3_GEN3" spirit:bitStringLength="16">0x0012</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>RXCDR_CFG3_GEN4</spirit:name>
|
|
<spirit:displayName>Rxcdr Cfg3 Gen4</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.RXCDR_CFG3_GEN4" spirit:bitStringLength="16">0x0024</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>RXDFE_KH_CFG2</spirit:name>
|
|
<spirit:displayName>Rxdfe Kh Cfg2</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.RXDFE_KH_CFG2" spirit:bitStringLength="16">0x0200</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>RXDFE_KH_CFG3</spirit:name>
|
|
<spirit:displayName>Rxdfe Kh Cfg3</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.RXDFE_KH_CFG3" spirit:bitStringLength="16">0x4101</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>RX_WIDEMODE_CDR</spirit:name>
|
|
<spirit:displayName>Rx Widemode Cdr</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_WIDEMODE_CDR" spirit:bitStringLength="2">"00"</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>RX_XMODE_SEL</spirit:name>
|
|
<spirit:displayName>Rx Xmode Sel</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_XMODE_SEL" spirit:bitStringLength="1">"1"</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TXDRV_FREQBAND</spirit:name>
|
|
<spirit:displayName>Txdrv Freqband</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.TXDRV_FREQBAND">0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TXFE_CFG0</spirit:name>
|
|
<spirit:displayName>Txfe Cfg0</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.TXFE_CFG0" spirit:bitStringLength="16">0x03C2</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TXFE_CFG1</spirit:name>
|
|
<spirit:displayName>Txfe Cfg1</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.TXFE_CFG1" spirit:bitStringLength="16">0x6C00</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TXFE_CFG2</spirit:name>
|
|
<spirit:displayName>Txfe Cfg2</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.TXFE_CFG2" spirit:bitStringLength="16">0x6C00</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TXFE_CFG3</spirit:name>
|
|
<spirit:displayName>Txfe Cfg3</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.TXFE_CFG3" spirit:bitStringLength="16">0x6C00</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TXPI_CFG0</spirit:name>
|
|
<spirit:displayName>Txpi Cfg0</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.TXPI_CFG0" spirit:bitStringLength="16">0x0300</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TXPI_CFG1</spirit:name>
|
|
<spirit:displayName>Txpi Cfg1</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.TXPI_CFG1" spirit:bitStringLength="16">0x1000</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TXSWBST_EN</spirit:name>
|
|
<spirit:displayName>Txswbst En</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.TXSWBST_EN">0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>RX_LANE_INVERT</spirit:name>
|
|
<spirit:displayName>Rx Lane Invert</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_LANE_INVERT">0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>Component_Name</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">util_adxcvr_v1_0</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:coreExtensions>
|
|
<xilinx:supportedFamilies>
|
|
<xilinx:family xilinx:lifeCycle="Production">virtex7</xilinx:family>
|
|
</xilinx:supportedFamilies>
|
|
<xilinx:taxonomies>
|
|
<xilinx:taxonomy>/Analog_Devices</xilinx:taxonomy>
|
|
</xilinx:taxonomies>
|
|
<xilinx:displayName>util_adxcvr_v1_0</xilinx:displayName>
|
|
<xilinx:autoFamilySupportLevel>level_2</xilinx:autoFamilySupportLevel>
|
|
<xilinx:definitionSource>package_project</xilinx:definitionSource>
|
|
<xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
|
|
<xilinx:vendorURL>https://wiki.analog.com/resources/fpga/docs/util_xcvr</xilinx:vendorURL>
|
|
<xilinx:coreRevision>1</xilinx:coreRevision>
|
|
<xilinx:coreCreationDateTime>2024-06-06T03:15:47Z</xilinx:coreCreationDateTime>
|
|
</xilinx:coreExtensions>
|
|
<xilinx:packagingInfo>
|
|
<xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
|
|
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="b550c633"/>
|
|
<xilinx:checksum xilinx:scope="ports" xilinx:value="d70ad8a4"/>
|
|
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="ef4432cb"/>
|
|
<xilinx:checksum xilinx:scope="parameters" xilinx:value="46f75622"/>
|
|
</xilinx:packagingInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:component>
|