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bugfix(tdma): fix 3.125 frame sync tic pos(param)

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ZoroGH
2024-10-11 12:11:08 +08:00
parent 4b4f9dc671
commit 26c24ae5b2
3 changed files with 19 additions and 17 deletions
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hdl/phy_control.v
+7 -1
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@@ -74,7 +74,8 @@ module phy_control #(
output wire [31:0] tdma_tic_2_ps, output wire [31:0] tdma_tic_2_ps,
output wire [31:0] tdma_id_cfg, output wire [31:0] tdma_id_cfg,
output wire tdma_recv_cur_slot_id_valid, output wire tdma_recv_cur_slot_id_valid,
output wire [ 7:0] tdma_recv_cur_slot_id output wire [ 7:0] tdma_recv_cur_slot_id,
output wire [31:0] tdma_frame_sync_tic
//--- ADD YOUR OWN PORTS END //--- ADD YOUR OWN PORTS END
); );
@@ -344,6 +345,7 @@ module phy_control #(
localparam integer TDMA_TIC_2_PS = 'h0000_000C >> 2; localparam integer TDMA_TIC_2_PS = 'h0000_000C >> 2;
localparam integer TDMA_ID_CFG = 'h0000_0010 >> 2; localparam integer TDMA_ID_CFG = 'h0000_0010 >> 2;
localparam integer TDMA_RECV_ID = 'h0000_0014 >> 2; localparam integer TDMA_RECV_ID = 'h0000_0014 >> 2;
localparam integer TDMA_FRAME_SYNC_TIC = 'h0000_0018 >> 2;
// Register definitions // Register definitions
reg [31:0] phy_cr_reg = 32'h0; reg [31:0] phy_cr_reg = 32'h0;
@@ -352,6 +354,7 @@ module phy_control #(
reg [31:0] tdma_tic_2_ps_reg = 32'h0; reg [31:0] tdma_tic_2_ps_reg = 32'h0;
reg [31:0] tdma_id_cfg_reg = 32'h0; // 2B zero pad, 1B slot num, 1B local id reg [31:0] tdma_id_cfg_reg = 32'h0; // 2B zero pad, 1B slot num, 1B local id
reg [31:0] tdma_recv_id_reg = 32'h0; reg [31:0] tdma_recv_id_reg = 32'h0;
reg [31:0] tdma_frame_sync_tic_reg = 32'h0;
// Register Reading // Register Reading
always @(posedge local_clk) begin always @(posedge local_clk) begin
@@ -378,6 +381,7 @@ module phy_control #(
TDMA_TIC_2_PS: tdma_tic_2_ps_reg <= up_wdata_s; TDMA_TIC_2_PS: tdma_tic_2_ps_reg <= up_wdata_s;
TDMA_ID_CFG: tdma_id_cfg_reg <= up_wdata_s; TDMA_ID_CFG: tdma_id_cfg_reg <= up_wdata_s;
TDMA_RECV_ID: tdma_recv_id_reg <= up_wdata_s; TDMA_RECV_ID: tdma_recv_id_reg <= up_wdata_s;
TDMA_FRAME_SYNC_TIC: tdma_frame_sync_tic_reg <= up_wdata_s;
endcase endcase
end end
else begin else begin
@@ -403,6 +407,8 @@ module phy_control #(
// received mac frame // received mac frame
assign tdma_recv_cur_slot_id = tdma_recv_id_reg[7:0]; assign tdma_recv_cur_slot_id = tdma_recv_id_reg[7:0];
assign tdma_recv_cur_slot_id_valid = tdma_recv_id_reg[8]; assign tdma_recv_cur_slot_id_valid = tdma_recv_id_reg[8];
// frame sync tic
assign tdma_frame_sync_tic = tdma_frame_sync_tic_reg;
vio_phy_param u_vio_phy_param ( vio_phy_param u_vio_phy_param (
.clk (local_clk), .clk (local_clk),
hdl/system_top.v
+3
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@@ -127,6 +127,7 @@ module system_top (
wire [31:0] tdma_id_cfg; wire [31:0] tdma_id_cfg;
wire tdma_recv_cur_slot_id_valid; wire tdma_recv_cur_slot_id_valid;
wire [ 7:0] tdma_recv_cur_slot_id; wire [ 7:0] tdma_recv_cur_slot_id;
wire [31:0] tdma_frame_sync_tic;
// tx signal // tx signal
@@ -257,6 +258,7 @@ module system_top (
.tdma_id_cfg (tdma_id_cfg), .tdma_id_cfg (tdma_id_cfg),
.tdma_recv_cur_slot_id_valid(tdma_recv_cur_slot_id_valid), .tdma_recv_cur_slot_id_valid(tdma_recv_cur_slot_id_valid),
.tdma_recv_cur_slot_id (tdma_recv_cur_slot_id), .tdma_recv_cur_slot_id (tdma_recv_cur_slot_id),
.tdma_frame_sync_tic (tdma_frame_sync_tic),
// uart // uart
.uart_rx (uart_rx), .uart_rx (uart_rx),
.uart_tx (uart_tx) .uart_tx (uart_tx)
@@ -269,6 +271,7 @@ module system_top (
.tdma_slot_len (tdma_slot_len[23:0]), .tdma_slot_len (tdma_slot_len[23:0]),
.tdma_tic_2_ps (tdma_tic_2_ps[23:0]), .tdma_tic_2_ps (tdma_tic_2_ps[23:0]),
.tdma_slot_num (tdma_id_cfg[15:8]), .tdma_slot_num (tdma_id_cfg[15:8]),
.tdma_frame_sync_tic (tdma_frame_sync_tic[23:0]),
.local_id (tdma_id_cfg[7:0]), .local_id (tdma_id_cfg[7:0]),
.recevied_cur_slot_id_valid(tdma_recv_cur_slot_id_valid), .recevied_cur_slot_id_valid(tdma_recv_cur_slot_id_valid),
.recevied_cur_slot_id (tdma_recv_cur_slot_id), .recevied_cur_slot_id (tdma_recv_cur_slot_id),
hdl/tdma.v
+9 -16
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@@ -13,9 +13,7 @@
// ! PLEASE MAKE SURE THE PARAMETER ARE VALID // ! PLEASE MAKE SURE THE PARAMETER ARE VALID
// ! WHEN U INSTANTIATE THIS MODULE // ! WHEN U INSTANTIATE THIS MODULE
module tdma #( module tdma (
parameter TIC_FRAME_SYNC = 44432
) (
input clk, input clk,
input rst, input rst,
// PHY parameter // PHY parameter
@@ -24,6 +22,7 @@ module tdma #(
input wire [23:0] tdma_slot_len, input wire [23:0] tdma_slot_len,
input wire [23:0] tdma_tic_2_ps, input wire [23:0] tdma_tic_2_ps,
input wire [ 7:0] tdma_slot_num, input wire [ 7:0] tdma_slot_num,
input wire [23:0] tdma_frame_sync_tic,
input wire [ 7:0] local_id, // ID number for this device input wire [ 7:0] local_id, // ID number for this device
// update while received valid // update while received valid
input wire recevied_cur_slot_id_valid, // recevied ID number of the frame input wire recevied_cur_slot_id_valid, // recevied ID number of the frame
@@ -102,15 +101,9 @@ module tdma #(
cnt_tdma_slot_len <= 0; cnt_tdma_slot_len <= 0;
end end
else if (flag_frame_sync) begin else if (flag_frame_sync) begin
cnt_tdma_slot_len <= tdma_tic_frame_sync_vio; cnt_tdma_slot_len <= tdma_frame_sync_tic;
end end
else begin else begin
// if (cnt_tdma_slot_len < tdma_slot_len - 1) begin
// cnt_tdma_slot_len <= cnt_tdma_slot_len + 1;
// end
// else begin
// cnt_tdma_slot_len <= 0;
// end
if (flag_end_of_one_slot) begin if (flag_end_of_one_slot) begin
cnt_tdma_slot_len <= 0; cnt_tdma_slot_len <= 0;
end end
@@ -172,12 +165,12 @@ module tdma #(
// ******** Debug ******** // ******** Debug ********
vio_tdma u_vio_tdma ( vio_tdma u_vio_tdma (
.clk (clk), .clk (clk),
.probe_in0 (tdma_slot_len), .probe_in0(tdma_slot_len),
.probe_in1 (tdma_tic_2_ps), .probe_in1(tdma_tic_2_ps),
.probe_in2 (tdma_slot_num), .probe_in2(tdma_slot_num),
.probe_in3 (local_id), .probe_in3(local_id),
.probe_out0(tdma_tic_frame_sync_vio) .probe_in4(tdma_frame_sync_tic)
); );
ila_mac_layer u_ila_mac_layer ( ila_mac_layer u_ila_mac_layer (