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feat(top): adjust rf control logic, ila for 3rd test

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ZoroGH
2024-10-18 19:14:09 +08:00
parent 6ddf033548
commit 3bdfbd31dc
3 changed files with 41 additions and 9 deletions
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hdl/RecvTop.v
+12 -9
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@@ -662,15 +662,18 @@ module RecvTop (
);
ila_recv_top u_ila_recv_top (
.clk (clk_quarter),
.probe0(dagc_data_in_i), // width: 12
.probe1(dagc_data_in_q), // width: 12
.probe2(flag_frame_sync), // width: 1
.probe3(phase_adjust_rdy), // width: 1
.probe4(phase_adjust_douti), // width: 10
.probe5(phase_adjust_doutq), // width: 10
.probe6(good_frames), // width: 9
.probe7(bad_frames) // width: 9
.clk (clk_quarter),
.probe0 (dagc_data_in_i), // width: 12
.probe1 (dagc_data_in_q), // width: 12
.probe2 (flag_frame_sync), // width: 1
.probe3 (phase_adjust_rdy), // width: 1
.probe4 (phase_adjust_douti), // width: 10
.probe5 (phase_adjust_doutq), // width: 10
.probe6 (IntpARdy), // width: 1
.probe7 (IntpOuti), // width: 10
.probe8 (IntpOutq), // width: 10
.probe9 (good_frames), // width: 9
.probe10(bad_frames) // width: 9
);