feat(top): adjust rf control logic, ila for 3rd test

hdl/system_top.v

@@ -144,6 +144,12 @@ module system_top (
     // rx
     wire        rx_err_flag_pos;
 
+    wire        rf_io3_d1_12db;
+    wire        rf_io4_d2_6db;
+    wire        rf_io0_d3_18db;
+    wire        rf_io1_d4_12db;
+    wire        rf_io2_trx;  // 1 for tx on, 0 for rx
+
     // vio
     wire        rst_manual;
     wire        rx_rst_vio;
@@ -166,6 +172,19 @@ module system_top (
     assign ad9361_tx_data_q = phy_tx_iq_reverse ? bb_tx_i : bb_tx_q;
     assign bb_rx_i          = phy_rx_iq_reverse ? ad9361_rx_data_q : ad9361_rx_data_i;
     assign bb_rx_q          = phy_rx_iq_reverse ? ad9361_rx_data_i : ad9361_rx_data_q;
+    // gpio  rf control
+    assign rf_gpio[0]       = rf_io0_d3_18db;
+    assign rf_gpio[1]       = rf_io1_d4_12db;
+    assign rf_gpio[2]       = rf_io2_trx;
+    assign rf_gpio[3]       = rf_io3_d1_12db;
+    assign rf_gpio[4]       = rf_io4_d2_6db;
+    assign rf_gpio[5]       = 0;
+    // at send slot, rx rst is on, and trx is 1 for tx
+    assign rf_io2_trx       = rx_rst;
+    assign rf_io0_d3_18db   = 0;
+    assign rf_io1_d4_12db   = 0;
+    assign rf_io3_d1_12db   = 0;
+    assign rf_io4_d2_6db    = 0;
 
     // ******** Logic Block ********
 
@@ -383,4 +402,13 @@ module system_top (
     //     .probe1(ad9361_tx_data_q)   // input wire [11:0]  probe1
     // );
 
+    // vio_rf u_vio_rf (
+    //     .clk       (clk_poweron),
+    //     .probe_out0(),
+    //     .probe_out1(rf_io3_d1_12db),
+    //     .probe_out2(rf_io4_d2_6db),
+    //     .probe_out3(rf_io0_d3_18db),
+    //     .probe_out4(rf_io1_d4_12db)
+    // );
+
 endmodule