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temp review

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ZoroGH
2024-07-22 20:45:33 +08:00
parent da1073f750
commit 48c59b64ff
2 changed files with 8 additions and 43 deletions
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hdl/RecvTop.v
+8 -42
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@@ -128,7 +128,7 @@ module RecvTop (
end end
end end
assign mgc_start = (nt_mgc_delay == 8'hff); assign mgc_start = (cnt_mgc_delay == 8'hff);
ad9361_mgc_pin_ctrl u_ad9361_mgc_pin_ctrl ( ad9361_mgc_pin_ctrl u_ad9361_mgc_pin_ctrl (
.clk (clk), .clk (clk),
@@ -258,7 +258,7 @@ module RecvTop (
.mag (mag), .mag (mag),
.mag_valid(mag_valid) .mag_valid(mag_valid)
); );
// frame sync threashold judgement
PAPR #( PAPR #(
.MAG_WIDTH (22), .MAG_WIDTH (22),
.WINDOW_DEPTH(1023) .WINDOW_DEPTH(1023)
@@ -280,31 +280,6 @@ module RecvTop (
wire mgc_rdy; wire mgc_rdy;
wire rst_dagc; wire rst_dagc;
DAGC_v2 DAGC_v2 (
.clk (clk),
.rst (~mgc1_rdy),
.mgc1_rdy (MF_rdy),
.framesync_d0 (framesync),
.vio_powertest_h (2'b00),
.vio_powertest_l (2'b00),
.matchfilterout_i(FrameSync_douti),
.matchfilterout_q(FrameSync_doutq),
// output
.DAGC_out_i (DAGC_out_i),
.DAGC_out_q (DAGC_out_q),
//flag
.flag_agch (flag_agch),
.flag_agcl (flag_agcl),
.flag_agc_power (flag_agc_power),
.agc_ref (agc_ref),
.agc_check (agc_check),
.dagc_rdy (dagc_rdy),
.mgc_rdy (mgc_rdy),
.rst_dagc (rst_dagc)
);
//帧同步模块 //帧同步模块
assign FrameSync_dini = DAGC_out_i; assign FrameSync_dini = DAGC_out_i;
@@ -348,16 +323,8 @@ module RecvTop (
end end
end end
end end
// wire [9:0] DAGC_out_i;
// wire [9:0] DAGC_out_q;
// wire flag_agch;
// wire flag_agcl;
// wire flag_agc_power;
// wire [12:0] agc_ref;
// wire [12:0] agc_check;
wire dagc_rdy;
wire mgc_rdy;
wire rst_dagc;
DAGC_v2 DAGC_v2 ( DAGC_v2 DAGC_v2 (
.clk (clk), .clk (clk),
.rst (~mgc1_rdy), .rst (~mgc1_rdy),
@@ -365,11 +332,11 @@ module RecvTop (
.framesync_d0 (framesync), .framesync_d0 (framesync),
.vio_powertest_h (2'b00), .vio_powertest_h (2'b00),
.vio_powertest_l (2'b00), .vio_powertest_l (2'b00),
.matchfilterout_i(FrameSync_douti), // input, .matchfilterout_i(FrameSync_douti), // input,
.matchfilterout_q(FrameSync_doutq), // input .matchfilterout_q(FrameSync_doutq), // input
.DAGC_out_i(DAGC_out_i), // output .DAGC_out_i(DAGC_out_i), // output
.DAGC_out_q(DAGC_out_q), // output .DAGC_out_q(DAGC_out_q), // output
.flag_agch (flag_agch), .flag_agch (flag_agch),
.flag_agcl (flag_agcl), .flag_agcl (flag_agcl),
@@ -401,7 +368,6 @@ module RecvTop (
.framesync_delay(framesync_delay), .framesync_delay(framesync_delay),
.data_save (data_save), .data_save (data_save),
.rst_freq (rst_freq) .rst_freq (rst_freq)
); );
//位同步 //位同步
hdl/ad9361_mgc_pin_ctrl.v
-1
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@@ -33,7 +33,6 @@ module ad9361_mgc_pin_ctrl (
// ******** Wire & Reg ******** // ******** Wire & Reg ********
wire start;
reg start_d1; reg start_d1;
wire start_posedge; wire start_posedge;
wire inc_pulse; wire inc_pulse;