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feat(top): new (de)scrambler, crc16

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ZoroGH
2024-08-13 22:07:58 +08:00
parent a4eb609aae
commit 5e8d69a0b0
13 changed files with 766 additions and 90 deletions
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hdl/system_top.v
+100 -76
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@@ -90,6 +90,11 @@ module system_top (
// tx signal
wire tx_test_flag;
wire flag_mgc_done_pulse;
// rx bus
wire [31:0] rx_data_src_fifo_tdata;
wire rx_data_src_fifo_tlast;
wire rx_data_src_fifo_tready;
wire rx_data_src_fifo_tvalid;
// baseband signal
wire [11:0] ad9361_rx_data_i;
@@ -132,6 +137,7 @@ module system_top (
// vio
wire rst_manual;
wire rx_rst_vio;
wire [ 7:0] node_id;
wire intr_2ps;
wire [ 7:0] max_slot_num;
@@ -178,71 +184,78 @@ module system_top (
);
MM7020_BD_wrapper u_MM7020_BD_wrapper (
.ad9361_spi_clk (ad9361_spi_clk),
.ad9361_spi_csn (ad9361_spi_csn),
.ad9361_spi_miso (ad9361_spi_miso),
.ad9361_spi_mosi (ad9361_spi_mosi),
.clk_ps (clk_poweron),
.rst_ps (rst_sys),
.ad9361_spi_clk (ad9361_spi_clk),
.ad9361_spi_csn (ad9361_spi_csn),
.ad9361_spi_miso (ad9361_spi_miso),
.ad9361_spi_mosi (ad9361_spi_mosi),
.clk_ps (clk_poweron),
.rst_ps (rst_sys),
// ddr
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
// fixed io
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
// gpio ps
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
// intr pl to ps
.pl2ps_intr2 (intr_2ps),
.pl2ps_intr3 (flag_mgc_done_pulse),
.pl_tx_intr (intr_2ps | intr_2ps_vio_pos),
.pl_rx_intr (rx_data_src_fifo_tlast),
// tx fifo
.tx_data_src_count (tx_data_src_count),
.tx_data_src_tdata (tx_data_src_tdata),
.tx_data_src_tready (tx_data_src_tready),
.tx_data_src_tvalid (tx_data_src_tvalid),
//phy control signal
.phy_rst (phy_rst),
.phy_tx_test_flag (phy_tx_test_flag),
.phy_tx_iq_reverse (phy_tx_iq_reverse),
.phy_rx_iq_reverse (phy_rx_iq_reverse),
.tdma_flag_is_master(tdma_flag_is_master),
.tdma_slot_len (tdma_slot_len),
.tdma_tic_2_ps (tdma_tic_2_ps),
.tx_data_src_count (tx_data_src_count),
.tx_data_src_tdata (tx_data_src_tdata),
.tx_data_src_tready (tx_data_src_tready),
.tx_data_src_tvalid (tx_data_src_tvalid),
// rx fifo
.clk_rx_data_src_fifo (clk_2x),
.rst_rx_data_src_fifo (rx_rst),
.rx_data_src_fifo_tdata (rx_data_src_fifo_tdata),
.rx_data_src_fifo_tlast (rx_data_src_fifo_tlast),
.rx_data_src_fifo_tready(rx_data_src_fifo_tready),
.rx_data_src_fifo_tvalid(rx_data_src_fifo_tvalid),
// phy control signal
.phy_rst (phy_rst),
.phy_tx_test_flag (phy_tx_test_flag),
.phy_tx_iq_reverse (phy_tx_iq_reverse),
.phy_rx_iq_reverse (phy_rx_iq_reverse),
.tdma_flag_is_master (tdma_flag_is_master),
.tdma_slot_len (tdma_slot_len),
.tdma_tic_2_ps (tdma_tic_2_ps),
// uart
.uart_rx (uart_rx),
.uart_tx (uart_tx)
.uart_rx (uart_rx),
.uart_tx (uart_tx)
);
tdma u_tdma (
.clk (clk_1x),
.rst (rst_sys),
.flag_is_master (tdma_flag_is_master),
.flag_frame_sync(frame_sync_pulse),
.tdma_slot_len (tdma_slot_len[23:0]),
.tdma_tic_2_ps (tdma_tic_2_ps[23:0]),
.intr_2ps (intr_2ps),
.tx_start (tx_start),
.rx_rst (rx_rst)
);
// tdma u_tdma (
// .clk (clk_1x),
// .rst (rst_sys),
// .flag_is_master (tdma_flag_is_master),
// .flag_frame_sync(frame_sync_pulse),
// .tdma_slot_len (tdma_slot_len[23:0]),
// .tdma_tic_2_ps (tdma_tic_2_ps[23:0]),
// .intr_2ps (intr_2ps),
// .tx_start (tx_start),
// .rx_rst (rx_rst)
// );
@@ -292,7 +305,7 @@ module system_top (
.rst (rst_sys | phy_rst),
.speed_mode (2),
.send_data_ready (send_data_ready),
.send_start (tx_start),
.send_start (tx_start | tx_start_vio_pos),
.send_over (tx_done),
.clk_data_src (clk_data_src),
.tx_data_src_tdata (enc_fifo_dout_map),
@@ -306,24 +319,28 @@ module system_top (
);
RecvTop u_RecvTop (
.clk (clk_1x),
.clk_2x (clk_2x),
.clk_4x (clk_4x),
.rst (rst_sys | rx_rst | phy_rst),
.rst2 (rst_sys | phy_rst),
.dini (bb_rx_i),
.dinq (bb_rx_q),
.ad9361_ctrl_in (ad9361_ctrl_in),
.flag_mgc_done_pulse(flag_mgc_done_pulse),
.frame_sync_pulse (frame_sync_pulse),
.vio_tsync_inter16 (1),
.EQUenable_vio (1),
.Zerozone_vio (8'd29),
.vio_stopbit (7'd60),
.flag_stop (flag_stop),
.addr_stop (addr_stop),
.recvNetData (recvNetData),
.recvNetDataNd (recvNetDataNd)
.clk (clk_1x),
.clk_2x (clk_2x),
.clk_4x (clk_4x),
.rst (rst_sys | rx_rst | phy_rst | rx_rst_vio),
.rst2 (rst_sys | phy_rst),
.dini (bb_rx_i),
.dinq (bb_rx_q),
.ad9361_ctrl_in (ad9361_ctrl_in),
.flag_mgc_done_pulse (flag_mgc_done_pulse),
.frame_sync_pulse (frame_sync_pulse),
.vio_tsync_inter16 (1),
.EQUenable_vio (1),
.Zerozone_vio (8'd29),
.vio_stopbit (7'd60),
.flag_stop (flag_stop),
.addr_stop (addr_stop),
.recvNetData (recvNetData),
.recvNetDataNd (recvNetDataNd),
.rx_data_src_fifo_tdata (rx_data_src_fifo_tdata),
.rx_data_src_fifo_tlast (rx_data_src_fifo_tlast),
.rx_data_src_fifo_tready(rx_data_src_fifo_tready),
.rx_data_src_fifo_tvalid(rx_data_src_fifo_tvalid)
);
@@ -382,4 +399,11 @@ module system_top (
end
vio_system_top u_vio_system_top (
.clk (clk_1x),
.probe_out0(rx_rst_vio),
.probe_out1(tx_start_vio),
.probe_out2(intr_2ps_vio)
);
endmodule