feat(top): new (de)scrambler, crc16

sim/tb_extract_mac_frame.v

@@ -0,0 +1,82 @@
+`timescale 1ns / 1ns
+
+module tb_extract_mac_frame ();
+
+    reg clk = 0;
+    always #1 clk <= ~clk;
+
+    reg  [ 3:0] cnt_startup = 0;
+    reg         rst;
+
+    reg         ldpc_in;
+    reg  [31:0] cnt_in = 0;
+    reg  [ 4:0] cnt_sleep = 0;
+    reg         sleep = 0;
+    reg         cnt_in_valid = 0;
+
+
+    wire        m_axis_mac_frame_tvalid;
+    wire [31:0] m_axis_mac_frame_tdata;
+    wire        m_axis_mac_frame_tlast;
+
+    always @(posedge clk) begin
+
+        if (m_axis_mac_frame_tlast == 1) begin
+            cnt_startup <= 0;
+        end
+        else if (cnt_startup < 4'hF) begin
+            cnt_startup <= cnt_startup + 1;
+        end
+        rst <= cnt_startup <= 4'hC;
+
+    end
+
+    always @(posedge clk) begin
+        if (rst) begin
+            cnt_in <= 0;
+        end
+
+        ldpc_in <= $random();
+
+        if (cnt_startup == 4'hF) begin
+            if (sleep) begin
+                cnt_in       <= 0;
+                cnt_in_valid <= 0;
+                cnt_sleep    <= cnt_sleep + 1;
+                if (cnt_sleep == 5'b11111) begin
+                    sleep <= 0;
+                end
+            end
+            else begin
+                cnt_sleep <= 0;
+                if (cnt_in < 1024) begin
+                    cnt_in <= cnt_in + 1;
+                end
+
+                if (cnt_in == 1023) begin
+                    sleep <= 1;
+                end
+
+                cnt_in_valid <= 1;
+            end
+        end
+    end
+
+    extract_mac_frame u_extract_mac_frame (
+        .clk                    (clk),
+        .rst                    (rst),
+        .ldpc_dec_out_start     (cnt_startup == 4'hD),
+        .ldpc_dec_out_valid     (cnt_in_valid),
+        .ldpc_dec_out_data      (ldpc_in),
+        .m_axis_mac_frame_tvalid(m_axis_mac_frame_tvalid),
+        .m_axis_mac_frame_tdata (m_axis_mac_frame_tdata),
+        .m_axis_mac_frame_tready(1),
+        .m_axis_mac_frame_tlast (m_axis_mac_frame_tlast)
+    );
+
+
+
+
+
+
+endmodule

sim/tb_scrambler.v

@@ -0,0 +1,53 @@
+`timescale 1ns / 1ns
+module tb_scrambler ();
+
+
+    reg clk = 0;
+    always #1 clk <= ~clk;
+    reg [3:0] cnt_startup = 0;
+    reg       rst;
+
+    always @(posedge clk) begin
+        if (cnt_startup < 4'hF) begin
+            cnt_startup <= cnt_startup + 1;
+        end
+        rst <= cnt_startup <= 4'hC;
+    end
+
+
+    reg  [31:0] s_axis_tdata;
+    reg         s_axis_tvalid;
+    wire        s_axis_tready;
+    reg         s_axis_tlast;
+    wire [31:0] m_axis_tdata;
+    wire        m_axis_tvalid;
+    // wire        m_axis_tvalid;
+    wire        m_axis_tlast;
+    reg  [31:0] cnt = 0;
+
+    always @(posedge clk) begin
+        s_axis_tvalid <= (cnt_startup == 4'hF && cnt < 32);
+        if (rst) begin
+            s_axis_tdata <= 0;
+        end
+        else if (s_axis_tready && cnt < 32) begin
+            s_axis_tdata <= cnt;
+            cnt          <= cnt + 1;
+        end
+    end
+
+    scrambler u_scrambler (
+        .clk          (clk),
+        .rst          (rst),
+        .s_axis_tdata (s_axis_tdata),
+        .s_axis_tvalid(s_axis_tvalid),
+        .s_axis_tready(s_axis_tready),
+        .s_axis_tlast (s_axis_tlast),
+        .m_axis_tdata (m_axis_tdata),
+        .m_axis_tvalid(m_axis_tvalid),
+        .m_axis_tready(1),
+        .m_axis_tlast (m_axis_tlast)
+    );
+
+
+endmodule