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perf(sys): delete some ila, optimize timing

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ZoroGH
2024-10-13 19:34:35 +08:00
parent 26c24ae5b2
commit 6ddf033548
6 changed files with 50 additions and 52 deletions
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hdl/RecvTop.v
+10 -20
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@@ -140,7 +140,7 @@ module RecvTop (
end
end
assign mgc_start = (cnt_mgc_delay == 8'hFE);
assign mgc_start = (cnt_mgc_delay == 8'hFE);
assign mgc_start_quarter = (cnt_mgc_delay >= 8'hF0) && (cnt_mgc_delay <= 8'hFE);
// * MGC module
@@ -662,25 +662,15 @@ module RecvTop (
);
ila_recv_top u_ila_recv_top (
.clk (clk_quarter),
.probe0 (dagc_data_in_i), // width: 12
.probe1 (dagc_data_in_q), // width: 12
.probe2 (flag_mgc_done), // width: 1
.probe3 (flag_frame_sync), // width: 1
.probe4 (flag_cfo_done), // width: 1
.probe5 (freqdataout_i), // width: 10
.probe6 (freqdataout_q), // width: 10
.probe7 (IntpARdy), // width: 1
.probe8 (IntpOuti), // width: 10
.probe9 (IntpOutq), // width: 10
.probe10(nd_SC_FDE_dout), // width: 1
.probe11(SC_FDE_douti), // width: 10
.probe12(SC_FDE_doutq), // width: 10
.probe13(phase_adjust_rdy), // width: 1
.probe14(phase_adjust_douti), // width: 10
.probe15(phase_adjust_doutq), // width: 10
.probe16(good_frames), // width: 9
.probe17(bad_frames) // width: 9
.clk (clk_quarter),
.probe0(dagc_data_in_i), // width: 12
.probe1(dagc_data_in_q), // width: 12
.probe2(flag_frame_sync), // width: 1
.probe3(phase_adjust_rdy), // width: 1
.probe4(phase_adjust_douti), // width: 10
.probe5(phase_adjust_doutq), // width: 10
.probe6(good_frames), // width: 9
.probe7(bad_frames) // width: 9
);