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feat(top): add mac layer control, half tested

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ZoroGH
2024-07-29 19:04:48 +08:00
parent de8ca3db68
commit 92583b785c
6 changed files with 738 additions and 306 deletions
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hdl/RecvTop.v
+43 -21
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@@ -19,27 +19,28 @@
//
//////////////////////////////////////////////////////////////////////////////////
module RecvTop (
input clk,
input clk_2x, // clk_2x
input clk_4x,
input rst,
input rst2, // TODO： delete the signal
input clk,
input clk_2x, // clk_2x
input clk_4x,
input rst,
input rst2, // TODO： delete the signal
// phy wave
input [11:0] dini,
input [11:0] dinq,
input [11:0] dini,
input [11:0] dinq,
// mgc control
output [ 3:0] ad9361_ctrl_in,
output [ 3:0] ad9361_ctrl_in,
output wire frame_sync_pulse, // in domain clk
//vio
input vio_tsync_inter16, //为1的时候启用内插，从16倍过采样中挑一路
input EQUenable_vio, //为1时启用均衡
input [ 7:0] Zerozone_vio, //零域估计，默认值为8'd29
input [ 6:0] vio_stopbit, //寻找停止位，默认值为7'd60
input vio_tsync_inter16, //为1的时候启用内插，从16倍过采样中挑一路
input EQUenable_vio, //为1时启用均衡
input [ 7:0] Zerozone_vio, //零域估计，默认值为8'd29
input [ 6:0] vio_stopbit, //寻找停止位，默认值为7'd60
// stop signal
output flag_stop, //给shx，拉高8个clk表示当前时帧有效数据接收完毕
output [16:0] addr_stop, //给shx，拉高8个clk,与flag_stop对齐，指示位置与最后1bit有效数据的位置对齐
output flag_stop, //给shx，拉高8个clk表示当前时帧有效数据接收完毕
output [16:0] addr_stop, //给shx，拉高8个clk,与flag_stop对齐，指示位置与最后1bit有效数据的位置对齐
// mac frame header
output [63:0] recvNetData,
output recvNetDataNd
output [63:0] recvNetData,
output recvNetDataNd
);
wire rst_TimeSync;
@@ -255,12 +256,12 @@ module RecvTop (
.m_axis_data_tdata (dmf_tdata_interp4_q)
);
localparam CNT_CHU_SEQ_SYNC_MAX = 40;//! should not less than 3 due to the minimum rst of aresetn
localparam CNT_CHU_SEQ_SYNC_MAX = 40; //! should not less than 3 due to the minimum rst of aresetn
wire [21:0] mag;
wire mag_valid;
wire frame_sync_4x;
wire frame_sync_pulse; // in domain clk
// wire frame_sync_pulse;
reg flag_frame_sync; // active high level
wire rst_frame_sync; // derive from frame sync pulse
reg [ 7:0] cnt_chu_seq_sync; // frame sync delay to chu seq sample start pos
@@ -411,9 +412,9 @@ module RecvTop (
.clk (clk),
.rst (rst_frame_sync),
// param
.EQUenable_vio (EQUenable_vio), //为1时启用均衡
.Zerozone_vio (Zerozone_vio), //零域估计，默认值为8'd29
.flag_ow_left (framesync_tsync), //在一帧内，与第一个数据段的pilot的ow第一个nd对齐
.EQUenable_vio (EQUenable_vio), //为1时启用均衡
.Zerozone_vio (Zerozone_vio), //零域估计，默认值为8'd29
.flag_ow_left (framesync_tsync), //在一帧内，与第一个数据段的pilot的ow第一个nd对齐
.nd (IntpARdy),
.dini (IntpOuti),
.dinq (IntpOutq),
@@ -533,6 +534,27 @@ module RecvTop (
.src_rst () // 1-bit input: optional; required when RST_USED = 1
);
// ***** debug *****
ila_recv_top u_ila_recv_top (
.clk (clk),
.probe0 (flag_mgc_done), // width: 1
.probe1 (flag_frame_sync), // width: 1
.probe2 (mf_data_interp4_q), // width: 32
.probe3 (mf_data_interp4_i), // width: 32
.probe4 (freqestm.freq_out), // width: 14
.probe5 (freqdataout_i), // width: 10
.probe6 (freqdataout_q), // width: 10
.probe7 (nd_SC_FDE_dout), // width: 1
.probe8 (SC_FDE_douti), // width: 10
.probe9 (SC_FDE_doutq), // width: 10
.probe10(LDPC_SyncOut), // width: 1
.probe11(LDPC_Rdy), // width: 1
.probe12(LDPC_Dout), // width: 1
.probe13(bad_frames), // width: 9
.probe14(total_frames), // width: 9
.probe15(mgc_start) // width: 1
);
endmodule