refactor(top): set ps config param, adjust timing

hdl/phy_control.v

@@ -63,8 +63,16 @@ module phy_control #(
     // resetn (should synchronised with "clk")
     input rstn, // can be floating if ASYNC_CLK == 0
 
-    output wire phy_rst,
-    output wire phy_tx_test_flag
+    // control sigal
+    output wire        phy_rst,
+    output wire        phy_tx_test_flag,
+    output wire        phy_tx_iq_reverse,
+    output wire        phy_rx_iq_reverse,
+    // tdma parameters
+    output wire        tdma_flag_is_master,
+    output wire [31:0] tdma_slot_len,
+    output wire [31:0] tdma_tic_2_ps
+
     //--- ADD YOUR OWN PORTS END
 );
 
@@ -329,10 +337,14 @@ module phy_control #(
 
     localparam integer PHY_CR = 'h00000000 >> 2;  // RW
     localparam integer PHY_SR = 'h00000004 >> 2;  // RW
+    localparam integer TDMA_SLOT_LEN = 'h0000_0008 >> 2;
+    localparam integer TDMA_TIC_2_PS = 'h0000_000C >> 2;
 
     // Register definitions
     reg [31:0] phy_cr_reg = 32'h0;
     reg [31:0] phy_sr_reg = 32'h0;
+    reg [31:0] tdma_slot_len_reg = 32'h0;
+    reg [31:0] tdma_tic_2_ps_reg = 32'h0;
 
     // Register Reading
     always @(posedge local_clk) begin
@@ -355,20 +367,26 @@ module phy_control #(
                 case (up_waddr_s)
                     PHY_CR: phy_cr_reg <= up_wdata_s;
                     PHY_SR: phy_sr_reg <= up_wdata_s;
+                    TDMA_SLOT_LEN: tdma_slot_len_reg <= up_wdata_s;
+                    TDMA_TIC_2_PS: tdma_tic_2_ps_reg <= up_wdata_s;
                 endcase
             end
             else begin
-                // self logic 
+                // self logic
             end
         end
     end
 
 
     // control reg definition
-    assign phy_rst          = ~phy_cr_reg[0];
-    assign phy_tx_test_flag = phy_cr_reg[1];
-
-
+    assign phy_rst             = ~phy_cr_reg[0];
+    assign phy_tx_test_flag    = phy_cr_reg[1];
+    assign phy_tx_iq_reverse   = phy_cr_reg[2];
+    assign phy_rx_iq_reverse   = phy_cr_reg[3];
+    assign tdma_flag_is_master = phy_cr_reg[4];
+    // tdma
+    assign tdma_slot_len       = tdma_slot_len_reg;
+    assign tdma_tic_2_ps       = tdma_tic_2_ps_reg;
 
 
     //--- ADD YOUR OWN LOGIC END