refactor(top): set ps config param, adjust timing
This commit is contained in:
+62
-88
@@ -109,10 +109,14 @@ module system_top (
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// phy control signal
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wire phy_rst_vio;
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wire phy_rst_ps;
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wire phy_rst;
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wire phy_tx_test_flag_vio;
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wire phy_tx_test_flag;
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wire phy_tx_iq_reverse;
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wire phy_rx_iq_reverse;
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wire tdma_flag_is_master;
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wire [31:0] tdma_slot_len;
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wire [31:0] tdma_tic_2_ps;
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// tx signal
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wire frame_sync_pulse;
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@@ -143,10 +147,10 @@ module system_top (
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assign ad9361_txnrx = gpio_o[3]; // ad9361 txnrx
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assign ad9361_tx_data_i = bb_tx_iq_reverse ? bb_tx_q : bb_tx_i;
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assign ad9361_tx_data_q = bb_tx_iq_reverse ? bb_tx_i : bb_tx_q;
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assign bb_rx_i = bb_rx_iq_reverse ? ad9361_rx_data_q : ad9361_rx_data_i;
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assign bb_rx_q = bb_rx_iq_reverse ? ad9361_rx_data_i : ad9361_rx_data_q;
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assign ad9361_tx_data_i = phy_tx_iq_reverse ? bb_tx_q : bb_tx_i;
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assign ad9361_tx_data_q = phy_tx_iq_reverse ? bb_tx_i : bb_tx_q;
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assign bb_rx_i = phy_rx_iq_reverse ? ad9361_rx_data_q : ad9361_rx_data_i;
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assign bb_rx_q = phy_rx_iq_reverse ? ad9361_rx_data_i : ad9361_rx_data_q;
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// ******** Logic Block ********
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@@ -174,73 +178,74 @@ module system_top (
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);
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MM7020_BD_wrapper u_MM7020_BD_wrapper (
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.ad9361_spi_clk (ad9361_spi_clk),
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.ad9361_spi_csn (ad9361_spi_csn),
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.ad9361_spi_miso (ad9361_spi_miso),
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.ad9361_spi_mosi (ad9361_spi_mosi),
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.clk_ps (clk_poweron),
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.rst_ps (rst_sys),
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.ad9361_spi_clk (ad9361_spi_clk),
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.ad9361_spi_csn (ad9361_spi_csn),
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.ad9361_spi_miso (ad9361_spi_miso),
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.ad9361_spi_mosi (ad9361_spi_mosi),
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.clk_ps (clk_poweron),
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.rst_ps (rst_sys),
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// ddr
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.ddr_addr (ddr_addr),
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.ddr_ba (ddr_ba),
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.ddr_cas_n (ddr_cas_n),
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.ddr_ck_n (ddr_ck_n),
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.ddr_ck_p (ddr_ck_p),
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.ddr_cke (ddr_cke),
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.ddr_cs_n (ddr_cs_n),
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.ddr_dm (ddr_dm),
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.ddr_dq (ddr_dq),
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.ddr_dqs_n (ddr_dqs_n),
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.ddr_dqs_p (ddr_dqs_p),
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.ddr_odt (ddr_odt),
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.ddr_ras_n (ddr_ras_n),
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.ddr_reset_n (ddr_reset_n),
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.ddr_we_n (ddr_we_n),
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.ddr_addr (ddr_addr),
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.ddr_ba (ddr_ba),
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.ddr_cas_n (ddr_cas_n),
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.ddr_ck_n (ddr_ck_n),
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.ddr_ck_p (ddr_ck_p),
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.ddr_cke (ddr_cke),
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.ddr_cs_n (ddr_cs_n),
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.ddr_dm (ddr_dm),
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.ddr_dq (ddr_dq),
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.ddr_dqs_n (ddr_dqs_n),
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.ddr_dqs_p (ddr_dqs_p),
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.ddr_odt (ddr_odt),
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.ddr_ras_n (ddr_ras_n),
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.ddr_reset_n (ddr_reset_n),
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.ddr_we_n (ddr_we_n),
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// fixed io
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.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
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.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
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.fixed_io_mio (fixed_io_mio),
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.fixed_io_ps_clk (fixed_io_ps_clk),
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.fixed_io_ps_porb (fixed_io_ps_porb),
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.fixed_io_ps_srstb (fixed_io_ps_srstb),
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.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
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.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
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.fixed_io_mio (fixed_io_mio),
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.fixed_io_ps_clk (fixed_io_ps_clk),
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.fixed_io_ps_porb (fixed_io_ps_porb),
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.fixed_io_ps_srstb (fixed_io_ps_srstb),
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// gpio ps
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.gpio_i (gpio_i),
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.gpio_o (gpio_o),
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.gpio_t (gpio_t),
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.gpio_i (gpio_i),
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.gpio_o (gpio_o),
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.gpio_t (gpio_t),
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// intr pl to ps
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.pl2ps_intr2 (intr_2ps),
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.pl2ps_intr3 (flag_mgc_done_pulse),
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.pl2ps_intr2 (intr_2ps),
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.pl2ps_intr3 (flag_mgc_done_pulse),
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// tx fifo
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.tx_data_src_count (tx_data_src_count),
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.tx_data_src_tdata (tx_data_src_tdata),
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.tx_data_src_tready(tx_data_src_tready),
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.tx_data_src_tvalid(tx_data_src_tvalid),
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.tx_data_src_count (tx_data_src_count),
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.tx_data_src_tdata (tx_data_src_tdata),
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.tx_data_src_tready (tx_data_src_tready),
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.tx_data_src_tvalid (tx_data_src_tvalid),
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//phy control signal
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.phy_rst (phy_rst_ps),
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.phy_tx_test_flag (phy_tx_test_flag),
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.phy_rst (phy_rst),
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.phy_tx_test_flag (phy_tx_test_flag),
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.phy_tx_iq_reverse (phy_tx_iq_reverse),
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.phy_rx_iq_reverse (phy_rx_iq_reverse),
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.tdma_flag_is_master(tdma_flag_is_master),
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.tdma_slot_len (tdma_slot_len),
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.tdma_tic_2_ps (tdma_tic_2_ps),
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// uart
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.uart_rx (uart_rx),
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.uart_tx (uart_tx)
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.uart_rx (uart_rx),
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.uart_tx (uart_tx)
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);
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tdma #(
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.SLOT_LEN (750000), // 50MHz--> 15ms
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.TIC_TO_PS_LEN (700000),
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.TIC_FRAME_SYNC(42344)
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// .SLOT_LEN (625001), // 50MHz--> 15ms
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// .TIC_TO_PS_LEN (575000),
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// .TIC_FRAME_SYNC(42344)
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) u_tdma (
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tdma u_tdma (
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.clk (clk_1x),
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.rst (rst_sys),
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.flag_is_master (flag_is_master),
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.flag_is_master (tdma_flag_is_master),
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.flag_frame_sync(frame_sync_pulse),
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.tdma_slot_len (tdma_slot_len[23:0]),
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.tdma_tic_2_ps (tdma_tic_2_ps[23:0]),
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.intr_2ps (intr_2ps),
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.tx_start (tx_start),
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.rx_rst (rx_rst)
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);
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// net_city u_net_city (
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// .clk (clk_1x),
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// .rst_initial (rst_sys),
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@@ -270,7 +275,7 @@ module system_top (
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enc_control u_enc_control (
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.clk (clk_poweron),
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.rst (rst_sys | phy_rst_ps),
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.rst (rst_sys | phy_rst),
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.s_axis_fifo_tvalid (tx_data_src_tvalid),
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.s_axis_fifo_tready (tx_data_src_tready),
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.s_axis_fifo_tdata (tx_data_src_tdata),
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@@ -296,7 +301,7 @@ module system_top (
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.hopping_freq (),
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.ad9361_tx_data_i (bb_tx_i),
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.ad9361_tx_data_q (bb_tx_q),
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.test (tx_test_flag | phy_tx_test_flag_vio),
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.test (phy_tx_test_flag),
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.hop_wait (100)
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);
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@@ -349,28 +354,6 @@ module system_top (
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// ******** CDC ********
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xpm_cdc_single #(
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.DEST_SYNC_FF (4), // DECIMAL; range: 2-10
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.INIT_SYNC_FF (0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
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.SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
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.SRC_INPUT_REG (1) // DECIMAL; 0=do not register input, 1=register input
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) xpm_cdc_single_tx_test_flag_ps_inst (
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.dest_out(tx_test_flag), // 1-bit output: src_in synchronized to the destination clock domain. This output is registered.
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.dest_clk(clk_1x), // 1-bit input: Clock signal for the destination clock domain.
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.src_clk (clk_poweron), // 1-bit input: optional; required when SRC_INPUT_REG = 1
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.src_in (phy_tx_test_flag) // 1-bit input: Input signal to be synchronized to dest_clk domain.
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);
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xpm_cdc_sync_rst #(
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.DEST_SYNC_FF (4), // DECIMAL; range: 2-10
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.INIT (1), // DECIMAL; 0=initialize synchronization registers to 0, 1=initialize synchronization registers to 1
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.INIT_SYNC_FF (0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
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.SIM_ASSERT_CHK(0) // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
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) xpm_cdc_sync_rst_phy_rst_inst (
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.dest_rst(phy_rst), // 1-bit output: src_rst synchronized to the destination clock domain. This output is registered.
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.dest_clk(clk_1x), // 1-bit input: Destination clock.
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.src_rst (phy_rst_ps) // 1-bit input: Source reset signal.
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);
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// ******** Debug ********
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@@ -399,13 +382,4 @@ module system_top (
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end
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vio_phy_control u_vio_phy_control (
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.clk (clk_1x), // input wire clk
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.probe_out0(flag_is_master), // output wire [0 : 0]
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.probe_out1(bb_tx_iq_reverse), // output wire [0 : 0]
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.probe_out2(bb_rx_iq_reverse) // output wire [0 : 0]
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);
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endmodule
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