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refactor(top): set ps config param, adjust timing

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ZoroGH
2024-08-03 21:02:08 +08:00
parent 145e8c0930
commit a4eb609aae
4 changed files with 106 additions and 123 deletions
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hdl/tdma.v
+11 -27
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@@ -14,17 +14,17 @@
// ! PLEASE MAKE SURE THE PARAMETER ARE VALID
// ! WHEN U INSTANTIATE THIS MODULE
module tdma #(
parameter SLOT_LEN = 750000,
parameter TIC_TO_PS_LEN = 700000,
parameter TIC_FRAME_SYNC = 42344
) (
input clk,
input rst,
input flag_is_master, // TODO: refactor it to parameters
input flag_frame_sync,
output intr_2ps,
output tx_start,
output reg rx_rst
input clk,
input rst,
input flag_is_master,
input flag_frame_sync,
input wire [23:0] tdma_slot_len,
input wire [23:0] tdma_tic_2_ps,
output intr_2ps,
output tx_start,
output reg rx_rst
);
// TODO: 需要检查综合后电路是否会被优化
@@ -38,7 +38,7 @@ module tdma #(
// ******** Assingment ********
assign tx_start = flag_is_master & (cnt == 16'd10);
assign intr_2ps = flag_is_master & (cnt == TIC_TO_PS_LEN - 1);
assign intr_2ps = flag_is_master & (cnt == tdma_tic_2_ps - 1);
// ******** Logic Block ********
@@ -55,7 +55,7 @@ module tdma #(
end
else begin
// master
if (cnt < SLOT_LEN - 1) begin
if (cnt < tdma_slot_len - 1) begin
cnt <= cnt + 1;
end
else begin
@@ -75,22 +75,6 @@ module tdma #(
end
end
// always @(posedge clk) begin
// if (rst) begin
// flag_is_tx_slot <= 0;
// end
// else if (!flag_is_master && flag_frame_sync) begin
// flag_is_tx_slot <= 0;
// end
// else if (cnt == 16'd1) begin
// flag_is_tx_slot <= ~flag_is_tx_slot;
// end
// end
// ******** Inst ********
// ******** Debug ********