ZoroGH/MM7020
1
0
Fork 0
Code Issues 2 Pull Requests Actions Packages Projects Releases 3 Wiki Activity

stash pop

Browse Source
This commit is contained in:
ZoroGH
2024-07-22 15:09:15 +08:00
parent d210233e74
commit da1073f750
13 changed files with 12668 additions and 158 deletions
Download Patch File Download Diff File Expand all files Collapse all files
hdl/RecvTop.v
+232 -139
View File
@@ -28,44 +28,12 @@ module RecvTop (
input [11:0] dini,
input [11:0] dinq,
//视频数据存储，shx
input [13:0] recv_addr_new_0,
input [13:0] recv_addr_new_1,
input [13:0] recv_addr_new_2,
input [13:0] recv_addr_new_3,
output [ 7:0] recv_data_new_0,
output [ 7:0] recv_data_new_1,
output [ 7:0] recv_data_new_2,
output [ 7:0] recv_data_new_3,
output [16:0] RAMaddra_write_0,
output [16:0] RAMaddra_write_1,
output [16:0] RAMaddra_write_2,
output [16:0] RAMaddra_write_3,
output [16:0] RAMaddra_new_0,
output [16:0] RAMaddra_new_1,
output [16:0] RAMaddra_new_2,
output [16:0] RAMaddra_new_3,
output flag_stop, //给shx，拉高8个clk表示当前时帧有效数据接收完毕
output [16:0] addr_stop, //给shx，拉高8个clk,与flag_stop对齐，指示位置与最后1bit有效数据的位置对齐
output [3:0] ad9361_ctrl_in,
//vio
// input DC_move_able, //为1的时候启用去直流，为0的时候不启用
// input [1:0] vio_powertest_h, //DAGC
// input [1:0] vio_powertest_l, //DAGC
// input DAGC_enab, //为1的时候启用DAGC，为0的时候不启用DAGC
// input vio_tsync_inter16, //为1的时候启用内插，从16倍过采样中挑一路
// input EQUenable_vio, //为1时启用均衡
// input [7:0] Zerozone_vio, //零域估计，默认值为8'd29
input [6:0] vio_stopbit, //寻找停止位，默认值为7'd60
output flag_stop, //给shx，拉高8个clk表示当前时帧有效数据接收完毕
output [16:0] addr_stop, //给shx，拉高8个clk,与flag_stop对齐，指示位置与最后1bit有效数据的位置对齐
//9361、射频增益控制
output [7:0] data_9361,
output [9:0] addr_9361,
output enab_9361,
output D1_12dB,
output D2_6dB,
output D3_18dB,
output D4_12dB,
input [6:0] vio_stopbit, //寻找停止位，默认值为7'd60
//debug
//trigger
@@ -139,74 +107,212 @@ module RecvTop (
output reg flagoverflow = 1'd0, //总溢出标志
output Pilot_rdy_hide1_d1,
output [63:0] recvNetData,
output recvNetDataNd,
input debug_loss
// input [ 7:0] MAC_idNum
// input [ 7:0] video_id01,
// input [ 7:0] video_id02,
// input [ 7:0] video_id03
);
reg [7:0] cnt_mgc_delay;
wire mgc_start;
wire flag_mgc_done; // level flag
wire flag_mgc_done_4x; // level flag
always @(posedge clk) begin
if (rst) begin
cnt_mgc_delay <= 0;
end
else if (cnt_mgc_delay < 8'hff) begin
cnt_mgc_delay <= cnt_mgc_delay + 1;
end
else begin
cnt_mgc_delay <= cnt_mgc_delay;
end
end
assign mgc_start = (nt_mgc_delay == 8'hff);
MGC_adaptation MGC_adaptation (
.clk (clk),
.rst (rst),
.dini(dini),
.dinq(dinq),
.data_9361(data_9361),
.addr_9361(addr_9361),
.enab_9361(enab_9361),
.D1_12dB (D1_12dB),
.D2_6dB (D2_6dB),
.D3_18dB (D3_18dB),
.D4_12dB (D4_12dB),
.mgc1_rdy(mgc1_rdy)
ad9361_mgc_pin_ctrl u_ad9361_mgc_pin_ctrl (
.clk (clk),
.rst (rst),
.start (mgc_start),
.rx_data_i (dini),
.rx_data_q (dinq),
.ad9361_ctrl_in(ad9361_ctrl_in),
.flag_mgc_done (flag_mgc_done)
);
wire MF_rdy; // flag_mgc_done_d1
wire MF_rst; // flag_mgc_done_pulse_d2
wire MF_rdy;
wire MF_rst;
wire fifo_out_valid;
reg [ 2:0] cnt_fifo_out_valid;
reg [ 2:0] cnt_fifo_out_valid_sel = 1; // 根据speed mode对应的计数器边界值
wire [31:0] fifo_out;
reg dmf_s_valid;
wire dmf_tvalid_interp4_i;
wire dmf_tvalid_interp4_q;
wire [31:0] mf_data_interp4_i;
wire [31:0] mf_data_interp4_q;
wire [23:0] dmf_tdata_interp4_i;
wire [23:0] dmf_tdata_interp4_q;
// valid signal for dmf
always @(posedge clk_4x) begin
if (rst) begin
dmf_s_valid <= 1'd0;
end
else if (flag_mgc_done_4x && fifo_out_valid && cnt_fifo_out_valid == cnt_fifo_out_valid_sel) begin
// fifo_out_valid may be not trustable at the rst state
dmf_s_valid <= 1'd1;
end
else begin
dmf_s_valid <= 1'd0;
end
end
always @(posedge clk_4x) begin
if (rst) begin
cnt_fifo_out_valid <= 3'd0;
end
else if (fifo_out_valid) begin
if (cnt_fifo_out_valid == cnt_fifo_out_valid_sel) begin // refer to Receiver.v
cnt_fifo_out_valid <= 3'd0;
end
else begin
cnt_fifo_out_valid <= cnt_fifo_out_valid + 3'd1;
end
end
else begin
cnt_fifo_out_valid <= cnt_fifo_out_valid;
end
end
MF_Top MF_Top (
.clk(clk),
.rst(rst),
// .rst (rst),
.dini (dini),
.dinq (dinq),
.start(mgc1_rdy),
.matchfilterout_i(matchfilterout_i),
.matchfilterout_q(matchfilterout_q),
.MF_rdy (MF_rdy),
.MF_rst (MF_rst)
// Match filter
fir_match_interp4 u_fir_match_filter_interp4_i (
.aclk (clk), // input wire aclk
.s_axis_data_tvalid(flag_mgc_done), // input wire s_axis_data_tvalid
.s_axis_data_tready(), // output wire s_axis_data_tready
.s_axis_data_tdata ({4'd0, dini}), // input wire [15 : 0] s_axis_data_tdata
.m_axis_data_tvalid(), // output wire m_axis_data_tvalid
.m_axis_data_tdata (mf_data_interp4_i) // output wire [31 : 0] m_axis_data_tdata
);
fir_match_interp4 u_fir_match_filter_interp4_q (
.aclk (clk), // input wire aclk
.s_axis_data_tvalid(flag_mgc_done), // input wire s_axis_data_tvalid
.s_axis_data_tready(), // output wire s_axis_data_tready
.s_axis_data_tdata ({4'd0, dinq}), // input wire [15 : 0] s_axis_data_tdata
.m_axis_data_tvalid(), // output wire m_axis_data_tvalid
.m_axis_data_tdata (mf_data_interp4_q) // output wire [31 : 0] m_axis_data_tdata
);
// CDC into clk_4x
fifo_shift u_fifo_shift (
// input
.s_aclk (clk), // input wire s_aclk
.s_aresetn (flag_mgc_done), // input wire s_aresetn
.s_axis_tvalid(flag_mgc_done), // input wire s_axis_tvalid
.s_axis_tready(), // output wire s_axis_tready
.s_axis_tdata ({8'd0, mf_data_interp4_q[29-:12], mf_data_interp4_i[29-:12]}), // input wire [31 : 0] s_axis_tdata
// output
.m_aclk (clk_4x), // input wire m_aclk
.m_axis_tvalid(fifo_out_valid), // output wire m_axis_tvalid
.m_axis_tready(1'b1), // input wire m_axis_tready
.m_axis_tdata (fifo_out), // output wire [31 : 0] m_axis_tdata
.wr_rst_busy (),
.rd_rst_busy ()
);
fir_dmf_interp4 u_fir_dmf_interp4_i (
.aclk (clk_4x),
.s_axis_data_tvalid(dmf_s_valid),
.s_axis_data_tready(),
.s_axis_data_tdata ({4'd0, fifo_out[11:0]}),
.m_axis_data_tvalid(dmf_tvalid_interp4_i),
.m_axis_data_tdata (dmf_tdata_interp4_i)
);
fir_dmf_interp4 u_fir_dmf_interp4_q (
.aclk (clk_4x),
.s_axis_data_tvalid(dmf_s_valid),
.s_axis_data_tready(),
.s_axis_data_tdata ({4'd0, fifo_out[23:12]}),
.m_axis_data_tvalid(dmf_tvalid_interp4_q),
.m_axis_data_tdata (dmf_tdata_interp4_q)
);
wire [21:0] mag;
wire mag_valid;
wire frame_sync_4x;
wire frame_sync_pulse; // in domain clk
MagnitudeEstimator #(
.VEC_WIDTH(21)
) u_MagnitudeEstimator (
.clk (clk_4x),
.rst (rst),
.vec_valid(dmf_tvalid_interp4_i),
.I (dmf_tdata_interp4_i),
.Q (dmf_tdata_interp4_q),
.mag (mag),
.mag_valid(mag_valid)
);
PAPR #(
.MAG_WIDTH (22),
.WINDOW_DEPTH(1023)
) u_PAPR (
.clk (clk_4x),
.rst (rst),
.vec_mag (mag),
.mag_valid (mag_valid),
.frame_sync (frame_sync_4x),
.frame_sync_pulse()
);
// wire [9:0] DAGC_out_i;
// wire [9:0] DAGC_out_q;
wire [9:0] FrameSync_douti;
wire [9:0] FrameSync_doutq;
wire dagc_rdy;
wire mgc_rdy;
wire rst_dagc;
DAGC_v2 DAGC_v2 (
.clk (clk),
.rst (~mgc1_rdy),
.mgc1_rdy (MF_rdy),
.framesync_d0 (framesync),
.vio_powertest_h (2'b00),
.vio_powertest_l (2'b00),
.matchfilterout_i(FrameSync_douti),
.matchfilterout_q(FrameSync_doutq),
// output
.DAGC_out_i (DAGC_out_i),
.DAGC_out_q (DAGC_out_q),
//flag
.flag_agch (flag_agch),
.flag_agcl (flag_agcl),
.flag_agc_power (flag_agc_power),
.agc_ref (agc_ref),
.agc_check (agc_check),
.dagc_rdy (dagc_rdy),
.mgc_rdy (mgc_rdy),
.rst_dagc (rst_dagc)
);
//帧同步模块
assign FrameSync_dini = (DAGC_enab) ? DAGC_out_i : matchfilterout_i;
assign FrameSync_dinq = (DAGC_enab) ? DAGC_out_q : matchfilterout_q;
assign FrameSync_dini = DAGC_out_i;
assign FrameSync_dinq = DAGC_out_q;
// wire framesync;
wire Sync_rdy;
wire Pilot_rdy;
wire Sync_rdy;
wire Pilot_rdy;
wire [9:0] FrameSync_douti;
wire [9:0] FrameSync_doutq;
SCFDE_recv_FrameSync SCFDE_recv_FrameSync_inst (
@@ -217,10 +323,10 @@ module RecvTop (
.datain_q (matchfilterout_q),
.Sync_i (FrameSync_douti),
.Sync_q (FrameSync_doutq),
.Sync_rdy (Sync_rdy), // 帧同步找到了过门限峰值
.Pilot_rdy (Pilot_rdy),// 开始取导频的标志位 not used
.flag_sync (framesync), // high level flag
.Pilot_rdy_hide1_d1(Pilot_rdy_hide1_d1) // not used
.Sync_rdy (Sync_rdy), // 帧同步找到了过门限峰值
.Pilot_rdy (Pilot_rdy), // 开始取导频的标志位 not used
.flag_sync (framesync), // high level flag not used
.Pilot_rdy_hide1_d1(Pilot_rdy_hide1_d1) // not used
);
//
@@ -230,12 +336,13 @@ module RecvTop (
if (Pilot_rdy_hide1_d1) begin
cnt_lost <= 21'd0;
framelost <= 1'b0;
end else begin
end
else begin
if (cnt_lost >= 21'd750000) begin
;
cnt_lost <= 21'd0;
framelost <= 1'b1;
end else begin
end
else begin
cnt_lost <= 21'd1 + cnt_lost;
framelost <= 1'b0;
end
@@ -490,61 +597,47 @@ module RecvTop (
.nd_ber (nd_ber),
.recvNetData (recvNetData),
.recvNetDataNd(recvNetDataNd)
// .MAC_idNum (MAC_idNum)
// .video_id01 (8'd0),
// .video_id02 (8'd0),
// .video_id03 (8'd0)
);
/*ila_recvtop ila_recvtop(
.clk(clk),
.probe0(framesync),
.probe1(framesync_delay),
.probe2(phase_adjust_rdy),
.probe3(nd_SC_FDE_dout),
.probe4(IQmergerdy),
.probe5(IQmergedout),
.probe6(LDPC_Rdy),
.probe7(LDPC_Dout),
.probe8(SC_FDE_douti),
.probe9(SC_FDE_doutq),
.probe10(total_frames),
.probe11(good_frames),
.probe12(dini),
.probe13(dinq),
.probe14(phase_adjust_douti),
.probe15(phase_adjust_doutq),
.probe16(D1_12dB),
.probe17(D2_6dB),
.probe18(D3_18dB),
.probe19(D4_12dB)
);*/
ila_recvtest ila_recvtest (
.clk (clk),
.probe0(framesync),
.probe1(framesync_delay),
.probe2(D1_12dB),
.probe3(D2_6dB),
.probe4(D3_18dB),
.probe5(D4_12dB),
.probe6(mgc1_rdy),
.probe7(rst),
.probe8(dini),
.probe9(dinq)
// **** cdc ****
xpm_cdc_single #(
.DEST_SYNC_FF (2), // DECIMAL; range: 2-10
.INIT_SYNC_FF (1), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
.SIM_ASSERT_CHK(1), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
.SRC_INPUT_REG (1) // DECIMAL; 0=do not register input, 1=register input
) xpm_cdc_startup_inst (
.dest_out(flag_mgc_done_4x), // 1-bit output: src_in synchronized to the destination clock domain. This output is
// registered.
.dest_clk(clk_4x), // 1-bit input: Clock signal for the destination clock domain.
.src_clk (clk), // 1-bit input: optional; required when SRC_INPUT_REG = 1
.src_in (flag_mgc_done) // 1-bit input: Input signal to be synchronized to dest_clk domain.
);
/*ila_decode ila_decode(
.clk(clk2),
.probe0(IQmergerdy),
.probe1(IQmergedout),
.probe2(LDPC_Dout),
.probe3(LDPC_Rdy),
.probe4(framerdy),
.probe5(total_frames),
.probe6(good_frames)
);*/
xpm_cdc_pulse #(
.DEST_SYNC_FF (4), // DECIMAL; range: 2-10
.INIT_SYNC_FF (0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
.REG_OUTPUT (0), // DECIMAL; 0=disable registered output, 1=enable registered output
.RST_USED (0), // DECIMAL; 0=no reset, 1=implement reset
.SIM_ASSERT_CHK(1) // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
) xpm_cdc_frame_sync_pulse_inst (
.dest_pulse(frame_sync_pulse), // 1-bit output: Outputs a pulse the size of one dest_clk period when a pulse
// transfer is correctly initiated on src_pulse input. This output is
// combinatorial unless REG_OUTPUT is set to 1.
.dest_clk (clk), // 1-bit input: Destination clock.
.dest_rst (), // 1-bit input: optional; required when RST_USED = 1
.src_clk (clk_4x), // 1-bit input: Source clock.
.src_pulse (frame_sync_4x), // 1-bit input: Rising edge of this signal initiates a pulse transfer to the
// destination clock domain. The minimum gap between each pulse transfer must be
// at the minimum 2*(larger(src_clk period, dest_clk period)). This is measured
// between the falling edge of a src_pulse to the rising edge of the next
// src_pulse. This minimum gap will guarantee that each rising edge of src_pulse
// will generate a pulse the size of one dest_clk period in the destination
// clock domain. When RST_USED = 1, pulse transfers will not be guaranteed while
// src_rst and/or dest_rst are asserted.
.src_rst () // 1-bit input: optional; required when RST_USED = 1
);
endmodule