stash pop

hdl/ad9361_mgc_pin_ctrl.v

@@ -14,13 +14,14 @@
 
 
 module ad9361_mgc_pin_ctrl (
-    input              clk, 
+    input              clk,
     input              rst,
-    // input               start,
+    input              start,
     input       [11:0] rx_data_i,
     input       [11:0] rx_data_q,
     // this port is from zynq to ad9361
-    output wire [ 3:0] ad9361_ctrl_in
+    output wire [ 3:0] ad9361_ctrl_in,
+    output reg         flag_mgc_done
 
 );
 
@@ -41,6 +42,9 @@ module ad9361_mgc_pin_ctrl (
     wire       flag_too_low;  // low amplitude
     wire       flag_adjust;
     reg  [3:0] cnt_pulse_width;
+    // indicating the mgc done ready
+    wire       power_measure_done_pulse;
+
 
     // adjust fsm
     localparam S_IDLE = 0;
@@ -76,6 +80,15 @@ module ad9361_mgc_pin_ctrl (
         start_d1 <= start;
     end
 
+    // single pulse to level signal
+    always @(posedge clk) begin
+        if (rst) begin
+            flag_mgc_done <= 0;
+        end
+        else if (power_measure_done_pulse) begin
+            flag_mgc_done <= 1;
+        end
+    end
 
     // FSM
     always @(posedge clk) begin
@@ -122,21 +135,22 @@ module ad9361_mgc_pin_ctrl (
     // measuring the signal power
     // two cases, amplitute too high or amplitude too low
     power_measure u_power_measure (
-        .clk          (clk),
-        .rst          (rst),
-        .start        (start_posedge),
-        .data_i       (rx_data_i),
-        .data_q       (rx_data_q),
-        .flag_too_high(flag_too_high),
-        .flag_too_low (flag_too_low)
+        .clk                     (clk),
+        .rst                     (rst),
+        .start                   (start_posedge),
+        .data_i                  (rx_data_i),
+        .data_q                  (rx_data_q),
+        .flag_too_high           (flag_too_high),
+        .flag_too_low            (flag_too_low),
+        .power_measure_done_pulse(power_measure_done_pulse)
     );
 
     // ********    Debug    ********
 
-    vio_mgc_control_in u_vio_mgc_control_in (
-        .clk       (clk),   // input wire clk
-        .probe_out0(start)  // output wire [0 : 0] probe_out0
-    );
+    // vio_mgc_control_in u_vio_mgc_control_in (
+    //     .clk       (clk),   // input wire clk
+    //     .probe_out0(start)  // output wire [0 : 0] probe_out0
+    // );
 
     ila_ad9361_mgc u_ila_ad9361_mgc (
         .clk   (clk),                                 // input wire clk
@@ -148,7 +162,7 @@ module ad9361_mgc_pin_ctrl (
         .probe5(flag_too_high),                       // input wire [0:0]  probe5 
         .probe6(flag_too_low),                        // input wire [0:0]  probe6
         .probe7(u_power_measure.cnt_amp_too_high),    // input wire [0:0]  probe6
-        .probe8(u_power_measure.cnt_startup)           // input wire [11:0]  probe6
+        .probe8(u_power_measure.cnt_startup)          // input wire [11:0]  probe6
     );