stash pop

hdl/power_measure.v

@@ -25,7 +25,8 @@ module power_measure (
     input  wire [11:0] data_i,
     input  wire [11:0] data_q,
     output reg         flag_too_high,
-    output reg         flag_too_low
+    output reg         flag_too_low,
+    output reg         power_measure_done_pulse
 );
 
     localparam CNT_WAIT_9361_MAX = 80;  //* 等待周期数
@@ -56,11 +57,11 @@ module power_measure (
     reg [ 3:0] sign_bit_num_min_i;
     reg [ 3:0] sign_bit_num_q;
     reg [ 3:0] sign_bit_num_min_q;
-    
+
     // startup
     reg [ 7:0] cnt_startup;  // set rx gain to max each time start posedge comes
     reg [ 3:0] cnt_amp_too_high;  // for short cuirt 
-    
+
     // abs
     reg [11:0] data_i_abs;
     reg [11:0] data_q_abs;
@@ -200,6 +201,15 @@ module power_measure (
         end
     end
 
+    always @(posedge clk) begin
+        if (cs == S_MEASURE_ADJ && ns == S_MEASURE_IDLE) begin
+            power_measure_done_pulse <= 1;
+        end
+        else begin
+            power_measure_done_pulse <= 0;
+        end
+    end
+
 
     // get the abs value
     always @(posedge clk) begin