Add the recv hdl file

hdl/IQmerge.v

@@ -0,0 +1,149 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    16:01:14 07/21/2018 
+// Design Name: 
+// Module Name:    IQmerge 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module IQmerge(
+	input clk,
+	input clk2,
+	input rst,
+	input nd,
+	input framesync,
+	input [9:0] dini,
+	input [9:0] dinq,
+	
+	output reg rdy = 1'b0,
+	output reg ldpcsyncin = 1'b0,
+	output  [7:0] dout
+    );
+	
+	
+
+	
+	
+	reg  [9:0] addra = 10'd0;
+	reg [15:0] dina = 16'd0;
+	reg [10:0] addrb = 11'd0;
+	RAM_IQmerge RAM_IQmerge (
+	  .clka(clk), // input clka
+	  .wea(1'b1), // input [0 : 0] wea
+	  .addra(addra), // input [9 : 0] addra
+	  .dina(dina), // input [15 : 0] dina
+	  .clkb(clk2), // input clkb
+	  .addrb(addrb), // input [10 : 0] addrb
+	  .doutb(dout) // output [7 : 0] doutb
+	);
+	
+	
+	
+	
+	reg [9:0] addradelay = 10'd0;
+	reg [8:0] bagcount = 9'd0;
+	reg [1:0] writevalid = 2'd0;
+	always @(posedge clk)begin
+		if(rst)begin
+			addra		<= 10'd0;
+			addradelay	<= 10'd0;
+			dina		<= 16'd0;
+			writevalid	<= 2'd0;
+			bagcount	<= 9'd0;
+		end else begin
+			case(writevalid)
+			2'd0:begin
+				if(framesync)begin
+					writevalid	<= 2'd1;
+				end else begin
+					writevalid	<= 2'd0;
+				end
+				bagcount	<= 9'd0;
+			end
+			2'd1:begin		
+				if(nd)begin
+					addradelay	<= addradelay + 10'd1;
+					dina		<= {dinq[9:2],dini[9:2]};
+					addra 		<= addradelay;
+					if(addradelay == 10'd1023)begin
+						writevalid	<= 2'd2;							
+					end else begin
+						writevalid	<= 2'd1;
+					end
+				end else begin
+					addradelay	<= addradelay;
+					addra		<= addra;
+					dina		<= dina;
+					writevalid	<= 2'd1;
+				end
+			end
+			2'd2:begin
+				bagcount	<= bagcount + 9'd1;
+				if(bagcount == 9'd104)begin
+					writevalid	<= 2'd0;
+				end else begin
+					writevalid	<= 2'd1;
+				end
+			end
+			default:writevalid	<= 2'd0;
+			endcase
+		end			
+	end
+	
+	reg readvalid = 1'b0;
+	always @(posedge clk2)begin
+		if(rst)begin
+			addrb		<= 11'd0;
+			readvalid	<= 1'b0;
+			ldpcsyncin	<= 1'b0;
+		end else begin
+			if(!readvalid)begin
+				addrb	<= 11'd0;
+				if(addra == 10'd1000)begin
+					ldpcsyncin	<= 1'b1;
+					readvalid	<= 1'b1;
+				end else begin	
+					ldpcsyncin	<= 1'b0;
+					readvalid	<= 1'b0;
+				end 
+			end else begin
+				ldpcsyncin	<= 1'b0;
+				addrb		<= addrb + 11'd1;
+				if(addrb == 11'd2047)begin	
+					readvalid	<= 1'b0;
+				end else begin
+					readvalid	<= 1'b1;
+				end				
+			end
+		end			
+	end
+	
+	
+	always @(posedge clk2)begin
+		rdy <= readvalid;
+	end
+	
+	/*ila_IQmerge ila_IQmerge(
+		.clk(clk2),
+		.probe0(clk),
+		.probe1(writevalid),
+		.probe2(dini[9:2]),
+		.probe3(dinq[9:2]),
+		.probe4(dout),
+		.probe5(framesync)
+	);*/
+
+
+endmodule