Add the recv hdl file

hdl/Interp_quarter.v

@@ -0,0 +1,69 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2019/11/18 21:06:38
+// Design Name: 
+// Module Name: Interp_quarter
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module Interp_quarter(
+	input clk,
+	input [9:0] din_p1,
+	input [9:0] din_t0,
+	input [9:0] din_n1,
+	input [9:0] din_n2,
+	
+	output reg [9:0] dout
+
+    );
+	
+	wire [13:0] multquartern2;
+	wire [15:0] multquartern1;
+	wire [16:0] multquartert0;
+	wire [13:0] multquarterp1;
+	CN2 CN2_quarter (.CLK(clk), .A(din_p1), .P(multquartern2));	
+	CN1 CN1_quarter (.CLK(clk), .A(din_t0), .P(multquartern1));	
+	CT0 CT0_quarter (.CLK(clk), .A(din_n1), .P(multquartert0));	
+	CP1 CP1_quarter (.CLK(clk), .A(din_n2), .P(multquarterp1));	
+	
+
+
+	reg [16:0] sumquarter1 = 17'd0;
+	reg [17:0] sumquarter2 = 18'd0;
+	always @(posedge clk)begin
+		sumquarter1 <= {{3{multquartern2[13]}},multquartern2}+{multquartern1[15],multquartern1};
+		sumquarter2 <= {{4{multquarterp1[13]}},multquarterp1}+{multquartert0[16],multquartert0};
+	end
+	
+	
+	reg [18:0] sumquarter3 = 19'd0;
+	always @(posedge clk)begin
+		sumquarter3 <= {{2{sumquarter1[16]}},sumquarter1}+{sumquarter2[17],sumquarter2};		
+	end
+	
+	
+	always @(posedge clk)begin
+		if(sumquarter3[18:16]==3'b111||sumquarter3[18:16]==3'b000)begin
+			dout 	<=   sumquarter3[16:7];	
+		end else begin
+			dout	<=	(sumquarter3[18]==1'b1) ? 10'b10_0000_0000	:	10'b01_1111_1111;
+		end
+	end	
+	
+
+endmodule
+