Add the recv hdl file

2024-07-19 21:31:49 +08:00
parent 9a1f168184
commit e33875ef8f
20 changed files with 7725 additions and 0 deletions
@@ -0,0 +1,100 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2019/11/18 21:03:55
+// Design Name: 
+// Module Name: Interpolation
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+module Interpolation(
+	input clk,
+	input [9:0] dini,
+	input [9:0] dinq,
+	
+	input 		framesync,
+	output reg 	framesync_Interpolation = 1'd0,
+	
+	output reg [9:0] doutiA = 10'd0,
+	output reg [9:0] doutqA = 10'd0,
+	output [9:0] doutiB,
+	output [9:0] doutqB,
+	output [9:0] doutiC,
+	output [9:0] doutqC,
+	output [9:0] doutiD,
+	output [9:0] doutqD
+    );
+	
+	reg [9:0] dini_p1 = 10'd0;
+	reg [9:0] dini_t0 = 10'd0;
+	reg [9:0] dini_n1 = 10'd0;
+	reg [9:0] dini_n2 = 10'd0;
+	reg [9:0] dini_n3 = 10'd0;
+	reg [9:0] dini_n4 = 10'd0;
+
+	
+	reg [9:0] dinq_p1 = 10'd0;
+	reg [9:0] dinq_t0 = 10'd0;
+	reg [9:0] dinq_n1 = 10'd0;
+	reg [9:0] dinq_n2 = 10'd0;
+	reg [9:0] dinq_n3 = 10'd0;
+	reg [9:0] dinq_n4 = 10'd0;
+
+	reg [0:0] framesync_p1 = 1'd0;
+	reg [0:0] framesync_t0 = 1'd0;
+	reg [0:0] framesync_n1 = 1'd0;
+	reg [0:0] framesync_n2 = 1'd0;
+	reg [0:0] framesync_n3 = 1'd0;
+	reg [0:0] framesync_n4 = 1'd0;
+
+	always @(posedge clk)begin
+		dini_p1 <= dini;
+		dini_t0 <= dini_p1;
+		dini_n1 <= dini_t0;
+		dini_n2 <= dini_n1;
+		dini_n3 <= dini_n2;
+		dini_n4 <= dini_n3;
+		doutiA  <= dini_n4;
+		
+		dinq_p1 <= dinq;
+		dinq_t0 <= dinq_p1;
+		dinq_n1 <= dinq_t0;
+		dinq_n2 <= dinq_n1;
+		dinq_n3 <= dinq_n2;
+		dinq_n4 <= dinq_n3;
+		doutqA  <= dinq_n4;
+		
+		framesync_p1 <= framesync;
+		framesync_t0 <= framesync_p1;
+		framesync_n1 <= framesync_t0;
+		framesync_n2 <= framesync_n1;
+		framesync_n3 <= framesync_n2;
+		framesync_n4 <= framesync_n3;
+		framesync_Interpolation  <= framesync_n4;
+	end
+	
+	
+	
+	Interp_quarter Interp_quarteri (.clk(clk), .din_p1(dini_p1), .din_t0(dini_t0), .din_n1(dini_n1), .din_n2(dini_n2), .dout(doutiB));	
+	Interp_quarter Interp_quarterq (.clk(clk), .din_p1(dinq_p1), .din_t0(dinq_t0), .din_n1(dinq_n1), .din_n2(dinq_n2), .dout(doutqB));	
+	
+	Interp_half Interp_halfi (.clk(clk), .din_p1(dini_p1), .din_t0(dini_t0), .din_n1(dini_n1), .din_n2(dini_n2), .dout(doutiC));	
+	Interp_half Interp_halfq (.clk(clk), .din_p1(dinq_p1), .din_t0(dinq_t0), .din_n1(dinq_n1), .din_n2(dinq_n2), .dout(doutqC));
+
+	Interp_quarter Interp_quarteri3 (.clk(clk), .din_p1(dini_n2), .din_t0(dini_n1), .din_n1(dini_t0), .din_n2(dini_p1), .dout(doutiD));	
+	Interp_quarter Interp_quarterq3 (.clk(clk), .din_p1(dinq_n2), .din_t0(dinq_n1), .din_n1(dinq_t0), .din_n2(dinq_p1), .dout(doutqD));		
+
+endmodule
+