feat(top): adjust rf control logic, ila for 3rd test

coe/rf_control_map.coe

@@ -1,10 +0,0 @@
-memory_initialization_radix=2;
-memory_initialization_vector=
-1000
-0100
-0001
-1001
-0101
-1101
-0111
-1111;

contraint/mm7020_timing.xdc

@@ -11,3 +11,12 @@ set_false_path -through [get_nets tdma_slot_len*]
 set_false_path -through [get_nets tdma_tic_2_ps*]
 set_false_path -through [get_nets u_tdma/tdma_tic_frame_sync_vio*]
 set_false_path -through [get_nets rx_rst]
+set_false_path -through [get_nets rst_sys]
+set_false_path -through [get_nets rst20]
+set_false_path -through [get_nets u_tdma/rx_rst]
+
+set_false_path -through [get_nets u_RecvTop/flag_mgc_done]
+set_false_path -through [get_nets u_RecvTop/flag_frame_sync]
+set_false_path -through [get_nets u_RecvTop/mgc_start_quarter]
+set_false_path -through [get_nets u_RecvTop/rst_frame_sync]
+set_false_path -through [get_nets u_RecvTop/err_flag]

hdl/PAPR.v

@@ -38,7 +38,7 @@ module PAPR #(
     localparam SUM_WIDTH = 32;
     localparam CNT_START = 16;  // 32*4 / 8   * mag_valid signal is active high per 8 clk
     localparam CNT_END = 44;  // 88*4 / 8
-    localparam PULSE_PERIOD = 32;
+    localparam PULSE_PERIOD = 50;
 
 
     reg  [MAG_WIDTH-1:0] vec_mag_d1;
@@ -181,15 +181,14 @@ module PAPR #(
         end
     end
 
-    // ila_frame_sync u_ila_frame_sync (
-    //     .clk   (clk),              // input wire clk
-    //     .probe0(vec_mag),          // input wire [21:0]  probe0  
-    //     .probe1(data_avg),         // input wire [21:0]  probe0  
-    //     .probe2(cs),               // input wire [2:0]  probe2
-    //     .probe3(cnt),              // input wire [7:0]  probe2
-    //     .probe4(frame_sync),       // input wire [0:0]  probe2
-    //     .probe5(vec_mag_reserved)  // input wire [21:0]  probe2
-    // );
+    ila_frame_sync u_ila_frame_sync (
+        .clk   (clk),        // input wire clk
+        .probe0(vec_mag),    // input wire [21:0]  probe0  
+        .probe1(data_avg),   // input wire [21:0]  probe0  
+        .probe2(cs),         // input wire [2:0]  probe2
+        .probe3(cnt),        // input wire [7:0]  probe2
+        .probe4(frame_sync)  // input wire [0:0]  probe2
+    );
 
 
 

hdl/RecvTop.v

@@ -22,6 +22,8 @@ module RecvTop (
     input              clk,
     input              clk_2x,                   // clk_2x
     input              clk_4x,
+    input              clk_half,                 // clk_1/2
+    input              clk_quarter,              // clk_1/4 
     input              rst,
     input              rst2,                     // TODO： delete the signal
     // phy wave
@@ -30,7 +32,7 @@ module RecvTop (
     // mgc control
     output      [ 3:0] ad9361_ctrl_in,
     output wire        flag_mgc_done_pulse,      // active high pulse signal
-    output wire        frame_sync_pulse,         // in domain clk
+    output wire        frame_sync_pulse_1x,      // in domain clk
     //vio
     input              vio_tsync_inter16,        //为1的时候启用内插，从16倍过采样中挑一路
     input              EQUenable_vio,            //为1时启用均衡
@@ -121,7 +123,8 @@ module RecvTop (
 
     reg  [ 7:0] cnt_mgc_delay;
     wire        mgc_start;
-    wire        flag_mgc_done;  // level flag
+    wire        mgc_start_quarter;
+    wire        flag_mgc_done;  // level flag, under clk_1x
     wire        flag_mgc_done_4x;  // level flag
 
     // startup delay
@@ -137,7 +140,8 @@ module RecvTop (
         end
     end
 
-    assign mgc_start = (cnt_mgc_delay == 8'hFE);
+    assign mgc_start         = (cnt_mgc_delay == 8'hFE);
+    assign mgc_start_quarter = (cnt_mgc_delay >= 8'hF0) && (cnt_mgc_delay <= 8'hFE);
 
     // * MGC module 
     ad9361_mgc_pin_ctrl u_ad9361_mgc_pin_ctrl (
@@ -155,7 +159,7 @@ module RecvTop (
 
     reg  MF_rdy;  // flag_mgc_done_d1
     wire MF_rst;  // flag_mgc_done_pulse_d2
-    always @(posedge clk) begin
+    always @(posedge clk_quarter) begin
         if (rst) begin
             MF_rdy <= 0;
         end
@@ -166,16 +170,21 @@ module RecvTop (
 
     wire        fifo_out_valid;
     reg  [ 2:0] cnt_fifo_out_valid;
-    reg  [ 2:0] cnt_fifo_out_valid_sel = 1;  // 根据speed mode对应的计数器边界值
+    reg  [ 2:0] cnt_fifo_out_valid_sel = 7;  // 根据speed mode对应的计数器边界值 // refer to Receiver.v
 
     wire [31:0] fifo_out;
     reg         dmf_s_valid;
-    wire        dmf_tvalid_interp4_i;
-    wire        dmf_tvalid_interp4_q;
-    wire [31:0] mf_data_interp4_i;
-    wire [31:0] mf_data_interp4_q;
-    wire [23:0] dmf_tdata_interp4_i;
-    wire [23:0] dmf_tdata_interp4_q;
+    wire        dmf_tvalid_interp16_i;
+    wire        dmf_tvalid_interp16_q;
+    wire [31:0] mf_data_interp16_i;
+    wire [31:0] mf_data_interp16_q;
+    wire [23:0] dmf_tdata_interp16_i;
+    wire [23:0] dmf_tdata_interp16_q;
+
+    // in domain clk_quarter
+    wire [ 9:0] mf_data_downsample_i;
+    wire [ 9:0] mf_data_downsample_q;
+
 
     // valid signal for dmf
     always @(posedge clk_4x) begin
@@ -213,65 +222,102 @@ module RecvTop (
     wire mf_fir_s_tready_q;
 
     // Match filter
-    fir_match_interp4 u_fir_match_filter_interp4_i (
+    // fir_match_interp4 u_fir_match_filter_interp4_i (
+    //     .aclk              (clk),                // input wire aclk
+    //     .s_axis_data_tvalid(flag_mgc_done),      // input wire s_axis_data_tvalid
+    //     .s_axis_data_tready(mf_fir_s_tready_i),  // output wire s_axis_data_tready
+    //     .s_axis_data_tdata ({4'd0, dini}),       // input wire [15 : 0] s_axis_data_tdata
+    //     .m_axis_data_tvalid(),                   // output wire m_axis_data_tvalid
+    //     .m_axis_data_tdata (mf_data_interp4_i)   // output wire [31 : 0] m_axis_data_tdata
+    // );
+    // fir_match_interp4 u_fir_match_filter_interp4_q (
+    //     .aclk              (clk),                // input wire aclk
+    //     .s_axis_data_tvalid(flag_mgc_done),      // input wire s_axis_data_tvalid
+    //     .s_axis_data_tready(mf_fir_s_tready_q),  // output wire s_axis_data_tready
+    //     .s_axis_data_tdata ({4'd0, dinq}),       // input wire [15 : 0] s_axis_data_tdata
+    //     .m_axis_data_tvalid(),                   // output wire m_axis_data_tvalid
+    //     .m_axis_data_tdata (mf_data_interp4_q)   // output wire [31 : 0] m_axis_data_tdata
+    // );
+
+    fir_match_interp16 u_fir_match_filter_interp16_i (
         .aclk              (clk),                // input wire aclk
         .s_axis_data_tvalid(flag_mgc_done),      // input wire s_axis_data_tvalid
         .s_axis_data_tready(mf_fir_s_tready_i),  // output wire s_axis_data_tready
         .s_axis_data_tdata ({4'd0, dini}),       // input wire [15 : 0] s_axis_data_tdata
         .m_axis_data_tvalid(),                   // output wire m_axis_data_tvalid
-        .m_axis_data_tdata (mf_data_interp4_i)   // output wire [31 : 0] m_axis_data_tdata
+        .m_axis_data_tdata (mf_data_interp16_i)  // output wire [31 : 0] m_axis_data_tdata
     );
-    fir_match_interp4 u_fir_match_filter_interp4_q (
+    fir_match_interp16 u_fir_match_filter_interp16_q (
         .aclk              (clk),                // input wire aclk
         .s_axis_data_tvalid(flag_mgc_done),      // input wire s_axis_data_tvalid
         .s_axis_data_tready(mf_fir_s_tready_q),  // output wire s_axis_data_tready
         .s_axis_data_tdata ({4'd0, dinq}),       // input wire [15 : 0] s_axis_data_tdata
         .m_axis_data_tvalid(),                   // output wire m_axis_data_tvalid
-        .m_axis_data_tdata (mf_data_interp4_q)   // output wire [31 : 0] m_axis_data_tdata
+        .m_axis_data_tdata (mf_data_interp16_q)  // output wire [31 : 0] m_axis_data_tdata
     );
 
     // CDC into clk_4x
     fifo_shift u_fifo_shift (
         // input 
-        .s_aclk       (clk),                                                           // input wire s_aclk
-        .s_aresetn    (flag_mgc_done),                                                 // input wire s_aresetn
-        .s_axis_tvalid(flag_mgc_done),                                                 // input wire s_axis_tvalid
-        .s_axis_tready(),                                                              // output wire s_axis_tready
-        .s_axis_tdata ({8'd0, mf_data_interp4_q[29-:12], mf_data_interp4_i[29-:12]}),  // input wire [31 : 0] s_axis_tdata
+        .s_aclk       (clk),                                                             // input wire s_aclk
+        .s_aresetn    (flag_mgc_done),                                                   // input wire s_aresetn
+        .s_axis_tvalid(flag_mgc_done),                                                   // input wire s_axis_tvalid
+        .s_axis_tready(),                                                                // output wire s_axis_tready
+        .s_axis_tdata ({8'd0, mf_data_interp16_q[31-:12], mf_data_interp16_i[31-:12]}),  // input wire [31 : 0] s_axis_tdata
         // output
-        .m_aclk       (clk_4x),                                                        // input wire m_aclk
-        .m_axis_tvalid(fifo_out_valid),                                                // output wire m_axis_tvalid
-        .m_axis_tready(1'b1),                                                          // input wire m_axis_tready
-        .m_axis_tdata (fifo_out),                                                      // output wire [31 : 0] m_axis_tdata
+        .m_aclk       (clk_4x),                                                          // input wire m_aclk
+        .m_axis_tvalid(fifo_out_valid),                                                  // output wire m_axis_tvalid
+        .m_axis_tready(1'b1),                                                            // input wire m_axis_tready
+        .m_axis_tdata (fifo_out),                                                        // output wire [31 : 0] m_axis_tdata
         .wr_rst_busy  (),
         .rd_rst_busy  ()
     );
 
-    fir_dmf_interp4 u_fir_dmf_interp4_i (
-        .aclk              (clk_4x),
-        .s_axis_data_tvalid(dmf_s_valid),
-        .s_axis_data_tready(),
-        .s_axis_data_tdata ({4'd0, fifo_out[11:0]}),
-        .m_axis_data_tvalid(dmf_tvalid_interp4_i),
-        .m_axis_data_tdata (dmf_tdata_interp4_i)
+    // fir_dmf_interp4 u_fir_dmf_interp4_i (
+    //     .aclk              (clk_4x),
+    //     .s_axis_data_tvalid(dmf_s_valid),
+    //     .s_axis_data_tready(),
+    //     .s_axis_data_tdata ({4'd0, fifo_out[11:0]}),
+    //     .m_axis_data_tvalid(dmf_tvalid_interp4_i),
+    //     .m_axis_data_tdata (dmf_tdata_interp4_i)
+    // );
+
+    // fir_dmf_interp4 u_fir_dmf_interp4_q (
+    //     .aclk              (clk_4x),
+    //     .s_axis_data_tvalid(dmf_s_valid),
+    //     .s_axis_data_tready(),
+    //     .s_axis_data_tdata ({4'd0, fifo_out[23:12]}),
+    //     .m_axis_data_tvalid(dmf_tvalid_interp4_q),
+    //     .m_axis_data_tdata (dmf_tdata_interp4_q)
+    // );
+
+    // dmf filter 
+    fir_dmf_interp16 u_fir_dmf_interp16_i (
+        .aclk              (clk_4x),                  // input wire aclk
+        .s_axis_data_tvalid(dmf_s_valid),             // input wire s_axis_data_tvalid
+        .s_axis_data_tready(),                        // output wire s_axis_data_tready
+        .s_axis_data_tdata ({4'd0, fifo_out[11:0]}),  // input wire [15 : 0] s_axis_data_tdata
+        .m_axis_data_tvalid(dmf_tvalid_interp16_i),   // output wire m_axis_data_tvalid
+        .m_axis_data_tdata (dmf_tdata_interp16_i)     // output wire [31 : 0] m_axis_data_tdata
     );
 
-    fir_dmf_interp4 u_fir_dmf_interp4_q (
-        .aclk              (clk_4x),
-        .s_axis_data_tvalid(dmf_s_valid),
-        .s_axis_data_tready(),
-        .s_axis_data_tdata ({4'd0, fifo_out[23:12]}),
-        .m_axis_data_tvalid(dmf_tvalid_interp4_q),
-        .m_axis_data_tdata (dmf_tdata_interp4_q)
+    fir_dmf_interp16 u_fir_dmf_interp16_q (
+        .aclk              (clk_4x),                   // input wire aclk
+        .s_axis_data_tvalid(dmf_s_valid),              // input wire s_axis_data_tvalid
+        .s_axis_data_tready(),                         // output wire s_axis_data_tready
+        .s_axis_data_tdata ({4'd0, fifo_out[23:12]}),  // input wire [15 : 0] s_axis_data_tdata
+        .m_axis_data_tvalid(dmf_tvalid_interp16_q),    // output wire m_axis_data_tvalid
+        .m_axis_data_tdata (dmf_tdata_interp16_q)      // output wire [31 : 0] m_axis_data_tdata
     );
 
+
     wire [7:0] cnt_chu_seq_sync_max_vio;
     localparam CNT_CHU_SEQ_SYNC_MAX = 40;  //! should not less than 3 due to the minimum rst of aresetn
 
     wire [21:0] mag;
     wire        mag_valid;
     wire        frame_sync_4x;
-    // wire        frame_sync_pulse; 
+    wire        frame_sync_pulse;  // in baseband process clock domain, quater clock
     reg         flag_frame_sync;  // active high level
     wire        rst_frame_sync;  // derive from frame sync pulse 
     reg  [ 7:0] cnt_chu_seq_sync;  // frame sync delay to chu seq sample start pos
@@ -284,9 +330,9 @@ module RecvTop (
     ) u_MagnitudeEstimator (
         .clk      (clk_4x),
         .rst      (rst),
-        .vec_valid(dmf_tvalid_interp4_i),
-        .I        (dmf_tdata_interp4_i[20:0]),
-        .Q        (dmf_tdata_interp4_q[20:0]),
+        .vec_valid(dmf_tvalid_interp16_i),
+        .I        (dmf_tdata_interp16_i[20:0]),
+        .Q        (dmf_tdata_interp16_q[20:0]),
         .mag      (mag),
         .mag_valid(mag_valid)
     );
@@ -303,7 +349,10 @@ module RecvTop (
         .frame_sync_pulse()                // under clk_4x
     );
 
-    always @(posedge clk) begin
+
+    // ! ATTENTION  
+    // frame_sync_pulse is under clk_quarter 
+    always @(posedge clk_quarter) begin
         if (frame_sync_pulse && ~flag_frame_sync) begin
             cnt_chu_seq_sync <= 1;
         end
@@ -318,7 +367,7 @@ module RecvTop (
 
     assign rst_frame_sync = ((cnt_chu_seq_sync >= 1) && (cnt_chu_seq_sync < cnt_chu_seq_sync_max_vio));
 
-    always @(posedge clk) begin
+    always @(posedge clk_quarter) begin
         if (rst) begin
             flag_frame_sync <= 0;
         end
@@ -331,49 +380,62 @@ module RecvTop (
     end
 
 
-    wire [ 9:0] FrameSync_douti;
-    wire [ 9:0] FrameSync_doutq;
-    wire        dagc_rdy;
-    wire        mgc_rdy;
-    wire        rst_dagc;
-
-
-    // * lost the connection with other nodes
-    reg  [20:0] cnt_lost;
-    reg         framelost;
-    always @(posedge clk) begin
-        if (rst_frame_sync) begin
-            cnt_lost  <= 21'd0;
-            framelost <= 1'b0;
-        end
-        else begin
-            if (cnt_lost >= 21'd750000) begin
-                cnt_lost  <= 21'd0;
-                framelost <= 1'b1;
-            end
-            else begin
-                cnt_lost  <= 21'd1 + cnt_lost;
-                framelost <= 1'b0;
-            end
-        end
-    end
+    wire [9:0] FrameSync_douti;
+    wire [9:0] FrameSync_doutq;
+    wire       dagc_rdy;
+    wire       mgc_rdy;
+    wire       rst_dagc;
 
     wire [9:0] dagc_data_in_i;
     wire [9:0] dagc_data_in_q;
 
+    reg  [1:0] cnt_downsample = 0;
+    wire       pulse_downsample_enable;
+
+    assign pulse_downsample_enable = (cnt_downsample == 3);
+    always @(posedge clk) begin
+        cnt_downsample <= cnt_downsample + 1;
+    end
+
+    fifo_cdc_downsample_1_4 u_fifo_cdc_downsample_1_4_i (
+        .rst   (rst),                         // input wire rst
+        .wr_clk(clk),                         // input wire wr_clk
+        .rd_clk(clk_quarter),                 // input wire rd_clk
+        .din   (mf_data_interp16_i[31-:10]),  // input wire [9 : 0] din
+        .wr_en (pulse_downsample_enable),     // input wire wr_en
+        .rd_en (1),                           // input wire rd_en
+        .dout  (mf_data_downsample_i),        // output wire [9 : 0] dout
+        .full  (),                            // output wire full
+        .empty ()                             // output wire empty
+    );
+
+    fifo_cdc_downsample_1_4 u_fifo_cdc_downsample_1_4_q (
+        .rst   (rst),                         // input wire rst
+        .wr_clk(clk),                         // input wire wr_clk
+        .rd_clk(clk_quarter),                 // input wire rd_clk
+        .din   (mf_data_interp16_q[31-:10]),  // input wire [9 : 0] din
+        .wr_en (pulse_downsample_enable),     // input wire wr_en
+        .rd_en (1),                           // input wire rd_en
+        .dout  (mf_data_downsample_q),        // output wire [9 : 0] dout
+        .full  (),                            // output wire full
+        .empty ()                             // output wire empty
+    );
+
+    //* CLOCK_QUARTER DOMAIN
+
     shift_register_64 u_shift_register_64_i (
-        .D  (mf_data_interp4_i[29-:10]),  // input wire [9 : 0] D
-        .CLK(clk),                        // input wire CLK
-        .Q  (dagc_data_in_i)              // output wire [9 : 0] Q
+        .D  (mf_data_downsample_i),  // input wire [9 : 0] D
+        .CLK(clk_quarter),           // input wire CLK
+        .Q  (dagc_data_in_i)         // output wire [9 : 0] Q
     );
     shift_register_64 u_shift_register_64_q (
-        .D  (mf_data_interp4_q[29-:10]),  // input wire [9 : 0] D
-        .CLK(clk),                        // input wire CLK
-        .Q  (dagc_data_in_q)              // output wire [9 : 0] Q
+        .D  (mf_data_downsample_q),  // input wire [9 : 0] D
+        .CLK(clk_quarter),           // input wire CLK
+        .Q  (dagc_data_in_q)         // output wire [9 : 0] Q
     );
 
     DAGC_v2 DAGC_v2 (
-        .clk             (clk),
+        .clk             (clk_quarter),
         .rst             (~flag_mgc_done),
         .mgc1_rdy        (MF_rdy),
         .framesync_d0    (flag_frame_sync),
@@ -397,8 +459,8 @@ module RecvTop (
 
     // CFO estimation
     freqestm freqestm (
-        .clk            (clk),
-        .rst            (mgc_start),
+        .clk            (clk_quarter),
+        .rst            (mgc_start_quarter),
         .mgc_rdy        (mgc_rdy),
         .framesync      (dagc_rdy),
         .datain_i       (DAGC_out_i),
@@ -413,7 +475,7 @@ module RecvTop (
     //位同步
     wire [1:0] cnt_tsync;
     TimeSync_top TimeSync_top (
-        .clk              (clk),
+        .clk              (clk_quarter),
         .rst              (rst_frame_sync),
         .dini             (freqdataout_i),
         .dinq             (freqdataout_q),
@@ -434,7 +496,7 @@ module RecvTop (
 
     // SC-FDE
     SC_FDE_TOP SC_FDE_TOP_djy (
-        .clk                                (clk),
+        .clk                                (clk_quarter),
         .rst                                (rst_frame_sync),
         // param
         .EQUenable_vio                      (EQUenable_vio),    //为1时启用均衡
@@ -468,7 +530,7 @@ module RecvTop (
     wire [9:0] phase_adjust_douti;
     wire [9:0] phase_adjust_doutq;
     phase_adjust phase_adjust (
-        .clk      (clk),
+        .clk      (clk_quarter),
         .rst      (rst_frame_sync),
         .din_i    (SC_FDE_douti),
         .din_q    (SC_FDE_doutq),
@@ -484,8 +546,8 @@ module RecvTop (
     wire [7:0] IQmergedout;
 
     IQmerge IQmerge (
-        .clk       (clk),
-        .clk2      (clk_2x),
+        .clk       (clk_quarter),
+        .clk2      (clk_half),
         .rst       (rst2 || rst_frame_sync),
         .nd        (phase_adjust_rdy),
         .framesync (framesync_tsync),
@@ -504,7 +566,7 @@ module RecvTop (
     wire [8:0] total_frames;
 
     CCSDS_LDPC_DEC_K1024_R12_TOPP LDPC_decode (
-        .clk         (clk_2x),
+        .clk         (clk_half),
         .Rst         (rst2 || rst_frame_sync),
         .FrameSync   (ldpcsyncin),
         .Nd          (IQmergerdy),
@@ -518,7 +580,7 @@ module RecvTop (
     );
 
     extract_mac_frame u_extract_mac_frame (
-        .clk                    (clk_2x),
+        .clk                    (clk_half),
         .rst                    (rst2 || rst_frame_sync),
         .ldpc_dec_out_start     (LDPC_SyncOut),
         .ldpc_dec_out_valid     (LDPC_Rdy),
@@ -563,60 +625,55 @@ module RecvTop (
     );
 
     xpm_cdc_pulse #(
-        .DEST_SYNC_FF  (4),  // DECIMAL; range: 2-10
-        .INIT_SYNC_FF  (1),  // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
-        .REG_OUTPUT    (1),  // DECIMAL; 0=disable registered output, 1=enable registered output
-        .RST_USED      (0),  // DECIMAL; 0=no reset, 1=implement reset
-        .SIM_ASSERT_CHK(1)   // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
-    ) xpm_cdc_frame_sync_pulse_inst (
-        .dest_pulse(frame_sync_pulse),  // 1-bit output: Outputs a pulse the size of one dest_clk period when a pulse
-        // transfer is correctly initiated on src_pulse input. This output is
-        // combinatorial unless REG_OUTPUT is set to 1.
-        .dest_clk  (clk),               // 1-bit input: Destination clock.
-        .dest_rst  (),                  // 1-bit input: optional; required when RST_USED = 1
-        .src_clk   (clk_4x),            // 1-bit input: Source clock.
-        .src_pulse (frame_sync_4x),     // 1-bit input: Rising edge of this signal initiates a pulse transfer to the
-        // destination clock domain. The minimum gap between each pulse transfer must be
-        // at the minimum 2*(larger(src_clk period, dest_clk period)). This is measured
-        // between the falling edge of a src_pulse to the rising edge of the next
-        // src_pulse. This minimum gap will guarantee that each rising edge of src_pulse
-        // will generate a pulse the size of one dest_clk period in the destination
-        // clock domain. When RST_USED = 1, pulse transfers will not be guaranteed while
-        // src_rst and/or dest_rst are asserted.
-        .src_rst   ()                   // 1-bit input: optional; required when RST_USED = 1
+        .DEST_SYNC_FF  (4),
+        .INIT_SYNC_FF  (1),
+        .REG_OUTPUT    (1),
+        .RST_USED      (0),
+        .SIM_ASSERT_CHK(1)
+    ) u_xpm_cdc_frame_sync_pulse_inst_clk_4x_to_clk_1x (
+        .dest_pulse(frame_sync_pulse_1x),
+        .dest_clk  (clk),
+        .dest_rst  (),
+        .src_clk   (clk_4x),
+        .src_pulse (frame_sync_4x),
+        .src_rst   ()
+    );
+
+    xpm_cdc_pulse #(
+        .DEST_SYNC_FF  (4),
+        .INIT_SYNC_FF  (1),
+        .REG_OUTPUT    (1),
+        .RST_USED      (0),
+        .SIM_ASSERT_CHK(1)
+    ) u_xpm_cdc_frame_sync_pulse_inst_clk_4x_to_clk_quarter (
+        .dest_pulse(frame_sync_pulse),
+        .dest_clk  (clk_quarter),
+        .dest_rst  (),
+        .src_clk   (clk_4x),
+        .src_pulse (frame_sync_4x),
+        .src_rst   ()
     );
 
     // ***** debug *****
 
     vio_recv_top u_vio_recv_top (
-        .clk       (clk),
+        .clk       (clk_quarter),
         .probe_out0(cnt_chu_seq_sync_max_vio)
     );
 
     ila_recv_top u_ila_recv_top (
-        .clk    (clk),
-        .probe0 (dini),                // width: 12
-        .probe1 (dinq),                // width: 12
-        .probe2 (dagc_data_in_i),      // width: 12
-        .probe3 (dagc_data_in_q),      // width: 12
-        .probe4 (flag_mgc_done),       // width: 1
-        .probe5 (flag_frame_sync),     // width: 1
-        .probe6 (flag_cfo_done),       // width: 1
-        .probe7 (freqdataout_i),       // width: 10
-        .probe8 (freqdataout_q),       // width: 10
-        .probe9 (IntpARdy),            // width: 1
-        .probe10(IntpOuti),            // width: 10
-        .probe11(IntpOutq),            // width: 10
-        .probe12(nd_SC_FDE_dout),      // width: 1
-        .probe13(SC_FDE_douti),        // width: 10
-        .probe14(SC_FDE_doutq),        // width: 10
-        .probe15(phase_adjust_rdy),    // width: 1
-        .probe16(phase_adjust_douti),  // width: 10
-        .probe17(phase_adjust_doutq),  // width: 10
-        .probe18(LDPC_Rdy),            // width: 1
-        .probe19(LDPC_Dout),           // width: 1
-        .probe20(good_frames),         // width: 9
-        .probe21(bad_frames)           // width: 9
+        .clk    (clk_quarter),
+        .probe0 (dagc_data_in_i),      // width: 12
+        .probe1 (dagc_data_in_q),      // width: 12
+        .probe2 (flag_frame_sync),     // width: 1
+        .probe3 (phase_adjust_rdy),    // width: 1
+        .probe4 (phase_adjust_douti),  // width: 10
+        .probe5 (phase_adjust_doutq),  // width: 10
+        .probe6 (IntpARdy),            // width: 1
+        .probe7 (IntpOuti),            // width: 10
+        .probe8 (IntpOutq),            // width: 10
+        .probe9 (good_frames),         // width: 9
+        .probe10(bad_frames)           // width: 9
     );
 
 

hdl/SC_FDE_TOP.v

@@ -556,4 +556,13 @@ module SC_FDE_TOP (
         .flagoverflow_FDE_dataout_29to10q(flagoverflow_FDE_dataout_29to10q)   //ifft结果截位，即均衡结果处，结果先除掉低8位，29-7=22截到10
     );
 
+    // ila_scfde u_ila_scfde (
+    //     .clk   (clk),            // input wire clk
+    //     .probe0(flag_ow_left),   // 1
+    //     .probe1(ifft_out_nd),    // 1
+    //     .probe2(ifft_index),     // 8
+    //     .probe3(ifft_out_tdata)  //64
+    // );
+
+
 endmodule

hdl/Transmitter.v

@@ -521,55 +521,55 @@ module Transmitter #(
         .m_axis_data_tdata (bb_wave_out_q_interp16)
     );
 
-    fir_shape_interp8 u_fir_shape_interp8_i (
-        .aclk              (clk),
-        .s_axis_data_tvalid(fir_tvalid_in),
-        .s_axis_data_tready(),
-        .s_axis_data_tdata (m_fir_tdata_i),
-        .m_axis_data_tvalid(),
-        .m_axis_data_tdata (bb_wave_out_i_interp8)
-    );
+    // fir_shape_interp8 u_fir_shape_interp8_i (
+    //     .aclk              (clk),
+    //     .s_axis_data_tvalid(fir_tvalid_in),
+    //     .s_axis_data_tready(),
+    //     .s_axis_data_tdata (m_fir_tdata_i),
+    //     .m_axis_data_tvalid(),
+    //     .m_axis_data_tdata (bb_wave_out_i_interp8)
+    // );
 
-    fir_shape_interp8 u_fir_shape_interp8_q (
-        .aclk              (clk),
-        .s_axis_data_tvalid(fir_tvalid_in),
-        .s_axis_data_tready(),
-        .s_axis_data_tdata (m_fir_tdata_q),
-        .m_axis_data_tvalid(),
-        .m_axis_data_tdata (bb_wave_out_q_interp8)
-    );
+    // fir_shape_interp8 u_fir_shape_interp8_q (
+    //     .aclk              (clk),
+    //     .s_axis_data_tvalid(fir_tvalid_in),
+    //     .s_axis_data_tready(),
+    //     .s_axis_data_tdata (m_fir_tdata_q),
+    //     .m_axis_data_tvalid(),
+    //     .m_axis_data_tdata (bb_wave_out_q_interp8)
+    // );
 
-    fir_shape_interp4 u_fir_shape_interp4_i (
-        .aclk              (clk),
-        .s_axis_data_tvalid(fir_tvalid_in),
-        .s_axis_data_tready(),
-        .s_axis_data_tdata (m_fir_tdata_i),
-        .m_axis_data_tvalid(),
-        .m_axis_data_tdata (bb_wave_out_i_interp4)
-    );
+    // fir_shape_interp4 u_fir_shape_interp4_i (
+    //     .aclk              (clk),
+    //     .s_axis_data_tvalid(fir_tvalid_in),
+    //     .s_axis_data_tready(),
+    //     .s_axis_data_tdata (m_fir_tdata_i),
+    //     .m_axis_data_tvalid(),
+    //     .m_axis_data_tdata (bb_wave_out_i_interp4)
+    // );
 
-    fir_shape_interp4 u_fir_shape_interp4_q (
-        .aclk              (clk),
-        .s_axis_data_tvalid(fir_tvalid_in),
-        .s_axis_data_tready(),
-        .s_axis_data_tdata (m_fir_tdata_q),
-        .m_axis_data_tvalid(),
-        .m_axis_data_tdata (bb_wave_out_q_interp4)
-    );
+    // fir_shape_interp4 u_fir_shape_interp4_q (
+    //     .aclk              (clk),
+    //     .s_axis_data_tvalid(fir_tvalid_in),
+    //     .s_axis_data_tready(),
+    //     .s_axis_data_tdata (m_fir_tdata_q),
+    //     .m_axis_data_tvalid(),
+    //     .m_axis_data_tdata (bb_wave_out_q_interp4)
+    // );
 
 
 
     // ********    Debug    ********
 
-    ila_transmitter u_ila_transmitter (
-        .clk   (clk),                // input wire clk
-        .probe0(cnt_sym_send),       // input wire [15:0]  probe0  
-        .probe1(cs),                 // input wire [3:0]  probe1 
-        .probe2(ns),                 // input wire [3:0]  probe2 
-        .probe3(send_data_ready),    // input wire [0:0]  probe3 
-        .probe4(send_start),         // input wire [0:0]  probe4 
-        .probe5(tx_data_src_tvalid)  // input wire [0:0]  probe5
-    );
+    // ila_transmitter u_ila_transmitter (
+    //     .clk   (clk),                // input wire clk
+    //     .probe0(cnt_sym_send),       // input wire [15:0]  probe0  
+    //     .probe1(cs),                 // input wire [3:0]  probe1 
+    //     .probe2(ns),                 // input wire [3:0]  probe2 
+    //     .probe3(send_data_ready),    // input wire [0:0]  probe3 
+    //     .probe4(send_start),         // input wire [0:0]  probe4 
+    //     .probe5(tx_data_src_tvalid)  // input wire [0:0]  probe5
+    // );
 
 
 endmodule

hdl/phy_control.v

@@ -410,10 +410,10 @@ module phy_control #(
     // frame sync tic
     assign tdma_frame_sync_tic         = tdma_frame_sync_tic_reg;
 
-    vio_phy_param u_vio_phy_param (
-        .clk      (local_clk),
-        .probe_in0(phy_cr_reg)
-    );
+    // vio_phy_param u_vio_phy_param (
+    //     .clk      (local_clk),
+    //     .probe_in0(phy_cr_reg)
+    // );
 
     //--- ADD YOUR OWN LOGIC END
 

hdl/power_measure.v

@@ -30,7 +30,7 @@ module power_measure (
 );
 
     localparam CNT_WAIT_9361_MAX = 80;  //* 等待周期数
-    localparam CNT_MEASURING_MAX = 256;  // * 观察64个周期
+    localparam CNT_MEASURING_MAX = 4096;  // * 观察4096个周期
     localparam CNT_ADJUST_TIMES_MAX = 25;
     localparam CNT_AMP_TOO_HIGH_THRESHOLD = 6;
     // ******** Wire & Reg  ********

hdl/system_top.v

@@ -70,6 +70,8 @@ module system_top (
     wire        clk_1x;
     wire        clk_2x;
     wire        clk_4x;
+    wire        clk_quarter;
+    wire        clk_half;
 
     // emio
     wire [31:0] gpio_i;
@@ -148,7 +150,6 @@ module system_top (
     wire        rf_io1_d4_12db;
     wire        rf_io2_trx;  // 1 for tx on, 0 for rx
 
-
     // vio
     wire        rst_manual;
     wire        rx_rst_vio;
@@ -156,9 +157,6 @@ module system_top (
     wire        intr_2ps;
     wire [ 7:0] max_slot_num;
 
-    reg  [15:0] cnt_pulse_wider_tx_start = 0;
-    reg  [15:0] cnt_pulse_wider_frame_sync = 0;
-
     // ******** Assingment  ********
 
     assign ad9361_tx_clk    = clk_1x;
@@ -177,40 +175,19 @@ module system_top (
     // gpio  rf control
     assign rf_gpio[0]       = rf_io0_d3_18db;
     assign rf_gpio[1]       = rf_io1_d4_12db;
-    // assign rf_gpio[2]       = rf_io2_trx;
-    // assign rf_gpio[3]       = rf_io3_d1_12db;
+    assign rf_gpio[2]       = rf_io2_trx;
+    assign rf_gpio[3]       = rf_io3_d1_12db;
     assign rf_gpio[4]       = rf_io4_d2_6db;
     assign rf_gpio[5]       = 0;
-    // temporary for test gpio
-    assign rf_gpio[2]       = (cnt_pulse_wider_tx_start != 0);
-    assign rf_gpio[3]       = (cnt_pulse_wider_frame_sync != 0);
-
+    // at send slot, rx rst is on, and trx is 1 for tx
+    assign rf_io2_trx       = rx_rst;
+    assign rf_io0_d3_18db   = 0;
+    assign rf_io1_d4_12db   = 0;
+    assign rf_io3_d1_12db   = 0;
+    assign rf_io4_d2_6db    = 0;
 
     // ******** Logic Block ********
 
-    always @(posedge clk_1x) begin
-        if (tx_start) begin
-            cnt_pulse_wider_tx_start <= 1;
-        end
-        else if (cnt_pulse_wider_tx_start > 0) begin
-            cnt_pulse_wider_tx_start <= cnt_pulse_wider_tx_start + 1;
-        end
-        else begin
-            cnt_pulse_wider_tx_start <= cnt_pulse_wider_tx_start;
-        end
-    end
-    always @(posedge clk_2x) begin
-        if (rx_data_src_fifo_tlast) begin
-            cnt_pulse_wider_frame_sync <= 1;
-        end
-        else if (cnt_pulse_wider_frame_sync > 0) begin
-            cnt_pulse_wider_frame_sync <= cnt_pulse_wider_frame_sync + 1;
-        end
-        else begin
-            cnt_pulse_wider_frame_sync <= cnt_pulse_wider_frame_sync;
-        end
-    end
-
     // ********    Inst     ********
 
     clk_wiz_poweron u_clk_wiz_poweron (
@@ -225,13 +202,15 @@ module system_top (
     // clock domain - ad9361 rx & tx 
     clk_wiz_baseband u_clk_wiz_baseband (
         // Clock out ports
-        .clk_1x (clk_1x),        // output clk_1x
-        .clk_2x (clk_2x),        // output clk_2x
-        .clk_4x (clk_4x),        // output clk_4x
+        .clk_1x     (clk_1x),        // output clk_1x
+        .clk_2x     (clk_2x),        // output clk_2x
+        .clk_4x     (clk_4x),        // output clk_4x
+        .clk_quarter(clk_quarter),
+        .clk_half   (clk_half),
         // Status and control signals
-        .locked (locked),        // output locked
+        .locked     (locked),        // output locked
         // Clock in ports
-        .clk_src(ad9361_rx_clk)  // input clk_src
+        .clk_src    (ad9361_rx_clk)  // input clk_src
     );
 
     MM7020_BD_wrapper u_MM7020_BD_wrapper (
@@ -278,7 +257,7 @@ module system_top (
         .tx_data_src_tready         (tx_data_src_tready),
         .tx_data_src_tvalid         (tx_data_src_tvalid),
         // rx fifo
-        .clk_rx_data_src_fifo       (clk_2x),
+        .clk_rx_data_src_fifo       (clk_half),
         .rst_rx_data_src_fifo       (rx_rst),
         .rx_data_src_fifo_tdata     (rx_data_src_fifo_tdata),
         .rx_data_src_fifo_tlast     (rx_data_src_fifo_tlast),
@@ -287,7 +266,7 @@ module system_top (
         // phy clock and rst to ps
         .clk_phy                    (clk_1x),
         .rst_phy_n                  (~rst_sys),
-        // phy control signal , under clk_1x domain
+        // phy control signal
         .phy_rst                    (phy_rst),
         .phy_tx_test_flag           (phy_tx_test_flag),
         .phy_tx_iq_reverse          (phy_tx_iq_reverse),
@@ -341,7 +320,7 @@ module system_top (
     Transmitter u_Transmitter (
         .clk               (clk_1x),
         .rst               (rst_sys | phy_rst),
-        .speed_mode        (2),
+        .speed_mode        (0),
         .send_data_ready   (send_data_ready),
         .send_start        (tx_start),
         .send_over         (tx_done),
@@ -360,13 +339,15 @@ module system_top (
         .clk                    (clk_1x),
         .clk_2x                 (clk_2x),
         .clk_4x                 (clk_4x),
+        .clk_half               (clk_half),
+        .clk_quarter            (clk_quarter),
         .rst                    (rst_sys | rx_rst | phy_rst),
         .rst2                   (rst_sys | phy_rst),
         .dini                   (bb_rx_i),
         .dinq                   (bb_rx_q),
         .ad9361_ctrl_in         (ad9361_ctrl_in),
         .flag_mgc_done_pulse    (flag_mgc_done_pulse),
-        .frame_sync_pulse       (frame_sync_pulse),
+        .frame_sync_pulse_1x    (frame_sync_pulse),
         .vio_tsync_inter16      (1),
         .EQUenable_vio          (1),
         .Zerozone_vio           (8'd29),
@@ -423,7 +404,7 @@ module system_top (
 
     // vio_rf u_vio_rf (
     //     .clk       (clk_poweron),
-    //     .probe_out0(rf_io2_trx),
+    //     .probe_out0(),
     //     .probe_out1(rf_io3_d1_12db),
     //     .probe_out2(rf_io4_d2_6db),
     //     .probe_out3(rf_io0_d3_18db),

sim/tb_tdma.v

@@ -29,73 +29,18 @@ module tb_tdma ();
         #10 rst <= 1'b0;
     end
 
-    reg [7:0] local_id = 0;
-
-    initial begin
-        #20 local_id <= 1;
-    end
-
-
-    reg       flag_frame_sync = 0;
-    reg       recevied_cur_slot_id_valid = 0;
-    reg [7:0] recevied_cur_slot_id = 0;
-
-    tdma u_tdma_master (
-        .clk                       (clk),
-        .rst                       (rst),
-        .flag_frame_sync           (flag_frame_sync),
-        .tdma_slot_len             (24'd7500),
-        .tdma_tic_2_ps             (24'd6000),
-        .tdma_slot_num             (8'd4),
-        .local_id                  (local_id),
-        .recevied_cur_slot_id_valid(recevied_cur_slot_id_valid),
-        .recevied_cur_slot_id      (recevied_cur_slot_id),
-        .intr_2ps                  (),
-        .tx_start                  (),
-        .rx_rst                    ()
+    tdma #(
+        .SLOT_LEN      (625000),  // 50MHz--> 15ms
+        .TIC_TO_PS_LEN (575000),
+        .TIC_FRAME_SYNC(42344)
+    ) u_tdma (
+        .clk            (clk),
+        .rst            (rst),
+        .flag_is_master (1),
+        .flag_frame_sync(0),
+        .intr_2ps       (intr_2ps),
+        .tx_start       (tx_start),
+        .rx_rst         (rx_rst)
     );
 
-
-    reg       flag_frame_sync_slave = 0;
-    reg       recevied_cur_slot_id_valid_slave = 0;
-    reg [7:0] recevied_cur_slot_id_slave = 7;
-    reg [7:0] local_id_slave = 10;
-    reg [7:0] cnt = 0;
-    always @(posedge clk) begin
-        if (cnt < 8'hFF) begin
-            cnt <= cnt + 1;
-        end
-    end
-
-    always @(posedge clk) begin
-        if (cnt == 8'hF3) begin
-            flag_frame_sync_slave <= 1;
-        end
-        else begin
-            flag_frame_sync_slave <= 0;
-        end
-        if (cnt == 8'hFE) begin
-            recevied_cur_slot_id_valid_slave <= 1;
-        end
-        else begin
-            recevied_cur_slot_id_valid_slave <= 0;
-        end
-    end
-
-    tdma u_tdma_slave (
-        .clk                       (clk),
-        .rst                       (rst),
-        .flag_frame_sync           (flag_frame_sync_slave),
-        .tdma_slot_len             (24'd7500),
-        .tdma_tic_2_ps             (24'd6000),
-        .tdma_slot_num             (8'd10),
-        .local_id                  (local_id_slave),
-        .recevied_cur_slot_id_valid(recevied_cur_slot_id_valid_slave),
-        .recevied_cur_slot_id      (recevied_cur_slot_id_slave),
-        .intr_2ps                  (),
-        .tx_start                  (),
-        .rx_rst                    ()
-    );
-
-
 endmodule

util.tcl

@@ -3,33 +3,28 @@
 # create a new ip ila named ila_rx2, if the ip already exists, skip create_ip step
 create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_tdma
 # set the ip property
-set_property -dict [list \
-  CONFIG.C_EN_STRG_QUAL {1} \
-  CONFIG.C_NUM_OF_PROBES {22} \
-  CONFIG.C_PROBE0_WIDTH {12} \
-  CONFIG.C_PROBE1_WIDTH {12} \
-  CONFIG.C_PROBE2_WIDTH {12} \
-  CONFIG.C_PROBE3_WIDTH {12} \
-  CONFIG.C_PROBE4_WIDTH {1} \
-  CONFIG.C_PROBE5_WIDTH {1} \
-  CONFIG.C_PROBE6_WIDTH {1} \
-  CONFIG.C_PROBE7_WIDTH {10} \
-  CONFIG.C_PROBE8_WIDTH {10} \
-  CONFIG.C_PROBE9_WIDTH {1} \
-  CONFIG.C_PROBE10_WIDTH {10} \
-  CONFIG.C_PROBE11_WIDTH {10} \
-  CONFIG.C_PROBE12_WIDTH {1} \
-  CONFIG.C_PROBE13_WIDTH {10} \
-  CONFIG.C_PROBE14_WIDTH {10} \
-  CONFIG.C_PROBE15_WIDTH {1} \
-  CONFIG.C_PROBE16_WIDTH {10} \
-  CONFIG.C_PROBE17_WIDTH {10} \
-  CONFIG.C_PROBE18_WIDTH {1} \
-  CONFIG.C_PROBE19_WIDTH {1} \
-  CONFIG.C_PROBE20_WIDTH {9} \
-  CONFIG.C_PROBE21_WIDTH {9} \
-
-] [get_ips ila_recv_top]
+set_property -dict {
+  CONFIG.C_EN_STRG_QUAL 1 
+  CONFIG.C_NUM_OF_PROBES {18}
+  CONFIG.C_PROBE0_WIDTH {12} 
+  CONFIG.C_PROBE1_WIDTH {12} 
+  CONFIG.C_PROBE2_WIDTH {1} 
+  CONFIG.C_PROBE3_WIDTH {1} 
+  CONFIG.C_PROBE4_WIDTH {1} 
+  CONFIG.C_PROBE5_WIDTH {10} 
+  CONFIG.C_PROBE6_WIDTH {10} 
+  CONFIG.C_PROBE7_WIDTH {1} 
+  CONFIG.C_PROBE8_WIDTH {10} 
+  CONFIG.C_PROBE9_WIDTH {10} 
+  CONFIG.C_PROBE10_WIDTH {1} 
+  CONFIG.C_PROBE11_WIDTH {10} 
+  CONFIG.C_PROBE12_WIDTH {10} 
+  CONFIG.C_PROBE13_WIDTH {1} 
+  CONFIG.C_PROBE14_WIDTH {10} 
+  CONFIG.C_PROBE15_WIDTH {10} 
+  CONFIG.C_PROBE16_WIDTH {9} 
+  CONFIG.C_PROBE17_WIDTH {9}
+} [get_ips ila_recv_top]
 
 
 set_property -dict [list \