fix(top): reverse iq in recv

contraint/mm7020_timing.xdc

@@ -1,3 +1,4 @@
-set_property MAX_FANOUT 512 [get_nets *u_Receiver/mag*]
+set_property MAX_FANOUT 512 [get_nets *u_RecvTop/mag*]
 # set_property MAX_FANOUT 512 [get_nets u_Receiver/mag_valid]
-set_false_path -through [get_nets u_Receiver/rst]
+# set_false_path -through [get_nets u_Receiver/rst]
+# set_false_path -through [get_nets  u_RecvTop/SR[0]]

hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v

@@ -20,13 +20,11 @@
 //////////////////////////////////////////////////////////////////////////////////
 
 
-module CCSDS_LDPC_DEC_K1024_R12_TOPP
+module CCSDS_LDPC_DEC_K1024_R12_TOPP #(
-	#(
     parameter MAX_ITER_NUM         = 6'd14,  //最大迭代次数常量                                     
     parameter WIDTH                = 4'd8,   //量化比特
-        parameter OUT_ONLY_INFORMATION = 1'b0   //译码输出格式选择标志，1:只输出信息位；0：输出整个码字
+    parameter OUT_ONLY_INFORMATION = 1'b1    //译码输出格式选择标志，1:只输出信息位；0：输出整个码字
-    )
+) (
-    (
     input             clk,        //工作时钟,100MHz
     input             Rst,        //同步复位信号,高有效
     input             FrameSync,  //帧同步标志,高脉冲
@@ -66,11 +64,9 @@ module CCSDS_LDPC_DEC_K1024_R12_TOPP
     wire [      8:0] total_frames_B;
 
 
-	LDPC_TopManage_2 
+    LDPC_TopManage_2 #(
-	#(
         .WIDTH(WIDTH)
-    )
+    ) TM (
-	TM (
         .clk              (clk),
         .Rst              (Rst),
         .FrameSync_TM     (FrameSync),
@@ -102,13 +98,11 @@ module CCSDS_LDPC_DEC_K1024_R12_TOPP
         .total_frames_TM  (total_frames)
     );
 
-	CCSDS_LDPC_DEC_K1024_R12
+    CCSDS_LDPC_DEC_K1024_R12 #(
-	#(
         .MAX_ITER_NUM(MAX_ITER_NUM),
         .WIDTH(WIDTH),
         .OUT_ONLY_INFORMATION(OUT_ONLY_INFORMATION)
-	)
+    ) inst_DEC_A (
-    inst_DEC_A (
         .clk         (clk),
         .Rst         (Rst),
         .FrameSync   (FrameSync_A_TM),
@@ -122,13 +116,11 @@ module CCSDS_LDPC_DEC_K1024_R12_TOPP
         .total_frames(total_frames_A)
     );
 
-	CCSDS_LDPC_DEC_K1024_R12
+    CCSDS_LDPC_DEC_K1024_R12 #(
-	#(
         .MAX_ITER_NUM(MAX_ITER_NUM),
         .WIDTH(WIDTH),
         .OUT_ONLY_INFORMATION(OUT_ONLY_INFORMATION)
-	)
+    ) inst_DEC_B (
-    inst_DEC_B (
         .clk         (clk),
         .Rst         (Rst),
         .FrameSync   (FrameSync_B_TM),

hdl/PAPR.v

@@ -64,11 +64,6 @@ module PAPR #(
     // accumulate ==> average ==> papr
     wire [MAG_WIDTH-1:0] vec_mag_1024;
     reg  [          5:0] cnt;
-    // shift_1024 shift_1024 (
-    //     .D  (vec_mag),      // input wire [21 : 0] D
-    //     .CLK(clk),          // input wire CLK
-    //     .Q  (vec_mag_1024)  // output wire [21 : 0] Q
-    // );
 
     shift_reg #(
         .DATA_WIDTH(MAG_WIDTH),
@@ -144,22 +139,10 @@ module PAPR #(
     end
 
 
-    // ******** Wire & Reg  ********
-
-    // ******** Assingment  ********
-
-    // ******** Logic Block ********
-
-    // ********    Inst     ********
-
-    // ********    Debug    ********
-
-    // NOTE: comment
-
     ila_frame_sync u_ila_frame_sync (
         .clk   (clk),        // input wire clk
         .probe0(vec_mag),    // input wire [21:0]  probe0  
-        .probe1(mag_valid),  // input wire [0:0]  probe1 
+        .probe1(data_avg),   // input wire [21:0]  probe0  
         .probe2(frame_sync)  // input wire [0:0]  probe2
     );
 

hdl/RecvTop.v

@@ -29,6 +29,8 @@ module RecvTop (
     input       [11:0] dinq,
     // mgc control
     output      [ 3:0] ad9361_ctrl_in,
+    output wire        flag_mgc_done_pulse,  // active high pulse signal
+    output wire        frame_sync_pulse,     // in domain clk
     //vio
     input              vio_tsync_inter16,    //为1的时候启用内插，从16倍过采样中挑一路
     input              EQUenable_vio,        //为1时启用均衡
@@ -46,7 +48,7 @@ module RecvTop (
     wire        rst_freq;
     wire        DAGC_rdy;
     wire        framesync;  //帧同步峰
-    wire        framesync_delay;  //帧同步峰，与频率补偿输出对应
+    wire        flag_cfo_done;  //帧同步峰，与频率补偿输出对应
     wire        framesync_tsync;  //帧同步标志，与TSync输出对应
     wire        IntpARdy;  //TSync输出nd
     wire        nd_SC_FDE_dout;  //SC_FDE输出nd
@@ -138,6 +140,7 @@ module RecvTop (
         .rx_data_i          (dini),
         .rx_data_q          (dinq),
         .ad9361_ctrl_in     (ad9361_ctrl_in),
+        .flag_mgc_done_pulse(flag_mgc_done_pulse),
         .flag_mgc_done      (flag_mgc_done)
     );
 
@@ -255,17 +258,18 @@ module RecvTop (
         .m_axis_data_tdata (dmf_tdata_interp4_q)
     );
 
+    wire [7:0] cnt_chu_seq_sync_max_vio;
     localparam CNT_CHU_SEQ_SYNC_MAX = 40;  //! should not less than 3 due to the minimum rst of aresetn
 
     wire [21:0] mag;
     wire        mag_valid;
     wire        frame_sync_4x;
-    wire        frame_sync_pulse;  // in domain clk
+    // wire        frame_sync_pulse; 
     reg         flag_frame_sync;  // active high level
     wire        rst_frame_sync;  // derive from frame sync pulse 
     reg  [ 7:0] cnt_chu_seq_sync;  // frame sync delay to chu seq sample start pos
 
-    assign rst_frame_sync = ((cnt_chu_seq_sync >= 1) && (cnt_chu_seq_sync < CNT_CHU_SEQ_SYNC_MAX));
+    assign rst_frame_sync = ((cnt_chu_seq_sync >= 1) && (cnt_chu_seq_sync < cnt_chu_seq_sync_max_vio));
 
     //* calc the magnitude
     MagnitudeEstimator #(
@@ -297,7 +301,7 @@ module RecvTop (
             cnt_chu_seq_sync <= 1;
         end
         // avoid the tailing of the convolution (here we use CNT_CHU_SEQ_SYNC_MAX clocks)
-        else if (cnt_chu_seq_sync >= 1 && cnt_chu_seq_sync < CNT_CHU_SEQ_SYNC_MAX) begin
+        else if (cnt_chu_seq_sync >= 1 && cnt_chu_seq_sync < cnt_chu_seq_sync_max_vio) begin
             cnt_chu_seq_sync <= cnt_chu_seq_sync + 1;
         end
         else begin
@@ -309,7 +313,7 @@ module RecvTop (
         if (rst) begin
             flag_frame_sync <= 0;
         end
-        else if (cnt_chu_seq_sync == CNT_CHU_SEQ_SYNC_MAX) begin
+        else if (cnt_chu_seq_sync == cnt_chu_seq_sync_max_vio) begin
             flag_frame_sync <= 1;
         end
         else begin
@@ -379,7 +383,7 @@ module RecvTop (
         .datain_q       (DAGC_out_q),
         .dataout_i      (freqdataout_i),
         .dataout_q      (freqdataout_q),
-        .framesync_delay(framesync_delay),
+        .framesync_delay(flag_cfo_done),
         .data_save      (data_save),
         .rst_freq       (rst_freq)
     );
@@ -395,7 +399,7 @@ module RecvTop (
         .douti            (IntpOuti),
         .doutq            (IntpOutq),
         .vio_tsync_inter16(vio_tsync_inter16),
-        .framesync        (framesync_delay),    //帧同步标志
+        .framesync        (flag_cfo_done),      //帧同步标志
         .framesync_tsync  (framesync_tsync),    //帧同步标志
         //debug
         .cnt_tsync        (cnt_tsync),
@@ -533,6 +537,38 @@ module RecvTop (
         .src_rst   ()                   // 1-bit input: optional; required when RST_USED = 1
     );
 
+    // ***** debug *****
+
+    vio_recv_top u_vio_recv_top (
+        .clk       (clk),
+        .probe_out0(cnt_chu_seq_sync_max_vio)
+    );
+
+    ila_recv_top u_ila_recv_top (
+        .clk    (clk),
+        .probe0 (dini),                       // width: 12
+        .probe1 (dinq),                       // width: 12
+        .probe2 (mf_data_interp4_i[29-:12]),  // width: 12
+        .probe3 (mf_data_interp4_q[29-:12]),  // width: 12
+        .probe4 (flag_mgc_done),              // width: 1
+        .probe5 (flag_frame_sync),            // width: 1
+        .probe6 (flag_cfo_done),              // width: 1
+        .probe7 (freqdataout_i),              // width: 10
+        .probe8 (freqdataout_q),              // width: 10
+        .probe9 (IntpARdy),                   // width: 1
+        .probe10(IntpOuti),                   // width: 10
+        .probe11(IntpOutq),                   // width: 10
+        .probe12(nd_SC_FDE_dout),             // width: 1
+        .probe13(SC_FDE_douti),               // width: 10
+        .probe14(SC_FDE_doutq),               // width: 10
+        .probe15(phase_adjust_rdy),           // width: 1
+        .probe16(phase_adjust_douti),         // width: 10
+        .probe17(phase_adjust_doutq),         // width: 10
+        .probe18(LDPC_Rdy),                   // width: 1
+        .probe19(LDPC_Dout),                  // width: 1
+        .probe20(good_frames),                // width: 9
+        .probe21(bad_frames)                  // width: 9
+    );
 
 
 endmodule

hdl/ad9361_mgc_pin_ctrl.v

@@ -21,6 +21,7 @@ module ad9361_mgc_pin_ctrl (
     input       [11:0] rx_data_q,
     // this port is from zynq to ad9361
     output wire [ 3:0] ad9361_ctrl_in,
+    output wire        flag_mgc_done_pulse,  // active high pulse signal
     output reg         flag_mgc_done = 0     // active high level signal
 
 );
@@ -62,6 +63,7 @@ module ad9361_mgc_pin_ctrl (
     assign dec_pulse           = (cs == S_DEC);
 
     assign start_posedge       = start & ~start_d1;
+    assign flag_mgc_done_pulse = power_measure_done_pulse;
 
     // ******** Logic Block ********
 

hdl/net_city.v

@@ -0,0 +1,417 @@
+`timescale 1ns / 1ps
+
+module net_city (
+    // basic
+    input              clk,
+    input              rst_initial,
+    input              rst_manual,              //manual
+    // tx signal
+    output reg         tx_start = 1'b0,         // pulse
+    output reg  [63:0] trans_net_data = 64'd0,
+    output reg         flag_video_send = 1'b0,
+    output reg  [07:0] recv_id = 8'd0,
+    // rx signal
+    input              frame_sync,
+    input              recv_net_data_nd,
+    input       [63:0] recv_net_data,
+    // net parameter
+    input       [31:0] frame_sync_time,
+    input       [07:0] id_num,
+    input       [07:0] max_slot_num,
+    input       [07:0] video_id01,
+    input       [07:0] video_id02,
+    input       [07:0] video_id03,
+    // net state
+    output reg         is_net = 1'b0,
+    output reg         flag_to_uc = 1'b0,
+    // intr 2 ps
+    output wire        intr_ps,
+    output reg         rx_rst,
+    input  wire        tx_done
+);
+    //----------parameter----------
+    localparam SLOT_TIME = 750000;  // 15ms
+
+    //----------rst----------
+    wire rst;
+    assign rst = rst_initial || rst_manual;
+
+    //----------counter_1s----------
+    reg [31:0] cnt_1s = 32'd0;
+    always @(posedge clk) begin
+        if (rst) begin
+            cnt_1s <= 32'd0;
+        end
+        else begin
+            if (cnt_1s == 32'd49999999) begin
+                cnt_1s <= 32'd0;
+            end
+            else begin
+                cnt_1s <= cnt_1s + 32'd1;
+            end
+        end
+    end
+
+    //----------flag_tx----------
+
+
+    //----------state_net----------
+    reg [07:0] state_net = 8'd0;
+    reg [31:0] cnt_trans_slot = 32'd0;
+    reg [31:0] cnt_inter_slot = 32'd0;
+    reg [07:0] cur_slot = 8'd0;
+    reg [07:0] cnt_video_slot = 8'd0;
+    reg [31:0] cnt_other = 32'd0;
+
+    reg [07:0] connect_node = 8'd0;
+    reg [63:0] trans_net_data_reg = 64'd0;
+    reg [07:0] recv_connect_node = 8'd0;
+    reg [07:0] recv_video_id01 = 8'd0;
+    reg [07:0] recv_video_id02 = 8'd0;
+    reg [07:0] recv_video_id03 = 8'd0;
+
+    // if u dont understand this code blew, plz contact NanzZ 😊
+    assign intr_ps = (cnt_trans_slot == SLOT_TIME - 50000) && ((id_num == 1 && (cur_slot == max_slot_num - 1)) || (id_num != 1 && (cur_slot == id_num - 8'd2)));
+
+    always @(posedge clk) begin
+        if (rst) begin
+            rx_rst <= 0;
+        end
+        else if (tx_start) begin
+            rx_rst <= 1;
+        end
+        else if (tx_done) begin
+            rx_rst <= 0;
+        end
+    end
+
+
+
+    always @(posedge clk) begin
+        if (rst) begin
+            state_net         <= 8'd0;
+            cnt_trans_slot    <= 32'd0;
+            cnt_inter_slot    <= 32'd0;
+            cnt_other         <= 32'd0;
+            recv_id           <= 8'd0;
+            recv_connect_node <= 8'd0;
+            recv_video_id01   <= 8'd0;
+            recv_video_id02   <= 8'd0;
+            recv_video_id03   <= 8'd0;
+            tx_start          <= 1'b0;
+            trans_net_data    <= 64'd0;
+            is_net            <= 1'b0;
+            flag_video_send   <= 1'b0;
+        end
+        else begin
+            case (state_net)
+                8'd0: begin
+                    state_net         <= 8'd1;
+                    cnt_trans_slot    <= 32'd0;
+                    cnt_inter_slot    <= 32'd0;
+                    cnt_other         <= 32'd0;
+                    recv_id           <= recv_id;
+                    recv_connect_node <= 8'd0;
+                    recv_video_id01   <= recv_video_id01;
+                    recv_video_id02   <= recv_video_id02;
+                    recv_video_id03   <= recv_video_id03;
+                    tx_start          <= 1'b0;
+                    trans_net_data    <= 64'd0;
+                    is_net            <= 1'b0;
+                    flag_video_send   <= 1'b0;
+                end
+                8'd1: begin
+                    state_net <= 8'd2;
+                end
+                8'd2: begin
+                    if (frame_sync) begin
+                        state_net      <= 8'd50;
+                        cnt_other      <= 32'd0;
+                        cnt_trans_slot <= frame_sync_time;
+                        cnt_inter_slot <= cnt_trans_slot + 32'd1;
+                    end
+                    else if (cnt_other == 32'd49999999) begin
+                        cnt_other <= 32'd0;
+                        state_net <= 8'd100;
+                        is_net    <= 1'b1;
+                    end
+                    else begin
+                        cnt_other <= cnt_other + 32'd1;
+                    end
+                end
+
+                8'd100: begin  // _tx
+                    state_net      <= 8'd101;
+                    tx_start       <= 1'b1;
+                    trans_net_data <= trans_net_data_reg;
+                    cnt_trans_slot <= 32'd0;
+                    cnt_inter_slot <= 32'd0;
+                end
+                8'd101: begin
+                    state_net      <= 8'd200;
+                    tx_start       <= 1'b0;
+                    cnt_trans_slot <= cnt_trans_slot + 32'd1;
+                end
+
+                8'd200: begin  // wait
+                    if ((cnt_trans_slot == SLOT_TIME - 2) && (id_num == 1 && (cur_slot == max_slot_num - 1))) begin
+                        state_net      <= 8'd100;
+                        cnt_trans_slot <= cnt_trans_slot + 32'd1;
+                        cnt_inter_slot <= 32'd0;
+                    end
+                    else if ((cnt_trans_slot == SLOT_TIME - 2) && (id_num != 1 && (cur_slot == id_num - 8'd2))) begin
+                        state_net      <= 8'd100;
+                        cnt_trans_slot <= cnt_trans_slot + 32'd1;
+                        cnt_inter_slot <= 32'd0;
+                    end
+                    else if (frame_sync) begin
+                        state_net      <= 8'd50;
+                        cnt_trans_slot <= frame_sync_time;
+                        cnt_inter_slot <= cnt_trans_slot + 32'd1;
+                    end
+                    else begin
+                        if (cnt_trans_slot == SLOT_TIME - 1) begin
+                            cnt_trans_slot <= 32'd0;
+                        end
+                        else begin
+                            cnt_trans_slot <= cnt_trans_slot + 32'd1;
+                        end
+                        cnt_inter_slot <= 32'd0;
+                    end
+
+                    case (id_num)
+                        recv_video_id01: begin
+                            if (cnt_trans_slot == SLOT_TIME - 2 && cnt_video_slot == 8'd0) begin
+                                flag_video_send <= 1'b1;
+                            end
+                            else begin
+                                flag_video_send <= 1'b0;
+                            end
+                        end
+                        recv_video_id02: begin
+                            if (cnt_trans_slot == SLOT_TIME - 2 && cnt_video_slot == 8'd1) begin
+                                flag_video_send <= 1'b1;
+                            end
+                            else begin
+                                flag_video_send <= 1'b0;
+                            end
+                        end
+                        recv_video_id03: begin
+                            if (cnt_trans_slot == SLOT_TIME - 2 && cnt_video_slot == 8'd2) begin
+                                flag_video_send <= 1'b1;
+                            end
+                            else begin
+                                flag_video_send <= 1'b0;
+                            end
+                        end
+                        default: begin
+                            flag_video_send <= 1'b0;
+                        end
+                    endcase
+                end
+
+                8'd50: begin
+                    // if (recv_net_data_nd) begin
+                    //     if (recv_net_data[23:00] == 24'h7e5a33) begin
+                    state_net         <= 8'd51;
+                    is_net            <= 1'b1;
+                    cnt_trans_slot    <= cnt_trans_slot + 32'd1;
+                    cnt_inter_slot    <= cnt_inter_slot + 32'd1;
+                    recv_id           <= recv_net_data[63:56];
+                    recv_video_id01   <= recv_net_data[55:48];
+                    recv_video_id02   <= recv_net_data[47:40];
+                    recv_video_id03   <= recv_net_data[39:32];
+                    recv_connect_node <= recv_net_data[31:24];
+                    //     end
+                    //     else begin
+                    //         state_net      <= 8'd200;
+                    //         is_net         <= 1'b0;
+
+                    //         cnt_trans_slot <= cnt_inter_slot + 32'd1;
+                    //     end
+                    // end
+                    // else begin
+                    //     cnt_trans_slot <= cnt_trans_slot + 32'd1;
+                    //     cnt_inter_slot <= cnt_inter_slot + 32'd1;
+                    // end
+                end
+                8'd51: begin
+                    state_net      <= 8'd200;
+                    cnt_trans_slot <= cnt_trans_slot + 32'd1;
+                end
+
+                default: begin
+                    state_net         <= 8'd0;
+                    cnt_trans_slot    <= 32'd0;
+                    cnt_inter_slot    <= 32'd0;
+                    cnt_other         <= 32'd0;
+                    recv_id           <= recv_id;
+                    recv_connect_node <= 8'd0;
+                    recv_video_id01   <= recv_video_id01;
+                    recv_video_id02   <= recv_video_id02;
+                    recv_video_id03   <= recv_video_id03;
+                    tx_start          <= 1'b0;
+                    trans_net_data    <= 64'd0;
+                    is_net            <= 1'b0;
+                    flag_video_send   <= 1'b0;
+                end
+            endcase
+        end
+    end
+
+    //----------connect_node----------
+    // always @(posedge clk) begin
+    //     if (rst) begin
+    //         connect_node <= 8'd0;
+    //     end else begin
+    //         if (state_net == 8'd51) begin
+    //             case (recv_id)
+    //                 8'd1: begin
+    //                     connect_node[07:06] <= 2'b11;
+    //                 end
+    //                 8'd2: begin
+    //                     connect_node[05:04] <= 2'b11;
+    //                 end
+    //                 8'd3: begin
+    //                     connect_node[03:02] <= 2'b11;
+    //                 end
+    //                 8'd4: begin
+    //                     connect_node[01:00] <= 2'b11;
+    //                 end
+    //                 default: begin
+    //                     connect_node <= 8'd0;
+    //                 end
+    //             endcase
+    //         end else if (cnt_trans_slot == SLOT_TIME / 2 && cur_slot == id_num) begin
+    //             connect_node <= 8'd0;
+    //         end else begin
+    //             connect_node <= connect_node;
+    //         end
+    //     end
+    // end
+
+    //----------trans_net_data_reg----------
+    reg [07:0] trans_video_id01;
+    reg [07:0] trans_video_id02;
+    reg [07:0] trans_video_id03;
+    always @(posedge clk) begin
+        if (rst) begin
+            trans_video_id01 <= 8'd0;
+            trans_video_id02 <= 8'd0;
+            trans_video_id03 <= 8'd0;
+        end
+        else begin
+            if (id_num == 8'd1) begin  //主节点
+                trans_video_id01 <= video_id01;
+                trans_video_id02 <= video_id02;
+                trans_video_id03 <= video_id03;
+            end
+            else if (recv_id == 8'd1) begin  //从节点只听从主节点命令
+                trans_video_id01 <= recv_video_id01;
+                trans_video_id02 <= recv_video_id02;
+                trans_video_id03 <= recv_video_id03;
+            end
+            else begin
+                trans_video_id01 <= trans_video_id01;
+                trans_video_id02 <= trans_video_id02;
+                trans_video_id03 <= trans_video_id03;
+            end
+        end
+    end
+    always @(posedge clk) begin
+        if (rst) begin
+            trans_net_data_reg <= 64'd0;
+        end
+        else begin
+            if (cnt_trans_slot == SLOT_TIME / 2 && cur_slot == id_num - 8'd1) begin
+                trans_net_data_reg[63:56] <= id_num;
+                trans_net_data_reg[55:48] <= trans_video_id01;
+                trans_net_data_reg[47:40] <= trans_video_id02;
+                trans_net_data_reg[39:32] <= trans_video_id03;
+                trans_net_data_reg[31:24] <= connect_node;
+                trans_net_data_reg[23:00] <= 24'h7e5a33;
+            end
+            else begin
+                trans_net_data_reg <= trans_net_data_reg;
+            end
+        end
+    end
+
+    //----------cur_slot----------
+    always @(posedge clk) begin
+        if (rst) begin
+            cur_slot <= 8'd0;
+        end
+        else begin
+            if (state_net == 8'd51) begin
+                if (recv_id <= max_slot_num) begin
+                    cur_slot <= recv_id - 8'd1;
+                end
+                else begin
+                    cur_slot <= cur_slot;
+                end
+            end
+            else if (cnt_trans_slot == SLOT_TIME - 1) begin
+                if (cur_slot == max_slot_num - 8'd1) begin
+                    cur_slot <= 8'd0;
+                end
+                else begin
+                    cur_slot <= cur_slot + 8'd1;
+                end
+            end
+            else begin
+                cur_slot <= cur_slot;
+            end
+        end
+    end
+
+    //----------cnt_video_slot----------
+    always @(posedge clk) begin
+        if (rst) begin
+            cnt_video_slot <= 8'd0;
+        end
+        else begin
+            if (cnt_trans_slot == SLOT_TIME - 1) begin
+                if (cnt_video_slot == 8'd2) begin
+                    cnt_video_slot <= 8'd0;
+                end
+                else begin
+                    cnt_video_slot <= cnt_video_slot + 8'd1;
+                end
+            end
+            else begin
+                cnt_video_slot <= cnt_video_slot;
+            end
+        end
+    end
+
+    always @(posedge clk) begin
+        if (rst) begin
+            flag_to_uc <= 1'b0;
+        end
+        else begin
+            if (cnt_trans_slot == SLOT_TIME / 2 - 1) begin
+                flag_to_uc <= 1'b1;
+            end
+            else begin
+                flag_to_uc <= 1'b0;
+            end
+        end
+    end
+
+    ila_MAC ila_MAC (
+        .clk    (clk),
+        .probe0 (tx_start),
+        .probe1 (connect_node),
+        .probe2 (cnt_trans_slot),
+        .probe3 (recv_net_data),
+        .probe4 (state_net),
+        .probe5 (recv_id),
+        .probe6 (cur_slot),
+        .probe7 (id_num),
+        .probe8 (frame_sync),
+        .probe9 (max_slot_num),
+        .probe10(recv_net_data_nd),
+        .probe11(trans_net_data)
+    );
+endmodule

hdl/power_measure.v

@@ -30,7 +30,7 @@ module power_measure (
 );
 
     localparam CNT_WAIT_9361_MAX = 80;  //* 等待周期数
-    localparam CNT_MEASURING_MAX = 512;  // * 观察64个周期
+    localparam CNT_MEASURING_MAX = 256;  // * 观察64个周期
     localparam CNT_ADJUST_TIMES_MAX = 25;
     localparam CNT_AMP_TOO_HIGH_THRESHOLD = 6;
     // ******** Wire & Reg  ********

hdl/system_top.v

@@ -89,6 +89,7 @@ module system_top (
     wire        tx_data_src_tvalid;
     // tx signal 
     wire        tx_test_flag;
+    wire        flag_mgc_done_pulse;
 
     // baseband signal
     wire [11:0] ad9361_rx_data_i;
@@ -98,6 +99,13 @@ module system_top (
     wire [11:0] ad9361_tx_data_i;
     wire [11:0] ad9361_tx_data_q;
     wire [ 2:0] speed_mode;
+    // mux
+    wire        bb_tx_iq_reverse;
+    wire        bb_rx_iq_reverse;
+    wire [11:0] bb_tx_i;
+    wire [11:0] bb_tx_q;
+    wire [11:0] bb_rx_i;
+    wire [11:0] bb_rx_q;
 
     // phy control signal
     wire        phy_rst_vio;
@@ -108,7 +116,21 @@ module system_top (
 
     // tx signal
     wire        frame_sync_pulse;
+    wire        rx_rst;
+    wire        tx_done;
+    wire        intr_2ps_vio;
+    reg         intr_2ps_vio_d1;
+    wire        intr_2ps_vio_pos;
 
+    wire        tx_start_vio;
+    reg         tx_start_vio_d1;
+    wire        tx_start_vio_pos;
+
+    // vio
+    wire        rst_manual;
+    wire [ 7:0] node_id;
+    wire        intr_2ps;
+    wire [ 7:0] max_slot_num;
 
     // ******** Assingment  ********
 
@@ -121,6 +143,11 @@ module system_top (
     assign ad9361_txnrx     = gpio_o[3];  // ad9361 txnrx
 
 
+    assign ad9361_tx_data_i = bb_tx_iq_reverse ? bb_tx_q : bb_tx_i;
+    assign ad9361_tx_data_q = bb_tx_iq_reverse ? bb_tx_i : bb_tx_q;
+    assign bb_rx_i          = bb_rx_iq_reverse ? ad9361_rx_data_q : ad9361_rx_data_i;
+    assign bb_rx_q          = bb_rx_iq_reverse ? ad9361_rx_data_i : ad9361_rx_data_q;
+
     // ******** Logic Block ********
 
     // ********    Inst     ********
@@ -182,7 +209,7 @@ module system_top (
         .gpio_t            (gpio_t),
         // intr  pl to ps
         .pl2ps_intr2       (intr_2ps),
-        .pl2ps_intr3       (pl2ps_intr3),
+        .pl2ps_intr3       (flag_mgc_done_pulse),
         // tx fifo
         .tx_data_src_count (tx_data_src_count),
         .tx_data_src_tdata (tx_data_src_tdata),
@@ -197,75 +224,104 @@ module system_top (
     );
 
 
+    tdma #(
+        .SLOT_LEN      (750000),  // 50MHz--> 15ms
+        .TIC_TO_PS_LEN (700000),
+        .TIC_FRAME_SYNC(42344)
+        // .SLOT_LEN      (625001),  // 50MHz--> 15ms
+        // .TIC_TO_PS_LEN (575000),
+        // .TIC_FRAME_SYNC(42344)
+    ) u_tdma (
+        .clk            (clk_1x),
+        .rst            (rst_sys),
+        .flag_is_master (flag_is_master),
+        .flag_frame_sync(frame_sync_pulse),
+        .intr_2ps       (intr_2ps),
+        .tx_start       (tx_start),
+        .rx_rst         (rx_rst)
+    );
+
+    // net_city u_net_city (
+    //     .clk             (clk_1x),
+    //     .rst_initial     (rst_sys),
+    //     .rst_manual      (rst_manual),
+    //     .tx_start        (tx_start),
+    //     .trans_net_data  (),
+    //     .flag_video_send (),
+    //     .recv_id         (),
+    //     .frame_sync      (frame_sync_pulse),
+    //     .recv_net_data_nd(1'b1),
+    //     .recv_net_data   (64'd0),
+    //     .frame_sync_time (42344),
+    //     .id_num          (node_id),
+    //     .max_slot_num    (max_slot_num),
+    //     .video_id01      (0),
+    //     .video_id02      (0),
+    //     .video_id03      (0),
+    //     .is_net          (),
+    //     .flag_to_uc      (),
+    //     .intr_ps         (intr_2ps),
+    //     .rx_rst          (rx_rst),
+    //     .tx_done         (tx_done)
+    // );
 
 
     // ---- PHY layer logic start
 
-    // enc_control u_enc_control (
+    enc_control u_enc_control (
-    //     .clk                  (clk_poweron),
+        .clk                  (clk_poweron),
-    //     .rst                  (rst_sys | phy_rst_ps),
+        .rst                  (rst_sys | phy_rst_ps),
-    //     .s_axis_fifo_tvalid   (tx_data_src_tvalid),
+        .s_axis_fifo_tvalid   (tx_data_src_tvalid),
-    //     .s_axis_fifo_tready   (tx_data_src_tready),
+        .s_axis_fifo_tready   (tx_data_src_tready),
-    //     .s_axis_fifo_tdata    (tx_data_src_tdata),
+        .s_axis_fifo_tdata    (tx_data_src_tdata),
-    //     .data_src_count       (tx_data_src_count),
+        .data_src_count       (tx_data_src_count),
-    //     .fifo_enc_out_rd_clk  (clk_1x),
+        .fifo_enc_out_rd_clk  (clk_1x),
-    //     .fifo_enc_out_rd_en   (enc_fifo_rd_en),
+        .fifo_enc_out_rd_en   (enc_fifo_rd_en),
-    //     .fifo_enc_out_dout_map(enc_fifo_dout_map),
+        .fifo_enc_out_dout_map(enc_fifo_dout_map),
-    //     .fifo_enc_out_empty   (enc_fifo_empty)
+        .fifo_enc_out_empty   (enc_fifo_empty)
-    // );
+    );
 
 
-    // tdma #(
+    Transmitter u_Transmitter (
-    //     .SLOT_LEN      (1250000),  // 50MHz--> 25ms
-    //     .TIC_TO_PS_LEN (1200000),
-    //     .TIC_FRAME_SYNC(42272)
-    // ) u_tdma (
-    //     .clk            (clk_1x),
-    //     .rst            (rst_sys),
-    //     .flag_is_master (1'b0),
-    //     .flag_frame_sync(frame_sync_pulse),
-    //     .intr_2ps       (intr_2ps),
-    //     .tx_start       (tx_start)
-    // );
-
-
-    // Transmitter u_Transmitter (
-    //     .clk               (clk_1x),
-    //     .rst               (rst_sys | phy_rst | phy_rst_vio),
-    //     .speed_mode        (speed_mode),
-    //     .send_data_ready   (send_data_ready),
-    //     .send_start        (send_start),
-    //     .send_over         (send_over),
-    //     .clk_data_src      (clk_data_src),
-    //     .tx_data_src_tdata (enc_fifo_dout_map),
-    //     .tx_data_src_tready(enc_fifo_rd_en),
-    //     .tx_data_src_tvalid(~enc_fifo_empty),
-    //     .hopping_freq      (),
-    //     .ad9361_tx_data_i  (ad9361_tx_data_i),
-    //     .ad9361_tx_data_q  (ad9361_tx_data_q),
-    //     .test              (tx_test_flag | phy_tx_test_flag_vio),
-    //     .hop_wait          (100)
-    // );
-
-    // Receiver u_Receiver (
-    //     .clk             (clk_1x),
-    //     .clk_2x          (clk_2x),
-    //     .clk_4x          (clk_4x),
-    //     .rst             (rst_sys | phy_rst | phy_rst_vio),
-    //     .speed_mode      (speed_mode),
-    //     .ad9361_rx_data_i(ad9361_rx_data_i),
-    //     .ad9361_rx_data_q(ad9361_rx_data_q),
-    //     .frame_sync_pulse(frame_sync_pulse)
-    // );
-
-    ad9361_mgc_pin_ctrl u_ad9361_mgc_pin_ctrl (
         .clk               (clk_1x),
         .rst               (rst_sys | phy_rst),
-        .rx_data_i     (ad9361_rx_data_i),
+        .speed_mode        (2),
-        .rx_data_q     (ad9361_rx_data_q),
+        .send_data_ready   (send_data_ready),
-        .ad9361_ctrl_in(ad9361_ctrl_in)
+        .send_start        (tx_start),
+        .send_over         (tx_done),
+        .clk_data_src      (clk_data_src),
+        .tx_data_src_tdata (enc_fifo_dout_map),
+        .tx_data_src_tready(enc_fifo_rd_en),
+        .tx_data_src_tvalid(~enc_fifo_empty),
+        .hopping_freq      (),
+        .ad9361_tx_data_i  (bb_tx_i),
+        .ad9361_tx_data_q  (bb_tx_q),
+        .test              (tx_test_flag | phy_tx_test_flag_vio),
+        .hop_wait          (100)
     );
 
+    RecvTop u_RecvTop (
+        .clk                (clk_1x),
+        .clk_2x             (clk_2x),
+        .clk_4x             (clk_4x),
+        .rst                (rst_sys | rx_rst | phy_rst),
+        .rst2               (rst_sys | phy_rst),
+        .dini               (bb_rx_i),
+        .dinq               (bb_rx_q),
+        .ad9361_ctrl_in     (ad9361_ctrl_in),
+        .flag_mgc_done_pulse(flag_mgc_done_pulse),
+        .frame_sync_pulse   (frame_sync_pulse),
+        .vio_tsync_inter16  (1),
+        .EQUenable_vio      (1),
+        .Zerozone_vio       (8'd29),
+        .vio_stopbit        (7'd60),
+        .flag_stop          (flag_stop),
+        .addr_stop          (addr_stop),
+        .recvNetData        (recvNetData),
+        .recvNetDataNd      (recvNetDataNd)
+    );
+
+
 
 
 
@@ -318,41 +374,38 @@ module system_top (
 
     // ********    Debug    ********
 
-    ila_ad9361_rx u_ila_ad9361_rx (
+    // ila_ad9361_rx u_ila_ad9361_rx (
-        .clk   (ad9361_rx_clk),
+    //     .clk   (ad9361_rx_clk),
-        .probe0(ad9361_rx_data_i),
+    //     .probe0(ad9361_rx_data_i),
-        .probe1(ad9361_rx_data_q),
+    //     .probe1(ad9361_rx_data_q),
-        .probe2(u_ad9361_mgc_pin_ctrl.flag_adjust)
+    //     .probe2(u_RecvTop.flag_mgc_done)
-    );
+    // );
+
+    // ila_ad9361_tx u_ila_ad9361_tx (
+    //     .clk   (ad9361_tx_clk),     // input wire clk
+    //     .probe0(ad9361_tx_data_i),  // input wire [11:0]  probe0
+    //     .probe1(ad9361_tx_data_q)   // input wire [11:0]  probe1
+    // );
+
+
+    assign tx_start_vio_pos = tx_start_vio & ~tx_start_vio_d1;
+    always @(posedge clk_1x) begin
+        tx_start_vio_d1 <= tx_start_vio;
+    end
+
+    assign intr_2ps_vio_pos = intr_2ps_vio & ~intr_2ps_vio_d1;
+    always @(posedge clk_1x) begin
+        intr_2ps_vio_d1 <= intr_2ps_vio;
+    end
 
-    ila_ad9361_tx u_ila_ad9361_tx (
-        .clk   (ad9361_tx_clk),     // input wire clk
-        .probe0(ad9361_tx_data_i),  // input wire [11:0]  probe0
-        .probe1(ad9361_tx_data_q)   // input wire [11:0]  probe1
-    );
 
 
     vio_phy_control u_vio_phy_control (
         .clk       (clk_1x),            // input wire clk
-        .probe_out0(phy_rst_vio),           // output wire [0 : 0] probe_out0
+        .probe_out0(flag_is_master),    // output wire [0 : 0]
-        .probe_out1(phy_tx_test_flag_vio),  // output wire [0 : 0] probe_out1
+        .probe_out1(bb_tx_iq_reverse),  // output wire [0 : 0]
-        .probe_out2(send_start)             // output wire [0 : 0] probe_out2
+        .probe_out2(bb_rx_iq_reverse)   // output wire [0 : 0]
     );
 
 
-    vio_gpio u_vio_gpio (
-        .clk       (clk_poweron),
-        .probe_out0(rf_gpio),
-        .probe_out1(led_red),
-        .probe_out2(led_yellow),
-        .probe_out3(led_blue)
-    );
-
-    vio_tx_speed_mode u_vio_tx_speed_mode (
-        .clk       (clk_1x),
-        .probe_out0(speed_mode)
-    );
-
-
-
 endmodule

hdl/tdma.v

@@ -14,107 +14,97 @@
 // ! PLEASE MAKE SURE THE PARAMETER ARE VALID 
 // ! WHEN U INSTANTIATE THIS MODULE
 module tdma #(
-    parameter SLOT_LEN = 1250000,
+    parameter SLOT_LEN = 750000,
-    parameter TIC_TO_PS_LEN = 1200000,
+    parameter TIC_TO_PS_LEN = 700000,
-    parameter TIC_FRAME_SYNC = 42272
+    parameter TIC_FRAME_SYNC = 42344
 ) (
     input      clk,
     input      rst,
-    input  flag_is_master,
+    input      flag_is_master,   // TODO: refactor it to parameters
     input      flag_frame_sync,
     output     intr_2ps,
-    // output tic_hop,
+    output     tx_start,
-    output tx_start
+    output reg rx_rst
 );
 
     // TODO: 需要检查综合后电路是否会被优化
     // BUG: 需要修复bug，重构代码，把主从分开写，通过参数进行优化
+
     // ******** Wire & Reg  ********
+
     reg        flag_is_tx_slot;
+    reg [23:0] cnt;
+
     // ******** Assingment  ********
 
+    assign tx_start = flag_is_master & (cnt == 16'd10);
+    assign intr_2ps = flag_is_master & (cnt == TIC_TO_PS_LEN - 1);
+
     // ******** Logic Block ********
 
-    generate
+
-        if (SLOT_LEN <= 65535) begin  // slot len is small
+
-            reg [15:0] cnt;
     always @(posedge clk) begin
         if (rst) begin
-                    cnt <= 16'd0;
+            cnt <= 0;
         end
         else begin
             if (!flag_is_master && flag_frame_sync) begin
                 // slave update cnt
                 cnt <= TIC_FRAME_SYNC;
             end
-                    else if (cnt >= SLOT_LEN - 1) begin
-                        cnt <= 16'd0;
-                    end
-                    else begin
-                        cnt <= cnt + 16'd1;
-                    end
-                end
-            end
-            assign tx_start = flag_is_tx_slot & (cnt == 16'd10);  // just a num for avoiding the zero,(cnt is also 0 in rst state)
-            assign intr_2ps = ~flag_is_tx_slot & (cnt == TIC_TO_PS_LEN);
-
-            always @(posedge clk) begin
-                if (rst) begin
-                    flag_is_tx_slot <= 0;
-                end
-                else if (!flag_is_master && flag_frame_sync) begin
-                    flag_is_tx_slot <= 0;
-                end
-                else if (cnt == 16'd1) begin
-                    flag_is_tx_slot <= ~flag_is_tx_slot;
-                end
-            end
-        end
-        else begin
-            reg [15:0] cnt_l;
-            reg [ 7:0] cnt_h;
-            always @(posedge clk) begin
-                if (rst) begin
-                    cnt_l <= 16'd0;
-                    cnt_h <= 8'd0;
-                end
-                else begin
-                    if (!flag_is_master && flag_frame_sync) begin
-                        // slave update cnt
-                        {cnt_h, cnt_l} <= TIC_FRAME_SYNC;
-                    end
             else begin
                 // master
-                        if ({cnt_h, cnt_l} >= SLOT_LEN) begin
+                if (cnt < SLOT_LEN - 1) begin
-                            cnt_h <= 8'd0;
+                    cnt <= cnt + 1;
-                            cnt_l <= 16'd0;
                 end
                 else begin
-                            {cnt_h, cnt_l} <= {cnt_h, cnt_l} + 24'd1;
+                    cnt <= 0;
                 end
             end
         end
     end
-            assign tx_start = flag_is_tx_slot & ({cnt_h, cnt_l} == 16'd10);
+
-            assign intr_2ps = ~flag_is_tx_slot & ({cnt_h, cnt_l} == TIC_TO_PS_LEN);
 
     always @(posedge clk) begin
-                if (rst) begin
+        if (flag_is_master) begin
-                    flag_is_tx_slot <= 0;
+            rx_rst <= 1;
         end
-                else if (!flag_is_master && flag_frame_sync) begin
+        else begin
-                    flag_is_tx_slot <= 0;
+            rx_rst <= flag_is_master | (cnt <= 16'd4);
-                end
-                else if ({cnt_h, cnt_l} == 16'd1) begin
-                    flag_is_tx_slot <= ~flag_is_tx_slot;
         end
     end
-        end
+
-    endgenerate
+    // always @(posedge clk) begin
+    //     if (rst) begin
+    //         flag_is_tx_slot <= 0;
+    //     end
+    //     else if (!flag_is_master && flag_frame_sync) begin
+    //         flag_is_tx_slot <= 0;
+    //     end
+    //     else if (cnt == 16'd1) begin
+    //         flag_is_tx_slot <= ~flag_is_tx_slot;
+    //     end
+    // end
+
+
+
 
 
     // ********    Inst     ********
 
     // ********    Debug    ********
 
+
+    ila_mac_layer u_ila_mac_layer (
+        .clk   (clk),
+        .probe0(cnt),             // width: 24
+        .probe1(tx_start),        // width: 1
+        .probe2(rx_rst),          // width: 1
+        .probe3(flag_is_master),  // width: 1
+        .probe4(intr_2ps),        // width: 1
+        .probe5(flag_frame_sync)  // width: 1
+    );
+
+
 endmodule

sim/tb_tdma.v

@@ -22,60 +22,25 @@
 
 module tb_tdma ();
 
-
-
     reg clk = 1;
-    reg clk_tx = 1;
     reg rst = 1;
     always #1 clk <= ~clk;
     initial begin
-        #1000 rst <= 1'b0;
+        #10 rst <= 1'b0;
     end
 
-    wire flag_frame_sync_m;
-    reg  flag_frame_sync_s = 0;
-    wire intr_2ps_m;
-    wire intr_2ps_s;
-    wire tic_hop_m;
-    wire tic_hop_s;
-    wire tx_start_m;
-    wire tx_start_s;
-
-    assign flag_frame_sync_m = 1'b0;
-
     tdma #(
-        .SLOT_LEN      (1250000),
+        .SLOT_LEN      (625000),  // 50MHz--> 15ms
-        .TIC_TO_PS_LEN (1200000),
+        .TIC_TO_PS_LEN (575000),
-        .TIC_FRAME_SYNC(42272)
+        .TIC_FRAME_SYNC(42344)
-    ) u_tdma_master (
+    ) u_tdma (
         .clk            (clk),
         .rst            (rst),
-        .flag_is_master (1'b1),
+        .flag_is_master (1),
-        .flag_frame_sync(flag_frame_sync_m),
+        .flag_frame_sync(0),
-        .intr_2ps       (intr_2ps_m),
+        .intr_2ps       (intr_2ps),
-        // .tic_hop        (tic_hop_m),
+        .tx_start       (tx_start),
-        .tx_start       (tx_start_m)
+        .rx_rst         (rx_rst)
     );
 
-
-    tdma #(
-        .SLOT_LEN      (20000),
-        .TIC_TO_PS_LEN (18000),
-        .TIC_FRAME_SYNC(2000)
-    ) u_tdma_slave (
-        .clk            (clk),
-        .rst            (rst),
-        .flag_is_master (1'b0),
-        .flag_frame_sync(flag_frame_sync_s),
-        .intr_2ps       (intr_2ps_s),
-        // .tic_hop        (tic_hop_s),
-        .tx_start       (tx_start_s)
-    );
-
-
-    initial begin
-        #12000 flag_frame_sync_s <= 1'b1;
-        #3 flag_frame_sync_s <= 1'b0;
-    end
-
 endmodule

util.tcl

@@ -0,0 +1,38 @@
+# this is a demo create ip using tcl script
+
+# create a new ip ila named ila_rx2, if the ip already exists, skip create_ip step
+create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_tdma
+# set the ip property
+set_property -dict [list \
+  CONFIG.C_EN_STRG_QUAL {1} \
+  CONFIG.C_NUM_OF_PROBES {22} \
+  CONFIG.C_PROBE0_WIDTH {12} \
+  CONFIG.C_PROBE1_WIDTH {12} \
+  CONFIG.C_PROBE2_WIDTH {12} \
+  CONFIG.C_PROBE3_WIDTH {12} \
+  CONFIG.C_PROBE4_WIDTH {1} \
+  CONFIG.C_PROBE5_WIDTH {1} \
+  CONFIG.C_PROBE6_WIDTH {1} \
+  CONFIG.C_PROBE7_WIDTH {10} \
+  CONFIG.C_PROBE8_WIDTH {10} \
+  CONFIG.C_PROBE9_WIDTH {1} \
+  CONFIG.C_PROBE10_WIDTH {10} \
+  CONFIG.C_PROBE11_WIDTH {10} \
+  CONFIG.C_PROBE12_WIDTH {1} \
+  CONFIG.C_PROBE13_WIDTH {10} \
+  CONFIG.C_PROBE14_WIDTH {10} \
+  CONFIG.C_PROBE15_WIDTH {1} \
+  CONFIG.C_PROBE16_WIDTH {10} \
+  CONFIG.C_PROBE17_WIDTH {10} \
+  CONFIG.C_PROBE18_WIDTH {1} \
+  CONFIG.C_PROBE19_WIDTH {1} \
+  CONFIG.C_PROBE20_WIDTH {9} \
+  CONFIG.C_PROBE21_WIDTH {9} \
+
+] [get_ips ila_recv_top]
+
+
+set_property -dict [list \
+  CONFIG.C_NUM_OF_PROBES {6} \
+  CONFIG.C_PROBE0_WIDTH {24} \
+] [get_ips ila_tdma]