feat(top): add abnormal logic to pass 3rd test

coe/rf_control_map.coe

@@ -0,0 +1,10 @@
+memory_initialization_radix=2;
+memory_initialization_vector=
+1000
+0100
+0001
+1001
+0101
+1101
+0111
+1111;

hdl/phy_control.v

@@ -74,7 +74,8 @@ module phy_control #(
     output wire [31:0] tdma_tic_2_ps,
     output wire [31:0] tdma_id_cfg,
     output wire        tdma_recv_cur_slot_id_valid,
-    output wire [ 7:0] tdma_recv_cur_slot_id
+    output wire [ 7:0] tdma_recv_cur_slot_id,
+    output wire [31:0] tdma_frame_sync_tic
 
     //--- ADD YOUR OWN PORTS END
 );
@@ -344,6 +345,7 @@ module phy_control #(
     localparam integer TDMA_TIC_2_PS = 'h0000_000C >> 2;
     localparam integer TDMA_ID_CFG = 'h0000_0010 >> 2;
     localparam integer TDMA_RECV_ID = 'h0000_0014 >> 2;
+    localparam integer TDMA_FRAME_SYNC_TIC = 'h0000_0018 >> 2;
 
     // Register definitions
     reg [31:0] phy_cr_reg = 32'h0;
@@ -352,6 +354,7 @@ module phy_control #(
     reg [31:0] tdma_tic_2_ps_reg = 32'h0;
     reg [31:0] tdma_id_cfg_reg = 32'h0;  // 2B zero pad, 1B slot num, 1B local id
     reg [31:0] tdma_recv_id_reg = 32'h0;
+    reg [31:0] tdma_frame_sync_tic_reg = 32'h0;
 
     // Register Reading
     always @(posedge local_clk) begin
@@ -378,6 +381,7 @@ module phy_control #(
                     TDMA_TIC_2_PS: tdma_tic_2_ps_reg <= up_wdata_s;
                     TDMA_ID_CFG: tdma_id_cfg_reg <= up_wdata_s;
                     TDMA_RECV_ID: tdma_recv_id_reg <= up_wdata_s;
+                    TDMA_FRAME_SYNC_TIC: tdma_frame_sync_tic_reg <= up_wdata_s;
                 endcase
             end
             else begin
@@ -403,6 +407,8 @@ module phy_control #(
     // received mac frame 
     assign tdma_recv_cur_slot_id       = tdma_recv_id_reg[7:0];
     assign tdma_recv_cur_slot_id_valid = tdma_recv_id_reg[8];
+    // frame sync tic
+    assign tdma_frame_sync_tic         = tdma_frame_sync_tic_reg;
 
     vio_phy_param u_vio_phy_param (
         .clk      (local_clk),

hdl/system_top.v

@@ -125,6 +125,8 @@ module system_top (
     wire [31:0] tdma_id_cfg;
     wire        tdma_recv_cur_slot_id_valid;
     wire [ 7:0] tdma_recv_cur_slot_id;
+    wire [31:0] tdma_frame_sync_tic;
+
 
     // tx signal
     wire        frame_sync_pulse;
@@ -154,6 +156,9 @@ module system_top (
     wire        intr_2ps;
     wire [ 7:0] max_slot_num;
 
+    reg  [15:0] cnt_pulse_wider_tx_start = 0;
+    reg  [15:0] cnt_pulse_wider_frame_sync = 0;
+
     // ******** Assingment  ********
 
     assign ad9361_tx_clk    = clk_1x;
@@ -170,15 +175,42 @@ module system_top (
     assign bb_rx_i          = phy_rx_iq_reverse ? ad9361_rx_data_q : ad9361_rx_data_i;
     assign bb_rx_q          = phy_rx_iq_reverse ? ad9361_rx_data_i : ad9361_rx_data_q;
     // gpio  rf control
-    assign rf_io0_d3_18db   = rf_gpio[0];
+    assign rf_gpio[0]       = rf_io0_d3_18db;
-    assign rf_io1_d4_12db   = rf_gpio[1];
+    assign rf_gpio[1]       = rf_io1_d4_12db;
-    assign rf_io2_trx       = rf_gpio[2];
+    // assign rf_gpio[2]       = rf_io2_trx;
-    assign rf_io3_d1_12db   = rf_gpio[3];
+    // assign rf_gpio[3]       = rf_io3_d1_12db;
-    assign rf_io4_d2_6db    = rf_gpio[4];
+    assign rf_gpio[4]       = rf_io4_d2_6db;
+    assign rf_gpio[5]       = 0;
+    // temporary for test gpio
+    assign rf_gpio[2]       = (cnt_pulse_wider_tx_start != 0);
+    assign rf_gpio[3]       = (cnt_pulse_wider_frame_sync != 0);
 
 
     // ******** Logic Block ********
 
+    always @(posedge clk_1x) begin
+        if (tx_start) begin
+            cnt_pulse_wider_tx_start <= 1;
+        end
+        else if (cnt_pulse_wider_tx_start > 0) begin
+            cnt_pulse_wider_tx_start <= cnt_pulse_wider_tx_start + 1;
+        end
+        else begin
+            cnt_pulse_wider_tx_start <= cnt_pulse_wider_tx_start;
+        end
+    end
+    always @(posedge clk_2x) begin
+        if (rx_data_src_fifo_tlast) begin
+            cnt_pulse_wider_frame_sync <= 1;
+        end
+        else if (cnt_pulse_wider_frame_sync > 0) begin
+            cnt_pulse_wider_frame_sync <= cnt_pulse_wider_frame_sync + 1;
+        end
+        else begin
+            cnt_pulse_wider_frame_sync <= cnt_pulse_wider_frame_sync;
+        end
+    end
+
     // ********    Inst     ********
 
     clk_wiz_poweron u_clk_wiz_poweron (
@@ -266,6 +298,7 @@ module system_top (
         .tdma_id_cfg                (tdma_id_cfg),
         .tdma_recv_cur_slot_id_valid(tdma_recv_cur_slot_id_valid),
         .tdma_recv_cur_slot_id      (tdma_recv_cur_slot_id),
+        .tdma_frame_sync_tic        (tdma_frame_sync_tic),
         // uart 
         .uart_rx                    (uart_rx),
         .uart_tx                    (uart_tx)
@@ -278,6 +311,7 @@ module system_top (
         .tdma_slot_len             (tdma_slot_len[23:0]),
         .tdma_tic_2_ps             (tdma_tic_2_ps[23:0]),
         .tdma_slot_num             (tdma_id_cfg[15:8]),
+        .tdma_frame_sync_tic       (tdma_frame_sync_tic[23:0]),
         .local_id                  (tdma_id_cfg[7:0]),
         .recevied_cur_slot_id_valid(tdma_recv_cur_slot_id_valid),
         .recevied_cur_slot_id      (tdma_recv_cur_slot_id),
@@ -288,32 +322,6 @@ module system_top (
 
 
 
-
-    // net_city u_net_city (
-    //     .clk             (clk_1x),
-    //     .rst_initial     (rst_sys),
-    //     .rst_manual      (rst_manual),
-    //     .tx_start        (tx_start),
-    //     .trans_net_data  (),
-    //     .flag_video_send (),
-    //     .recv_id         (),
-    //     .frame_sync      (frame_sync_pulse),
-    //     .recv_net_data_nd(1'b1),
-    //     .recv_net_data   (64'd0),
-    //     .frame_sync_time (42344),
-    //     .id_num          (node_id),
-    //     .max_slot_num    (max_slot_num),
-    //     .video_id01      (0),
-    //     .video_id02      (0),
-    //     .video_id03      (0),
-    //     .is_net          (),
-    //     .flag_to_uc      (),
-    //     .intr_ps         (intr_2ps),
-    //     .rx_rst          (rx_rst),
-    //     .tx_done         (tx_done)
-    // );
-
-
     // ---- PHY layer logic start
 
     enc_control u_enc_control (
@@ -374,11 +382,6 @@ module system_top (
         .err_flag_pos           (rx_err_flag_pos)
     );
 
-
-
-
-
-
     // ---- PHY layer logic end
 
 
@@ -400,50 +403,31 @@ module system_top (
         .tx_frame  (ad9361_tx_frame)
     );
 
-    // // ********     CDC     ********
+    // ********     CDC     ********
 
 
-    // // ********    Debug    ********
+    // ********    Debug    ********
 
-    // // ila_ad9361_rx u_ila_ad9361_rx (
+    // ila_ad9361_rx u_ila_ad9361_rx (
-    // //     .clk   (ad9361_rx_clk),
+    //     .clk   (ad9361_rx_clk),
-    // //     .probe0(ad9361_rx_data_i),
+    //     .probe0(ad9361_rx_data_i),
-    // //     .probe1(ad9361_rx_data_q),
+    //     .probe1(ad9361_rx_data_q),
-    // //     .probe2(u_RecvTop.flag_mgc_done)
+    //     .probe2(u_RecvTop.flag_mgc_done)
-    // // );
-
-    // // ila_ad9361_tx u_ila_ad9361_tx (
-    // //     .clk   (ad9361_tx_clk),     // input wire clk
-    // //     .probe0(ad9361_tx_data_i),  // input wire [11:0]  probe0
-    // //     .probe1(ad9361_tx_data_q)   // input wire [11:0]  probe1
-    // // );
-
-
-    // // assign tx_start_vio_pos = tx_start_vio & ~tx_start_vio_d1;
-    // // always @(posedge clk_1x) begin
-    // //     tx_start_vio_d1 <= tx_start_vio;
-    // // end
-
-    // // assign intr_2ps_vio_pos = intr_2ps_vio & ~intr_2ps_vio_d1;
-    // // always @(posedge clk_1x) begin
-    // //     intr_2ps_vio_d1 <= intr_2ps_vio;
-    // // end
-
-
-    // vio_system_top u_vio_system_top (
-    //     .clk       (clk_1x),
-    //     .probe_out0(node_id),
-    //     .probe_out1(max_slot_num),
-    //     .probe_out2(rst_manual)
     // );
 
-    vio_rf u_vio_rf (
+    // ila_ad9361_tx u_ila_ad9361_tx (
-        .clk       (clk_poweron),
+    //     .clk   (ad9361_tx_clk),     // input wire clk
-        .probe_out0(rf_io2_trx),
+    //     .probe0(ad9361_tx_data_i),  // input wire [11:0]  probe0
-        .probe_out1(rf_io3_d1_12db),
+    //     .probe1(ad9361_tx_data_q)   // input wire [11:0]  probe1
-        .probe_out2(rf_io4_d2_6db),
+    // );
-        .probe_out3(rf_io0_d3_18db),
+
-        .probe_out4(rf_io1_d4_12db)
+    // vio_rf u_vio_rf (
-    );
+    //     .clk       (clk_poweron),
+    //     .probe_out0(rf_io2_trx),
+    //     .probe_out1(rf_io3_d1_12db),
+    //     .probe_out2(rf_io4_d2_6db),
+    //     .probe_out3(rf_io0_d3_18db),
+    //     .probe_out4(rf_io1_d4_12db)
+    // );
 
 endmodule

hdl/tdma.v

@@ -13,9 +13,7 @@
 
 // ! PLEASE MAKE SURE THE PARAMETER ARE VALID 
 // ! WHEN U INSTANTIATE THIS MODULE
-module tdma #(
+module tdma (
-    parameter TIC_FRAME_SYNC = 44432
-) (
     input              clk,
     input              rst,
     // PHY parameter
@@ -24,6 +22,7 @@ module tdma #(
     input  wire [23:0] tdma_slot_len,
     input  wire [23:0] tdma_tic_2_ps,
     input  wire [ 7:0] tdma_slot_num,
+    input  wire [23:0] tdma_frame_sync_tic,
     input  wire [ 7:0] local_id,                    // ID number for this device
     // update while received valid     
     input  wire        recevied_cur_slot_id_valid,  // recevied ID number of the frame
@@ -102,15 +101,9 @@ module tdma #(
             cnt_tdma_slot_len <= 0;
         end
         else if (flag_frame_sync) begin
-            cnt_tdma_slot_len <= tdma_tic_frame_sync_vio;
+            cnt_tdma_slot_len <= tdma_frame_sync_tic;
         end
         else begin
-            // if (cnt_tdma_slot_len < tdma_slot_len - 1) begin
-            //     cnt_tdma_slot_len <= cnt_tdma_slot_len + 1;
-            // end
-            // else begin
-            //     cnt_tdma_slot_len <= 0;
-            // end
             if (flag_end_of_one_slot) begin
                 cnt_tdma_slot_len <= 0;
             end
@@ -177,7 +170,7 @@ module tdma #(
         .probe_in1(tdma_tic_2_ps),
         .probe_in2(tdma_slot_num),
         .probe_in3(local_id),
-        .probe_out0(tdma_tic_frame_sync_vio)
+        .probe_in4(tdma_frame_sync_tic)
     );
 
     ila_mac_layer u_ila_mac_layer (