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ZoroGH/MM7020:main ZoroGH/MM7020:speed_3125
ZoroGH/MM7020:ThirdTestRelease ZoroGH/MM7020:release_3125_v1.1 ZoroGH/MM7020:release_3125_v1 ZoroGH/MM7020:PhyTested ZoroGH/MM7020:PhyDone ZoroGH/MM7020:TxDone
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compare: ZoroGH/MM7020:main
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ZoroGH/MM7020:speed_3125 ZoroGH/MM7020:main
ZoroGH/MM7020:ThirdTestRelease ZoroGH/MM7020:release_3125_v1.1 ZoroGH/MM7020:release_3125_v1 ZoroGH/MM7020:PhyTested ZoroGH/MM7020:PhyDone ZoroGH/MM7020:TxDone
3 Commits
release_3125_v1 ... main
Author SHA1 Message Date
ZoroGH 9d566f6b74 feat(top): add abnormal logic to pass 3rd test 2024-10-18 14:05:04 +08:00
ZoroGH fea952e06a merge(sys): merge tdma update 2024-10-12 11:02:35 +08:00
ZoroGH ae78b3092d feat(tdma): update tdma logic 2024-10-09 20:13:52 +08:00
11 changed files with 709 additions and 476 deletions
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@@ -477,13 +477,15 @@ CN3_dout_04_00_VN hdl/LDPC_DEC_PRO.v /^ reg [WIDTH-1:0] CN3_dout_04_00_VN =
CNT_ADJUST_TIMES_MAX hdl/power_measure.v /^ localparam CNT_ADJUST_TIMES_MAX = 25;$/;" c module:power_measure
CNT_AMP_TOO_HIGH_THRESHOLD hdl/power_measure.v /^ localparam CNT_AMP_TOO_HIGH_THRESHOLD = 6;$/;" c module:power_measure
CNT_CHU_SEQ_SYNC_MAX hdl/RecvTop.v /^ localparam CNT_CHU_SEQ_SYNC_MAX = 40; \/\/! should not less than 3 due to the minimum rst o/;" c module:RecvTop
CNT_END hdl/PAPR.v /^ localparam CNT_END = 44; \/\/ 88*4 \/ 8$/;" c module:PAPR
CNT_IN_MAX hdl/enc_control.v /^ localparam CNT_IN_MAX = ENC_IN_LEN \/ INPUT_DATA_WIDTH;$/;" c module:enc_control
CNT_IN_MAX sim/tb_width_convert.v /^ localparam CNT_IN_MAX = 32;$/;" c module:tb_width_convert
CNT_IN_WIDTH hdl/enc_control.v /^ localparam CNT_IN_WIDTH = $clog2(CNT_IN_MAX);$/;" c module:enc_control
CNT_MAX hdl/width_convert.v /^ localparam CNT_MAX = INPUT_WIDTH \/ OUTPUT_WIDTH;$/;" c module:width_convert
CNT_MEASURING_MAX hdl/power_measure.v /^ localparam CNT_MEASURING_MAX = 512; \/\/ * 观察64个周期$/;" c module:power_measure
CNT_MEASURING_MAX hdl/power_measure.v /^ localparam CNT_MEASURING_MAX = 256; \/\/ * 观察64个周期$/;" c module:power_measure
CNT_OUT_MAX hdl/enc_control.v /^ localparam CNT_OUT_MAX = ENC_OUT_LEN;$/;" c module:enc_control
CNT_OUT_WIDTH hdl/enc_control.v /^ localparam CNT_OUT_WIDTH = $clog2(CNT_OUT_MAX); \/\/ 多留1bit$/;" c module:enc_control
CNT_START hdl/PAPR.v /^ localparam CNT_START = 16; \/\/ 32*4 \/ 8 * mag_valid signal is active high per 8 clk$/;" c module:PAPR
CNT_W adi_library/common/ad_pnmon.v /^ localparam CNT_W = $clog2(OOS_THRESHOLD);$/;" c module:ad_pnmon
CNT_WAIT_9361_MAX hdl/power_measure.v /^ localparam CNT_WAIT_9361_MAX = 80; \/\/* 等待周期数$/;" c module:power_measure
CNT_WIDTH hdl/add_prefix.v /^ localparam CNT_WIDTH = $clog2(DATA_LEN);$/;" c module:add_prefix
@@ -1116,9 +1118,10 @@ ID_WIDTH adi_library/axi_dmac/response_handler.v /^ parameter ID_WIDTH = 3)($/;
ID_WIDTH adi_library/axi_dmac/src_axi_mm.v /^ parameter ID_WIDTH = 3,$/;" c module:dmac_src_mm_axi
ID_WIDTH adi_library/axi_dmac/src_axi_stream.v /^ parameter ID_WIDTH = 3,$/;" c module:dmac_src_axi_stream
ID_WIDTH adi_library/axi_dmac/src_fifo_inf.v /^ parameter ID_WIDTH = 3,$/;" c module:dmac_src_fifo_inf
ILA_ON hdl/scrambler.v /^ parameter ILA_ON = 0$/;" c module:scrambler
INIT_DELAY adi_library/common/up_delay_cntrl.v /^ parameter INIT_DELAY = 0,$/;" c module:up_delay_cntrl
INPUT_DATA_WIDTH hdl/enc_control.v /^ parameter INPUT_DATA_WIDTH = 32$/;" c module:enc_control
INPUT_WIDTH hdl/width_convert.v /^ parameter INPUT_WIDTH = 16,$/;" c module:width_convert
INPUT_WIDTH hdl/width_convert.v /^ parameter INPUT_WIDTH = 32,$/;" c module:width_convert
IODELAY_CTRL adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ parameter IODELAY_CTRL = 1'b0,$/;" c module:util_gmii_to_rgmii
IODELAY_CTRL adi_library/xilinx/common/ad_data_in.v /^ parameter IODELAY_CTRL = 0,$/;" c module:ad_data_in
IODELAY_CTRL adi_library/xilinx/common/ad_data_out.v /^ parameter IODELAY_CTRL = 0,$/;" c module:ad_data_out
@@ -1255,6 +1258,9 @@ Lp2_01 hdl/Message_Store.v /^ RAM_512_8 Lp2_01 ($/;" i module:Message_Store t
Lp2_02 hdl/Message_Store.v /^ RAM_512_8 Lp2_02 ($/;" i module:Message_Store typeref:module:RAM_512_8
Lp2_03 hdl/Message_Store.v /^ RAM_512_8 Lp2_03 ($/;" i module:Message_Store typeref:module:RAM_512_8
Lp2_04 hdl/Message_Store.v /^ RAM_512_8 Lp2_04 ($/;" i module:Message_Store typeref:module:RAM_512_8
MAC_FRAME_LEN_BIT hdl/extract_mac_frame.v /^ localparam MAC_FRAME_LEN_BIT = 107520;$/;" c module:extract_mac_frame
MAC_FRAME_LEN_BYTE hdl/extract_mac_frame.v /^ localparam MAC_FRAME_LEN_BYTE = 13440;$/;" c module:extract_mac_frame
MAC_FRAME_LEN_QUAD_BYTE hdl/extract_mac_frame.v /^ localparam MAC_FRAME_LEN_QUAD_BYTE = 3360;$/;" c module:extract_mac_frame
MAG_WIDTH hdl/PAPR.v /^ parameter MAG_WIDTH = 22,$/;" c module:PAPR
MASTER_DATA_WIDTH adi_library/util_axis_resize/util_axis_resize.v /^ parameter MASTER_DATA_WIDTH = 64,$/;" c module:util_axis_resize
MAX_BEATS_PER_BURST adi_library/axi_dmac/address_generator.v /^localparam MAX_BEATS_PER_BURST = {1'b1,{BEATS_PER_BURST_WIDTH{1'b0}}};$/;" c module:dmac_address_generator
@@ -1427,7 +1433,7 @@ OFFLOAD0_CMD_MEM_ADDRESS_WIDTH adi_library/spi_engine/axi_spi_engine/axi_spi_eng
OFFLOAD0_SDO_MEM_ADDRESS_WIDTH adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ parameter OFFLOAD0_SDO_MEM_ADDRESS_WIDTH = 4,$/;" c module:axi_spi_engine
ON adi_library/common/ad_tdd_control.v /^ localparam [ 0:0] ON = 1;$/;" c module:ad_tdd_control
OOS_THRESHOLD adi_library/common/ad_pnmon.v /^ parameter OOS_THRESHOLD = 16,$/;" c module:ad_pnmon
OUTPUT_WIDTH hdl/width_convert.v /^ parameter OUTPUT_WIDTH = 2$/;" c module:width_convert
OUTPUT_WIDTH hdl/width_convert.v /^ parameter OUTPUT_WIDTH = 1$/;" c module:width_convert
OUT_CLK_SEL adi_library/xilinx/axi_adxcvr/axi_adxcvr.v /^ parameter [ 2:0] OUT_CLK_SEL = 3'd4) ($/;" c module:axi_adxcvr
OUT_CLK_SEL adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v /^ parameter [ 2:0] OUT_CLK_SEL = 3'd4) ($/;" c module:axi_adxcvr_up
OUT_ONLY_INFORMATION hdl/CCSDS_LDPC_DEC_K1024_R12.v /^ parameter OUT_ONLY_INFORMATION = 1'b0 \/\/译码输出格式选择标志，1:只输出信息/;" c module:CCSDS_LDPC_DEC_K1024_R12
@@ -1443,6 +1449,7 @@ PACK adi_library/util_pack/util_pack_common/pack_interconnect.v /^ parameter PA
PACK adi_library/util_pack/util_pack_common/pack_network.v /^ parameter PACK = 0,$/;" c module:pack_network
PACK adi_library/util_pack/util_pack_common/pack_shell.v /^ parameter PACK = 0$/;" c module:pack_shell
PAPR hdl/PAPR.v /^module PAPR #($/;" m
PAR_WIDTH hdl/ser2par.v /^ parameter PAR_WIDTH = 32$/;" c module:ser2par
PCORE_VERSION adi_library/axi_dmac/axi_dmac_regmap.v /^localparam PCORE_VERSION = 'h00040361;$/;" c module:axi_dmac_regmap
PCORE_VERSION adi_library/common/up_clkgen.v /^ localparam PCORE_VERSION = 32'h00050063;$/;" c module:up_clkgen
PCORE_VERSION adi_library/common/up_hdmi_rx.v /^ localparam PCORE_VERSION = 32'h00040063;$/;" c module:up_hdmi_rx
@@ -1478,6 +1485,7 @@ PREFIX_LEN hdl/add_prefix.v /^ parameter PREFIX_LEN = 32$/;" c module:add_pre
PREIQ_FREQ_BST adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ parameter integer PREIQ_FREQ_BST = 0,$/;" c module:util_adxcvr
PREIQ_FREQ_BST adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ parameter integer PREIQ_FREQ_BST = 0,$/;" c module:util_adxcvr_xch
PULSE_PERIOD adi_library/common/util_pulse_gen.v /^ parameter PULSE_PERIOD = 100000000)( \/\/ t_period * clk_freq$/;" c module:util_pulse_gen
PULSE_PERIOD hdl/PAPR.v /^ localparam PULSE_PERIOD = 32;$/;" c module:PAPR
PULSE_PERIOD hdl/ad9361_mgc_pin_ctrl.v /^ localparam PULSE_PERIOD = 5;$/;" c module:ad9361_mgc_pin_ctrl
PULSE_WIDTH adi_library/common/util_pulse_gen.v /^ parameter PULSE_WIDTH = 7,$/;" c module:util_pulse_gen
P_DW adi_library/common/ad_dds_cordic_pipe.v /^ parameter P_DW = 16,$/;" c module:ad_dds_cordic_pipe
@@ -1717,7 +1725,6 @@ SINGLE_ENDED adi_library/xilinx/common/ad_data_clk.v /^ parameter SINGLE_ENDE
SINGLE_ENDED adi_library/xilinx/common/ad_data_in.v /^ parameter SINGLE_ENDED = 0,$/;" c module:ad_data_in
SINGLE_ENDED adi_library/xilinx/common/ad_data_out.v /^ parameter SINGLE_ENDED = 0,$/;" c module:ad_data_out
SLAVE_DATA_WIDTH adi_library/util_axis_resize/util_axis_resize.v /^ parameter SLAVE_DATA_WIDTH = 64,$/;" c module:util_axis_resize
SLOT_LEN hdl/tdma.v /^ parameter SLOT_LEN = 1250000,$/;" c module:tdma
SLOT_TIME hdl/net_city.v /^ localparam SLOT_TIME = 750000; \/\/ 15ms$/;" c module:net_city
SPEED_GRADE adi_library/common/up_adc_common.v /^ parameter [ 7:0] SPEED_GRADE = 0,$/;" c module:up_adc_common
SPEED_GRADE adi_library/common/up_clkgen.v /^ parameter [ 7:0] SPEED_GRADE = 0,$/;" c module:up_clkgen
@@ -1765,6 +1772,7 @@ S_IDLE hdl/Transmitter.v /^ localparam [3:0] S_IDLE = 4'd0;$/;" c module:Tran
S_IDLE hdl/ad9361_mgc_pin_ctrl.v /^ localparam S_IDLE = 0;$/;" c module:ad9361_mgc_pin_ctrl
S_IDLE hdl/add_prefix.v /^ localparam [2:0] S_IDLE = 0;$/;" c module:add_prefix
S_IDLE hdl/enc_control.v /^ localparam [3:0] S_IDLE = 4'd0;$/;" c module:enc_control
S_IDLE hdl/scrambler.v /^ localparam S_IDLE = 0;$/;" c module:scrambler
S_IN hdl/add_prefix.v /^ localparam [2:0] S_IN = 1;$/;" c module:add_prefix
S_INC hdl/ad9361_mgc_pin_ctrl.v /^ localparam S_INC = 1;$/;" c module:ad9361_mgc_pin_ctrl
S_MEASURE_ADJ hdl/power_measure.v /^ localparam S_MEASURE_ADJ = 3;$/;" c module:power_measure
@@ -1784,6 +1792,7 @@ S_WAIT_ADD_PREFIX_DONE hdl/enc_control.v /^ localparam [3:0] S_WAIT_ADD_PREFI
S_WAIT_GAP hdl/Transmitter.v /^ localparam [3:0] S_WAIT_GAP = 4'd6; \/\/ wait for freq switch$/;" c module:Transmitter
S_WAIT_HOP hdl/Transmitter.v /^ localparam [3:0] S_WAIT_HOP = 4'd5;$/;" c module:Transmitter
S_WAIT_LDPC_OUT hdl/enc_control.v /^ localparam [3:0] S_WAIT_LDPC_OUT = 4'd2;$/;" c module:enc_control
S_WORKING hdl/scrambler.v /^ localparam S_WORKING = 1;$/;" c module:scrambler
Scramble hdl/FrameMerge.v /^ Scramble Scramble ($/;" i module:FrameMerge typeref:module:Scramble
Switch_VN_CN hdl/LDPC_DEC_PRO.v /^ reg Switch_VN_CN = 1'd0;$/;" r module:LDPC_DEC_PRO
Sync_i hdl/SCFDE_recv_FrameSync.v /^ output reg [9:0] Sync_i = 10'd0,$/;" p module:SCFDE_recv_FrameSync
@@ -1791,8 +1800,9 @@ Sync_q hdl/SCFDE_recv_FrameSync.v /^ output reg [9:0] Sync_q = 10'd0,$/;" p m
Sync_rdy hdl/SCFDE_recv_FrameSync.v /^ output reg Sync_rdy = 1'b0, \/\/判断出峰的标志位，出峰后拉高1c/;" p module:SCFDE_recv_FrameSync
TB_sys sim/TB_sys.v /^module TB_sys ();$/;" m
TDD_SYNC_PERIOD adi_library/util_tdd_sync/util_tdd_sync.v /^ parameter TDD_SYNC_PERIOD = 100000000) ($/;" c module:util_tdd_sync
TIC_FRAME_SYNC hdl/tdma.v /^ parameter TIC_FRAME_SYNC = 42272$/;" c module:tdma
TIC_TO_PS_LEN hdl/tdma.v /^ parameter TIC_TO_PS_LEN = 1200000,$/;" c module:tdma
TDMA_SLOT_LEN hdl/phy_control.v /^ localparam integer TDMA_SLOT_LEN = 'h0000_0008 >> 2;$/;" c module:phy_control
TDMA_TIC_2_PS hdl/phy_control.v /^ localparam integer TDMA_TIC_2_PS = 'h0000_000C >> 2;$/;" c module:phy_control
TIC_FRAME_SYNC hdl/tdma.v /^ parameter TIC_FRAME_SYNC = 42344$/;" c module:tdma
TIMEOUT adi_library/axi_dmac/tb/regmap_tb.v /^ `define TIMEOUT 1000000$/;" d module:dmac_regmap_tb
TIMEOUT adi_library/axi_dmac/tb/reset_manager_tb.v /^ `define TIMEOUT 1000000$/;" d module:dmac_reset_manager_tb
TIMEOUT adi_library/util_pack/tb/cpack_tb.v /^ `define TIMEOUT 1500000$/;" d module:cpack_tb
@@ -2491,8 +2501,11 @@ addr_rd2_02 hdl/Message_Store.v /^ reg [8:0] addr_rd1_01 = 9'd511, addr_rd1_0
addr_rd2_03 hdl/Message_Store.v /^ reg [8:0] addr_rd1_01 = 9'd511, addr_rd1_02 = 9'd511, addr_rd1_03 = 9'd511, addr_rd1_04 = 9'/;" r module:Message_Store
addr_rd2_04 hdl/Message_Store.v /^ reg [8:0] addr_rd1_01 = 9'd511, addr_rd1_02 = 9'd511, addr_rd1_03 = 9'd511, addr_rd1_04 = 9'/;" r module:Message_Store
addr_ready adi_library/axi_dmac/address_generator.v /^ input addr_ready,$/;" p module:dmac_address_generator
addr_scramble hdl/scrambler.v /^ reg [ 2:0] addr_scramble = 0;$/;" r module:scrambler
addr_scramble_d1 hdl/scrambler.v /^ reg [ 2:0] addr_scramble_d1 = 0;$/;" r module:scrambler
addr_scramble_d2 hdl/scrambler.v /^ reg [ 2:0] addr_scramble_d2 = 0;$/;" r module:scrambler
addr_stop hdl/FrameMerge.v /^ output reg [16:0] addr_stop = 17'd0, \/\/给shx，拉高一个clk,与flag_stop对齐，指示/;" p module:FrameMerge
addr_stop hdl/RecvTop.v /^ output [16:0] addr_stop, \/\/给shx，拉高8个clk,与flag_stop对齐，指示/;" p module:RecvTop
addr_stop hdl/RecvTop.v /^ output [16:0] addr_stop, \/\/给shx，拉高8个clk,与flag_stop对齐，/;" p module:RecvTop
addr_stop_0 hdl/FrameMerge.v /^ output [16:0] addr_stop_0, $/;" p module:FrameMerge
addr_tx_test hdl/Transmitter.v /^ reg [12:0] addr_tx_test = 'd0;$/;" r module:Transmitter
addr_valid adi_library/axi_dmac/address_generator.v /^ output reg addr_valid,$/;" p module:dmac_address_generator
@@ -2972,6 +2985,12 @@ bagcnt hdl/FrameMerge.v /^ reg [8:0] bagcnt = 9'd0;$/;" r module:FrameMerge
bagcount hdl/IQmerge.v /^ reg [8:0] bagcount = 9'd0;$/;" r module:IQmerge
base adi_library/util_pack/util_pack_common/pack_ctrl.v /^ localparam base = i*MUX_ORDER;$/;" c block:pack_ctrl.demux_gen_outer
base adi_library/util_pack/util_pack_common/pack_shell.v /^ localparam base = i * w;$/;" c block:pack_shell.gen_pack.gen_output_buffer.gen_out_data
bb_rx_i hdl/system_top.v /^ wire [11:0] bb_rx_i;$/;" n module:system_top
bb_rx_iq_reverse hdl/system_top.v /^ wire bb_rx_iq_reverse;$/;" n module:system_top
bb_rx_q hdl/system_top.v /^ wire [11:0] bb_rx_q;$/;" n module:system_top
bb_tx_i hdl/system_top.v /^ wire [11:0] bb_tx_i;$/;" n module:system_top
bb_tx_iq_reverse hdl/system_top.v /^ wire bb_tx_iq_reverse;$/;" n module:system_top
bb_tx_q hdl/system_top.v /^ wire [11:0] bb_tx_q;$/;" n module:system_top
bb_wave_out_i hdl/Transmitter.v /^ reg [31:0] bb_wave_out_i; \/\/ shape filter result$/;" r module:Transmitter
bb_wave_out_i_interp16 hdl/Transmitter.v /^ wire [31:0] bb_wave_out_i_interp16;$/;" n module:Transmitter
bb_wave_out_i_interp4 hdl/Transmitter.v /^ wire [31:0] bb_wave_out_i_interp4;$/;" n module:Transmitter
@@ -3189,12 +3208,15 @@ clk hdl/add_prefix.v /^ input clk,$/;" p module:add_prefix
clk hdl/data_equalizer.v /^ input clk,$/;" p module:data_equalizer
clk hdl/data_ow.v /^ input clk,$/;" p module:data_ow
clk hdl/enc_control.v /^ input clk,$/;" p module:enc_control
clk hdl/extract_mac_frame.v /^ input clk,$/;" p module:extract_mac_frame
clk hdl/frame_sync.v /^ input clk,$/;" p module:frame_sync
clk hdl/freqestm.v /^ input clk,$/;" p module:freqestm
clk hdl/net_city.v /^ input clk,$/;" p module:net_city
clk hdl/phase_adjust.v /^ input clk,$/;" p module:phase_adjust
clk hdl/phy_control.v /^ input clk, \/\/ can be floating if ASYNC_CLK == 0$/;" p module:phy_control
clk hdl/power_measure.v /^ input clk,$/;" p module:power_measure
clk hdl/scrambler.v /^ input clk,$/;" p module:scrambler
clk hdl/ser2par.v /^ input clk,$/;" p module:ser2par
clk hdl/shift_reg.v /^ input clk,$/;" p module:shift_reg
clk hdl/tdma.v /^ input clk,$/;" p module:tdma
clk hdl/trunc_25to12_2dly.v /^ input clk;$/;" p module:trunc_25to12_2dly
@@ -3204,7 +3226,9 @@ clk sim/tb_Receiver.v /^ reg clk;$/;" r module:tb_Receiver
clk sim/tb_Transmitter.v /^ reg clk = 1;$/;" r module:tb_Transmitter
clk sim/tb_add_prefix.v /^ reg clk = 0;$/;" r module:tb_add_prefix
clk sim/tb_enc_control.v /^ reg clk = 1;$/;" r module:tb_enc_control
clk sim/tb_extract_mac_frame.v /^ reg clk = 0;$/;" r module:tb_extract_mac_frame
clk sim/tb_recv_top.v /^ reg clk = 0;$/;" r module:tb_recv_top
clk sim/tb_scrambler.v /^ reg clk = 0;$/;" r module:tb_scrambler
clk sim/tb_tdma.v /^ reg clk = 1;$/;" r module:tb_tdma
clk sim/tb_width_convert.v /^ reg clk = 1;$/;" r module:tb_width_convert
clk2 adi_library/xilinx/common/ad_mmcm_drp.v /^ input clk2,$/;" p module:ad_mmcm_drp
@@ -3272,7 +3296,6 @@ clk_sel adi_library/common/up_clkgen.v /^ output clk_sel,$/;"
clk_sel adi_library/xilinx/common/ad_mmcm_drp.v /^ input clk_sel,$/;" p module:ad_mmcm_drp
clk_sel adi_library/xilinx/util_clkdiv/util_clkdiv.v /^ input clk_sel,$/;" p module:util_clkdiv
clk_tx sim/tb_Transmitter.v /^ reg clk_tx = 1;$/;" r module:tb_Transmitter
clk_tx sim/tb_tdma.v /^ reg clk_tx = 1;$/;" r module:tb_tdma
clk_tx_data_src hdl/system_top.v /^ wire clk_tx_data_src;$/;" n module:system_top
clk_tx_data_src sim/TB_sys.v /^ wire clk_tx_data_src;$/;" n module:TB_sys
clk_tx_data_src sim/tb_sys_tx_rx_e_d.v /^ wire clk_tx_data_src;$/;" n module:tb_sys_tx_rx_e_d
@@ -3302,12 +3325,13 @@ cmd_ready adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^ inp
cmd_valid adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v /^ output cmd_valid,$/;" p module:axi_spi_engine
cmd_valid adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^ input cmd_valid,$/;" p module:spi_engine_execution
cmd_valid adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v /^ output cmd_valid,$/;" p module:spi_engine_offload
cnt hdl/PAPR.v /^ reg [ 5:0] cnt;$/;" r module:PAPR
cnt hdl/PAPR.v /^ reg [ 7:0] cnt;$/;" r module:PAPR
cnt hdl/TSync_Abs_new16.v /^ output reg [1:0] cnt = 2'd0, \/\/12.5$/;" p module:TSync_Abs_new16
cnt hdl/TSync_Abs_new4.v /^ output reg [1:0] cnt = 2'd0, \/\/12.5$/;" p module:TSync_Abs_new4
cnt hdl/tdma.v /^ reg [23:0] cnt; $/;" r module:tdma
cnt hdl/tdma.v /^ reg [23:0] cnt;$/;" r module:tdma
cnt hdl/width_convert.v /^ reg [$clog2(CNT_MAX) - 1 : 0] cnt;$/;" r module:width_convert
cnt sim/TB_sys.v /^ reg [31:0] cnt;$/;" r module:TB_sys
cnt sim/tb_scrambler.v /^ reg [31:0] cnt = 0;$/;" r module:tb_scrambler
cnt_1024 hdl/TSync_Abs_new16.v /^ reg [9:0] cnt_1024 = 10'd0;$/;" r module:TSync_Abs_new16
cnt_1024 hdl/TSync_Abs_new4.v /^ reg [9:0] cnt_1024 = 10'd0;$/;" r module:TSync_Abs_new4
cnt_10data hdl/data_ow.v /^ reg [3:0] cnt_10data = 1'd0;$/;" r module:data_ow
@@ -3344,10 +3368,12 @@ cnt_add_prefix_in hdl/enc_control.v /^ reg [ 2:0] cnt_add_prefi
cnt_adjust_times hdl/power_measure.v /^ reg [ 7:0] cnt_adjust_times;$/;" r module:power_measure
cnt_agc_send hdl/Transmitter.v /^ reg [15:0] cnt_agc_send; \/\/ agc symbols have been sent$/;" r module:Transmitter
cnt_amp_too_high hdl/power_measure.v /^ reg [ 3:0] cnt_amp_too_high; \/\/ for short cuirt $/;" r module:power_measure
cnt_axis_out hdl/extract_mac_frame.v /^ reg [15:0] cnt_axis_out;$/;" r module:extract_mac_frame
cnt_bag hdl/freqestm.v /^ reg [ 7:0] cnt_bag;$/;" r module:freqestm
cnt_blocks_send hdl/Transmitter.v /^ reg [15:0] cnt_blocks_send; \/\/ blocks have been sent$/;" r module:Transmitter
cnt_chu_send hdl/Transmitter.v /^ reg [15:0] cnt_chu_send;$/;" r module:Transmitter
cnt_chu_seq_sync hdl/RecvTop.v /^ reg [ 7:0] cnt_chu_seq_sync; \/\/ frame sync delay to chu seq sample start pos$/;" r module:RecvTop
cnt_chu_seq_sync_max_vio hdl/RecvTop.v /^ wire [7:0] cnt_chu_seq_sync_max_vio;$/;" n module:RecvTop
cnt_cp hdl/freqestm.v /^ reg [11:0] cnt_cp;$/;" r module:freqestm
cnt_data_in sim/tb_width_convert.v /^ reg [3:0] cnt_data_in;$/;" r module:tb_width_convert
cnt_databag hdl/DAGC_v2.v /^ reg [14:0] cnt_databag = 15'd0;$/;" r module:DAGC_v2
@@ -3363,9 +3389,13 @@ cnt_fifo_out_valid hdl/RecvTop.v /^ reg [ 2:0] cnt_fifo_out_valid;$/;" r mod
cnt_fifo_out_valid_sel hdl/Receiver.v /^ reg [ 2:0] cnt_fifo_out_valid_sel; \/\/ 根据speed mode对应的计数器边界值$/;" r module:Receiver
cnt_fifo_out_valid_sel hdl/RecvTop.v /^ reg [ 2:0] cnt_fifo_out_valid_sel = 1; \/\/ 根据speed mode对应的计数器边界值$/;" r module:RecvTop
cnt_frame hdl/freqestm.v /^ reg [14:0] cnt_frame;$/;" r module:freqestm
cnt_idx hdl/ser2par.v /^ reg [$clog2(PAR_WIDTH):0] cnt_idx;$/;" r module:ser2par
cnt_in hdl/add_prefix.v /^ reg [CNT_WIDTH : 0] cnt_in;$/;" r module:add_prefix
cnt_in hdl/enc_control.v /^ reg [ CNT_IN_WIDTH : 0] cnt_in; \/\/ 多留1bit$/;" r module:enc_control
cnt_in hdl/scrambler.v /^ reg [ 3:0] cnt_in;$/;" r module:scrambler
cnt_in sim/tb_extract_mac_frame.v /^ reg [31:0] cnt_in = 0;$/;" r module:tb_extract_mac_frame
cnt_in sim/tb_width_convert.v /^ reg [5:0] cnt_in;$/;" r module:tb_width_convert
cnt_in_valid sim/tb_extract_mac_frame.v /^ reg cnt_in_valid = 0;$/;" r module:tb_extract_mac_frame
cnt_inter_slot hdl/net_city.v /^ reg [31:0] cnt_inter_slot = 32'd0;$/;" r module:net_city
cnt_interp hdl/Transmitter.v /^ reg [ 3:0] cnt_interp;$/;" r module:Transmitter
cnt_lost hdl/RecvTop.v /^ reg [20:0] cnt_lost;$/;" r module:RecvTop
@@ -3383,9 +3413,12 @@ cnt_pulse_width hdl/ad9361_mgc_pin_ctrl.v /^ reg [3:0] cnt_pulse_width;$/;"
cnt_rd sim/tb_enc_control.v /^ reg [1:0] cnt_rd;$/;" r module:tb_enc_control
cnt_rst hdl/DAGC_v2.v /^ reg [19:0] cnt_rst = 20'd0;$/;" r module:DAGC_v2
cnt_rst hdl/freqestm.v /^ reg [19:0] cnt_rst = 20'd0;$/;" r module:freqestm
cnt_sleep sim/tb_extract_mac_frame.v /^ reg [ 4:0] cnt_sleep = 0;$/;" r module:tb_extract_mac_frame
cnt_start sim/tb_enc_control.v /^ reg [31:0] cnt_start;$/;" r module:tb_enc_control
cnt_startup hdl/Receiver.v /^ reg [ 8:0] cnt_startup;$/;" r module:Receiver
cnt_startup hdl/power_measure.v /^ reg [ 7:0] cnt_startup; \/\/ set rx gain to max each time start posedge comes$/;" r module:power_measure
cnt_startup sim/tb_extract_mac_frame.v /^ reg [ 3:0] cnt_startup = 0;$/;" r module:tb_extract_mac_frame
cnt_startup sim/tb_scrambler.v /^ reg [3:0] cnt_startup = 0;$/;" r module:tb_scrambler
cnt_startup sim/tb_width_convert.v /^ reg [5:0] cnt_startup;$/;" r module:tb_width_convert
cnt_sym_send hdl/Transmitter.v /^ reg [15:0] cnt_sym_send; \/\/ symbols have been sent$/;" r module:Transmitter
cnt_trans_slot hdl/net_city.v /^ reg [31:0] cnt_trans_slot = 32'd0;$/;" r module:net_city
@@ -3497,11 +3530,13 @@ cr_cb_sel adi_library/common/ad_ss_422to444.v /^ reg cr_cb_sel = 'd
cr_cb_sel adi_library/common/ad_ss_444to422.v /^ reg cr_cb_sel = 'd0;$/;" r module:ad_ss_444to422
cr_s adi_library/common/ad_ss_444to422.v /^ wire [ 9:0] cr_s;$/;" n module:ad_ss_444to422
cs adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^ output reg [NUM_OF_CS-1:0] cs,$/;" p module:spi_engine_execution
cs hdl/PAPR.v /^ reg [2:0] cs = 0;$/;" r module:PAPR
cs hdl/Transmitter.v /^ reg [ 3:0] cs;$/;" r module:Transmitter
cs hdl/ad9361_mgc_pin_ctrl.v /^ reg [2:0] cs;$/;" r module:ad9361_mgc_pin_ctrl
cs hdl/add_prefix.v /^ reg [ 2:0] cs = 0;$/;" r module:add_prefix
cs hdl/enc_control.v /^ reg [ 3:0] cs;$/;" r module:enc_control
cs hdl/power_measure.v /^ reg [2:0] cs = S_MEASURE_IDLE;$/;" r module:power_measure
cs hdl/scrambler.v /^ reg [ 1:0] cs = 0;$/;" r module:scrambler
cs_active_s adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^wire cs_active_s = (inst_d1 == CMD_CHIPSELECT) & ~(&cmd_d1[NUM_OF_CS-1:0]);$/;" n module:spi_engine_execution
cs_sleep_counter adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^wire [1:0] cs_sleep_counter = counter[(BIT_COUNTER_WIDTH+2):(BIT_COUNTER_WIDTH+1)];$/;" n module:spi_engine_execution
cs_sleep_counter2 adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^wire [2:0] cs_sleep_counter2 = counter[(BIT_COUNTER_WIDTH+3):(BIT_COUNTER_WIDTH+1)];$/;" n module:spi_engine_execution
@@ -3732,6 +3767,8 @@ dac_xfer_req adi_library/util_dacfifo/util_dacfifo.v /^ reg
dac_xfer_req_d adi_library/util_dacfifo/util_dacfifo.v /^ reg dac_xfer_req_d = 1'b0;$/;" r module:util_dacfifo
dac_xfer_req_m adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v /^ reg [ 2:0] dac_xfer_req_m = 3'b0;$/;" r module:axi_dacfifo_rd
dac_xfer_req_m1 adi_library/util_dacfifo/util_dacfifo.v /^ reg dac_xfer_req_m1 = 1'b0;$/;" r module:util_dacfifo
dagc_data_in_i hdl/RecvTop.v /^ wire [9:0] dagc_data_in_i;$/;" n module:RecvTop
dagc_data_in_q hdl/RecvTop.v /^ wire [9:0] dagc_data_in_q;$/;" n module:RecvTop
dagc_rdy hdl/DAGC_v2.v /^ output reg dagc_rdy,$/;" p module:DAGC_v2
dagc_rdy hdl/RecvTop.v /^ wire dagc_rdy;$/;" n module:RecvTop
dagc_rdy_d0 hdl/DAGC_v2.v /^ reg dagc_rdy_d0;$/;" r module:DAGC_v2
@@ -3824,7 +3861,7 @@ data_in_n adi_library/xilinx/common/ad_serdes_in.v /^ input [(DATA_WIDTH-1):0
data_in_p adi_library/xilinx/common/ad_serdes_in.v /^ input [(DATA_WIDTH-1):0] data_in_p,$/;" p module:ad_serdes_in
data_in_r adi_library/util_gmii_to_rgmii/mdc_mdio.v /^ reg [31:0] data_in_r = 32'h0;$/;" r module:mdc_mdio
data_in_ready hdl/add_prefix.v /^ output reg data_in_ready,$/;" p module:add_prefix
data_in_ready hdl/width_convert.v /^ input wire data_in_ready,$/;" p module:width_convert
data_in_ready hdl/width_convert.v /^ output wire data_in_ready,$/;" p module:width_convert
data_in_ready sim/tb_width_convert.v /^ wire data_in_ready;$/;" n module:tb_width_convert
data_in_seq adi_library/util_cic/cic_comb.v /^reg [DATA_WIDTH-1:0] data_in_seq;$/;" r module:cic_comb
data_in_trigger adi_library/util_extract/util_extract.v /^ input [DATA_WIDTH-1:0] data_in_trigger,$/;" p module:util_extract
@@ -3900,6 +3937,7 @@ data_s6 adi_library/xilinx/common/ad_serdes_out.v /^ input [(DATA_WIDTH-1):0]
data_s7 adi_library/xilinx/common/ad_serdes_in.v /^ output [(DATA_WIDTH-1):0] data_s7, \/\/ 1st bit received$/;" p module:ad_serdes_in
data_s7 adi_library/xilinx/common/ad_serdes_out.v /^ input [(DATA_WIDTH-1):0] data_s7, \/\/ last bit to be transmitted$/;" p module:ad_serdes_out
data_save hdl/freqestm.v /^ output reg data_save,$/;" p module:freqestm
data_scramble_mask hdl/scrambler.v /^ wire [31:0] data_scramble_mask;$/;" n module:scrambler
data_sdi_shift adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^ reg [DATA_WIDTH-1:0] data_sdi_shift;$/;" r block:spi_engine_execution.g_sdi_shift_reg
data_sdo_shift adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^reg [(DATA_WIDTH-1):0] data_sdo_shift = 'h0;$/;" r module:spi_engine_execution
data_shift1_s adi_library/xilinx/common/ad_serdes_in.v /^ wire [(DATA_WIDTH-1):0] data_shift1_s;$/;" n module:ad_serdes_in
@@ -5364,6 +5402,7 @@ ext_data_in adi_library/util_pack/util_pack_common/pack_shell.v /^ wire [
ext_data_out adi_library/util_pack/util_pack_common/pack_shell.v /^ wire [TOTAL_DATA_WIDTH*2-1:0] ext_data_out;$/;" n block:pack_shell.gen_input_buffer
ext_data_shuffled adi_library/util_pack/util_pack_common/pack_shell.v /^ wire [TOTAL_DATA_WIDTH*2-1:0] ext_data_shuffled;$/;" n block:pack_shell.gen_input_buffer
ext_prefix_count adi_library/util_pack/util_pack_common/pack_shell.v /^ wire [(SAMPLE_ADDRESS_WIDTH+1)*(2*NUM_OF_SAMPLES)-1:0] ext_prefix_count;$/;" n block:pack_shell.gen_input_buffer
extract_mac_frame hdl/extract_mac_frame.v /^module extract_mac_frame ($/;" m
failed adi_library/axi_dmac/tb/axi_write_slave.v /^reg failed = 'b0;$/;" r module:axi_write_slave
failed adi_library/axi_dmac/tb/tb_base.v /^ reg failed = 1'b0;$/;" r
failed adi_library/util_pack/tb/tb_base.v /^ reg failed = 1'b0;$/;" r
@@ -5715,6 +5754,7 @@ flag_agcl hdl/RecvTop.v /^ wire flag_agcl;$/;" n module:RecvTop
flag_badframe hdl/RecvTop.v /^ reg flag_badframe = 1'd0;$/;" r module:RecvTop
flag_ber hdl/RecvTop.v /^ reg flag_ber = 1'd0;$/;" r module:RecvTop
flag_bercount hdl/RecvTop.v /^ reg flag_bercount = 1'd0;$/;" r module:RecvTop
flag_cfo_done hdl/RecvTop.v /^ wire flag_cfo_done; \/\/帧同步峰，与频率补偿输出对应$/;" n module:RecvTop
flag_clk16 hdl/TSync_Abs_new16.v /^ output reg [1:0] flag_clk16 = 2'd0, \/\/12.5$/;" p module:TSync_Abs_new16
flag_clk16 hdl/TimeSync_top.v /^ wire [1:0] flag_clk16;$/;" n module:TimeSync_top
flag_clk4 hdl/TSync_Abs_new4.v /^ output reg [1:0] flag_clk4 = 2'd0 \/\/12.5$/;" p module:TSync_Abs_new4
@@ -5746,11 +5786,10 @@ flag_dc hdl/RecvTop.v /^ wire flag_dc;$/;" n module:RecvTop
flag_end hdl/Message_Store.v /^ reg flag_end = 1'd0;$/;" r module:Message_Store
flag_frame_sync hdl/RecvTop.v /^ reg flag_frame_sync; \/\/ active high level$/;" r module:RecvTop
flag_frame_sync hdl/tdma.v /^ input flag_frame_sync,$/;" p module:tdma
flag_frame_sync_m sim/tb_tdma.v /^ wire flag_frame_sync_m;$/;" n module:tb_tdma
flag_frame_sync_s sim/tb_tdma.v /^ reg flag_frame_sync_s = 0;$/;" r module:tb_tdma
flag_framesync hdl/TSync_Abs_new16.v /^ reg flag_framesync = 1'd0;$/;" r module:TSync_Abs_new16
flag_framesync hdl/TSync_Abs_new4.v /^ reg flag_framesync = 1'd0;$/;" r module:TSync_Abs_new4
flag_is_master hdl/tdma.v /^ input flag_is_master, \/\/ TODO: refactor it to parameters$/;" p module:tdma
flag_handshake hdl/extract_mac_frame.v /^ wire flag_handshake;$/;" n module:extract_mac_frame
flag_is_master hdl/tdma.v /^ input flag_is_master,$/;" p module:tdma
flag_is_tx_slot hdl/tdma.v /^ reg flag_is_tx_slot;$/;" r module:tdma
flag_judge1 hdl/CK_PRO.v /^ reg flag_judge1 = 1'd0;$/;" r module:CK_PRO
flag_judge2 hdl/CK_PRO.v /^ reg flag_judge2 = 1'd0;$/;" r module:CK_PRO
@@ -5758,6 +5797,9 @@ flag_judge3 hdl/CK_PRO.v /^ reg flag_judge3 = 1'd0;$/;" r module:CK_PRO
flag_mgc_done hdl/RecvTop.v /^ wire flag_mgc_done; \/\/ level flag$/;" n module:RecvTop
flag_mgc_done hdl/ad9361_mgc_pin_ctrl.v /^ output reg flag_mgc_done = 0 \/\/ active high level signal$/;" p module:ad9361_mgc_pin_ctrl
flag_mgc_done_4x hdl/RecvTop.v /^ wire flag_mgc_done_4x; \/\/ level flag$/;" n module:RecvTop
flag_mgc_done_pulse hdl/RecvTop.v /^ output wire flag_mgc_done_pulse, \/\/ active high pulse signal$/;" p module:RecvTop
flag_mgc_done_pulse hdl/ad9361_mgc_pin_ctrl.v /^ output wire flag_mgc_done_pulse, \/\/ active high pulse signal$/;" p module:ad9361_mgc_pin_ctrl
flag_mgc_done_pulse hdl/system_top.v /^ wire flag_mgc_done_pulse;$/;" n module:system_top
flag_notbyte hdl/FrameMerge.v /^ output reg flag_notbyte = 1'd0,$/;" p module:FrameMerge
flag_num16 hdl/TSync_Abs_new16.v /^ output reg [1:0] flag_num16 = 2'd0$/;" p module:TSync_Abs_new16
flag_num16 hdl/TimeSync_top.v /^ wire [1:0] flag_num16;$/;" n module:TimeSync_top
@@ -5788,7 +5830,7 @@ flag_save hdl/TSync_Abs_new16.v /^ reg flag_save = 0;$/;" r module:TSync_Abs_new
flag_small hdl/RecvTop.v /^ wire flag_small;$/;" n module:RecvTop
flag_state_mgc hdl/RecvTop.v /^ wire flag_state_mgc;$/;" n module:RecvTop
flag_stop hdl/FrameMerge.v /^ output reg flag_stop = 1'd0, \/\/给shx，拉高一个clk表示当前时帧有效数据接/;" p module:FrameMerge
flag_stop hdl/RecvTop.v /^ output flag_stop, \/\/给shx，拉高8个clk表示当前时帧有效数/;" p module:RecvTop
flag_stop hdl/RecvTop.v /^ output flag_stop, \/\/给shx，拉高8个clk表示当前时帧有/;" p module:RecvTop
flag_stop_0 hdl/FrameMerge.v /^ output flag_stop_0, \/\/给shx，拉高1个clk表示当前时帧有效数据接收完毕$/;" p module:FrameMerge
flag_switch_MS hdl/Message_Store.v /^ reg flag_switch_MS = 1'd0;$/;" r module:Message_Store
flag_switch_in hdl/LDPC_TopManage_2.v /^ reg [0:0] flag_switch_in = 1'b1;$/;" r module:LDPC_TopManage_2
@@ -5854,7 +5896,6 @@ frame_sync hdl/frame_sync.v /^module frame_sync #($/;" m
frame_sync hdl/net_city.v /^ input frame_sync,$/;" p module:net_city
frame_sync_4x hdl/Receiver.v /^ wire frame_sync_4x;$/;" n module:Receiver
frame_sync_4x hdl/RecvTop.v /^ wire frame_sync_4x;$/;" n module:RecvTop
frame_sync_d1 hdl/PAPR.v /^ reg frame_sync_d1;$/;" r module:PAPR
frame_sync_pulse hdl/PAPR.v /^ output reg frame_sync_pulse$/;" p module:PAPR
frame_sync_pulse hdl/Receiver.v /^ output frame_sync_pulse \/\/ in domain clk$/;" p module:Receiver
frame_sync_pulse hdl/RecvTop.v /^ output wire frame_sync_pulse, \/\/ in domain clk$/;" p module:RecvTop
@@ -5889,7 +5930,6 @@ framesync_d3 hdl/DAGC_v2.v /^ reg framesync_d3;$/;" r module:DAGC_v2
framesync_d3 hdl/freqestm.v /^ wire framesync_d3;$/;" n module:freqestm
framesync_d4 hdl/DAGC_v2.v /^ reg framesync_d4;$/;" r module:DAGC_v2
framesync_d5 hdl/DAGC_v2.v /^ reg framesync_d5;$/;" r module:DAGC_v2
framesync_delay hdl/RecvTop.v /^ wire framesync_delay; \/\/帧同步峰，与频率补偿输出对应$/;" n module:RecvTop
framesync_delay hdl/freqestm.v /^ output reg framesync_delay,$/;" p module:freqestm
framesync_delay_d1 hdl/freqestm.v /^ reg framesync_delay_d1 = 1'b0;$/;" r module:freqestm
framesync_delay_d2 hdl/freqestm.v /^ reg framesync_delay_d2 = 1'b0;$/;" r module:freqestm
@@ -6561,8 +6601,6 @@ intr sim/tb_Transmitter.v /^ reg intr = 0;$/;" r module:tb_Transmitter
intr sim/tb_enc_control.v /^ reg intr = 0;$/;" r module:tb_enc_control
intr_2ps hdl/system_top.v /^ wire intr_2ps;$/;" n module:system_top
intr_2ps hdl/tdma.v /^ output intr_2ps,$/;" p module:tdma
intr_2ps_m sim/tb_tdma.v /^ wire intr_2ps_m;$/;" n module:tb_tdma
intr_2ps_s sim/tb_tdma.v /^ wire intr_2ps_s;$/;" n module:tb_tdma
intr_2ps_vio hdl/system_top.v /^ wire intr_2ps_vio;$/;" n module:system_top
intr_2ps_vio_d1 hdl/system_top.v /^ reg intr_2ps_vio_d1;$/;" r module:system_top
intr_2ps_vio_pos hdl/system_top.v /^ wire intr_2ps_vio_pos;$/;" n module:system_top
@@ -6618,11 +6656,15 @@ last_non_eot adi_library/axi_dmac/data_mover.v /^reg last_non_eot = 1'b0;$/;" r
last_req adi_library/axi_dmac/2d_transfer.v /^reg [3:0] last_req = 'h00;$/;" r module:dmac_2d_transfer
last_sdi_bit adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^wire last_sdi_bit;$/;" n module:spi_engine_execution
last_transfer adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^reg last_transfer;$/;" r module:spi_engine_execution
ldpc_dec_out_data hdl/extract_mac_frame.v /^ input ldpc_dec_out_data,$/;" p module:extract_mac_frame
ldpc_dec_out_start hdl/extract_mac_frame.v /^ input ldpc_dec_out_start,$/;" p module:extract_mac_frame
ldpc_dec_out_valid hdl/extract_mac_frame.v /^ input ldpc_dec_out_valid,$/;" p module:extract_mac_frame
ldpc_dout hdl/CCSDS_LDPC_DEC_K1024_R12.v /^ wire [ 0:0] ldpc_dout;$/;" n module:CCSDS_LDPC_DEC_K1024_R12
ldpc_dout hdl/LDPC_DEC_PRO.v /^ output reg ldpc_dout = 1'd0 \/\/译码输出信号$/;" p module:LDPC_DEC_PRO
ldpc_dout hdl/enc_control.v /^ wire ldpc_dout;$/;" n module:enc_control
ldpc_dout_OUT hdl/LDPC_DEC_PRO.v /^ wire ldpc_dout_OUT;$/;" n module:LDPC_DEC_PRO
ldpc_dout_OUT hdl/OUT_PRO.v /^ output reg [0:0] ldpc_dout_OUT=1'd0 $/;" p module:OUT_PRO
ldpc_in sim/tb_extract_mac_frame.v /^ reg ldpc_in;$/;" r module:tb_extract_mac_frame
ldpc_in_start hdl/enc_control.v /^ reg ldpc_in_start;$/;" r module:enc_control
ldpc_in_valid hdl/enc_control.v /^ reg ldpc_in_valid;$/;" r module:enc_control
ldpc_out_start hdl/enc_control.v /^ wire ldpc_out_start;$/;" n module:enc_control
@@ -6817,6 +6859,13 @@ m_axis_level adi_library/util_axis_fifo/address_gray.v /^ output reg [ADDRESS_W
m_axis_level adi_library/util_axis_fifo/address_gray_pipelined.v /^ output reg [ADDRESS_WIDTH:0] m_axis_level,$/;" p module:fifo_address_gray_pipelined
m_axis_level adi_library/util_axis_fifo/address_sync.v /^ output [ADDRESS_WIDTH:0] m_axis_level,$/;" p module:fifo_address_sync
m_axis_level adi_library/util_axis_fifo/util_axis_fifo.v /^ output [ADDRESS_WIDTH:0] m_axis_level,$/;" p module:util_axis_fifo
m_axis_mac_frame_tdata hdl/extract_mac_frame.v /^ output wire [31:0] m_axis_mac_frame_tdata,$/;" p module:extract_mac_frame
m_axis_mac_frame_tdata sim/tb_extract_mac_frame.v /^ wire [31:0] m_axis_mac_frame_tdata;$/;" n module:tb_extract_mac_frame
m_axis_mac_frame_tlast hdl/extract_mac_frame.v /^ output reg m_axis_mac_frame_tlast$/;" p module:extract_mac_frame
m_axis_mac_frame_tlast sim/tb_extract_mac_frame.v /^ wire m_axis_mac_frame_tlast;$/;" n module:tb_extract_mac_frame
m_axis_mac_frame_tready hdl/extract_mac_frame.v /^ input m_axis_mac_frame_tready,$/;" p module:extract_mac_frame
m_axis_mac_frame_tvalid hdl/extract_mac_frame.v /^ output wire m_axis_mac_frame_tvalid,$/;" p module:extract_mac_frame
m_axis_mac_frame_tvalid sim/tb_extract_mac_frame.v /^ wire m_axis_mac_frame_tvalid;$/;" n module:tb_extract_mac_frame
m_axis_raddr adi_library/util_axis_fifo/address_gray_pipelined.v /^ output [ADDRESS_WIDTH-1:0] m_axis_raddr,$/;" p module:fifo_address_gray_pipelined
m_axis_raddr adi_library/util_axis_fifo/address_sync.v /^ output reg [ADDRESS_WIDTH-1:0] m_axis_raddr,$/;" p module:fifo_address_sync
m_axis_raddr adi_library/util_axis_fifo/util_axis_fifo.v /^ reg m_axis_raddr = 1'b0;$/;" r module:util_axis_fifo
@@ -6833,6 +6882,13 @@ m_axis_ready adi_library/util_axis_fifo/address_gray_pipelined.v /^ input m_axi
m_axis_ready adi_library/util_axis_fifo/address_sync.v /^ input m_axis_ready,$/;" p module:fifo_address_sync
m_axis_ready adi_library/util_axis_fifo/util_axis_fifo.v /^ input m_axis_ready,$/;" p module:util_axis_fifo
m_axis_strb adi_library/axi_dmac/axi_dmac.v /^ output [DMA_DATA_WIDTH_DEST\/8-1:0] m_axis_strb,$/;" p module:axi_dmac
m_axis_tdata hdl/scrambler.v /^ output reg [31:0] m_axis_tdata,$/;" p module:scrambler
m_axis_tdata sim/tb_scrambler.v /^ wire [31:0] m_axis_tdata;$/;" n module:tb_scrambler
m_axis_tlast hdl/scrambler.v /^ output reg m_axis_tlast$/;" p module:scrambler
m_axis_tlast sim/tb_scrambler.v /^ wire m_axis_tlast;$/;" n module:tb_scrambler
m_axis_tready hdl/scrambler.v /^ input m_axis_tready,$/;" p module:scrambler
m_axis_tvalid hdl/scrambler.v /^ output reg m_axis_tvalid,$/;" p module:scrambler
m_axis_tvalid sim/tb_scrambler.v /^ wire m_axis_tvalid;$/;" n module:tb_scrambler
m_axis_user adi_library/axi_dmac/axi_dmac.v /^ output [0:0] m_axis_user,$/;" p module:axi_dmac
m_axis_valid adi_library/axi_dmac/axi_dmac.v /^ output m_axis_valid,$/;" p module:axi_dmac
m_axis_valid adi_library/axi_dmac/axi_dmac_transfer.v /^ output m_axis_valid,$/;" p module:axi_dmac_transfer
@@ -6966,7 +7022,6 @@ mag_valid hdl/MagnitudeEstimator.v /^ (* max_fanout=128 *) output reg
mag_valid hdl/PAPR.v /^ input mag_valid,$/;" p module:PAPR
mag_valid hdl/Receiver.v /^ wire mag_valid;$/;" n module:Receiver
mag_valid hdl/RecvTop.v /^ wire mag_valid;$/;" n module:RecvTop
mag_valid_d1 hdl/PAPR.v /^ reg mag_valid_d1;$/;" r module:PAPR
mask adi_library/axi_dmac/axi_dmac_resize_src.v /^ reg [RATIO-1:0] mask = 'h1;$/;" r module:axi_dmac_resize_src
mask adi_library/util_cic/cic_comb.v /^wire [DATA_WIDTH-1:0] mask;$/;" n module:cic_comb
mask adi_library/util_cic/cic_int.v /^wire [DATA_WIDTH-1:0] mask;$/;" n module:cic_int
@@ -7250,11 +7305,13 @@ node_id hdl/system_top.v /^ wire [ 7:0] node_id;$/;" n module:system_top
noisei hdl/Noise_Estimate.v /^ reg [9:0] noisei = 10'd0;$/;" r module:Noise_Estimate
noiseq hdl/Noise_Estimate.v /^ reg [9:0] noiseq = 10'd0;$/;" r module:Noise_Estimate
noiseqh hdl/Noise_Estimate.v /^ reg [9:0] noiseqh = 10'd0;$/;" r module:Noise_Estimate
ns hdl/PAPR.v /^ reg [2:0] ns = 0;$/;" r module:PAPR
ns hdl/Transmitter.v /^ reg [ 3:0] ns;$/;" r module:Transmitter
ns hdl/ad9361_mgc_pin_ctrl.v /^ reg [2:0] ns;$/;" r module:ad9361_mgc_pin_ctrl
ns hdl/add_prefix.v /^ reg [ 2:0] ns = 0;$/;" r module:add_prefix
ns hdl/enc_control.v /^ reg [ 3:0] ns;$/;" r module:enc_control
ns hdl/power_measure.v /^ reg [2:0] ns = S_MEASURE_IDLE;$/;" r module:power_measure
ns hdl/scrambler.v /^ reg [ 1:0] ns = 0;$/;" r module:scrambler
ntx_rx adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^wire ntx_rx = counter[0];$/;" n module:spi_engine_execution
num_beats adi_library/axi_dmac/axi_dmac_resize_src.v /^ reg [RATIO_WIDTH-1:0] num_beats = {RATIO_WIDTH{1'b1}};$/;" r module:axi_dmac_resize_src
nx_completion_req_valid adi_library/axi_dmac/request_generator.v /^reg nx_completion_req_valid;$/;" r module:dmac_request_generator
@@ -7353,6 +7410,10 @@ packed_fifo_wr_overflow adi_library/util_pack/util_cpack2/util_cpack2.v /^ inpu
packed_fifo_wr_overflow adi_library/util_pack/util_cpack2/util_cpack2_impl.v /^ input packed_fifo_wr_overflow,$/;" p module:util_cpack2_impl
packed_fifo_wr_sync adi_library/util_pack/util_cpack2/util_cpack2.v /^ output packed_fifo_wr_sync,$/;" p module:util_cpack2
packed_fifo_wr_sync adi_library/util_pack/util_cpack2/util_cpack2_impl.v /^ output reg packed_fifo_wr_sync = 1'b1,$/;" p module:util_cpack2_impl
par hdl/extract_mac_frame.v /^ wire [31:0] par;$/;" n module:extract_mac_frame
par hdl/ser2par.v /^ output reg [PAR_WIDTH -1:0] par,$/;" p module:ser2par
par_valid hdl/extract_mac_frame.v /^ wire par_valid;$/;" n module:extract_mac_frame
par_valid hdl/ser2par.v /^ output reg par_valid$/;" p module:ser2par
partial_burst adi_library/axi_dmac/axi_dmac_resize_src.v /^ reg partial_burst = 1'b0;$/;" r module:axi_dmac_resize_src
pending_burst adi_library/axi_dmac/data_mover.v /^reg pending_burst = 1'b0;$/;" r module:dmac_data_mover
pending_events adi_library/util_cdc/sync_event.v /^wire [NUM_OF_EVENTS-1:0] pending_events = in_event_sticky | in_event;$/;" n module:sync_event
@@ -7379,12 +7440,15 @@ phy_cr_reg hdl/phy_control.v /^ reg [31:0] phy_cr_reg = 32'h0;$/;" r module:p
phy_rst hdl/phy_control.v /^ output wire phy_rst,$/;" p module:phy_control
phy_rst hdl/system_top.v /^ wire phy_rst;$/;" n module:system_top
phy_rst sim/tb_sys_tx_rx_e_d.v /^ wire phy_rst;$/;" n module:tb_sys_tx_rx_e_d
phy_rst_ps hdl/system_top.v /^ wire phy_rst_ps;$/;" n module:system_top
phy_rst_ps sim/tb_sys_tx_rx_e_d.v /^ wire phy_rst_ps;$/;" n module:tb_sys_tx_rx_e_d
phy_rst_vio hdl/system_top.v /^ wire phy_rst_vio;$/;" n module:system_top
phy_rst_vio sim/tb_sys_tx_rx_e_d.v /^ wire phy_rst_vio;$/;" n module:tb_sys_tx_rx_e_d
phy_rx_iq_reverse hdl/phy_control.v /^ output wire phy_rx_iq_reverse,$/;" p module:phy_control
phy_rx_iq_reverse hdl/system_top.v /^ wire phy_rx_iq_reverse;$/;" n module:system_top
phy_sr_reg hdl/phy_control.v /^ reg [31:0] phy_sr_reg = 32'h0;$/;" r module:phy_control
phy_tx_test_flag hdl/phy_control.v /^ output wire phy_tx_test_flag$/;" p module:phy_control
phy_tx_iq_reverse hdl/phy_control.v /^ output wire phy_tx_iq_reverse,$/;" p module:phy_control
phy_tx_iq_reverse hdl/system_top.v /^ wire phy_tx_iq_reverse;$/;" n module:system_top
phy_tx_test_flag hdl/phy_control.v /^ output wire phy_tx_test_flag,$/;" p module:phy_control
phy_tx_test_flag hdl/system_top.v /^ wire phy_tx_test_flag;$/;" n module:system_top
phy_tx_test_flag sim/tb_sys_tx_rx_e_d.v /^ wire phy_tx_test_flag;$/;" n module:tb_sys_tx_rx_e_d
phy_tx_test_flag_vio hdl/system_top.v /^ wire phy_tx_test_flag_vio;$/;" n module:system_top
@@ -7545,7 +7609,7 @@ reb adi_library/common/ad_mem_asym.v /^ input reb,$
recvNetData hdl/FrameMerge.v /^ output reg [63:0] recvNetData,$/;" p module:FrameMerge
recvNetData hdl/RecvTop.v /^ output [63:0] recvNetData,$/;" p module:RecvTop
recvNetDataNd hdl/FrameMerge.v /^ output reg recvNetDataNd$/;" p module:FrameMerge
recvNetDataNd hdl/RecvTop.v /^ output recvNetDataNd$/;" p module:RecvTop
recvNetDataNd hdl/RecvTop.v /^ output recvNetDataNd,$/;" p module:RecvTop
recv_addr_new_0 hdl/FrameMerge.v /^ input [13:0] recv_addr_new_0,$/;" p module:FrameMerge
recv_addr_new_1 hdl/FrameMerge.v /^ input [13:0] recv_addr_new_1,$/;" p module:FrameMerge
recv_addr_new_2 hdl/FrameMerge.v /^ input [13:0] recv_addr_new_2,$/;" p module:FrameMerge
@@ -7556,8 +7620,6 @@ recv_data_new_1 hdl/FrameMerge.v /^ output [7:0] recv_data_new_1,$/;" p module
recv_data_new_2 hdl/FrameMerge.v /^ output [7:0] recv_data_new_2,$/;" p module:FrameMerge
recv_data_new_3 hdl/FrameMerge.v /^ output [7:0] recv_data_new_3,$/;" p module:FrameMerge
recv_id hdl/net_city.v /^ output reg [07:0] recv_id = 8'd0,$/;" p module:net_city
recv_net_data hdl/net_city.v /^ input [63:0] recv_net_data,$/;" p module:net_city
recv_net_data_nd hdl/net_city.v /^ input recv_net_data_nd,$/;" p module:net_city
recv_video_id01 hdl/net_city.v /^ reg [07:0] recv_video_id01 = 8'd0;$/;" r module:net_city
recv_video_id02 hdl/net_city.v /^ reg [07:0] recv_video_id02 = 8'd0;$/;" r module:net_city
recv_video_id03 hdl/net_city.v /^ reg [07:0] recv_video_id03 = 8'd0;$/;" r module:net_city
@@ -7960,11 +8022,14 @@ rst hdl/ad9361_mgc_pin_ctrl.v /^ input rst,$/;" p module:ad9361_
rst hdl/data_equalizer.v /^ input rst,$/;" p module:data_equalizer
rst hdl/data_ow.v /^ input rst,$/;" p module:data_ow
rst hdl/enc_control.v /^ input rst,$/;" p module:enc_control
rst hdl/extract_mac_frame.v /^ input rst,$/;" p module:extract_mac_frame
rst hdl/frame_sync.v /^ input rst,$/;" p module:frame_sync
rst hdl/freqestm.v /^ input rst,$/;" p module:freqestm
rst hdl/net_city.v /^ wire rst;$/;" n module:net_city
rst hdl/phase_adjust.v /^ input rst,$/;" p module:phase_adjust
rst hdl/power_measure.v /^ input rst,$/;" p module:power_measure
rst hdl/scrambler.v /^ wire rst;$/;" n module:scrambler
rst hdl/ser2par.v /^ input rst,$/;" p module:ser2par
rst hdl/shift_reg.v /^ (* max_fanout = 256 *) input rst,$/;" p module:shift_reg
rst hdl/tdma.v /^ input rst,$/;" p module:tdma
rst hdl/width_convert.v /^ input rst,$/;" p module:width_convert
@@ -7972,7 +8037,9 @@ rst sim/tb_Receiver.v /^ reg rst;$/;" r module:tb_Receiver
rst sim/tb_Transmitter.v /^ reg rst = 1;$/;" r module:tb_Transmitter
rst sim/tb_add_prefix.v /^ reg rst = 0;$/;" r module:tb_add_prefix
rst sim/tb_enc_control.v /^ reg rst = 1;$/;" r module:tb_enc_control
rst sim/tb_extract_mac_frame.v /^ reg rst;$/;" r module:tb_extract_mac_frame
rst sim/tb_recv_top.v /^ reg rst = 1;$/;" r module:tb_recv_top
rst sim/tb_scrambler.v /^ reg rst;$/;" r module:tb_scrambler
rst sim/tb_tdma.v /^ reg rst = 1;$/;" r module:tb_tdma
rst sim/tb_width_convert.v /^ reg rst = 1;$/;" r module:tb_width_convert
rst2 hdl/FrameMerge.v /^ input rst2,$/;" p module:FrameMerge
@@ -8001,6 +8068,7 @@ rst_freq hdl/freqestm.v /^ output reg rst_freq$/;" p module:freqestm
rst_initial hdl/net_city.v /^ input rst_initial,$/;" p module:net_city
rst_manual hdl/net_city.v /^ input rst_manual, \/\/manual$/;" p module:net_city
rst_manual hdl/system_top.v /^ wire rst_manual;$/;" n module:system_top
rst_n hdl/scrambler.v /^ input rst_n,$/;" p module:scrambler
rst_ready hdl/SCFDE_recv_FrameSync.v /^ input rst_ready,$/;" p module:SCFDE_recv_FrameSync
rst_sync adi_library/common/ad_rst.v /^ reg rst_sync = 1'd1;$/;" r module:ad_rst
rst_sync_d adi_library/common/ad_rst.v /^ reg rst_sync_d = 1'd1;$/;" r module:ad_rst
@@ -8141,6 +8209,14 @@ rx_data_q hdl/ad9361_dp_fdd_1r1t.v /^ output [11:0] rx_data_q,$/;" p module:a
rx_data_q hdl/ad9361_mgc_pin_ctrl.v /^ input [11:0] rx_data_q,$/;" p module:ad9361_mgc_pin_ctrl
rx_data_s adi_library/common/ad_xcvr_rx_if.v /^ wire [OCTETS_PER_BEAT*DW-1:0] rx_data_s;$/;" n module:ad_xcvr_rx_if
rx_data_s adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ wire [31:0] rx_data_s;$/;" n module:axi_xcvrlb_1
rx_data_src_fifo_tdata hdl/RecvTop.v /^ output wire [31:0] rx_data_src_fifo_tdata,$/;" p module:RecvTop
rx_data_src_fifo_tdata hdl/system_top.v /^ wire [31:0] rx_data_src_fifo_tdata;$/;" n module:system_top
rx_data_src_fifo_tlast hdl/RecvTop.v /^ output wire rx_data_src_fifo_tlast,$/;" p module:RecvTop
rx_data_src_fifo_tlast hdl/system_top.v /^ wire rx_data_src_fifo_tlast;$/;" n module:system_top
rx_data_src_fifo_tready hdl/RecvTop.v /^ input wire rx_data_src_fifo_tready,$/;" p module:RecvTop
rx_data_src_fifo_tready hdl/system_top.v /^ wire rx_data_src_fifo_tready;$/;" n module:system_top
rx_data_src_fifo_tvalid hdl/RecvTop.v /^ output wire rx_data_src_fifo_tvalid$/;" p module:RecvTop
rx_data_src_fifo_tvalid hdl/system_top.v /^ wire rx_data_src_fifo_tvalid;$/;" n module:system_top
rx_disperr adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ output [ 3:0] rx_disperr,$/;" p module:util_adxcvr_xch
rx_disperr_0 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_disperr_0,$/;" p module:util_adxcvr
rx_disperr_1 adi_library/xilinx/util_adxcvr/util_adxcvr.v /^ output [ 3:0] rx_disperr_1,$/;" p module:util_adxcvr
@@ -8221,8 +8297,9 @@ rx_rate_m2 adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ reg [ 2:0]
rx_reset_d1 adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ reg rx_reset_d1;$/;" r module:util_gmii_to_rgmii
rx_rst hdl/net_city.v /^ output reg rx_rst,$/;" p module:net_city
rx_rst hdl/system_top.v /^ wire rx_rst;$/;" n module:system_top
rx_rst hdl/tdma.v /^ (* KEEP = "TRUE" *) output rx_rst$/;" p module:tdma
rx_rst hdl/tdma.v /^ output reg rx_rst$/;" p module:tdma
rx_rst_done_s adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ wire rx_rst_done_s;$/;" n module:util_adxcvr_xch
rx_rst_vio hdl/system_top.v /^ wire rx_rst_vio;$/;" n module:system_top
rx_sof adi_library/common/ad_xcvr_rx_if.v /^ output reg rx_sof,$/;" p module:ad_xcvr_rx_if
rx_status_s adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v /^ wire rx_status_s;$/;" n module:axi_xcvrlb_1
rx_sys_clk_sel_s adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ wire [ 1:0] rx_sys_clk_sel_s;$/;" n module:util_adxcvr_xch
@@ -8523,6 +8600,7 @@ s_axis_last adi_library/axi_dmac/request_arb.v /^ input
s_axis_last adi_library/axi_dmac/src_axi_stream.v /^ input s_axis_last,$/;" p module:dmac_src_axi_stream
s_axis_raddr adi_library/util_axis_fifo/util_axis_fifo.v /^ wire s_axis_raddr;$/;" n module:util_axis_fifo
s_axis_raddr_gray adi_library/util_axis_fifo/address_gray.v /^wire [ADDRESS_WIDTH:0] s_axis_raddr_gray;$/;" n module:fifo_address_gray
s_axis_rd_data_count hdl/scrambler.v /^ input [31:0] s_axis_rd_data_count,$/;" p module:scrambler
s_axis_ready adi_library/axi_dmac/axi_dmac.v /^ output s_axis_ready,$/;" p module:axi_dmac
s_axis_ready adi_library/axi_dmac/axi_dmac_transfer.v /^ output s_axis_ready,$/;" p module:axi_dmac_transfer
s_axis_ready adi_library/axi_dmac/request_arb.v /^ output s_axis_ready,$/;" p module:dmac_request_arb
@@ -8541,6 +8619,18 @@ s_axis_room adi_library/util_axis_fifo/address_gray_pipelined.v /^ output reg [
s_axis_room adi_library/util_axis_fifo/address_sync.v /^ output [ADDRESS_WIDTH:0] s_axis_room$/;" p module:fifo_address_sync
s_axis_room adi_library/util_axis_fifo/util_axis_fifo.v /^ output [ADDRESS_WIDTH:0] s_axis_room$/;" p module:util_axis_fifo
s_axis_strb adi_library/axi_dmac/axi_dmac.v /^ input [DMA_DATA_WIDTH_SRC\/8-1:0] s_axis_strb,$/;" p module:axi_dmac
s_axis_tdata hdl/scrambler.v /^ input [31:0] s_axis_tdata,$/;" p module:scrambler
s_axis_tdata sim/tb_scrambler.v /^ reg [31:0] s_axis_tdata;$/;" r module:tb_scrambler
s_axis_tdata_d1 hdl/scrambler.v /^ reg [31:0] s_axis_tdata_d1;$/;" r module:scrambler
s_axis_tdata_d2 hdl/scrambler.v /^ reg [31:0] s_axis_tdata_d2;$/;" r module:scrambler
s_axis_tlast hdl/scrambler.v /^ input s_axis_tlast,$/;" p module:scrambler
s_axis_tlast sim/tb_scrambler.v /^ reg s_axis_tlast;$/;" r module:tb_scrambler
s_axis_tlast_d1 hdl/scrambler.v /^ reg s_axis_tlast_d1;$/;" r module:scrambler
s_axis_tready hdl/scrambler.v /^ output reg s_axis_tready,$/;" p module:scrambler
s_axis_tready sim/tb_scrambler.v /^ wire s_axis_tready;$/;" n module:tb_scrambler
s_axis_tready_d1 hdl/scrambler.v /^ reg s_axis_tready_d1;$/;" r module:scrambler
s_axis_tvalid hdl/scrambler.v /^ input s_axis_tvalid,$/;" p module:scrambler
s_axis_tvalid sim/tb_scrambler.v /^ reg s_axis_tvalid;$/;" r module:tb_scrambler
s_axis_user adi_library/axi_dmac/axi_dmac.v /^ input [0:0] s_axis_user,$/;" p module:axi_dmac
s_axis_user adi_library/axi_dmac/axi_dmac_transfer.v /^ input [0:0] s_axis_user,$/;" p module:axi_dmac_transfer
s_axis_user adi_library/axi_dmac/request_arb.v /^ input [0:0] s_axis_user,$/;" p module:dmac_request_arb
@@ -8587,6 +8677,7 @@ samples_enable adi_library/util_pack/util_pack_common/pack_shell.v /^ wire
scale adi_library/common/ad_dds_1.v /^ input [ 15:0] scale,$/;" p module:ad_dds_1
sclk adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^ output reg sclk,$/;" p module:spi_engine_execution
sclk_int adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^reg sclk_int = 1'b0;$/;" r module:spi_engine_execution
scrambler hdl/scrambler.v /^module scrambler #($/;" m
scramblestart hdl/FrameMerge.v /^ wire scramblestart;$/;" n module:FrameMerge
sdi adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^ input [NUM_OF_SDI-1:0] sdi,$/;" p module:spi_engine_execution
sdi_counter adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^reg [7:0] sdi_counter = 8'b0;$/;" r module:spi_engine_execution
@@ -8634,6 +8725,11 @@ send_data_ready hdl/Transmitter.v /^ input wire send_data_ready,$/;"
send_over hdl/Transmitter.v /^ output reg send_over,$/;" p module:Transmitter
send_start hdl/Transmitter.v /^ input wire send_start,$/;" p module:Transmitter
send_start sim/tb_sys_tx_rx_e_d.v /^ reg send_start = 0;$/;" r module:tb_sys_tx_rx_e_d
ser hdl/extract_mac_frame.v /^ wire ser;$/;" n module:extract_mac_frame
ser hdl/ser2par.v /^ input wire ser,$/;" p module:ser2par
ser2par hdl/ser2par.v /^module ser2par #($/;" m
ser_valid hdl/extract_mac_frame.v /^ wire ser_valid;$/;" n module:extract_mac_frame
ser_valid hdl/ser2par.v /^ input wire ser_valid,$/;" p module:ser2par
serdes_shift1_s adi_library/xilinx/common/ad_serdes_out.v /^ wire [(DATA_WIDTH-1):0] serdes_shift1_s;$/;" n module:ad_serdes_out
serdes_shift2_s adi_library/xilinx/common/ad_serdes_out.v /^ wire [(DATA_WIDTH-1):0] serdes_shift2_s;$/;" n module:ad_serdes_out
set_reset_reg_value adi_library/axi_dmac/tb/regmap_tb.v /^ task set_reset_reg_value;$/;" t module:dmac_regmap_tb
@@ -8688,6 +8784,7 @@ sine_int adi_library/common/ad_dds_sine.v /^ reg [15:0]
sine_s adi_library/common/ad_dds_1.v /^ wire [ DDS_D_DW-1:0] sine_s;$/;" n module:ad_dds_1
size adi_library/axi_dmac/address_generator.v /^ output [ 2:0] size,$/;" p module:dmac_address_generator
size adi_library/axi_dmac/tb/axi_slave.v /^ input [2:0] size,$/;" p module:axi_slave
sleep sim/tb_extract_mac_frame.v /^ reg sleep = 0;$/;" r module:tb_extract_mac_frame
sleep_counter adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^wire [7:0] sleep_counter = counter[(BIT_COUNTER_WIDTH+8):(BIT_COUNTER_WIDTH+1)];$/;" n module:spi_engine_execution
sleep_counter_compare adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^wire sleep_counter_compare;$/;" n module:spi_engine_execution
sm2tc adi_library/common/up_adc_channel.v /^ function [15:0] sm2tc;$/;" f module:up_adc_channel
@@ -8986,8 +9083,10 @@ tb_Receiver sim/tb_Receiver.v /^module tb_Receiver ();$/;" m
tb_Transmitter sim/tb_Transmitter.v /^module tb_Transmitter ();$/;" m
tb_add_prefix sim/tb_add_prefix.v /^module tb_add_prefix ();$/;" m
tb_enc_control sim/tb_enc_control.v /^module tb_enc_control ();$/;" m
tb_extract_mac_frame sim/tb_extract_mac_frame.v /^module tb_extract_mac_frame ();$/;" m
tb_led sim/tb_led.v /^module tb_led($/;" m
tb_recv_top sim/tb_recv_top.v /^module tb_recv_top ();$/;" m
tb_scrambler sim/tb_scrambler.v /^module tb_scrambler ();$/;" m
tb_sys_tx_rx_e_d sim/tb_sys_tx_rx_e_d.v /^module tb_sys_tx_rx_e_d ();$/;" m
tb_tdma sim/tb_tdma.v /^module tb_tdma ();$/;" m
tb_tx_with_enc sim/tb_tx_with_enc.v /^module tb_tx_with_enc ();$/;" m
@@ -9098,6 +9197,16 @@ tdd_vco_tx_on_2 adi_library/common/ad_tdd_control.v /^ input [23:0]
tdd_vco_tx_on_2 adi_library/common/up_tdd_cntrl.v /^ output [23:0] tdd_vco_tx_on_2,$/;" p module:up_tdd_cntrl
tdd_vco_tx_on_2_s adi_library/common/ad_tdd_control.v /^ wire [23:0] tdd_vco_tx_on_2_s;$/;" n module:ad_tdd_control
tdma hdl/tdma.v /^module tdma #($/;" m
tdma_flag_is_master hdl/phy_control.v /^ output wire tdma_flag_is_master,$/;" p module:phy_control
tdma_flag_is_master hdl/system_top.v /^ wire tdma_flag_is_master;$/;" n module:system_top
tdma_slot_len hdl/phy_control.v /^ output wire [31:0] tdma_slot_len,$/;" p module:phy_control
tdma_slot_len hdl/system_top.v /^ wire [31:0] tdma_slot_len;$/;" n module:system_top
tdma_slot_len hdl/tdma.v /^ input wire [23:0] tdma_slot_len,$/;" p module:tdma
tdma_slot_len_reg hdl/phy_control.v /^ reg [31:0] tdma_slot_len_reg = 32'h0;$/;" r module:phy_control
tdma_tic_2_ps hdl/phy_control.v /^ output wire [31:0] tdma_tic_2_ps$/;" p module:phy_control
tdma_tic_2_ps hdl/system_top.v /^ wire [31:0] tdma_tic_2_ps;$/;" n module:system_top
tdma_tic_2_ps hdl/tdma.v /^ input wire [23:0] tdma_tic_2_ps,$/;" p module:tdma
tdma_tic_2_ps_reg hdl/phy_control.v /^ reg [31:0] tdma_tic_2_ps_reg = 32'h0;$/;" r module:phy_control
temp_1_01 hdl/TSync_Abs_new16.v /^ reg [19:0] temp_1_01 = 20'd0;$/;" r module:TSync_Abs_new16
temp_1_01 hdl/TSync_Abs_new4.v /^ reg [19:0] temp_1_01 = 20'd0;$/;" r module:TSync_Abs_new4
temp_1_02 hdl/TSync_Abs_new16.v /^ reg [19:0] temp_1_02 = 20'd0;$/;" r module:TSync_Abs_new16
@@ -9118,8 +9227,6 @@ test hdl/Transmitter.v /^ input wire test,$/;" p module:Transmitter
test sim/tb_Transmitter.v /^ reg test=0;$/;" r module:tb_Transmitter
th_control hdl/SCFDE_recv_FrameSync.v /^ reg [ 3:0] th_control = 4'd8;$/;" r module:SCFDE_recv_FrameSync
three_wire adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v /^ output reg three_wire$/;" p module:spi_engine_execution
tic_hop_m sim/tb_tdma.v /^ wire tic_hop_m;$/;" n module:tb_tdma
tic_hop_s sim/tb_tdma.v /^ wire tic_hop_s;$/;" n module:tb_tdma
timestamp adi_library/axi_dmac/tb/axi_slave.v /^reg [31:0] timestamp = 'h00;$/;" r module:axi_slave
tl_frames hdl/CCSDS_LDPC_DEC_K1024_R12.v /^ wire [ 8:0] tl_frames;$/;" n module:CCSDS_LDPC_DEC_K1024_R12
tl_frames hdl/CK_PRO.v /^ output reg [8:0] tl_frames=9'd0 \/\/译码总帧数计数$/;" p module:CK_PRO
@@ -9323,9 +9430,7 @@ tx_reset_d1 adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ reg
tx_reset_sync adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v /^ reg tx_reset_sync;$/;" r module:util_gmii_to_rgmii
tx_rst_done_s adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v /^ wire tx_rst_done_s;$/;" n module:util_adxcvr_xch
tx_start hdl/net_city.v /^ output reg tx_start = 1'b0, \/\/ pulse$/;" p module:net_city
tx_start hdl/tdma.v /^ (* KEEP = "TRUE" *) output tx_start,$/;" p module:tdma
tx_start_m sim/tb_tdma.v /^ wire tx_start_m;$/;" n module:tb_tdma
tx_start_s sim/tb_tdma.v /^ wire tx_start_s;$/;" n module:tb_tdma
tx_start hdl/tdma.v /^ output tx_start,$/;" p module:tdma
tx_start_vio hdl/system_top.v /^ wire tx_start_vio;$/;" n module:system_top
tx_start_vio_d1 hdl/system_top.v /^ reg tx_start_vio_d1;$/;" r module:system_top
tx_start_vio_pos hdl/system_top.v /^ wire tx_start_vio_pos;$/;" n module:system_top
@@ -9359,6 +9464,7 @@ u_adder_i hdl/frame_sync.v /^ adder_iq u_adder_i ($/;" i block:fr
u_bram_agc_header hdl/Transmitter.v /^ bram_agc_header u_bram_agc_header ($/;" i module:Transmitter typeref:module:bram_agc_header
u_bram_chu_seq hdl/Transmitter.v /^ bram_chu_seq u_bram_chu_seq ($/;" i module:Transmitter typeref:module:bram_chu_seq
u_bram_m_seqs_512 hdl/Transmitter.v /^ bram_m_seqs_512 u_bram_m_seqs_512 ($/;" i module:Transmitter typeref:module:bram_m_seqs_512
u_bram_scramble hdl/scrambler.v /^ bram_scramble u_bram_scramble ($/;" i module:scrambler typeref:module:bram_scramble
u_bram_tx_test hdl/Transmitter.v /^ bram_tx_test u_bram_tx_test ($/;" i module:Transmitter typeref:module:bram_tx_test
u_clk_wiz_baseband hdl/system_top.v /^ clk_wiz_baseband u_clk_wiz_baseband ($/;" i module:system_top typeref:module:clk_wiz_baseband
u_clk_wiz_baseband sim/TB_sys.v /^ clk_wiz_baseband u_clk_wiz_baseband ($/;" i module:TB_sys typeref:module:clk_wiz_baseband
@@ -9372,6 +9478,8 @@ u_enc_control hdl/system_top.v /^ enc_control u_enc_control ($/;" i module:sy
u_enc_control sim/tb_enc_control.v /^ enc_control u_enc_control ($/;" i module:tb_enc_control typeref:module:enc_control
u_enc_control sim/tb_sys_tx_rx_e_d.v /^ enc_control u_enc_control ($/;" i module:tb_sys_tx_rx_e_d typeref:module:enc_control
u_enc_control sim/tb_tx_with_enc.v /^ enc_control u_enc_control ($/;" i module:tb_tx_with_enc typeref:module:enc_control
u_extract_mac_frame hdl/RecvTop.v /^ extract_mac_frame u_extract_mac_frame ($/;" i module:RecvTop typeref:module:extract_mac_frame
u_extract_mac_frame sim/tb_extract_mac_frame.v /^ extract_mac_frame u_extract_mac_frame ($/;" i module:tb_extract_mac_frame typeref:module:extract_mac_frame
u_fifo_enc_out hdl/enc_control.v /^ fifo_enc_out u_fifo_enc_out ($/;" i module:enc_control typeref:module:fifo_enc_out
u_fifo_shift hdl/Receiver.v /^ fifo_shift u_fifo_shift ($/;" i module:Receiver typeref:module:fifo_shift
u_fifo_shift hdl/RecvTop.v /^ fifo_shift u_fifo_shift ($/;" i module:RecvTop typeref:module:fifo_shift
@@ -9391,16 +9499,24 @@ u_fir_shape_interp4_q hdl/Transmitter.v /^ fir_shape_interp4 u_fir_shape_inte
u_fir_shape_interp8_i hdl/Transmitter.v /^ fir_shape_interp8 u_fir_shape_interp8_i ($/;" i module:Transmitter typeref:module:fir_shape_interp8
u_fir_shape_interp8_q hdl/Transmitter.v /^ fir_shape_interp8 u_fir_shape_interp8_q ($/;" i module:Transmitter typeref:module:fir_shape_interp8
u_ila_frame_sync hdl/PAPR.v /^ ila_frame_sync u_ila_frame_sync ($/;" i module:PAPR typeref:module:ila_frame_sync
u_ila_mac_layer hdl/tdma.v /^ ila_mac_layer u_ila_mac_layer ($/;" i module:tdma typeref:module:ila_mac_layer
u_ila_recv_top hdl/RecvTop.v /^ ila_recv_top u_ila_recv_top ($/;" i module:RecvTop typeref:module:ila_recv_top
u_ila_scrambler hdl/scrambler.v /^ ila_scrambler u_ila_scrambler ($/;" i module:scrambler typeref:module:ila_scrambler
u_ila_transmitter hdl/Transmitter.v /^ ila_transmitter u_ila_transmitter ($/;" i module:Transmitter typeref:module:ila_transmitter
u_net_city hdl/system_top.v /^ net_city u_net_city ($/;" i module:system_top typeref:module:net_city
u_power_measure hdl/ad9361_mgc_pin_ctrl.v /^ power_measure u_power_measure ($/;" i module:ad9361_mgc_pin_ctrl typeref:module:power_measure
u_scrambler sim/tb_scrambler.v /^ scrambler u_scrambler ($/;" i module:tb_scrambler typeref:module:scrambler
u_ser2par hdl/extract_mac_frame.v /^ ser2par u_ser2par ($/;" i module:extract_mac_frame typeref:module:ser2par
u_shift256_8 hdl/add_prefix.v /^ shift256_8 u_shift256_8 ($/;" i module:add_prefix typeref:module:shift256_8
u_shift_reg hdl/PAPR.v /^ ) u_shift_reg ($/;" i module:PAPR typeref:module:shift_reg
u_shift_register_64_i hdl/RecvTop.v /^ shift_register_64 u_shift_register_64_i ($/;" i module:RecvTop typeref:module:shift_register_64
u_shift_register_64_q hdl/RecvTop.v /^ shift_register_64 u_shift_register_64_q ($/;" i module:RecvTop typeref:module:shift_register_64
u_tdma hdl/system_top.v /^ tdma u_tdma ($/;" i module:system_top typeref:module:tdma
u_tdma sim/tb_tdma.v /^ ) u_tdma ($/;" i module:tb_tdma typeref:module:tdma
u_tdma sim/tb_tx_with_enc.v /^ ) u_tdma ($/;" i module:tb_tx_with_enc typeref:module:tdma
u_tdma_master sim/tb_tdma.v /^ ) u_tdma_master ($/;" i module:tb_tdma typeref:module:tdma
u_tdma_slave sim/tb_tdma.v /^ ) u_tdma_slave ($/;" i module:tb_tdma typeref:module:tdma
u_vio_phy_control hdl/system_top.v /^ vio_phy_control u_vio_phy_control ($/;" i module:system_top typeref:module:vio_phy_control
u_vio_phy_param hdl/phy_control.v /^ vio_phy_param u_vio_phy_param ($/;" i module:phy_control typeref:module:vio_phy_param
u_vio_recv_top hdl/RecvTop.v /^ vio_recv_top u_vio_recv_top ($/;" i module:RecvTop typeref:module:vio_recv_top
u_vio_system_top hdl/system_top.v /^ vio_system_top u_vio_system_top ($/;" i module:system_top typeref:module:vio_system_top
u_vio_tdma hdl/tdma.v /^ vio_tdma u_vio_tdma ($/;" i module:tdma typeref:module:vio_tdma
u_width_convert hdl/enc_control.v /^ ) u_width_convert ($/;" i module:enc_control typeref:module:width_convert
u_width_convert sim/tb_width_convert.v /^ ) u_width_convert ($/;" i module:tb_width_convert typeref:module:width_convert
uart_rx hdl/system_top.v /^ input uart_rx,$/;" p module:system_top
@@ -11754,6 +11870,7 @@ vec_mag_1024 hdl/PAPR.v /^ wire [MAG_WIDTH-1:0] vec_mag_1024;$/;" n module:PA
vec_mag_d1 hdl/PAPR.v /^ reg [MAG_WIDTH-1:0] vec_mag_d1;$/;" r module:PAPR
vec_mag_d2 hdl/PAPR.v /^ reg [MAG_WIDTH-1:0] vec_mag_d2;$/;" r module:PAPR
vec_mag_d3 hdl/PAPR.v /^ reg [MAG_WIDTH-1:0] vec_mag_d3;$/;" r module:PAPR
vec_mag_reserved hdl/PAPR.v /^ reg [MAG_WIDTH-1:0] vec_mag_reserved;$/;" r module:PAPR
vec_valid hdl/MagnitudeEstimator.v /^ input vec_valid,$/;" p module:MagnitudeEstimator
vec_valid_d1 hdl/MagnitudeEstimator.v /^ reg vec_valid_d1;$/;" r module:MagnitudeEstimator
vec_valid_d2 hdl/MagnitudeEstimator.v /^ reg vec_valid_d2;$/;" r module:MagnitudeEstimator
@@ -11764,7 +11881,7 @@ vio_powertest_h hdl/DAGC_v2.v /^ input [1:0] vio_powertest_h,$/;" p module:DA
vio_powertest_l hdl/DAGC_v2.v /^ input [1:0] vio_powertest_l,$/;" p module:DAGC_v2
vio_stopbit hdl/FrameMerge.v /^ input [6:0] vio_stopbit,$/;" p module:FrameMerge
vio_stopbit hdl/RecvTop.v /^ input [ 6:0] vio_stopbit, \/\/寻找停止位，默认值为7'd60$/;" p module:RecvTop
vio_tsync_inter16 hdl/RecvTop.v /^ input vio_tsync_inter16, \/\/为1的时候启用内插，从16倍过采样中挑/;" p module:RecvTop
vio_tsync_inter16 hdl/RecvTop.v /^ input vio_tsync_inter16, \/\/为1的时候启用内插，从16倍过采样/;" p module:RecvTop
vio_tsync_inter16 hdl/TimeSync_top.v /^ input vio_tsync_inter16,\/\/12.5$/;" p module:TimeSync_top
vtc_cnt adi_library/xilinx/common/ad_serdes_in.v /^ reg [4:0] vtc_cnt = {5{1'b1}};$/;" r block:ad_serdes_in.g_data
w adi_library/util_pack/util_pack_common/pack_interconnect.v /^ localparam w = PORT_DATA_WIDTH;$/;" c module:pack_interconnect
@@ -11857,11 +11974,9 @@ xor_level_2_01 hdl/CNU_6din.v /^ reg xor_level_1_01=1'd0,xor_level_1_02=1'd0,
xpm_cdc_frame_sync_pulse_inst hdl/Receiver.v /^ ) xpm_cdc_frame_sync_pulse_inst ($/;" i module:Receiver typeref:module:xpm_cdc_pulse
xpm_cdc_frame_sync_pulse_inst hdl/RecvTop.v /^ ) xpm_cdc_frame_sync_pulse_inst ($/;" i module:RecvTop typeref:module:xpm_cdc_pulse
xpm_cdc_single_inst hdl/enc_control.v /^ ) xpm_cdc_single_inst ($/;" i module:enc_control typeref:module:xpm_cdc_single
xpm_cdc_single_tx_test_flag_ps_inst hdl/system_top.v /^ ) xpm_cdc_single_tx_test_flag_ps_inst ($/;" i module:system_top typeref:module:xpm_cdc_single
xpm_cdc_startup_inst hdl/Receiver.v /^ ) xpm_cdc_startup_inst ($/;" i module:Receiver typeref:module:xpm_cdc_single
xpm_cdc_startup_inst hdl/RecvTop.v /^ ) xpm_cdc_startup_inst ($/;" i module:RecvTop typeref:module:xpm_cdc_single
xpm_cdc_sync_rst_inst hdl/Receiver.v /^ ) xpm_cdc_sync_rst_inst ($/;" i module:Receiver typeref:module:xpm_cdc_sync_rst
xpm_cdc_sync_rst_phy_rst_inst hdl/system_top.v /^ ) xpm_cdc_sync_rst_phy_rst_inst ($/;" i module:system_top typeref:module:xpm_cdc_sync_rst
y0 adi_library/common/ad_dds_sine_cordic.v /^ reg [CORDIC_DW-1:0] y0 = 'd0;$/;" r module:ad_dds_sine_cordic
y_length adi_library/axi_dmac/2d_transfer.v /^reg [DMA_LENGTH_WIDTH-1:0] y_length = 'h00;$/;" r module:dmac_2d_transfer
y_s adi_library/common/ad_dds_sine_cordic.v /^ wire [CORDIC_DW-1:0] y_s [0:CORDIC_DW-1];$/;" n module:ad_dds_sine_cordic
coe/rf_control_map.coe
+10
View File
@@ -0,0 +1,10 @@
memory_initialization_radix=2;
memory_initialization_vector=
1000
0100
0001
1001
0101
1101
0111
1111;
contraint/mm7020_timing.xdc
+2
View File
@@ -9,3 +9,5 @@ set_false_path -through [get_nets u_MM7020_BD_wrapper/phy_rx_iq_reverse]
set_false_path -through [get_nets tdma_flag_is_master]
set_false_path -through [get_nets tdma_slot_len*]
set_false_path -through [get_nets tdma_tic_2_ps*]
set_false_path -through [get_nets u_tdma/tdma_tic_frame_sync_vio*]
set_false_path -through [get_nets rx_rst]
hdl/PAPR.v
+93 -48
View File
@@ -36,19 +36,32 @@ module PAPR #(
);
localparam SUM_WIDTH = 32;
localparam CNT_START = 16; // 32*4 / 8 * mag_valid signal is active high per 8 clk
localparam CNT_END = 44; // 88*4 / 8
localparam PULSE_PERIOD = 32;
reg mag_valid_d1;
reg [MAG_WIDTH-1:0] vec_mag_d1;
reg [MAG_WIDTH-1:0] vec_mag_d2;
reg [MAG_WIDTH-1:0] vec_mag_d3;
reg frame_sync_d1;
reg [MAG_WIDTH-1:0] vec_mag_reserved;
// accumulate ==> average ==> papr
wire [MAG_WIDTH-1:0] vec_mag_1024;
reg [ 7:0] cnt;
wire [MAG_WIDTH-1:0] data_avg;
reg [SUM_WIDTH-1:0] data_sum;
assign data_avg = data_sum[SUM_WIDTH-1:10];
always @(posedge clk) begin
mag_valid_d1 <= mag_valid;
if (rst) begin
vec_mag_d1 <= 'd0;
vec_mag_d2 <= 'd0;
vec_mag_d3 <= 'd0;
vec_mag_d1 <= 0;
vec_mag_d2 <= 0;
vec_mag_d3 <= 0;
end
else if (mag_valid) begin
vec_mag_d1 <= vec_mag;
@@ -61,9 +74,7 @@ module PAPR #(
vec_mag_d3 <= vec_mag_d3;
end
end
// accumulate ==> average ==> papr
wire [MAG_WIDTH-1:0] vec_mag_1024;
reg [ 5:0] cnt;
shift_reg #(
.DATA_WIDTH(MAG_WIDTH),
@@ -77,10 +88,9 @@ module PAPR #(
);
reg [SUM_WIDTH-1:0] data_sum;
always @(posedge clk) begin
if (rst) begin
data_sum <= 'd0;
data_sum <= 0;
end
else begin
if (mag_valid) begin
@@ -92,59 +102,94 @@ module PAPR #(
end
end
wire [MAG_WIDTH-1:0] data_avg;
assign data_avg = data_sum[SUM_WIDTH-1:10];
// FSM
reg [2:0] cs = 0;
reg [2:0] ns = 0;
always @(posedge clk) begin
cs <= ns;
end
always @(*) begin
ns = cs;
case (cs)
0: begin
if (mag_valid && vec_mag_1024 != 'd0 && data_avg != 'd0 && ({3'd0, vec_mag_d2[MAG_WIDTH-1:3]} >= data_avg) && (vec_mag_d2 >= vec_mag_d1) && (vec_mag_d2 >= vec_mag_d3) && (vec_mag_d2 >= 22'h5000)) begin
ns = 1;
end
end
1: begin
if (cnt == CNT_START - 1) begin
ns = 2;
end
end
2: begin
if (vec_mag_reserved < {vec_mag[MAG_WIDTH-3:0], 2'b0}) begin
ns = 0;
end
else if (cnt == CNT_END - 1) begin
ns = 3;
end
end
3: begin
// generate pulse
ns = 4;
end
4: begin
if (cnt == PULSE_PERIOD - 1) begin
ns = 0;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
frame_sync <= 1'd0;
if (cs == 0 && ns == 1) begin
vec_mag_reserved <= vec_mag_d2;
end
else if (vec_mag_1024 != 'd0 && data_avg != 'd0) begin
// NOTE: 防止0均值的情况，比如，一开始信号很小，刚好接收到有信号，那么均值为0，峰值有值，那么一定会过门限。
if (mag_valid_d1 && ({3'd0, vec_mag_d2[MAG_WIDTH-1:3]} >= data_avg) && (vec_mag_d2 >= vec_mag_d1) && (vec_mag_d2 >= vec_mag_d3) && (vec_mag_d2 >= 22'h5000)) begin
frame_sync <= 1'd1;
end
else if (cnt == 6'b111111) begin
frame_sync <= 1'd0;
end
else begin
frame_sync <= frame_sync;
end
end
else begin
frame_sync <= frame_sync;
else if (cs == 0) begin
vec_mag_reserved <= 0;
end
end
always @(posedge clk) begin
frame_sync_d1 <= frame_sync;
if (frame_sync && ~frame_sync_d1) begin
frame_sync_pulse <= 1'd1;
if (cs == 1 || cs == 2) begin
if (mag_valid) begin
cnt <= cnt + 1;
end
else begin
frame_sync_pulse <= 1'd0;
end
else if (cs == 4) begin
cnt <= cnt + 1;
end
else if (cs == 0) begin
cnt <= 0;
end
end
always @(posedge clk) begin
if (rst) begin
cnt <= 6'd0;
frame_sync_pulse <= (cs == 3);
if (cs == 4) begin
frame_sync <= 1;
end
else if (frame_sync && mag_valid_d1) begin
cnt <= cnt + 6'd1;
end
else if (cnt == 6'b111111) begin
cnt <= 6'd0;
else begin
frame_sync <= 0;
end
end
ila_frame_sync u_ila_frame_sync (
.clk (clk), // input wire clk
.probe0(vec_mag), // input wire [21:0] probe0
.probe1(data_avg), // input wire [21:0] probe0
.probe2(frame_sync) // input wire [0:0] probe2
);
// ila_frame_sync u_ila_frame_sync (
// .clk (clk), // input wire clk
// .probe0(vec_mag), // input wire [21:0] probe0
// .probe1(data_avg), // input wire [21:0] probe0
// .probe2(cs), // input wire [2:0] probe2
// .probe3(cnt), // input wire [7:0] probe2
// .probe4(frame_sync), // input wire [0:0] probe2
// .probe5(vec_mag_reserved) // input wire [21:0] probe2
// );
hdl/RecvTop.v
+41 -8
View File
@@ -46,7 +46,9 @@ module RecvTop (
output wire [31:0] rx_data_src_fifo_tdata,
output wire rx_data_src_fifo_tlast,
input wire rx_data_src_fifo_tready,
output wire rx_data_src_fifo_tvalid
output wire rx_data_src_fifo_tvalid,
// ber
output reg err_flag_pos
);
wire rst_TimeSync;
@@ -274,7 +276,7 @@ module RecvTop (
wire rst_frame_sync; // derive from frame sync pulse
reg [ 7:0] cnt_chu_seq_sync; // frame sync delay to chu seq sample start pos
assign rst_frame_sync = ((cnt_chu_seq_sync >= 1) && (cnt_chu_seq_sync < cnt_chu_seq_sync_max_vio));
//* calc the magnitude
MagnitudeEstimator #(
@@ -302,7 +304,7 @@ module RecvTop (
);
always @(posedge clk) begin
if (frame_sync_pulse) begin
if (frame_sync_pulse && ~flag_frame_sync) begin
cnt_chu_seq_sync <= 1;
end
// avoid the tailing of the convolution (here we use CNT_CHU_SEQ_SYNC_MAX clocks)
@@ -314,6 +316,8 @@ module RecvTop (
end
end
assign rst_frame_sync = ((cnt_chu_seq_sync >= 1) && (cnt_chu_seq_sync < cnt_chu_seq_sync_max_vio));
always @(posedge clk) begin
if (rst) begin
flag_frame_sync <= 0;
@@ -354,6 +358,19 @@ module RecvTop (
end
end
wire [9:0] dagc_data_in_i;
wire [9:0] dagc_data_in_q;
shift_register_64 u_shift_register_64_i (
.D (mf_data_interp4_i[29-:10]), // input wire [9 : 0] D
.CLK(clk), // input wire CLK
.Q (dagc_data_in_i) // output wire [9 : 0] Q
);
shift_register_64 u_shift_register_64_q (
.D (mf_data_interp4_q[29-:10]), // input wire [9 : 0] D
.CLK(clk), // input wire CLK
.Q (dagc_data_in_q) // output wire [9 : 0] Q
);
DAGC_v2 DAGC_v2 (
.clk (clk),
@@ -362,8 +379,8 @@ module RecvTop (
.framesync_d0 (flag_frame_sync),
.vio_powertest_h (2'b00),
.vio_powertest_l (2'b00),
.matchfilterout_i(mf_data_interp4_i[29-:10]), // input,
.matchfilterout_q(mf_data_interp4_q[29-:10]), // input
.matchfilterout_i(dagc_data_in_i), // input,
.matchfilterout_q(dagc_data_in_q), // input
.DAGC_out_i (DAGC_out_i), // output
.DAGC_out_q (DAGC_out_q), // output
// debug
@@ -502,7 +519,7 @@ module RecvTop (
extract_mac_frame u_extract_mac_frame (
.clk (clk_2x),
.rst (rst2 || rst_frame_sync || ~flag_frame_sync),
.rst (rst2 || rst_frame_sync),
.ldpc_dec_out_start (LDPC_SyncOut),
.ldpc_dec_out_valid (LDPC_Rdy),
.ldpc_dec_out_data (LDPC_Dout),
@@ -512,6 +529,22 @@ module RecvTop (
.m_axis_mac_frame_tlast (rx_data_src_fifo_tlast)
);
reg err_flag;
reg err_flag_d1;
// reg err_flag_pos;
always @(posedge clk) begin
if (rst2 || rst_frame_sync) begin
err_flag <= 0;
end
else if (total_frames == 105 && bad_frames > 0) begin
err_flag <= 1;
end
err_flag_d1 <= err_flag;
err_flag_pos <= err_flag & ~err_flag_d1;
end
@@ -564,8 +597,8 @@ module RecvTop (
.clk (clk),
.probe0 (dini), // width: 12
.probe1 (dinq), // width: 12
.probe2 (mf_data_interp4_i[29-:12]), // width: 12
.probe3 (mf_data_interp4_q[29-:12]), // width: 12
.probe2 (dagc_data_in_i), // width: 12
.probe3 (dagc_data_in_q), // width: 12
.probe4 (flag_mgc_done), // width: 1
.probe5 (flag_frame_sync), // width: 1
.probe6 (flag_cfo_done), // width: 1
hdl/descrambler.v
-161
View File
@@ -1,161 +0,0 @@
// * Engineer:
// * *************************************************** *
// * ███████╗ ██████╗ ██████╗ ██████╗ ██████╗ ██╗ ██╗ *
// * ╚══███╔╝██╔═══██╗██╔══██╗██╔═══██╗██╔════╝ ██║ ██║ *
// * ███╔╝ ██║ ██║██████╔╝██║ ██║██║ ███╗███████║ *
// * ███╔╝ ██║ ██║██╔══██╗██║ ██║██║ ██║██╔══██║ *
// * ███████╗╚██████╔╝██║ ██║╚██████╔╝╚██████╔╝██║ ██║ *
// * ╚══════╝ ╚═════╝ ╚═╝ ╚═╝ ╚═════╝ ╚═════╝ ╚═╝ ╚═╝ *
// * *************************************************** *
// * Update Date:
// * NOTE :
module scrambler #(
parameter ILA_ON = 0
) (
input clk,
input rst_n,
// s_axis_stream
input [31:0] s_axis_tdata,
input s_axis_tvalid,
output reg s_axis_tready,
input s_axis_tlast,
input [31:0] s_axis_rd_data_count,
// m_axis_stream
output reg [31:0] m_axis_tdata,
output reg m_axis_tvalid,
input m_axis_tready,
output reg m_axis_tlast
);
// ******** Wire & Reg ********
wire rst;
reg [ 2:0] addr_scramble = 0;
reg [ 2:0] addr_scramble_d1 = 0;
reg [ 2:0] addr_scramble_d2 = 0;
wire [31:0] data_scramble_mask;
reg [ 3:0] cnt_in;
reg [31:0] s_axis_tdata_d1;
reg [31:0] s_axis_tdata_d2;
reg s_axis_tready_d1;
reg s_axis_tlast_d1;
// fsm
reg [ 1:0] cs = 0;
reg [ 1:0] ns = 0;
localparam S_IDLE = 0;
localparam S_WORKING = 1;
// ******** Assingment ********
assign rst = ~rst_n;
// ******** Logic Block ********
always @(posedge clk) begin
cs <= ns;
end
always @(*) begin
ns = cs;
case (cs)
S_IDLE: begin
if (s_axis_tvalid && m_axis_tready && s_axis_rd_data_count >= 16) begin
ns = S_WORKING;
end
end
S_WORKING: begin
if (addr_scramble_d2 == 3'h7) begin
ns = S_IDLE;
end
end
default: begin
ns = S_IDLE;
end
endcase
end
always @(posedge clk) begin
if (cs == S_IDLE) begin
addr_scramble <= 0;
end
else begin
addr_scramble <= addr_scramble + 1;
end
addr_scramble_d1 <= addr_scramble;
addr_scramble_d2 <= addr_scramble_d1;
end
always @(posedge clk) begin
if (cs == S_WORKING) begin
m_axis_tdata <= s_axis_tdata_d1 ^ data_scramble_mask;
end
else begin
m_axis_tdata <= 0;
end
end
always @(posedge clk) begin
if (cs == S_WORKING && s_axis_tvalid && cnt_in < 4'd8) begin
s_axis_tready <= 1;
end
else begin
s_axis_tready <= 0;
end
end
always @(posedge clk) begin
s_axis_tdata_d1 <= s_axis_tdata;
s_axis_tready_d1 <= s_axis_tready;
m_axis_tvalid <= s_axis_tready_d1;
s_axis_tlast_d1 <= s_axis_tlast;
m_axis_tlast <= s_axis_tlast_d1;
end
always @(posedge clk) begin
if (cs == S_IDLE) begin
cnt_in <= 0;
end
else if (cs == S_WORKING && cnt_in < 4'd8) begin
cnt_in <= cnt_in + 1;
end
end
// ******** Inst ********
bram_scramble u_bram_scramble (
.clka (clk), // input wire clka
.addra(addr_scramble), // input wire [2 : 0] addra
.douta(data_scramble_mask) // output wire [31 : 0] douta
);
// ******** Debug ********
generate
if (ILA_ON)
ila_scrambler u_ila_scrambler (
.clk (clk), // input wire clk
.probe0(s_axis_tvalid), // input wire [0:0] probe0
.probe1(s_axis_tready), // input wire [0:0] probe1
.probe2(s_axis_tdata), // input wire [31:0] probe2
.probe3(s_axis_tlast), // input wire [0:0] probe3
.probe4(m_axis_tvalid), // input wire [0:0] probe4
.probe5(m_axis_tready), // input wire [0:0] probe5
.probe6(m_axis_tdata), // input wire [31:0] probe6
.probe7(m_axis_tlast), // input wire [0:0] probe7
.probe8(data_scramble_mask) // input wire [31:0] probe8
);
endgenerate
endmodule
hdl/net_city.v
+9 -9
View File
@@ -12,8 +12,8 @@ module net_city (
output reg [07:0] recv_id = 8'd0,
// rx signal
input frame_sync,
input recv_net_data_nd,
input [63:0] recv_net_data,
// input recv_net_data_nd,
// input [63:0] recv_net_data,
// net parameter
input [31:0] frame_sync_time,
input [07:0] id_num,
@@ -215,13 +215,13 @@ module net_city (
// if (recv_net_data[23:00] == 24'h7e5a33) begin
state_net <= 8'd51;
is_net <= 1'b1;
cnt_trans_slot <= cnt_trans_slot + 32'd1;
cnt_inter_slot <= cnt_inter_slot + 32'd1;
recv_id <= recv_net_data[63:56];
recv_video_id01 <= recv_net_data[55:48];
recv_video_id02 <= recv_net_data[47:40];
recv_video_id03 <= recv_net_data[39:32];
recv_connect_node <= recv_net_data[31:24];
// cnt_trans_slot <= cnt_trans_slot + 32'd1;
// cnt_inter_slot <= cnt_inter_slot + 32'd1;
// recv_id <= recv_net_data[63:56];
// recv_video_id01 <= recv_net_data[55:48];
// recv_video_id02 <= recv_net_data[47:40];
// recv_video_id03 <= recv_net_data[39:32];
// recv_connect_node <= recv_net_data[31:24];
// end
// else begin
// state_net <= 8'd200;
hdl/phy_control.v
+23 -2
View File
@@ -71,7 +71,11 @@ module phy_control #(
// tdma parameters
output wire tdma_flag_is_master,
output wire [31:0] tdma_slot_len,
output wire [31:0] tdma_tic_2_ps
output wire [31:0] tdma_tic_2_ps,
output wire [31:0] tdma_id_cfg,
output wire tdma_recv_cur_slot_id_valid,
output wire [ 7:0] tdma_recv_cur_slot_id,
output wire [31:0] tdma_frame_sync_tic
//--- ADD YOUR OWN PORTS END
);
@@ -339,12 +343,18 @@ module phy_control #(
localparam integer PHY_SR = 'h00000004 >> 2; // RW
localparam integer TDMA_SLOT_LEN = 'h0000_0008 >> 2;
localparam integer TDMA_TIC_2_PS = 'h0000_000C >> 2;
localparam integer TDMA_ID_CFG = 'h0000_0010 >> 2;
localparam integer TDMA_RECV_ID = 'h0000_0014 >> 2;
localparam integer TDMA_FRAME_SYNC_TIC = 'h0000_0018 >> 2;
// Register definitions
reg [31:0] phy_cr_reg = 32'h0;
reg [31:0] phy_sr_reg = 32'h0;
reg [31:0] tdma_slot_len_reg = 32'h0;
reg [31:0] tdma_tic_2_ps_reg = 32'h0;
reg [31:0] tdma_id_cfg_reg = 32'h0; // 2B zero pad, 1B slot num, 1B local id
reg [31:0] tdma_recv_id_reg = 32'h0;
reg [31:0] tdma_frame_sync_tic_reg = 32'h0;
// Register Reading
always @(posedge local_clk) begin
@@ -369,10 +379,16 @@ module phy_control #(
PHY_SR: phy_sr_reg <= up_wdata_s;
TDMA_SLOT_LEN: tdma_slot_len_reg <= up_wdata_s;
TDMA_TIC_2_PS: tdma_tic_2_ps_reg <= up_wdata_s;
TDMA_ID_CFG: tdma_id_cfg_reg <= up_wdata_s;
TDMA_RECV_ID: tdma_recv_id_reg <= up_wdata_s;
TDMA_FRAME_SYNC_TIC: tdma_frame_sync_tic_reg <= up_wdata_s;
endcase
end
else begin
// self logic
if (tdma_recv_id_reg[8] == 1) begin
tdma_recv_id_reg[8] <= 0;
end
end
end
end
@@ -387,7 +403,12 @@ module phy_control #(
// tdma
assign tdma_slot_len = tdma_slot_len_reg;
assign tdma_tic_2_ps = tdma_tic_2_ps_reg;
assign tdma_id_cfg = tdma_id_cfg_reg;
// received mac frame
assign tdma_recv_cur_slot_id = tdma_recv_id_reg[7:0];
assign tdma_recv_cur_slot_id_valid = tdma_recv_id_reg[8];
// frame sync tic
assign tdma_frame_sync_tic = tdma_frame_sync_tic_reg;
vio_phy_param u_vio_phy_param (
.clk (local_clk),
hdl/system_top.v
+90 -66
View File
@@ -122,6 +122,11 @@ module system_top (
wire tdma_flag_is_master;
wire [31:0] tdma_slot_len;
wire [31:0] tdma_tic_2_ps;
wire [31:0] tdma_id_cfg;
wire tdma_recv_cur_slot_id_valid;
wire [ 7:0] tdma_recv_cur_slot_id;
wire [31:0] tdma_frame_sync_tic;
// tx signal
wire frame_sync_pulse;
@@ -134,6 +139,15 @@ module system_top (
wire tx_start_vio;
reg tx_start_vio_d1;
wire tx_start_vio_pos;
// rx
wire rx_err_flag_pos;
wire rf_io3_d1_12db;
wire rf_io4_d2_6db;
wire rf_io0_d3_18db;
wire rf_io1_d4_12db;
wire rf_io2_trx; // 1 for tx on, 0 for rx
// vio
wire rst_manual;
@@ -142,6 +156,9 @@ module system_top (
wire intr_2ps;
wire [ 7:0] max_slot_num;
reg [15:0] cnt_pulse_wider_tx_start = 0;
reg [15:0] cnt_pulse_wider_frame_sync = 0;
// ******** Assingment ********
assign ad9361_tx_clk = clk_1x;
@@ -157,9 +174,43 @@ module system_top (
assign ad9361_tx_data_q = phy_tx_iq_reverse ? bb_tx_i : bb_tx_q;
assign bb_rx_i = phy_rx_iq_reverse ? ad9361_rx_data_q : ad9361_rx_data_i;
assign bb_rx_q = phy_rx_iq_reverse ? ad9361_rx_data_i : ad9361_rx_data_q;
// gpio rf control
assign rf_gpio[0] = rf_io0_d3_18db;
assign rf_gpio[1] = rf_io1_d4_12db;
// assign rf_gpio[2] = rf_io2_trx;
// assign rf_gpio[3] = rf_io3_d1_12db;
assign rf_gpio[4] = rf_io4_d2_6db;
assign rf_gpio[5] = 0;
// temporary for test gpio
assign rf_gpio[2] = (cnt_pulse_wider_tx_start != 0);
assign rf_gpio[3] = (cnt_pulse_wider_frame_sync != 0);
// ******** Logic Block ********
always @(posedge clk_1x) begin
if (tx_start) begin
cnt_pulse_wider_tx_start <= 1;
end
else if (cnt_pulse_wider_tx_start > 0) begin
cnt_pulse_wider_tx_start <= cnt_pulse_wider_tx_start + 1;
end
else begin
cnt_pulse_wider_tx_start <= cnt_pulse_wider_tx_start;
end
end
always @(posedge clk_2x) begin
if (rx_data_src_fifo_tlast) begin
cnt_pulse_wider_frame_sync <= 1;
end
else if (cnt_pulse_wider_frame_sync > 0) begin
cnt_pulse_wider_frame_sync <= cnt_pulse_wider_frame_sync + 1;
end
else begin
cnt_pulse_wider_frame_sync <= cnt_pulse_wider_frame_sync;
end
end
// ******** Inst ********
clk_wiz_poweron u_clk_wiz_poweron (
@@ -218,8 +269,9 @@ module system_top (
.gpio_o (gpio_o),
.gpio_t (gpio_t),
// intr pl to ps
.pl_tx_intr (intr_2ps | intr_2ps_vio_pos),
.pl_tx_intr (intr_2ps),
.pl_rx_intr (rx_data_src_fifo_tlast),
.pl_intr0 (rx_err_flag_pos),
// tx fifo
.tx_data_src_count (tx_data_src_count),
.tx_data_src_tdata (tx_data_src_tdata),
@@ -230,9 +282,12 @@ module system_top (
.rst_rx_data_src_fifo (rx_rst),
.rx_data_src_fifo_tdata (rx_data_src_fifo_tdata),
.rx_data_src_fifo_tlast (rx_data_src_fifo_tlast),
.rx_data_src_fifo_tready(rx_data_src_fifo_tready),
.rx_data_src_fifo_tvalid(rx_data_src_fifo_tvalid),
// phy control signal
.rx_data_src_fifo_tready (rx_data_src_fifo_tready),
.rx_data_src_fifo_tvalid (rx_data_src_fifo_tvalid),
// phy clock and rst to ps
.clk_phy (clk_1x),
.rst_phy_n (~rst_sys),
// phy control signal , under clk_1x domain
.phy_rst (phy_rst),
.phy_tx_test_flag (phy_tx_test_flag),
.phy_tx_iq_reverse (phy_tx_iq_reverse),
@@ -240,50 +295,33 @@ module system_top (
.tdma_flag_is_master (tdma_flag_is_master),
.tdma_slot_len (tdma_slot_len),
.tdma_tic_2_ps (tdma_tic_2_ps),
.tdma_id_cfg (tdma_id_cfg),
.tdma_recv_cur_slot_id_valid(tdma_recv_cur_slot_id_valid),
.tdma_recv_cur_slot_id (tdma_recv_cur_slot_id),
.tdma_frame_sync_tic (tdma_frame_sync_tic),
// uart
.uart_rx (uart_rx),
.uart_tx (uart_tx)
);
// tdma u_tdma (
// .clk (clk_1x),
// .rst (rst_sys),
// .flag_is_master (tdma_flag_is_master),
// .flag_frame_sync(frame_sync_pulse),
// .tdma_slot_len (tdma_slot_len[23:0]),
// .tdma_tic_2_ps (tdma_tic_2_ps[23:0]),
// .intr_2ps (intr_2ps),
// .tx_start (tx_start),
// .rx_rst (rx_rst)
// );
tdma u_tdma (
.clk (clk_1x),
.rst (rst_sys),
.flag_frame_sync (frame_sync_pulse),
.tdma_slot_len (tdma_slot_len[23:0]),
.tdma_tic_2_ps (tdma_tic_2_ps[23:0]),
.tdma_slot_num (tdma_id_cfg[15:8]),
.tdma_frame_sync_tic (tdma_frame_sync_tic[23:0]),
.local_id (tdma_id_cfg[7:0]),
.recevied_cur_slot_id_valid(tdma_recv_cur_slot_id_valid),
.recevied_cur_slot_id (tdma_recv_cur_slot_id),
.intr_2ps (intr_2ps),
.tx_start (tx_start),
.rx_rst (rx_rst)
);
// net_city u_net_city (
// .clk (clk_1x),
// .rst_initial (rst_sys),
// .rst_manual (rst_manual),
// .tx_start (tx_start),
// .trans_net_data (),
// .flag_video_send (),
// .recv_id (),
// .frame_sync (frame_sync_pulse),
// .recv_net_data_nd(1'b1),
// .recv_net_data (64'd0),
// .frame_sync_time (42344),
// .id_num (node_id),
// .max_slot_num (max_slot_num),
// .video_id01 (0),
// .video_id02 (0),
// .video_id03 (0),
// .is_net (),
// .flag_to_uc (),
// .intr_ps (intr_2ps),
// .rx_rst (rx_rst),
// .tx_done (tx_done)
// );
// ---- PHY layer logic start
enc_control u_enc_control (
@@ -305,7 +343,7 @@ module system_top (
.rst (rst_sys | phy_rst),
.speed_mode (2),
.send_data_ready (send_data_ready),
.send_start (tx_start | tx_start_vio_pos),
.send_start (tx_start),
.send_over (tx_done),
.clk_data_src (clk_data_src),
.tx_data_src_tdata (enc_fifo_dout_map),
@@ -322,7 +360,7 @@ module system_top (
.clk (clk_1x),
.clk_2x (clk_2x),
.clk_4x (clk_4x),
.rst (rst_sys | rx_rst | phy_rst | rx_rst_vio),
.rst (rst_sys | rx_rst | phy_rst),
.rst2 (rst_sys | phy_rst),
.dini (bb_rx_i),
.dinq (bb_rx_q),
@@ -340,14 +378,10 @@ module system_top (
.rx_data_src_fifo_tdata (rx_data_src_fifo_tdata),
.rx_data_src_fifo_tlast (rx_data_src_fifo_tlast),
.rx_data_src_fifo_tready(rx_data_src_fifo_tready),
.rx_data_src_fifo_tvalid(rx_data_src_fifo_tvalid)
.rx_data_src_fifo_tvalid(rx_data_src_fifo_tvalid),
.err_flag_pos (rx_err_flag_pos)
);
// ---- PHY layer logic end
@@ -387,23 +421,13 @@ module system_top (
// .probe1(ad9361_tx_data_q) // input wire [11:0] probe1
// );
assign tx_start_vio_pos = tx_start_vio & ~tx_start_vio_d1;
always @(posedge clk_1x) begin
tx_start_vio_d1 <= tx_start_vio;
end
assign intr_2ps_vio_pos = intr_2ps_vio & ~intr_2ps_vio_d1;
always @(posedge clk_1x) begin
intr_2ps_vio_d1 <= intr_2ps_vio;
end
vio_system_top u_vio_system_top (
.clk (clk_1x),
.probe_out0(rx_rst_vio),
.probe_out1(tx_start_vio),
.probe_out2(intr_2ps_vio)
);
// vio_rf u_vio_rf (
// .clk (clk_poweron),
// .probe_out0(rf_io2_trx),
// .probe_out1(rf_io3_d1_12db),
// .probe_out2(rf_io4_d2_6db),
// .probe_out3(rf_io0_d3_18db),
// .probe_out4(rf_io1_d4_12db)
// );
endmodule
hdl/tdma.v
+115 -26
View File
@@ -13,53 +13,138 @@
// ! PLEASE MAKE SURE THE PARAMETER ARE VALID
// ! WHEN U INSTANTIATE THIS MODULE
module tdma #(
parameter TIC_FRAME_SYNC = 42344
) (
module tdma (
input clk,
input rst,
input flag_is_master,
// PHY parameter
input flag_frame_sync,
// general parameter, update only once
input wire [23:0] tdma_slot_len,
input wire [23:0] tdma_tic_2_ps,
input wire [ 7:0] tdma_slot_num,
input wire [23:0] tdma_frame_sync_tic,
input wire [ 7:0] local_id, // ID number for this device
// update while received valid
input wire recevied_cur_slot_id_valid, // recevied ID number of the frame
input wire [ 7:0] recevied_cur_slot_id,
output intr_2ps,
output tx_start,
output reg rx_rst
);
// TODO: 需要检查综合后电路是否会被优化
// BUG: 需要修复bug，重构代码，把主从分开写，通过参数进行优化
// ******** Wire & Reg ********
reg flag_is_tx_slot;
reg [23:0] cnt;
reg flag_next_slot_is_tx_slot;
reg [23:0] cnt_tdma_slot_len;
reg [ 7:0] cur_slot_id;
wire flag_end_of_one_slot; // the last period of the slot
wire [23:0] tdma_tic_frame_sync_vio;
// fsm
localparam S_IDLE = 0;
localparam S_RX = 1;
localparam S_TX = 2;
reg [1:0] cs = 0;
reg [1:0] ns = 0;
// ******** Assingment ********
assign tx_start = flag_is_master & (cnt == 16'd10);
assign intr_2ps = flag_is_master & (cnt == tdma_tic_2_ps - 1);
assign flag_end_of_one_slot = (cnt_tdma_slot_len == tdma_slot_len - 1);
assign tx_start = (cs == S_TX) & (cnt_tdma_slot_len == 16'd10);
assign intr_2ps = flag_next_slot_is_tx_slot & (cnt_tdma_slot_len == tdma_tic_2_ps - 1);
// ******** Logic Block ********
// fsm
always @(posedge clk) begin
if (rst) begin
cs <= S_IDLE;
end
else begin
cs <= ns;
end
end
// conditional transition
always @(*) begin
ns = cs;
case (cs)
S_IDLE: begin
// if this device is master node, ps should first send one packet to the fifo
if (local_id == 1) begin
ns = S_TX;
end
else if (recevied_cur_slot_id_valid) begin
ns = S_RX;
end
end
S_RX: begin
if (flag_next_slot_is_tx_slot && flag_end_of_one_slot) begin
ns = S_TX;
end
end
S_TX: begin
if (~flag_next_slot_is_tx_slot && flag_end_of_one_slot) begin
ns = S_RX;
end
end
default: begin
ns = S_IDLE;
end
endcase
end
always @(posedge clk) begin
if (rst) begin
cnt <= 0;
cnt_tdma_slot_len <= 0;
end
else if (flag_frame_sync) begin
cnt_tdma_slot_len <= tdma_frame_sync_tic;
end
else begin
if (!flag_is_master && flag_frame_sync) begin
// slave update cnt
cnt <= TIC_FRAME_SYNC;
if (flag_end_of_one_slot) begin
cnt_tdma_slot_len <= 0;
end
else begin
// master
if (cnt < tdma_slot_len - 1) begin
cnt <= cnt + 1;
cnt_tdma_slot_len <= cnt_tdma_slot_len + 1;
end
end
end
always @(*) begin
if (cs == S_TX || cnt_tdma_slot_len <= 10) begin
rx_rst <= 1;
end
else begin
cnt <= 0;
rx_rst <= 0;
end
end
always @(posedge clk) begin
if (cs == S_IDLE) begin
if (ns == S_TX) begin // indicating master node
cur_slot_id <= 1;
end
else if (recevied_cur_slot_id_valid) begin // from ps update, first sync, indicating slave
cur_slot_id <= recevied_cur_slot_id;
end
else begin
cur_slot_id <= 0;
end
end
else begin
if (recevied_cur_slot_id_valid) begin // from ps update
cur_slot_id <= recevied_cur_slot_id;
end
else if (flag_end_of_one_slot) begin // at the changing moment
if (cur_slot_id == tdma_slot_num) begin
cur_slot_id <= 1;
end
else begin
cur_slot_id <= cur_slot_id + 1;
end
end
end
@@ -67,11 +152,11 @@ module tdma #(
always @(posedge clk) begin
if (flag_is_master) begin
rx_rst <= 1;
if (local_id == 1) begin
flag_next_slot_is_tx_slot <= (cur_slot_id == tdma_slot_num);
end
else begin
rx_rst <= flag_is_master | (cnt <= 16'd4);
flag_next_slot_is_tx_slot <= (cur_slot_id + 1 == local_id);
end
end
@@ -83,17 +168,21 @@ module tdma #(
.clk (clk),
.probe_in0(tdma_slot_len),
.probe_in1(tdma_tic_2_ps),
.probe_in2(flag_is_master)
.probe_in2(tdma_slot_num),
.probe_in3(local_id),
.probe_in4(tdma_frame_sync_tic)
);
ila_mac_layer u_ila_mac_layer (
.clk (clk),
.probe0(cnt), // width: 24
.probe0(cnt_tdma_slot_len), // width: 24
.probe1(tx_start), // width: 1
.probe2(rx_rst), // width: 1
.probe3(flag_is_master), // width: 1
.probe3(cur_slot_id), // width: 8
.probe4(intr_2ps), // width: 1
.probe5(flag_frame_sync) // width: 1
.probe5(flag_frame_sync), // width: 1
.probe6(recevied_cur_slot_id), // width: 8
.probe7(recevied_cur_slot_id_valid) // width: 1
);
sim/tb_tdma.v
+65 -10
View File
@@ -29,18 +29,73 @@ module tb_tdma ();
#10 rst <= 1'b0;
end
tdma #(
.SLOT_LEN (625000), // 50MHz--> 15ms
.TIC_TO_PS_LEN (575000),
.TIC_FRAME_SYNC(42344)
) u_tdma (
reg [7:0] local_id = 0;
initial begin
#20 local_id <= 1;
end
reg flag_frame_sync = 0;
reg recevied_cur_slot_id_valid = 0;
reg [7:0] recevied_cur_slot_id = 0;
tdma u_tdma_master (
.clk (clk),
.rst (rst),
.flag_is_master (1),
.flag_frame_sync(0),
.intr_2ps (intr_2ps),
.tx_start (tx_start),
.rx_rst (rx_rst)
.flag_frame_sync (flag_frame_sync),
.tdma_slot_len (24'd7500),
.tdma_tic_2_ps (24'd6000),
.tdma_slot_num (8'd4),
.local_id (local_id),
.recevied_cur_slot_id_valid(recevied_cur_slot_id_valid),
.recevied_cur_slot_id (recevied_cur_slot_id),
.intr_2ps (),
.tx_start (),
.rx_rst ()
);
reg flag_frame_sync_slave = 0;
reg recevied_cur_slot_id_valid_slave = 0;
reg [7:0] recevied_cur_slot_id_slave = 7;
reg [7:0] local_id_slave = 10;
reg [7:0] cnt = 0;
always @(posedge clk) begin
if (cnt < 8'hFF) begin
cnt <= cnt + 1;
end
end
always @(posedge clk) begin
if (cnt == 8'hF3) begin
flag_frame_sync_slave <= 1;
end
else begin
flag_frame_sync_slave <= 0;
end
if (cnt == 8'hFE) begin
recevied_cur_slot_id_valid_slave <= 1;
end
else begin
recevied_cur_slot_id_valid_slave <= 0;
end
end
tdma u_tdma_slave (
.clk (clk),
.rst (rst),
.flag_frame_sync (flag_frame_sync_slave),
.tdma_slot_len (24'd7500),
.tdma_tic_2_ps (24'd6000),
.tdma_slot_num (8'd10),
.local_id (local_id_slave),
.recevied_cur_slot_id_valid(recevied_cur_slot_id_valid_slave),
.recevied_cur_slot_id (recevied_cur_slot_id_slave),
.intr_2ps (),
.tx_start (),
.rx_rst ()
);
endmodule