625 lines
18 KiB
Verilog
625 lines
18 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2020/01/04 21:09:20
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// Design Name:
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// Module Name: data_equalizer
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module data_equalizer(
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input clk,
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input rst,
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input EQUenable_vio,
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input nd_pilot2,
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input flag_ChnEstFFT_done, //信道估计两次fft输入完毕后拉高1clk(Chn_Estimate给出)
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//数据的fifo，4个
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input [9:0] dout_data1i,
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input [9:0] dout_data1q,
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output reg rd_en_data1 = 1'd0,
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input [9:0] dout_data2i,
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input [9:0] dout_data2q,
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output reg rd_en_data2 = 1'd0,
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input flag_dataow, //拉高1clk，说明一段数据ow存储完毕，后端可开始连续读取
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//fft核
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input [25:0] fft_out_i,
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input [25:0] fft_out_q,
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input fft_out_nd,
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input [7:0] fft_index,
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output reg [16:0] fft_in_i = 17'd0,
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output reg [16:0] fft_in_q = 17'd0,
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output reg fft_in_nd = 1'd0,
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//ifft核
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input [28:0] ifft_out_i,
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input [28:0] ifft_out_q,
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input ifft_out_nd,
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input [7:0] ifft_index,
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output reg [19:0] ifft_in_i = 20'd0,
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output reg [19:0] ifft_in_q = 20'd0,
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output reg ifft_in_nd = 1'd0,
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//MMSE信道估计结果RAM
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output reg [7:0] addrout_MMSE = 8'd0,
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input [21:0] dout_MMSE,
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//均衡结果输出
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output reg nd_SC_FDE_dout = 1'd0,
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output reg [9:0] SC_FDE_douti = 10'd0,
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output reg [9:0] SC_FDE_doutq = 10'd0,
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//debug,溢出标志
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output reg flagoverflow_ifftindata_28to20i = 1'd0, //均衡完毕后（频域结果）的截位，即乘法器输出结果的截位，28截到20
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output reg flagoverflow_ifftindata_28to20q = 1'd0, //均衡完毕后（频域结果）的截位，即乘法器输出结果的截位，28截到20
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output reg flagoverflow_fftdata_26to16i = 1'd0, //数据段ow的fft输出截位，26截到16
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output reg flagoverflow_fftdata_26to16q = 1'd0, //数据段ow的fft输出截位，26截到16
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output reg flagoverflow_FDE_dataout_29to10i = 1'd0, //ifft结果截位，即均衡结果处，结果先除掉低8位，29-7=22截到10
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output reg flagoverflow_FDE_dataout_29to10q = 1'd0 //ifft结果截位，即均衡结果处，结果先除掉低8位，29-7=22截到10
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);
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//----------------------------------------------------fft的输入控制状态机---------------------------------------------------------//
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reg [3:0] state_fftin = 4'd0;
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reg [7:0] cnt_256 = 8'd0;
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always @(posedge clk)begin
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if(rst)begin
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state_fftin <= 4'd0;
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cnt_256 <= 8'd0;
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rd_en_data1 <= 1'd0;
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rd_en_data2 <= 1'd0;
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fft_in_i <= 17'd0;
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fft_in_q <= 17'd0;
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fft_in_nd <= 1'd0;
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end
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else begin
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case(state_fftin)
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//帧间复位结束后，等待nd_pilot2,即导频部分全部到达
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4'd0:begin
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fft_in_i <= 17'd0;
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fft_in_q <= 17'd0;
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fft_in_nd <= 1'd0;
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if(nd_pilot2) state_fftin <= state_fftin + 4'd1;
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else state_fftin <= state_fftin;
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end
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//等待flag_ChnEstFFT_done,即信道估计的两次fft输入全部完成
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4'd1:begin
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fft_in_i <= 17'd0;
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fft_in_q <= 17'd0;
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fft_in_nd <= 1'd0;
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if(flag_ChnEstFFT_done) state_fftin <= state_fftin + 4'd1;
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else state_fftin <= state_fftin;
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end
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//计数60clk,开始输入第一组data的ow给fft，保证其输出的时候MMSE信道估计结果已全部准备完毕
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4'd2:begin
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fft_in_i <= 17'd0;
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fft_in_q <= 17'd0;
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fft_in_nd <= 1'd0;
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rd_en_data2 <= 1'd0;
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if(cnt_256==8'd60) begin
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rd_en_data1 <= 1'd1;
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cnt_256 <= 8'd0;
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state_fftin <= state_fftin + 4'd1;
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end
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else begin
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rd_en_data1 <= 1'd0;
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cnt_256 <= cnt_256 + 8'd1;
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state_fftin <= state_fftin;
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end
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end
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//从rd_en_data1为1的第一个clk开始，输出第0组数据。rd_en_data1保持有效共需256clk，即最后一个clk的数据出到出口时仍需一个读nd（用于读空fifo）
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4'd3:begin
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rd_en_data2 <= 1'd0;
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if(cnt_256==8'd254) begin
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rd_en_data1 <= 1'd1;
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fft_in_i <= {{7{dout_data1i[9]}},dout_data1i};
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fft_in_q <= {{7{dout_data1q[9]}},dout_data1q};
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fft_in_nd <= 1'd1;
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cnt_256 <= 6'd0;
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state_fftin <= state_fftin + 4'd1;
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end
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else begin
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rd_en_data1 <= 1'd1;
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fft_in_i <= {{7{dout_data1i[9]}},dout_data1i};
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fft_in_q <= {{7{dout_data1q[9]}},dout_data1q};
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fft_in_nd <= 1'd1;
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cnt_256 <= cnt_256 + 6'd1;
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state_fftin <= state_fftin;
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end
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end
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4'd4:begin
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rd_en_data2 <= 1'd0;
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rd_en_data1 <= 1'd0;
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fft_in_i <= {{7{dout_data1i[9]}},dout_data1i};
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fft_in_q <= {{7{dout_data1q[9]}},dout_data1q};
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fft_in_nd <= 1'd1;
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cnt_256 <= 6'd0;
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state_fftin <= state_fftin + 4'd1;
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end
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//data1读空，等待flag_dataow，说明下一个256数据段缓存完毕，可以取用
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4'd5:begin
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fft_in_i <= 17'd0;
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fft_in_q <= 17'd0;
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fft_in_nd <= 1'd0;
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rd_en_data1 <= 1'd0;
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cnt_256 <= 8'd0;
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if(flag_dataow) begin
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rd_en_data2 <= 1'd1;
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state_fftin <= state_fftin + 4'd1;
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end
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else begin
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rd_en_data2 <= 1'd0;
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state_fftin <= state_fftin;
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end
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end
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//从rd_en_data2为1的第一个clk开始，输出第0组数据。rd_en_data2保持有效共需256clk，即最后一个clk的数据出到出口时仍需一个读nd（用于读空fifo）
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4'd6:begin
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rd_en_data1 <= 1'd0;
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if(cnt_256==8'd254) begin
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rd_en_data2 <= 1'd1;
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fft_in_i <= {{7{dout_data2i[9]}},dout_data2i};
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fft_in_q <= {{7{dout_data2q[9]}},dout_data2q};
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fft_in_nd <= 1'd1;
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cnt_256 <= 6'd0;
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state_fftin <= state_fftin + 4'd1;
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end
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else begin
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rd_en_data2 <= 1'd1;
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fft_in_i <= {{7{dout_data2i[9]}},dout_data2i};
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fft_in_q <= {{7{dout_data2q[9]}},dout_data2q};
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fft_in_nd <= 1'd1;
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cnt_256 <= cnt_256 + 6'd1;
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state_fftin <= state_fftin;
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end
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end
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4'd7:begin
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rd_en_data2 <= 1'd0;
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rd_en_data1 <= 1'd0;
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fft_in_i <= {{7{dout_data2i[9]}},dout_data2i};
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fft_in_q <= {{7{dout_data2q[9]}},dout_data2q};
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fft_in_nd <= 1'd1;
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cnt_256 <= 6'd0;
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state_fftin <= state_fftin + 4'd1;
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end
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//data2读空，等待flag_dataow，说明下一个256数据段缓存完毕，可以取用；或等待nd_pilot2，说明本数据段结束，下一数据段的导频缓存完毕
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4'd8:begin
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fft_in_i <= 17'd0;
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fft_in_q <= 17'd0;
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fft_in_nd <= 1'd0;
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rd_en_data2 <= 1'd0;
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cnt_256 <= 8'd0;
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if(flag_dataow) begin
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rd_en_data1 <= 1'd1;
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state_fftin <= 4'd3;
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end
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else begin
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if(nd_pilot2) begin
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rd_en_data1 <= 1'd0;
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state_fftin <= 4'd1;
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end
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else begin
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rd_en_data1 <= 1'd0;
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state_fftin <= state_fftin;
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end
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end
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end
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default:state_fftin <= 4'd0;
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endcase
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end
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end
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//----------------------------------------------------fft的输出控制状态机---------------------------------------------------------//
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reg [1:0] state_fftout = 2'd0;
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reg fft_out_nd_d1 = 1'd0;
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reg [25:0] fft_out_i_d1 = 26'd0;
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reg [25:0] fft_out_q_d1 = 26'd0;
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always @(posedge clk)begin
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if(rst)begin
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state_fftout <= 2'd0;
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fft_out_nd_d1 <= 1'd0;
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fft_out_i_d1 <= 26'd0;
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fft_out_q_d1 <= 26'd0;
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end
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else begin
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case(state_fftout)
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//帧间复位结束后，等待nd_pilot2,即导频部分全部到达
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2'd0:begin
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fft_out_nd_d1 <= 1'd0;
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fft_out_i_d1 <= 26'd0;
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fft_out_q_d1 <= 26'd0;
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if(nd_pilot2) state_fftout <= state_fftout + 2'd1;
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else state_fftout <= state_fftout;
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end
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//等待flag_ChnEstFFT_done,即信道估计的两次fft输入全部完成
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2'd1:begin
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fft_out_nd_d1 <= 1'd0;
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fft_out_i_d1 <= 26'd0;
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fft_out_q_d1 <= 26'd0;
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if(flag_ChnEstFFT_done) state_fftout <= state_fftout + 2'd1;
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else state_fftout <= state_fftout;
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end
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//等待第一组fft结果输出完毕。此组结果应为信道估计的第二次fft结果，本模块不取用
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2'd2:begin
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fft_out_nd_d1 <= 1'd0;
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fft_out_i_d1 <= 26'd0;
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fft_out_q_d1 <= 26'd0;
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if(fft_index==8'd255) state_fftout <= state_fftout + 2'd1;
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else state_fftout <= state_fftout;
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end
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//fft_out_nd指示fft结果有效。将fft输出延时1clk。nd_pilot2有效说明下一帧的导频部分输入完毕，转回状态1
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2'd3:begin
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fft_out_nd_d1 <= fft_out_nd;
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fft_out_i_d1 <= fft_out_i;
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fft_out_q_d1 <= fft_out_q;
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if(nd_pilot2) state_fftout <= 2'd1;
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else state_fftout <= state_fftout;
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end
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endcase
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end
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end
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//----------------------------------------------------复数乘法器+输出截位及溢出标志---------------------------------------------------------//
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reg mulin_nd = 1'd0;
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reg [15:0] mulin_ai = 16'd0;
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reg [15:0] mulin_aq = 16'd0;
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reg [10:0] mulin_bi = 11'd0;
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reg [10:0] mulin_bq = 11'd0;
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wire mulout_nd;
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wire[63:0] mulout_data;
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SC_FDE_commul SC_FDE_commul (
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.aclk (clk), // input wire aclk
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.s_axis_a_tvalid (mulin_nd), // input wire s_axis_a_tvalid
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.s_axis_a_tdata ({mulin_aq,mulin_ai}), // input wire [31 : 0] s_axis_a_tdata
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.s_axis_b_tvalid (mulin_nd), // input wire s_axis_b_tvalid
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.s_axis_b_tdata ({5'd0,mulin_bq,5'd0,mulin_bi}), // input wire [31 : 0] s_axis_b_tdata
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.m_axis_dout_tvalid (mulout_nd), // output wire m_axis_dout_tvalid
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.m_axis_dout_tdata (mulout_data) // output wire [63 : 0] m_axis_dout_tdata
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);
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wire [27:0] mulout_datai;
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wire [27:0] mulout_dataq;
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assign mulout_datai = mulout_data[27:0];
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assign mulout_dataq = mulout_data[59:32];
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reg mulifft_nd = 1'd0;
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reg [19:0] mulifft_datai = 20'd0;
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reg [19:0] mulifft_dataq = 20'd0;
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always @(posedge clk)begin
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if(rst)begin
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mulifft_nd <= 1'd0;
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mulifft_datai <= 20'd0;
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mulifft_dataq <= 20'd0;
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flagoverflow_ifftindata_28to20i <= 1'd0;
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flagoverflow_ifftindata_28to20q <= 1'd0;
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end
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else begin
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if(mulout_nd) begin
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mulifft_nd <= 1'd1;
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if(mulout_datai[27:19]!=9'd511&&mulout_datai[27:19]!=9'd0) begin
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flagoverflow_ifftindata_28to20i <= 1'd1;
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mulifft_datai <= (mulout_datai[27])? 20'b1000_0000_0000_0000_0000 : 20'b0111_1111_1111_1111_1111;
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end
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else begin
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flagoverflow_ifftindata_28to20i <= 1'd0;
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mulifft_datai <= mulout_datai[19:0];
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end
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if(mulout_dataq[27:19]!=9'd511&&mulout_dataq[27:19]!=9'd0) begin
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flagoverflow_ifftindata_28to20q <= 1'd1;
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mulifft_dataq <= (mulout_dataq[27])? 20'b1000_0000_0000_0000_0000 : 20'b0111_1111_1111_1111_1111;
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end
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else begin
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flagoverflow_ifftindata_28to20q <= 1'd0;
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mulifft_dataq <= mulout_dataq[19:0];
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end
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end
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else begin
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mulifft_nd <= 1'd0;
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mulifft_datai <= 20'd0;
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mulifft_dataq <= 20'd0;
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flagoverflow_ifftindata_28to20i <= 1'd0;
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flagoverflow_ifftindata_28to20q <= 1'd0;
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end
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end
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end
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//----------------------------------------------------复数乘法器输入控制状态机---------------------------------------------------------//
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reg mulin_nd_d0 = 1'd0;
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reg [15:0] mulin_i_d0 = 16'd0;
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reg [15:0] mulin_q_d0 = 16'd0;
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always @(posedge clk)begin
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if(rst)begin
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addrout_MMSE <= 8'd0;
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mulin_nd_d0 <= 1'd0;
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mulin_i_d0 <= 16'd0;
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mulin_q_d0 <= 16'd0;
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flagoverflow_fftdata_26to16i <= 1'd0;
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flagoverflow_fftdata_26to16q <= 1'd0;
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mulin_nd <= 1'd0;
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mulin_ai <= 16'd0;
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mulin_aq <= 16'd0;
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mulin_bi <= 11'd0;
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mulin_bq <= 11'd0;
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end
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else begin
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//fft输出再延时1clk，利用这个延时取出mmse信道估计结果。截位到16bit，设置溢出标志
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if(fft_out_nd_d1) begin
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addrout_MMSE <= addrout_MMSE + 8'd1;
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mulin_nd_d0 <= 1'd1;
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if(fft_out_i_d1[25:15]!=11'd2047&&fft_out_i_d1[25:15]!=11'd0) begin
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flagoverflow_fftdata_26to16i <= 1'd1;
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mulin_i_d0 <= (fft_out_i_d1[25])? 16'b1000_0000_0000_0000 : 16'b0111_1111_1111_1111;
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end
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else begin
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flagoverflow_fftdata_26to16i <= 1'd0;
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mulin_i_d0 <= fft_out_i_d1[15:0];
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end
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if(fft_out_q_d1[25:15]!=11'd2047&&fft_out_q_d1[25:15]!=11'd0) begin
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flagoverflow_fftdata_26to16q <= 1'd1;
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mulin_q_d0 <= (fft_out_q_d1[25])? 16'b1000_0000_0000_0000 : 16'b0111_1111_1111_1111;
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end
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else begin
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flagoverflow_fftdata_26to16q <= 1'd0;
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mulin_q_d0 <= fft_out_q_d1[15:0];
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end
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end
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else begin
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addrout_MMSE <= 8'd0;
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mulin_nd_d0 <= 1'd0;
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mulin_i_d0 <= 16'd0;
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mulin_q_d0 <= 16'd0;
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flagoverflow_fftdata_26to16i <= 1'd0;
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||
flagoverflow_fftdata_26to16q <= 1'd0;
|
||
end
|
||
|
||
if(mulin_nd_d0) begin
|
||
mulin_nd <= 1'd1;
|
||
mulin_ai <= mulin_i_d0;
|
||
mulin_aq <= mulin_q_d0;
|
||
if(EQUenable_vio) begin
|
||
mulin_bi <= dout_MMSE[10:0];
|
||
mulin_bq <= dout_MMSE[21:11];
|
||
end
|
||
else begin
|
||
mulin_bi <= 11'd1;
|
||
mulin_bq <= 11'd0;
|
||
end
|
||
end
|
||
else begin
|
||
mulin_nd <= 1'd0;
|
||
mulin_ai <= 16'd0;
|
||
mulin_aq <= 16'd0;
|
||
mulin_bi <= 11'd0;
|
||
mulin_bq <= 11'd0;
|
||
end
|
||
end
|
||
end
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
//----------------------------------------------------乘法器输出->ifft的输入控制------------------------------------------------------//
|
||
always @(posedge clk)begin
|
||
if(rst)begin
|
||
ifft_in_i <= 20'd0;
|
||
ifft_in_q <= 20'd0;
|
||
ifft_in_nd <= 1'd0;
|
||
end
|
||
else begin
|
||
if(mulifft_nd) begin
|
||
ifft_in_i <= mulifft_datai;
|
||
ifft_in_q <= mulifft_dataq;
|
||
ifft_in_nd <= 1'd1;
|
||
end
|
||
else begin
|
||
ifft_in_i <= 20'd0;
|
||
ifft_in_q <= 20'd0;
|
||
ifft_in_nd <= 1'd0;
|
||
end
|
||
end
|
||
end
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
//-----------------------------------------------ifft的输出控制+截位+溢出标志设置--------------------------------------------------//
|
||
reg ifft_out_ce = 1'd0;
|
||
reg ifft_out_nd_d1 = 1'd0;
|
||
reg [28:0] ifft_out_i_d1 = 29'd0;
|
||
reg [28:0] ifft_out_q_d1 = 29'd0;
|
||
|
||
always @(posedge clk)begin
|
||
if(rst)begin
|
||
ifft_out_ce <= 1'd0;
|
||
ifft_out_nd_d1 <= 1'd0;
|
||
ifft_out_i_d1 <= 29'd0;
|
||
ifft_out_q_d1 <= 29'd0;
|
||
end
|
||
else begin
|
||
if(ifft_out_ce==1'd0) begin
|
||
if(flag_ChnEstFFT_done) begin
|
||
ifft_out_ce <= 1'd1;
|
||
end
|
||
else begin
|
||
ifft_out_ce <= 1'd0;
|
||
end
|
||
ifft_out_nd_d1 <= 1'd0;
|
||
ifft_out_i_d1 <= 29'd0;
|
||
ifft_out_q_d1 <= 29'd0;
|
||
end
|
||
else begin
|
||
if(nd_pilot2) begin
|
||
ifft_out_ce <= 1'd0;
|
||
end
|
||
else begin
|
||
ifft_out_ce <= 1'd1;
|
||
end
|
||
ifft_out_nd_d1 <= ifft_out_nd;
|
||
ifft_out_i_d1 <= ifft_out_i;
|
||
ifft_out_q_d1 <= ifft_out_q;
|
||
end
|
||
end
|
||
end
|
||
|
||
|
||
always @(posedge clk)begin
|
||
if(rst)begin
|
||
nd_SC_FDE_dout <= 1'd0;
|
||
SC_FDE_douti <= 10'd0;
|
||
SC_FDE_doutq <= 10'd0;
|
||
flagoverflow_FDE_dataout_29to10i <= 1'd0;
|
||
flagoverflow_FDE_dataout_29to10q <= 1'd0;
|
||
end
|
||
else begin
|
||
if(ifft_out_nd_d1) begin
|
||
nd_SC_FDE_dout <= 1'd1;
|
||
if(EQUenable_vio) begin //均衡开启，结果保留10bit，低位截掉8+5=13bit
|
||
if(ifft_out_i_d1[28:22]!=7'd127&&ifft_out_i_d1[28:22]!=7'd0) begin
|
||
flagoverflow_FDE_dataout_29to10i <= 1'd1;
|
||
SC_FDE_douti <= (ifft_out_i_d1[28])? 10'b100000_0000 : 10'b01_1111_1111;
|
||
end
|
||
else begin
|
||
flagoverflow_FDE_dataout_29to10i <= 1'd0;
|
||
SC_FDE_douti <= ifft_out_i_d1[22:13];
|
||
end
|
||
if(ifft_out_q_d1[28:22]!=7'd127&&ifft_out_q_d1[28:22]!=7'd0) begin
|
||
flagoverflow_FDE_dataout_29to10q <= 1'd1;
|
||
SC_FDE_doutq <= (ifft_out_q_d1[28])? 10'b100000_0000 : 10'b01_1111_1111;
|
||
end
|
||
else begin
|
||
flagoverflow_FDE_dataout_29to10q <= 1'd0;
|
||
SC_FDE_doutq <= ifft_out_q_d1[22:13];
|
||
end
|
||
end
|
||
else begin //均衡关闭，结果保留10bit，低位截掉8bit（结果应与输入相同）
|
||
if(ifft_out_i_d1[28:17]!=12'd4095&&ifft_out_i_d1[28:17]!=12'd0) begin
|
||
flagoverflow_FDE_dataout_29to10i <= 1'd1;
|
||
SC_FDE_douti <= (ifft_out_i_d1[28])? 10'b100000_0000 : 10'b01_1111_1111;
|
||
end
|
||
else begin
|
||
flagoverflow_FDE_dataout_29to10i <= 1'd0;
|
||
SC_FDE_douti <= ifft_out_i_d1[17:8];
|
||
end
|
||
if(ifft_out_q_d1[28:17]!=12'd4095&&ifft_out_q_d1[28:17]!=12'd0) begin
|
||
flagoverflow_FDE_dataout_29to10q <= 1'd1;
|
||
SC_FDE_doutq <= (ifft_out_q_d1[28])? 10'b100000_0000 : 10'b01_1111_1111;
|
||
end
|
||
else begin
|
||
flagoverflow_FDE_dataout_29to10q <= 1'd0;
|
||
SC_FDE_doutq <= ifft_out_q_d1[17:8];
|
||
end
|
||
end
|
||
end
|
||
else begin
|
||
nd_SC_FDE_dout <= 1'd0;
|
||
SC_FDE_douti <= 10'd0;
|
||
SC_FDE_doutq <= 10'd0;
|
||
flagoverflow_FDE_dataout_29to10i <= 1'd0;
|
||
flagoverflow_FDE_dataout_29to10q <= 1'd0;
|
||
end
|
||
end
|
||
end
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
//------------------------------------------------------仿真文件保存---------------------------------------------------//
|
||
// integer handle01;
|
||
// integer handle02;
|
||
// integer handle03;
|
||
// integer handle04;
|
||
// integer handle05;
|
||
// integer handle06;
|
||
|
||
// reg enable1 = 0;
|
||
// initial begin
|
||
|
||
// handle01=$fopen("mulin_ai.txt","w"); $fclose(handle01);
|
||
// handle02=$fopen("mulin_aq.txt","w"); $fclose(handle02);
|
||
// handle03=$fopen("mulin_bi.txt","w"); $fclose(handle03);
|
||
// handle04=$fopen("mulin_bq.txt","w"); $fclose(handle04);
|
||
// handle05=$fopen("mulout_datai.txt","w"); $fclose(handle05);
|
||
// handle06=$fopen("mulout_dataq.txt","w"); $fclose(handle06);
|
||
|
||
// #10;
|
||
// enable1 = 1;
|
||
// end
|
||
|
||
// always@(posedge clk)begin
|
||
// if(enable1)begin
|
||
|
||
// if(mulin_nd)begin
|
||
// handle01=$fopen("mulin_ai.txt","a+");$fwrite(handle01,"%d\n",$signed(mulin_ai));$fclose(handle01);
|
||
// handle02=$fopen("mulin_aq.txt","a+");$fwrite(handle02,"%d\n",$signed(mulin_aq));$fclose(handle02);
|
||
// handle03=$fopen("mulin_bi.txt","a+");$fwrite(handle03,"%d\n",$signed(mulin_bi));$fclose(handle03);
|
||
// handle04=$fopen("mulin_bq.txt","a+");$fwrite(handle04,"%d\n",$signed(mulin_bq));$fclose(handle04);
|
||
// end
|
||
// if(mulout_nd)begin
|
||
// handle05=$fopen("mulout_datai.txt","a+");$fwrite(handle05,"%d\n",$signed(mulout_datai));$fclose(handle05);
|
||
// handle06=$fopen("mulout_dataq.txt","a+");$fwrite(handle06,"%d\n",$signed(mulout_dataq));$fclose(handle06);
|
||
// end
|
||
// end
|
||
// end
|
||
|
||
|
||
|
||
endmodule
|