feat: 增加跨域电源接口板工程
This commit is contained in:
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################################################################################
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############################### Project Specific ###############################
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################################################################################
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# everything
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*
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# git related
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!/.gitignore
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!/.gitattributes
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# project documents
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!/*.md
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!/*.txt
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################################################################################
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############################### Vivado Specific ################################
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################################################################################
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# xpr: needed for recreating design
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!/*.xpr
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# source: include everything
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!/*.srcs/
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!/*.srcs/**/*
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# runs: exclude everything but design run results
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!/*.runs/
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!/*.runs/impl_*/
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!/*.runs/impl_*/*.bit
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!/*.runs/impl_*/*.ltx
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# xsa (Xilinx support archive): include for ps
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!/*.xsa
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################################################################################
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################################ Vitis Specific ################################
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################################################################################
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# include sdk directory and everything in it
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!/vitis*/
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!/vitis*/**
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/vitis*/**.log
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/vitis*/.analytics
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# exclude some obscure hidden SDK folders
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/vitis*/.metadata/
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/vitis*/.sdk/
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/vitis*/RemoteSystemsTempFiles/
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/vitis*/webtalk/
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# hw_platform: exclude the entire hw_platform folder, as everything can be
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# generated from the .hdf file. Make sure to include the bitstream in the .hdf
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# file when exporting from Vivado!
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/vitis*/*_hw_platform_*/
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# BSP: only keep `.cproject`, `.project`, `.sdkproject`, `.system.mss` and
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# Makefile, ps lib files are regenerated automatically
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/vitis*/*_bsp/*
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!/vitis*/*_bsp/*.cproject
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!/vitis*/*_bsp/*.project
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!/vitis*/*_bsp/*.sdkproject
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!/vitis*/*_bsp/system.mss
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!/vitis*/*_bsp/Makefile
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# Application: ignored file patterns, exclude Debug & Release folders
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/vitis*/**/*.o
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/vitis*/**/*.d
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/vitis*/**/*.a
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/vitis*/*/Debug/
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/vitis*/*/Release/
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################################################################################
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############################ Vivado & Vitis Common #############################
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################################################################################
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# file patterns that should always be ignored (journal files, log files, dump
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# files that are created upon Vivado/SDK errors)
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*.jou
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*.log
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*.backup.jou
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*.backup.log
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*.upgrade_log
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*.dmp
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*.debug
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vivado_pid*
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# vivado workspace files
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xsim.dir/
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xvlog.pb
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# Xilinx tools generated files
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.metadata/
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.settings/
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.wsdata/
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.Xil/
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logs/
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Packages/
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*.log*
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# System generated files
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# -- macOS
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.DS_Store
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.AppleDouble
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.LSOverride
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._*
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# -- Windows
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Thumbs.db
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ehthumbs.db
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Desktop.ini
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# -- Linux
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*~
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# IDEs and editors' files
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*.idea
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*.vscode
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*.sublime-workspace
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*.sublime-project
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@@ -0,0 +1,148 @@
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{
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"ltx_root": {
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"version": 4,
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"minor": 0,
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"ltx_data": [
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{
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"name": "EDA_PROBESET",
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"active": true,
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"debug_cores": [
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{
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"type": "XSDB_V3",
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"name": "dbg_hub",
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"spec": "labtools_xsdbm_v3",
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"clk_input_freq_hz": "30000301"
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},
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{
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"type": "ILA_V3",
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"name": "u_ila_cnt",
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"spec": "labtools_ila_v6",
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"ipName": "ila",
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"core_location": {
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"user_chain": 1,
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"slave_index": 0,
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"bscan_switch_index": 0
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},
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"uuid": "E055752C10485C0D9D7994B1C888EC3A",
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"pins": [
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{
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"name": "probe0",
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"id": 0,
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"type": "DATA_TRIGGER",
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"direction": "IN",
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"isVector": true,
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"leftIndex": 0,
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"rightIndex": 31,
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"portIndex": 0,
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"nets": [
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{
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"name": "cnt",
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"isBus": true,
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"subnets": [
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{
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"name": "cnt[31]"
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},
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{
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"name": "cnt[30]"
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},
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{
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"name": "cnt[29]"
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},
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{
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"name": "cnt[28]"
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},
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{
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"name": "cnt[27]"
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},
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{
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"name": "cnt[26]"
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},
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{
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"name": "cnt[25]"
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},
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{
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"name": "cnt[24]"
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},
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{
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"name": "cnt[23]"
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},
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{
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"name": "cnt[22]"
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},
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{
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"name": "cnt[21]"
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},
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{
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"name": "cnt[20]"
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},
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{
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"name": "cnt[19]"
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},
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{
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"name": "cnt[18]"
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},
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{
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"name": "cnt[17]"
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},
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{
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"name": "cnt[16]"
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},
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{
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"name": "cnt[15]"
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},
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{
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"name": "cnt[14]"
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},
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{
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"name": "cnt[13]"
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},
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{
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"name": "cnt[12]"
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},
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{
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"name": "cnt[11]"
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},
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{
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"name": "cnt[10]"
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},
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{
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"name": "cnt[9]"
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},
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{
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"name": "cnt[8]"
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},
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{
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"name": "cnt[7]"
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},
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{
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"name": "cnt[6]"
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},
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{
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"name": "cnt[5]"
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},
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{
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"name": "cnt[4]"
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},
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{
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"name": "cnt[3]"
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},
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{
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"name": "cnt[2]"
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},
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{
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"name": "cnt[1]"
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},
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{
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"name": "cnt[0]"
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}
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]
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}
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]
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}
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]
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}
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]
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}
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]
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}
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}
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Binary file not shown.
@@ -0,0 +1,148 @@
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{
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"ltx_root": {
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"version": 4,
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"minor": 0,
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"ltx_data": [
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||||
{
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||||
"name": "EDA_PROBESET",
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"active": true,
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"debug_cores": [
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{
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"type": "XSDB_V3",
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"name": "dbg_hub",
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"spec": "labtools_xsdbm_v3",
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"clk_input_freq_hz": "30000301"
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},
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{
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"type": "ILA_V3",
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"name": "u_ila_cnt",
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"spec": "labtools_ila_v6",
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"ipName": "ila",
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"core_location": {
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"user_chain": 1,
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"slave_index": 0,
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||||
"bscan_switch_index": 0
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||||
},
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"uuid": "E055752C10485C0D9D7994B1C888EC3A",
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||||
"pins": [
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{
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"name": "probe0",
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"id": 0,
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"type": "DATA_TRIGGER",
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"direction": "IN",
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"isVector": true,
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||||
"leftIndex": 0,
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"rightIndex": 31,
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||||
"portIndex": 0,
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||||
"nets": [
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||||
{
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||||
"name": "cnt",
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||||
"isBus": true,
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||||
"subnets": [
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||||
{
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||||
"name": "cnt[31]"
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||||
},
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||||
{
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"name": "cnt[30]"
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},
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||||
{
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"name": "cnt[29]"
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},
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{
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"name": "cnt[28]"
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},
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{
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"name": "cnt[27]"
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},
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{
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"name": "cnt[26]"
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},
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{
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"name": "cnt[25]"
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},
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||||
{
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"name": "cnt[24]"
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},
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{
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"name": "cnt[23]"
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},
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||||
{
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"name": "cnt[22]"
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},
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{
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"name": "cnt[21]"
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},
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{
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"name": "cnt[20]"
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},
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||||
{
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||||
"name": "cnt[19]"
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||||
},
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||||
{
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||||
"name": "cnt[18]"
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},
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||||
{
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||||
"name": "cnt[17]"
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},
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||||
{
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||||
"name": "cnt[16]"
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},
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||||
{
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||||
"name": "cnt[15]"
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},
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||||
{
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||||
"name": "cnt[14]"
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},
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||||
{
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||||
"name": "cnt[13]"
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},
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||||
{
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||||
"name": "cnt[12]"
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},
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||||
{
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||||
"name": "cnt[11]"
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},
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||||
{
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||||
"name": "cnt[10]"
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||||
},
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||||
{
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||||
"name": "cnt[9]"
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||||
},
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||||
{
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"name": "cnt[8]"
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},
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{
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"name": "cnt[7]"
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},
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{
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"name": "cnt[6]"
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},
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||||
{
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"name": "cnt[5]"
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},
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||||
{
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"name": "cnt[4]"
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},
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||||
{
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"name": "cnt[3]"
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},
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||||
{
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||||
"name": "cnt[2]"
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},
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||||
{
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"name": "cnt[1]"
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},
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||||
{
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||||
"name": "cnt[0]"
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||||
}
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||||
]
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||||
}
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||||
]
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||||
}
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]
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}
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]
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}
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]
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}
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}
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@@ -0,0 +1,179 @@
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# dx_z7100_power_interface
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## Timing Assertions Section
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## Physical Constraints Section
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# GLINK
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set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVCMOS33} [get_ports clk_glink_25m ] ;# GLNIK_25M
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set_property -dict {PACKAGE_PIN N8 } [get_ports clk_glink_125m_p ] ;# GLINK_REFCLK_P
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set_property -dict {PACKAGE_PIN V6 } [get_ports {glink_rx_p[0]} ] ;# GLINK_BUF_RX1_P
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set_property -dict {PACKAGE_PIN U4 } [get_ports {glink_rx_p[1]} ] ;# GLINK_BUF_RX2_P
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# set_property -dict {PACKAGE_PIN T2 } [get_ports {glink_tx_p[0]} ] ;# GLINK_BUF_TX1_P
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# set_property -dict {PACKAGE_PIN R4 } [get_ports {glink_tx_p[1]} ] ;# GLINK_BUF_TX2_P
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# KK LVDS
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set_property -dict {PACKAGE_PIN Y25 IOSTANDARD LVCMOS33} [get_ports kk_rx_rf ] ;# KK_RX_RF
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set_property -dict {PACKAGE_PIN Y30 IOSTANDARD LVCMOS33} [get_ports kk_rx_ss ] ;# KK_RX_SS
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set_property -dict {PACKAGE_PIN AA30 IOSTANDARD LVCMOS33} [get_ports kk_rx_rng[0] ] ;# KK_RX_PNG0
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set_property -dict {PACKAGE_PIN AB29 IOSTANDARD LVCMOS33} [get_ports kk_rx_rng[1] ] ;# KK_RX_PNG1
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set_property -dict {PACKAGE_PIN AB30 IOSTANDARD LVCMOS33} [get_ports kk_rx_pwdnb ] ;# KK_RX_PWDNB
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set_property -dict {PACKAGE_PIN AC28 IOSTANDARD LVCMOS33} [get_ports kk_rx_pclk ] ;# KK_RX_PCLK_OUT
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set_property -dict {PACKAGE_PIN AB26 IOSTANDARD LVCMOS33} [get_ports kk_rx_lock ] ;# KK_RX_LOCK
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set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVCMOS33} [get_ports kk_rx_de ] ;# KK_RX_DE_OUT
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||||
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set_property -dict {PACKAGE_PIN AD26 IOSTANDARD LVCMOS33} [get_ports kk_rx_cntl[0] ] ;# KK_RX_CNTL_OUT0
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||||
set_property -dict {PACKAGE_PIN AD30 IOSTANDARD LVCMOS33} [get_ports kk_rx_cntl[1] ] ;# KK_RX_CNTL_OUT1
|
||||
set_property -dict {PACKAGE_PIN AE30 IOSTANDARD LVCMOS33} [get_ports kk_rx_cntl[2] ] ;# KK_RX_CNTL_OUT2
|
||||
set_property -dict {PACKAGE_PIN AC29 IOSTANDARD LVCMOS33} [get_ports kk_rx_cntl[3] ] ;# KK_RX_CNTL_OUT3
|
||||
set_property -dict {PACKAGE_PIN AD29 IOSTANDARD LVCMOS33} [get_ports kk_rx_cntl[4] ] ;# KK_RX_CNTL_OUT4
|
||||
set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVCMOS33} [get_ports kk_rx_cntl[5] ] ;# KK_RX_CNTL_OUT5
|
||||
set_property -dict {PACKAGE_PIN AE26 IOSTANDARD LVCMOS33} [get_ports kk_rx_cntl[6] ] ;# KK_RX_CNTL_OUT6
|
||||
set_property -dict {PACKAGE_PIN AB27 IOSTANDARD LVCMOS33} [get_ports kk_rx_cntl[7] ] ;# KK_RX_CNTL_OUT7
|
||||
set_property -dict {PACKAGE_PIN AC27 IOSTANDARD LVCMOS33} [get_ports kk_rx_cntl[8] ] ;# KK_RX_CNTL_OUT8
|
||||
|
||||
set_property -dict {PACKAGE_PIN AE28 IOSTANDARD LVCMOS33} [get_ports kk_rx_rgb[0] ] ;# KK_RX_RGB_OUT0
|
||||
set_property -dict {PACKAGE_PIN AF28 IOSTANDARD LVCMOS33} [get_ports kk_rx_rgb[1] ] ;# KK_RX_RGB_OUT1
|
||||
set_property -dict {PACKAGE_PIN AE27 IOSTANDARD LVCMOS33} [get_ports kk_rx_rgb[2] ] ;# KK_RX_RGB_OUT2
|
||||
set_property -dict {PACKAGE_PIN AF27 IOSTANDARD LVCMOS33} [get_ports kk_rx_rgb[3] ] ;# KK_RX_RGB_OUT3
|
||||
set_property -dict {PACKAGE_PIN AF29 IOSTANDARD LVCMOS33} [get_ports kk_rx_rgb[4] ] ;# KK_RX_RGB_OUT4
|
||||
set_property -dict {PACKAGE_PIN AG29 IOSTANDARD LVCMOS33} [get_ports kk_rx_rgb[5] ] ;# KK_RX_RGB_OUT5
|
||||
set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVCMOS33} [get_ports kk_rx_rgb[6] ] ;# KK_RX_RGB_OUT6
|
||||
set_property -dict {PACKAGE_PIN AG30 IOSTANDARD LVCMOS33} [get_ports kk_rx_rgb[7] ] ;# KK_RX_RGB_OUT7
|
||||
set_property -dict {PACKAGE_PIN AG26 IOSTANDARD LVCMOS33} [get_ports kk_rx_rgb[8] ] ;# KK_RX_RGB_OUT8
|
||||
set_property -dict {PACKAGE_PIN AG27 IOSTANDARD LVCMOS33} [get_ports kk_rx_rgb[9] ] ;# KK_RX_RGB_OUT9
|
||||
set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVCMOS33} [get_ports kk_rx_rgb[10] ] ;# KK_RX_RGB_OUT10
|
||||
set_property -dict {PACKAGE_PIN AF25 IOSTANDARD LVCMOS33} [get_ports kk_rx_rgb[11] ] ;# KK_RX_RGB_OUT11
|
||||
set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVCMOS33} [get_ports kk_rx_rgb[12] ] ;# KK_RX_RGB_OUT12
|
||||
set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVCMOS33} [get_ports kk_rx_rgb[13] ] ;# KK_RX_RGB_OUT13
|
||||
set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVCMOS33} [get_ports kk_rx_rgb[14] ] ;# KK_RX_RGB_OUT14
|
||||
set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVCMOS33} [get_ports kk_rx_rgb[15] ] ;# KK_RX_RGB_OUT15
|
||||
set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVCMOS33} [get_ports kk_rx_rgb[16] ] ;# KK_RX_RGB_OUT16
|
||||
set_property -dict {PACKAGE_PIN AJ29 IOSTANDARD LVCMOS33} [get_ports kk_rx_rgb[17] ] ;# KK_RX_RGB_OUT17
|
||||
|
||||
set_property -dict {PACKAGE_PIN U21 IOSTANDARD LVCMOS33} [get_ports kk_tx_pre ] ;# KK_TX_PRE
|
||||
set_property -dict {PACKAGE_PIN P30 IOSTANDARD LVCMOS33} [get_ports kk_tx_rng[0] ] ;# KK_TX_RNG0
|
||||
set_property -dict {PACKAGE_PIN R30 IOSTANDARD LVCMOS33} [get_ports kk_tx_rng[1] ] ;# KK_TX_RNG1
|
||||
set_property -dict {PACKAGE_PIN T30 IOSTANDARD LVCMOS33} [get_ports kk_tx_pwdnb ] ;# KK_TX_PWDNB
|
||||
|
||||
set_property -dict {PACKAGE_PIN U26 IOSTANDARD LVCMOS33} [get_ports clk_lvds_30m ] ;# LVDS_30M
|
||||
set_property -dict {PACKAGE_PIN R25 IOSTANDARD LVCMOS33} [get_ports kk_tx_pclk_in ] ;# KK_TX_PCLK_IN
|
||||
set_property -dict {PACKAGE_PIN V28 IOSTANDARD LVCMOS33} [get_ports kk_tx_de_in ] ;# KK_TX_DE_IN
|
||||
|
||||
set_property -dict {PACKAGE_PIN V29 IOSTANDARD LVCMOS33} [get_ports kk_tx_cntl[0] ] ;# KK_TX_CNTL_OUT0
|
||||
set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS33} [get_ports kk_tx_cntl[1] ] ;# KK_TX_CNTL_OUT1
|
||||
set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVCMOS33} [get_ports kk_tx_cntl[2] ] ;# KK_TX_CNTL_OUT2
|
||||
set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVCMOS33} [get_ports kk_tx_cntl[3] ] ;# KK_TX_CNTL_OUT3
|
||||
set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVCMOS33} [get_ports kk_tx_cntl[4] ] ;# KK_TX_CNTL_OUT4
|
||||
set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVCMOS33} [get_ports kk_tx_cntl[5] ] ;# KK_TX_CNTL_OUT5
|
||||
set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS33} [get_ports kk_tx_cntl[6] ] ;# KK_TX_CNTL_OUT6
|
||||
set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVCMOS33} [get_ports kk_tx_cntl[7] ] ;# KK_TX_CNTL_OUT7
|
||||
set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVCMOS33} [get_ports kk_tx_cntl[8] ] ;# KK_TX_CNTL_OUT8
|
||||
|
||||
set_property -dict {PACKAGE_PIN R27 IOSTANDARD LVCMOS33} [get_ports kk_tx_rgb[0] ] ;# KK_TX_RGB_OUT0
|
||||
set_property -dict {PACKAGE_PIN T27 IOSTANDARD LVCMOS33} [get_ports kk_tx_rgb[1] ] ;# KK_TX_RGB_OUT1
|
||||
set_property -dict {PACKAGE_PIN N26 IOSTANDARD LVCMOS33} [get_ports kk_tx_rgb[2] ] ;# KK_TX_RGB_OUT2
|
||||
set_property -dict {PACKAGE_PIN N27 IOSTANDARD LVCMOS33} [get_ports kk_tx_rgb[3] ] ;# KK_TX_RGB_OUT3
|
||||
set_property -dict {PACKAGE_PIN P25 IOSTANDARD LVCMOS33} [get_ports kk_tx_rgb[4] ] ;# KK_TX_RGB_OUT4
|
||||
set_property -dict {PACKAGE_PIN P26 IOSTANDARD LVCMOS33} [get_ports kk_tx_rgb[5] ] ;# KK_TX_RGB_OUT5
|
||||
set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVCMOS33} [get_ports kk_tx_rgb[6] ] ;# KK_TX_RGB_OUT6
|
||||
set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS33} [get_ports kk_tx_rgb[7] ] ;# KK_TX_RGB_OUT7
|
||||
set_property -dict {PACKAGE_PIN P23 IOSTANDARD LVCMOS33} [get_ports kk_tx_rgb[8] ] ;# KK_TX_RGB_OUT8
|
||||
set_property -dict {PACKAGE_PIN P24 IOSTANDARD LVCMOS33} [get_ports kk_tx_rgb[9] ] ;# KK_TX_RGB_OUT9
|
||||
set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS33} [get_ports kk_tx_rgb[10] ] ;# KK_TX_RGB_OUT10
|
||||
set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS33} [get_ports kk_tx_rgb[11] ] ;# KK_TX_RGB_OUT11
|
||||
set_property -dict {PACKAGE_PIN T22 IOSTANDARD LVCMOS33} [get_ports kk_tx_rgb[12] ] ;# KK_TX_RGB_OUT12
|
||||
set_property -dict {PACKAGE_PIN T23 IOSTANDARD LVCMOS33} [get_ports kk_tx_rgb[13] ] ;# KK_TX_RGB_OUT13
|
||||
set_property -dict {PACKAGE_PIN R22 IOSTANDARD LVCMOS33} [get_ports kk_tx_rgb[14] ] ;# KK_TX_RGB_OUT14
|
||||
set_property -dict {PACKAGE_PIN R23 IOSTANDARD LVCMOS33} [get_ports kk_tx_rgb[15] ] ;# KK_TX_RGB_OUT15
|
||||
set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVCMOS33} [get_ports kk_tx_rgb[16] ] ;# KK_TX_RGB_OUT16
|
||||
set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS33} [get_ports kk_tx_rgb[17] ] ;# KK_TX_RGB_OUT17
|
||||
|
||||
# YC LVDS
|
||||
set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVCMOS33} [get_ports yc_rx ] ;# LVDS_YC_RX
|
||||
set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVCMOS33} [get_ports yc_tx ] ;# LVDS_YC_TX
|
||||
|
||||
# RS422/RS485
|
||||
set_property -dict {PACKAGE_PIN W23 IOSTANDARD LVCMOS33} [get_ports rs422_gg_rxd ] ;# RS422_GG_RXD
|
||||
set_property -dict {PACKAGE_PIN AJ25 IOSTANDARD LVCMOS33} [get_ports rs422_gg_reb ] ;# RS422_GG_REB
|
||||
set_property -dict {PACKAGE_PIN AK25 IOSTANDARD LVCMOS33} [get_ports rs422_gg_de ] ;# RS422_GG_DE
|
||||
set_property -dict {PACKAGE_PIN AK22 IOSTANDARD LVCMOS33} [get_ports rs422_gg_txd ] ;# RS422_GG_TXD
|
||||
|
||||
set_property -dict {PACKAGE_PIN AJ21 IOSTANDARD LVCMOS33} [get_ports rs422_dg_rxd ] ;# RS422_DG_RXD
|
||||
set_property -dict {PACKAGE_PIN AK21 IOSTANDARD LVCMOS33} [get_ports rs422_dg_reb ] ;# RS422_DG_REB
|
||||
set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVCMOS33} [get_ports rs422_dg_de ] ;# RS422_DG_DE
|
||||
set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVCMOS33} [get_ports rs422_dg_txd ] ;# RS422_DG_TXD
|
||||
|
||||
set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS33} [get_ports rs422_ts_rxd ] ;# RS422_TS_RXD
|
||||
set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVCMOS33} [get_ports rs422_ts_reb ] ;# RS422_TS_REB
|
||||
set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVCMOS33} [get_ports rs422_ts_de ] ;# RS422_TS_DE
|
||||
set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS33} [get_ports rs422_ts_txd ] ;# RS422_TS_TXD
|
||||
|
||||
set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVCMOS33} [get_ports rs485_by_rxd ] ;# RS485_BY_RXD
|
||||
set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVCMOS33} [get_ports rs485_by_reb ] ;# RS485_BY_REB
|
||||
set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS33} [get_ports rs485_by_de ] ;# RS485_BY_DE
|
||||
set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVCMOS33} [get_ports rs485_by_txd ] ;# RS485_BY_TXD
|
||||
|
||||
set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS33} [get_ports rs422_int_mc_rxd ] ;# RS422_INT_MC_RXD
|
||||
set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS33} [get_ports rs422_int_mc_reb ] ;# RS422_INT_MC_REB
|
||||
set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS33} [get_ports rs422_int_mc_de ] ;# RS422_INT_MC_DE
|
||||
set_property -dict {PACKAGE_PIN AE22 IOSTANDARD LVCMOS33} [get_ports rs422_int_mc_txd ] ;# RS422_INT_MC_TXD
|
||||
|
||||
set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVCMOS33} [get_ports rs422_int_dh_rxd ] ;# RS422_INT_DH_RXD
|
||||
set_property -dict {PACKAGE_PIN AG20 IOSTANDARD LVCMOS33} [get_ports rs422_int_dh_reb ] ;# RS422_INT_DH_REB
|
||||
set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVCMOS33} [get_ports rs422_int_dh_de ] ;# RS422_INT_DH_DE
|
||||
set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVCMOS33} [get_ports rs422_int_dh_txd ] ;# RS422_INT_DH_TXD
|
||||
|
||||
# Inter-board Ports
|
||||
set_property -dict {PACKAGE_PIN AD10 } [get_ports clk_s2p_0_p ] ;# GTCLK0_S2P_P
|
||||
set_property -dict {PACKAGE_PIN U8 } [get_ports clk_s2p_1_p ] ;# GTCLK1_S2P_P
|
||||
|
||||
set_property -dict {PACKAGE_PIN AJ14 IOSTANDARD LVDS_25 } [get_ports f1_lvds_io_p[0] ] ;# F1_LVDS_IO1P
|
||||
set_property -dict {PACKAGE_PIN AK13 IOSTANDARD LVDS_25 } [get_ports f1_lvds_io_p[1] ] ;# F1_LVDS_IO2P
|
||||
set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD LVDS_25 } [get_ports f1_lvds_io_p[2] ] ;# F1_LVDS_IO3P
|
||||
set_property -dict {PACKAGE_PIN AJ16 IOSTANDARD LVDS_25 } [get_ports f1_lvds_io_p[3] ] ;# F1_LVDS_IO4P
|
||||
set_property -dict {PACKAGE_PIN AH18 IOSTANDARD LVDS_25 } [get_ports f1_lvds_io_p[4] ] ;# F1_LVDS_IO5P
|
||||
|
||||
set_property -dict {PACKAGE_PIN AF14 IOSTANDARD LVDS_25 } [get_ports f2_lvds_io_p[0] ] ;# F2_LVDS_IO1P
|
||||
set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVDS_25 } [get_ports f2_lvds_io_p[1] ] ;# F2_LVDS_IO2P
|
||||
set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVDS_25 } [get_ports f2_lvds_io_p[2] ] ;# F2_LVDS_IO3P
|
||||
set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVDS_25 } [get_ports f2_lvds_io_p[3] ] ;# F2_LVDS_IO4P
|
||||
set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVDS_25 } [get_ports f2_lvds_io_p[4] ] ;# F2_LVDS_IO5P
|
||||
|
||||
set_property -dict {PACKAGE_PIN AH10 } [get_ports f1_gtx_s2p_p[0] ] ;# F1_GTX0_S2P_P
|
||||
set_property -dict {PACKAGE_PIN AJ8 } [get_ports f1_gtx_s2p_p[1] ] ;# F1_GTX1_S2P_P
|
||||
set_property -dict {PACKAGE_PIN AG8 } [get_ports f1_gtx_s2p_p[2] ] ;# F1_GTX2_S2P_P
|
||||
set_property -dict {PACKAGE_PIN AE8 } [get_ports f1_gtx_s2p_p[3] ] ;# F1_GTX3_S2P_P
|
||||
|
||||
# set_property -dict {PACKAGE_PIN AK10 } [get_ports f1_gtx_p2s_p[0] ] ;# F1_GTX0_P2S_P
|
||||
# set_property -dict {PACKAGE_PIN AK6 } [get_ports f1_gtx_p2s_p[1] ] ;# F1_GTX1_P2S_P
|
||||
# set_property -dict {PACKAGE_PIN AJ4 } [get_ports f1_gtx_p2s_p[2] ] ;# F1_GTX2_P2S_P
|
||||
# set_property -dict {PACKAGE_PIN AK2 } [get_ports f1_gtx_p2s_p[3] ] ;# F1_GTX3_P2S_P
|
||||
|
||||
set_property -dict {PACKAGE_PIN AC4 } [get_ports f2_gtx_s2p_p[0] ] ;# F2_GTX0_S2P_P
|
||||
set_property -dict {PACKAGE_PIN AB6 } [get_ports f2_gtx_s2p_p[1] ] ;# F2_GTX1_S2P_P
|
||||
set_property -dict {PACKAGE_PIN Y6 } [get_ports f2_gtx_s2p_p[2] ] ;# F2_GTX2_S2P_P
|
||||
set_property -dict {PACKAGE_PIN AA4 } [get_ports f2_gtx_s2p_p[3] ] ;# F2_GTX3_S2P_P
|
||||
|
||||
# set_property -dict {PACKAGE_PIN AB2 } [get_ports f2_gtx_p2s_p[0] ] ;# F2_GTX0_P2S_P
|
||||
# set_property -dict {PACKAGE_PIN Y2 } [get_ports f2_gtx_p2s_p[1] ] ;# F2_GTX1_P2S_P
|
||||
# set_property -dict {PACKAGE_PIN W4 } [get_ports f2_gtx_p2s_p[2] ] ;# F2_GTX2_P2S_P
|
||||
# set_property -dict {PACKAGE_PIN V2 } [get_ports f2_gtx_p2s_p[3] ] ;# F2_GTX3_P2S_P
|
||||
|
||||
# 3.3V Debug IO
|
||||
set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS33} [get_ports uart1_txd ] ;# UART_1_TXD
|
||||
set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVCMOS33} [get_ports uart1_rxd ] ;# UART_1_RXD
|
||||
set_property -dict {PACKAGE_PIN AC18 IOSTANDARD LVCMOS33} [get_ports uart2_txd ] ;# UART_2_TXD
|
||||
set_property -dict {PACKAGE_PIN AC19 IOSTANDARD LVCMOS33} [get_ports uart2_rxd ] ;# UART_2_RXD
|
||||
set_property -dict {PACKAGE_PIN AD18 IOSTANDARD LVCMOS33} [get_ports uart3_txd ] ;# UART_3_TXD
|
||||
set_property -dict {PACKAGE_PIN AD19 IOSTANDARD LVCMOS33} [get_ports uart3_rxd ] ;# UART_3_RXD
|
||||
|
||||
set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS33} [get_ports debug_io_1 ] ;# DEBUG_IO_1
|
||||
set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS33} [get_ports debug_io_2 ] ;# DEBUG_IO_2
|
||||
set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS33} [get_ports debug_io_3 ] ;# DEBUG_IO_3
|
||||
set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVCMOS33} [get_ports debug_io_4 ] ;# DEBUG_IO_4
|
||||
set_property -dict {PACKAGE_PIN AC23 IOSTANDARD LVCMOS33} [get_ports debug_io_5 ] ;# DEBUG_IO_5
|
||||
set_property -dict {PACKAGE_PIN AC21 IOSTANDARD LVCMOS33} [get_ports debug_io_6 ] ;# DEBUG_IO_6
|
||||
|
||||
+1259
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,390 @@
|
||||
{
|
||||
"design": {
|
||||
"design_info": {
|
||||
"boundary_crc": "0x2F8D5EA807D17186",
|
||||
"device": "xc7z100ffg900-2",
|
||||
"name": "system_bd",
|
||||
"synth_flow_mode": "Hierarchical",
|
||||
"tool_version": "2019.1.3",
|
||||
"validated": "true",
|
||||
"gen_directory": "../../../../dx_pwr_basic.gen/sources_1/bd/system_bd"
|
||||
},
|
||||
"design_tree": {
|
||||
"processing_system7": ""
|
||||
},
|
||||
"interface_ports": {
|
||||
"ddr": {
|
||||
"mode": "Master",
|
||||
"vlnv": "xilinx.com:interface:ddrx_rtl:1.0",
|
||||
"parameters": {
|
||||
"AXI_ARBITRATION_SCHEME": {
|
||||
"value": "TDM",
|
||||
"value_src": "default"
|
||||
},
|
||||
"BURST_LENGTH": {
|
||||
"value": "8",
|
||||
"value_src": "default"
|
||||
},
|
||||
"CAN_DEBUG": {
|
||||
"value": "false",
|
||||
"value_src": "default"
|
||||
},
|
||||
"CAS_LATENCY": {
|
||||
"value": "11",
|
||||
"value_src": "default"
|
||||
},
|
||||
"CAS_WRITE_LATENCY": {
|
||||
"value": "11",
|
||||
"value_src": "default"
|
||||
},
|
||||
"CS_ENABLED": {
|
||||
"value": "true",
|
||||
"value_src": "default"
|
||||
},
|
||||
"DATA_MASK_ENABLED": {
|
||||
"value": "true",
|
||||
"value_src": "default"
|
||||
},
|
||||
"DATA_WIDTH": {
|
||||
"value": "8",
|
||||
"value_src": "default"
|
||||
},
|
||||
"MEMORY_TYPE": {
|
||||
"value": "COMPONENTS",
|
||||
"value_src": "default"
|
||||
},
|
||||
"MEM_ADDR_MAP": {
|
||||
"value": "ROW_COLUMN_BANK",
|
||||
"value_src": "default"
|
||||
},
|
||||
"SLOT": {
|
||||
"value": "Single",
|
||||
"value_src": "default"
|
||||
},
|
||||
"TIMEPERIOD_PS": {
|
||||
"value": "1250",
|
||||
"value_src": "default"
|
||||
}
|
||||
}
|
||||
},
|
||||
"fixed_io": {
|
||||
"mode": "Master",
|
||||
"vlnv": "xilinx.com:display_processing_system7:fixedio_rtl:1.0",
|
||||
"parameters": {
|
||||
"CAN_DEBUG": {
|
||||
"value": "false",
|
||||
"value_src": "default"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"components": {
|
||||
"processing_system7": {
|
||||
"vlnv": "xilinx.com:ip:processing_system7:5.5",
|
||||
"xci_name": "system_bd_processing_system7_0_0",
|
||||
"parameters": {
|
||||
"PCW_ACT_APU_PERIPHERAL_FREQMHZ": {
|
||||
"value": "666.666687"
|
||||
},
|
||||
"PCW_ACT_CAN_PERIPHERAL_FREQMHZ": {
|
||||
"value": "10.000000"
|
||||
},
|
||||
"PCW_ACT_DCI_PERIPHERAL_FREQMHZ": {
|
||||
"value": "10.158730"
|
||||
},
|
||||
"PCW_ACT_ENET0_PERIPHERAL_FREQMHZ": {
|
||||
"value": "10.000000"
|
||||
},
|
||||
"PCW_ACT_ENET1_PERIPHERAL_FREQMHZ": {
|
||||
"value": "10.000000"
|
||||
},
|
||||
"PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ": {
|
||||
"value": "50.000000"
|
||||
},
|
||||
"PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ": {
|
||||
"value": "10.000000"
|
||||
},
|
||||
"PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ": {
|
||||
"value": "10.000000"
|
||||
},
|
||||
"PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ": {
|
||||
"value": "10.000000"
|
||||
},
|
||||
"PCW_ACT_PCAP_PERIPHERAL_FREQMHZ": {
|
||||
"value": "200.000000"
|
||||
},
|
||||
"PCW_ACT_QSPI_PERIPHERAL_FREQMHZ": {
|
||||
"value": "200.000000"
|
||||
},
|
||||
"PCW_ACT_SDIO_PERIPHERAL_FREQMHZ": {
|
||||
"value": "10.000000"
|
||||
},
|
||||
"PCW_ACT_SMC_PERIPHERAL_FREQMHZ": {
|
||||
"value": "10.000000"
|
||||
},
|
||||
"PCW_ACT_SPI_PERIPHERAL_FREQMHZ": {
|
||||
"value": "10.000000"
|
||||
},
|
||||
"PCW_ACT_TPIU_PERIPHERAL_FREQMHZ": {
|
||||
"value": "200.000000"
|
||||
},
|
||||
"PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ": {
|
||||
"value": "111.111115"
|
||||
},
|
||||
"PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ": {
|
||||
"value": "111.111115"
|
||||
},
|
||||
"PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ": {
|
||||
"value": "111.111115"
|
||||
},
|
||||
"PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ": {
|
||||
"value": "111.111115"
|
||||
},
|
||||
"PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ": {
|
||||
"value": "111.111115"
|
||||
},
|
||||
"PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ": {
|
||||
"value": "111.111115"
|
||||
},
|
||||
"PCW_ACT_UART_PERIPHERAL_FREQMHZ": {
|
||||
"value": "100.000000"
|
||||
},
|
||||
"PCW_ACT_WDT_PERIPHERAL_FREQMHZ": {
|
||||
"value": "111.111115"
|
||||
},
|
||||
"PCW_CLK0_FREQ": {
|
||||
"value": "50000000"
|
||||
},
|
||||
"PCW_CLK1_FREQ": {
|
||||
"value": "10000000"
|
||||
},
|
||||
"PCW_CLK2_FREQ": {
|
||||
"value": "10000000"
|
||||
},
|
||||
"PCW_CLK3_FREQ": {
|
||||
"value": "10000000"
|
||||
},
|
||||
"PCW_DDR_RAM_HIGHADDR": {
|
||||
"value": "0x1FFFFFFF"
|
||||
},
|
||||
"PCW_DUAL_PARALLEL_QSPI_DATA_MODE": {
|
||||
"value": "x8"
|
||||
},
|
||||
"PCW_EN_QSPI": {
|
||||
"value": "1"
|
||||
},
|
||||
"PCW_EN_UART1": {
|
||||
"value": "1"
|
||||
},
|
||||
"PCW_FPGA_FCLK0_ENABLE": {
|
||||
"value": "1"
|
||||
},
|
||||
"PCW_MIO_0_IOTYPE": {
|
||||
"value": "LVCMOS 3.3V"
|
||||
},
|
||||
"PCW_MIO_0_PULLUP": {
|
||||
"value": "enabled"
|
||||
},
|
||||
"PCW_MIO_0_SLEW": {
|
||||
"value": "slow"
|
||||
},
|
||||
"PCW_MIO_10_IOTYPE": {
|
||||
"value": "LVCMOS 3.3V"
|
||||
},
|
||||
"PCW_MIO_10_PULLUP": {
|
||||
"value": "enabled"
|
||||
},
|
||||
"PCW_MIO_10_SLEW": {
|
||||
"value": "slow"
|
||||
},
|
||||
"PCW_MIO_11_IOTYPE": {
|
||||
"value": "LVCMOS 3.3V"
|
||||
},
|
||||
"PCW_MIO_11_PULLUP": {
|
||||
"value": "enabled"
|
||||
},
|
||||
"PCW_MIO_11_SLEW": {
|
||||
"value": "slow"
|
||||
},
|
||||
"PCW_MIO_12_IOTYPE": {
|
||||
"value": "LVCMOS 3.3V"
|
||||
},
|
||||
"PCW_MIO_12_PULLUP": {
|
||||
"value": "enabled"
|
||||
},
|
||||
"PCW_MIO_12_SLEW": {
|
||||
"value": "slow"
|
||||
},
|
||||
"PCW_MIO_13_IOTYPE": {
|
||||
"value": "LVCMOS 3.3V"
|
||||
},
|
||||
"PCW_MIO_13_PULLUP": {
|
||||
"value": "enabled"
|
||||
},
|
||||
"PCW_MIO_13_SLEW": {
|
||||
"value": "slow"
|
||||
},
|
||||
"PCW_MIO_1_IOTYPE": {
|
||||
"value": "LVCMOS 3.3V"
|
||||
},
|
||||
"PCW_MIO_1_PULLUP": {
|
||||
"value": "enabled"
|
||||
},
|
||||
"PCW_MIO_1_SLEW": {
|
||||
"value": "slow"
|
||||
},
|
||||
"PCW_MIO_2_IOTYPE": {
|
||||
"value": "LVCMOS 3.3V"
|
||||
},
|
||||
"PCW_MIO_2_SLEW": {
|
||||
"value": "slow"
|
||||
},
|
||||
"PCW_MIO_3_IOTYPE": {
|
||||
"value": "LVCMOS 3.3V"
|
||||
},
|
||||
"PCW_MIO_3_SLEW": {
|
||||
"value": "slow"
|
||||
},
|
||||
"PCW_MIO_48_IOTYPE": {
|
||||
"value": "LVCMOS 3.3V"
|
||||
},
|
||||
"PCW_MIO_48_PULLUP": {
|
||||
"value": "enabled"
|
||||
},
|
||||
"PCW_MIO_48_SLEW": {
|
||||
"value": "slow"
|
||||
},
|
||||
"PCW_MIO_49_IOTYPE": {
|
||||
"value": "LVCMOS 3.3V"
|
||||
},
|
||||
"PCW_MIO_49_PULLUP": {
|
||||
"value": "enabled"
|
||||
},
|
||||
"PCW_MIO_49_SLEW": {
|
||||
"value": "slow"
|
||||
},
|
||||
"PCW_MIO_4_IOTYPE": {
|
||||
"value": "LVCMOS 3.3V"
|
||||
},
|
||||
"PCW_MIO_4_SLEW": {
|
||||
"value": "slow"
|
||||
},
|
||||
"PCW_MIO_5_IOTYPE": {
|
||||
"value": "LVCMOS 3.3V"
|
||||
},
|
||||
"PCW_MIO_5_SLEW": {
|
||||
"value": "slow"
|
||||
},
|
||||
"PCW_MIO_6_IOTYPE": {
|
||||
"value": "LVCMOS 3.3V"
|
||||
},
|
||||
"PCW_MIO_6_SLEW": {
|
||||
"value": "slow"
|
||||
},
|
||||
"PCW_MIO_9_IOTYPE": {
|
||||
"value": "LVCMOS 3.3V"
|
||||
},
|
||||
"PCW_MIO_9_PULLUP": {
|
||||
"value": "enabled"
|
||||
},
|
||||
"PCW_MIO_9_SLEW": {
|
||||
"value": "slow"
|
||||
},
|
||||
"PCW_MIO_TREE_PERIPHERALS": {
|
||||
"value": "Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#unassigned#unassigned#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#UART 1#UART 1#unassigned#unassigned#unassigned#unassigned"
|
||||
},
|
||||
"PCW_MIO_TREE_SIGNALS": {
|
||||
"value": "qspi1_ss_b#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#unassigned#unassigned#qspi1_sclk#qspi1_io[0]#qspi1_io[1]#qspi1_io[2]#qspi1_io[3]#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#tx#rx#unassigned#unassigned#unassigned#unassigned"
|
||||
},
|
||||
"PCW_QSPI_GRP_FBCLK_ENABLE": {
|
||||
"value": "0"
|
||||
},
|
||||
"PCW_QSPI_GRP_IO1_ENABLE": {
|
||||
"value": "1"
|
||||
},
|
||||
"PCW_QSPI_GRP_IO1_IO": {
|
||||
"value": "MIO 0 9 .. 13"
|
||||
},
|
||||
"PCW_QSPI_GRP_SINGLE_SS_ENABLE": {
|
||||
"value": "0"
|
||||
},
|
||||
"PCW_QSPI_GRP_SS1_ENABLE": {
|
||||
"value": "0"
|
||||
},
|
||||
"PCW_QSPI_INTERNAL_HIGHADDRESS": {
|
||||
"value": "0xFDFFFFFF"
|
||||
},
|
||||
"PCW_QSPI_PERIPHERAL_ENABLE": {
|
||||
"value": "1"
|
||||
},
|
||||
"PCW_QSPI_PERIPHERAL_FREQMHZ": {
|
||||
"value": "200"
|
||||
},
|
||||
"PCW_QSPI_QSPI_IO": {
|
||||
"value": "MIO 1 .. 6"
|
||||
},
|
||||
"PCW_UART1_GRP_FULL_ENABLE": {
|
||||
"value": "0"
|
||||
},
|
||||
"PCW_UART1_PERIPHERAL_ENABLE": {
|
||||
"value": "1"
|
||||
},
|
||||
"PCW_UART1_UART1_IO": {
|
||||
"value": "MIO 48 .. 49"
|
||||
},
|
||||
"PCW_UART_PERIPHERAL_FREQMHZ": {
|
||||
"value": "100"
|
||||
},
|
||||
"PCW_UART_PERIPHERAL_VALID": {
|
||||
"value": "1"
|
||||
},
|
||||
"PCW_UIPARAM_ACT_DDR_FREQ_MHZ": {
|
||||
"value": "533.333374"
|
||||
},
|
||||
"PCW_UIPARAM_DDR_BUS_WIDTH": {
|
||||
"value": "16 Bit"
|
||||
},
|
||||
"PCW_UIPARAM_DDR_ECC": {
|
||||
"value": "Disabled"
|
||||
},
|
||||
"PCW_UIPARAM_DDR_PARTNO": {
|
||||
"value": "MT41J256M16 RE-125"
|
||||
}
|
||||
},
|
||||
"xci_path": "ip/system_bd_processing_system7_0_0/system_bd_processing_system7_0_0.xci"
|
||||
}
|
||||
},
|
||||
"interface_nets": {
|
||||
"processing_system7_DDR": {
|
||||
"interface_ports": [
|
||||
"ddr",
|
||||
"processing_system7/DDR"
|
||||
]
|
||||
},
|
||||
"processing_system7_FIXED_IO": {
|
||||
"interface_ports": [
|
||||
"fixed_io",
|
||||
"processing_system7/FIXED_IO"
|
||||
]
|
||||
}
|
||||
},
|
||||
"nets": {
|
||||
"processing_system7_FCLK_CLK0": {
|
||||
"ports": [
|
||||
"processing_system7/FCLK_CLK0",
|
||||
"processing_system7/M_AXI_GP0_ACLK"
|
||||
]
|
||||
}
|
||||
},
|
||||
"addressing": {
|
||||
"/processing_system7": {
|
||||
"address_spaces": {
|
||||
"Data": {
|
||||
"range": "4G",
|
||||
"width": "32"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,203 @@
|
||||
{
|
||||
"graphjs": {
|
||||
"version": "1.0",
|
||||
"keys": [
|
||||
{
|
||||
"abrv": "VH",
|
||||
"name": "vert_hid",
|
||||
"type": "int",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "VM",
|
||||
"name": "vert_name",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "VT",
|
||||
"name": "vert_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BA",
|
||||
"name": "base_addr",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "HA",
|
||||
"name": "high_addr",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BP",
|
||||
"name": "base_param",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "HP",
|
||||
"name": "high_param",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MA",
|
||||
"name": "master_addrspace",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MX",
|
||||
"name": "master_instance",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MI",
|
||||
"name": "master_interface",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MS",
|
||||
"name": "master_segment",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MV",
|
||||
"name": "master_vlnv",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SX",
|
||||
"name": "slave_instance",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SI",
|
||||
"name": "slave_interface",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MM",
|
||||
"name": "slave_memmap",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SS",
|
||||
"name": "slave_segment",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SV",
|
||||
"name": "slave_vlnv",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "TM",
|
||||
"name": "memory_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "TU",
|
||||
"name": "usage_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "LT",
|
||||
"name": "lock_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BT",
|
||||
"name": "boot_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "EH",
|
||||
"name": "edge_hid",
|
||||
"type": "int",
|
||||
"for": "edge"
|
||||
}
|
||||
],
|
||||
"vertice_type_order": [
|
||||
{
|
||||
"abrv": "BC",
|
||||
"desc": "Block Container"
|
||||
},
|
||||
{
|
||||
"abrv": "PR",
|
||||
"desc": "Parital Reference"
|
||||
},
|
||||
{
|
||||
"abrv": "VR",
|
||||
"desc": "Variant"
|
||||
},
|
||||
{
|
||||
"abrv": "PM",
|
||||
"desc": "Variant Permutations"
|
||||
},
|
||||
{
|
||||
"abrv": "CX",
|
||||
"desc": "Boundary Connection"
|
||||
},
|
||||
{
|
||||
"abrv": "AC",
|
||||
"desc": "Assignment Coordinate"
|
||||
},
|
||||
{
|
||||
"abrv": "ACE",
|
||||
"desc": "Excluded Assign Coordinate"
|
||||
},
|
||||
{
|
||||
"abrv": "APX",
|
||||
"desc": "Boundary Aperture"
|
||||
},
|
||||
{
|
||||
"abrv": "CIP",
|
||||
"desc": "High level Processing System"
|
||||
}
|
||||
],
|
||||
"vertices": {
|
||||
"V0": {
|
||||
"VM": "system_bd",
|
||||
"VT": "BC"
|
||||
},
|
||||
"V1": {
|
||||
"VH": "2",
|
||||
"VM": "system_bd",
|
||||
"VT": "VR"
|
||||
},
|
||||
"V2": {
|
||||
"VH": "2",
|
||||
"VT": "PM",
|
||||
"TU": "active"
|
||||
}
|
||||
},
|
||||
"edges": [
|
||||
{
|
||||
"src": "V0",
|
||||
"trg": "V1"
|
||||
},
|
||||
{
|
||||
"src": "V1",
|
||||
"trg": "V2"
|
||||
}
|
||||
]
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,20 @@
|
||||
{
|
||||
"ActiveEmotionalView":"Default View",
|
||||
"Default View_ScaleFactor":"1.0",
|
||||
"Default View_TopLeft":"-642,-677",
|
||||
"ExpandedHierarchyInLayout":"",
|
||||
"guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS
|
||||
# -string -flagsOSRD
|
||||
preplace port ddr -pg 1 -lvl 2 -x 430 -y -320 -defaultsOSRD
|
||||
preplace port fixed_io -pg 1 -lvl 2 -x 430 -y -300 -defaultsOSRD
|
||||
preplace inst processing_system7 -pg 1 -lvl 1 -x 210 -y -280 -defaultsOSRD
|
||||
preplace netloc processing_system7_FCLK_CLK0 1 0 2 10 -180 410
|
||||
preplace netloc processing_system7_DDR 1 1 1 NJ -320
|
||||
preplace netloc processing_system7_FIXED_IO 1 1 1 NJ -300
|
||||
levelinfo -pg 1 -10 210 430
|
||||
pagesize -pg 1 -db -bbox -sgen -10 -380 540 200
|
||||
"
|
||||
}
|
||||
{
|
||||
"da_ps7_cnt":"1"
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,657 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "lvds_clk_gen",
|
||||
"component_reference": "xilinx.com:ip:clk_wiz:6.0",
|
||||
"ip_revision": "14",
|
||||
"gen_directory": "../../../../dx_pwr_basic.gen/sources_1/ip/lvds_clk_gen",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "lvds_clk_gen", "resolve_type": "user", "usage": "all" } ],
|
||||
"USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"ENABLE_CLOCK_MONITOR": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ENABLE_USER_CLOCK0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ENABLE_USER_CLOCK1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ENABLE_USER_CLOCK2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ENABLE_USER_CLOCK3": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Enable_PLL0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Enable_PLL1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PRECISION": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
|
||||
"PRIMTYPE_SEL": [ { "value": "mmcm_adv", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLOCK_MGR_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_FREQ_SYNTH": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_SPREAD_SPECTRUM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_PHASE_ALIGNMENT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_MIN_POWER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_DYN_PHASE_SHIFT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_DYN_RECONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "user", "usage": "all" } ],
|
||||
"PRIM_IN_FREQ": [ { "value": "30", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "user", "usage": "all" } ],
|
||||
"PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "user", "usage": "all" } ],
|
||||
"IN_JITTER_UNITS": [ { "value": "Units_UI", "resolve_type": "user", "usage": "all" } ],
|
||||
"RELATIVE_INCLK": [ { "value": "REL_PRIMARY", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_INCLK_SWITCHOVER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "user", "usage": "all" } ],
|
||||
"SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
|
||||
"JITTER_OPTIONS": [ { "value": "UI", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKIN1_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKIN2_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKIN1_JITTER_PS": [ { "value": "333.33000000000004", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT2_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT3_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT4_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT5_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT6_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT7_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"NUM_OUT_CLKS": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLK_OUT1_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_OUT2_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_OUT3_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_OUT4_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_OUT5_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_OUT6_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_OUT7_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "user", "usage": "all" } ],
|
||||
"DADDR_PORT": [ { "value": "daddr", "resolve_type": "user", "usage": "all" } ],
|
||||
"DCLK_PORT": [ { "value": "dclk", "resolve_type": "user", "usage": "all" } ],
|
||||
"DRDY_PORT": [ { "value": "drdy", "resolve_type": "user", "usage": "all" } ],
|
||||
"DWE_PORT": [ { "value": "dwe", "resolve_type": "user", "usage": "all" } ],
|
||||
"DIN_PORT": [ { "value": "din", "resolve_type": "user", "usage": "all" } ],
|
||||
"DOUT_PORT": [ { "value": "dout", "resolve_type": "user", "usage": "all" } ],
|
||||
"DEN_PORT": [ { "value": "den", "resolve_type": "user", "usage": "all" } ],
|
||||
"PSCLK_PORT": [ { "value": "psclk", "resolve_type": "user", "usage": "all" } ],
|
||||
"PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ],
|
||||
"PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ],
|
||||
"PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "30", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"USE_MAX_I_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_MIN_O_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
||||
"FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "user", "usage": "all" } ],
|
||||
"PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "user", "usage": "all" } ],
|
||||
"SUMMARY_STRINGS": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_LOCKED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CALC_DONE": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_RESET": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_POWER_DOWN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_STATUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_FREEZE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_CLK_VALID": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_INCLK_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_CLKFB_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"RESET_PORT": [ { "value": "reset", "resolve_type": "user", "usage": "all" } ],
|
||||
"LOCKED_PORT": [ { "value": "locked", "resolve_type": "user", "usage": "all" } ],
|
||||
"POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "user", "usage": "all" } ],
|
||||
"STATUS_PORT": [ { "value": "STATUS", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "user", "usage": "all" } ],
|
||||
"INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "user", "usage": "all" } ],
|
||||
"SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "user", "usage": "all" } ],
|
||||
"SS_MOD_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
|
||||
"MMCM_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
|
||||
"MMCM_CLKFBOUT_MULT_F": [ { "value": "32.500", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKIN1_PERIOD": [ { "value": "33.333", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "user", "usage": "all" } ],
|
||||
"MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT0_DIVIDE_F": [ { "value": "32.500", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"OVERRIDE_PLL": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"PLL_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
|
||||
"PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
|
||||
"PLL_CLKFBOUT_MULT": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "user", "usage": "all" } ],
|
||||
"PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKIN_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "user", "usage": "all" } ],
|
||||
"PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"RESET_TYPE": [ { "value": "ACTIVE_HIGH", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_SAFE_CLOCK_STARTUP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_CLOCK_SEQUENCING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"DIFF_CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"DIFF_CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
|
||||
"RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"ENABLE_CDDC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "user", "usage": "all" } ],
|
||||
"CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "user", "usage": "all" } ],
|
||||
"ENABLE_CLKOUTPHY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_JITTER": [ { "value": "317.943", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_PHASE_ERROR": [ { "value": "210.329", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT2_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT2_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT3_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT3_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT4_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT4_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT5_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT5_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT6_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT6_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT7_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT7_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"INPUT_MODE": [ { "value": "frequency", "resolve_type": "user", "usage": "all" } ],
|
||||
"INTERFACE_SELECTION": [ { "value": "Enable_AXI", "resolve_type": "user", "usage": "all" } ],
|
||||
"AXI_DRP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"PHASE_DUTY_CONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_CLKOUT2_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_ENABLE_CLOCK_MONITOR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_USER_CLOCK0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_USER_CLOCK1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_USER_CLOCK2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_USER_CLOCK3": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_Enable_PLL0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_Enable_PLL1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PRECISION": [ { "value": "1", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT4_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT5_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT6_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT7_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_CLKOUT1_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_CLKOUT2_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_CLKOUT3_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_CLKOUT4_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"c_component_name": [ { "value": "lvds_clk_gen", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_FREQ_SYNTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_PHASE_ALIGNMENT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_MIN_POWER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_MIN_O_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_MAX_I_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_DYN_PHASE_SHIFT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_INCLK_SWITCHOVER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_DYN_RECONFIG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_SPREAD_SPECTRUM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_FAST_SIMULATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRIMTYPE_SEL": [ { "value": "AUTO", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_CLK_VALID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRIM_IN_FREQ": [ { "value": "30", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_RESET": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RESET_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_LOCKED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_INCLK_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_CLKFB_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_POWER_DOWN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_STATUS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_FREEZE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_OUT_CLKS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_INCLK_SUM_ROW0": [ { "value": "Input Clock Freq (MHz) Input Jitter (UI)", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_INCLK_SUM_ROW1": [ { "value": "__primary______________30____________0.010", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_INCLK_SUM_ROW2": [ { "value": "no_secondary_input_clock ", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW0A": [ { "value": " Output Output Phase Duty Cycle Pk-to-Pk Phase", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW0B": [ { "value": " Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__30.00000______0.000______50.0______317.943____210.329", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW2": [ { "value": "no_CLK_OUT2_output", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW3": [ { "value": "no_CLK_OUT3_output", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW4": [ { "value": "no_CLK_OUT4_output", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW5": [ { "value": "no_CLK_OUT5_output", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW6": [ { "value": "no_CLK_OUT6_output", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW7": [ { "value": "no_CLK_OUT7_output", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "30", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT1_OUT_FREQ": [ { "value": "30.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT5_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT6_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT7_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT7_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT1_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT5_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT6_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT7_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_USE_SAFE_CLOCK_STARTUP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_CLOCK_SEQUENCING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_NOTES": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKFBOUT_MULT_F": [ { "value": "32.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKIN1_PERIOD": [ { "value": "33.333", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT4_CASCADE": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"C_MMCM_CLOCK_HOLD": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"C_MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_STARTUP_WAIT": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "32.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLL_NOTES": [ { "value": "No notes", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLL_CLKFBOUT_MULT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKIN_PERIOD": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLOCK_MGR_TYPE": [ { "value": "NA", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OVERRIDE_MMCM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OVERRIDE_PLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_RESET_PORT": [ { "value": "reset", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_LOCKED_PORT": [ { "value": "locked", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DADDR_PORT": [ { "value": "daddr", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DCLK_PORT": [ { "value": "dclk", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DRDY_PORT": [ { "value": "drdy", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DWE_PORT": [ { "value": "dwe", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIN_PORT": [ { "value": "din", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DOUT_PORT": [ { "value": "dout", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DEN_PORT": [ { "value": "den", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PSCLK_PORT": [ { "value": "psclk", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PSEN_PORT": [ { "value": "psen", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PSDONE_PORT": [ { "value": "psdone", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_STATUS_PORT": [ { "value": "STATUS", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKIN1_JITTER_PS": [ { "value": "333.33000000000004", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SS_MOD_PERIOD": [ { "value": "4000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_HAS_CDDC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUTPHY_MODE": [ { "value": "VCO", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_ENABLE_CLKOUTPHY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INTERFACE_SELECTION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_ADDR_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_POWER_REG": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT0_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT0_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT1_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT1_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT2_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT2_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT3_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT3_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT4_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT4_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT5_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT5_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT6_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT6_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFBOUT_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFBOUT_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVCLK": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_LOCK_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_LOCK_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_LOCK_3": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_FILTER_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_FILTER_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE1_AUTO": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE2_AUTO": [ { "value": "0.03076923076923077", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE3_AUTO": [ { "value": "0.03076923076923077", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE4_AUTO": [ { "value": "0.03076923076923077", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE5_AUTO": [ { "value": "0.03076923076923077", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE6_AUTO": [ { "value": "0.03076923076923077", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE7_AUTO": [ { "value": "0.03076923076923077", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLLBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLLBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLLBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLLBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLLBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV5": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV6": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV7": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT0_ACTUAL_FREQ": [ { "value": "30.00000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT1_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT2_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT3_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT4_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT5_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT6_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_M_MAX": [ { "value": "64.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_M_MIN": [ { "value": "2.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_D_MAX": [ { "value": "93.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_D_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_O_MAX": [ { "value": "128.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_O_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_VCO_MIN": [ { "value": "600.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_VCO_MAX": [ { "value": "1440.000", "resolve_type": "generated", "format": "float", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z100" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "14" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../dx_pwr_basic.gen/sources_1/ip/lvds_clk_gen" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"clk_in1": [ { "direction": "in" } ],
|
||||
"clk_out1": [ { "direction": "out" } ],
|
||||
"locked": [ { "direction": "out" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"clock_CLK_IN1": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BOARD.ASSOCIATED_PARAM": [ { "value": "CLK_IN1_BOARD_INTERFACE", "usage": "all", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK_IN1": [ { "physical_name": "clk_in1" } ]
|
||||
}
|
||||
},
|
||||
"clock_CLK_OUT1": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK_OUT1": [ { "physical_name": "clk_out1" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,243 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 09/09/2024 04:20:47 PM
|
||||
// Design Name:
|
||||
// Module Name: system_top
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module system_top
|
||||
(
|
||||
/***************************************************************************
|
||||
* Contents
|
||||
* 01. Clocks
|
||||
* 02. HMC7044 Interface
|
||||
* 03. AD9361-1 Interface
|
||||
* 04. AD9361-2 Interface
|
||||
* 05. Phased-Array Control
|
||||
* 06. RF Synthesizer Control
|
||||
* 07. Debug IO
|
||||
* 08. DDR and Fixed-io (Do NOT Modify)
|
||||
**************************************************************************/
|
||||
|
||||
// *************************************************************************
|
||||
// ********************************* GLINK *********************************
|
||||
// *************************************************************************
|
||||
// clocks
|
||||
input clk_glink_25m ,
|
||||
input clk_glink_125m_p,
|
||||
input clk_glink_125m_n,
|
||||
// data
|
||||
input [1:0] glink_rx_p ,
|
||||
input [1:0] glink_rx_n ,
|
||||
// output [1:0] glink_tx_p ,
|
||||
// output [1:0] glink_tx_n ,
|
||||
// *************************************************************************
|
||||
// ******************************** KK LVDS ********************************
|
||||
// *************************************************************************
|
||||
// kk rx lvds (control)
|
||||
output kk_rx_rf ,
|
||||
output kk_rx_ss ,
|
||||
output [1:0] kk_rx_rng ,
|
||||
output kk_rx_pwdnb ,
|
||||
// kk rx lvds (data)
|
||||
input kk_rx_pclk ,
|
||||
input kk_rx_lock ,
|
||||
input kk_rx_de ,
|
||||
input [8:0] kk_rx_cntl ,
|
||||
input [17:0] kk_rx_rgb ,
|
||||
// kk tx lvds (control)
|
||||
output kk_tx_pre ,
|
||||
output [1:0] kk_tx_rng ,
|
||||
output kk_tx_pwdnb ,
|
||||
// kk tx lvds (data)
|
||||
input clk_lvds_30m ,
|
||||
output kk_tx_pclk_in ,
|
||||
output kk_tx_de_in ,
|
||||
output [8:0] kk_tx_cntl ,
|
||||
output [17:0] kk_tx_rgb ,
|
||||
// *************************************************************************
|
||||
// ******************************** YC LVDS ********************************
|
||||
// *************************************************************************
|
||||
input yc_rx ,
|
||||
output yc_tx ,
|
||||
// *************************************************************************
|
||||
// ****************************** RS422/RS485 ******************************
|
||||
// *************************************************************************
|
||||
// gg - high orbit
|
||||
input rs422_gg_rxd ,
|
||||
output rs422_gg_reb ,
|
||||
output rs422_gg_de ,
|
||||
output rs422_gg_txd ,
|
||||
// dg - low orbit
|
||||
input rs422_dg_rxd ,
|
||||
output rs422_dg_reb ,
|
||||
output rs422_dg_de ,
|
||||
output rs422_dg_txd ,
|
||||
// ts - test
|
||||
input rs422_ts_rxd ,
|
||||
output rs422_ts_reb ,
|
||||
output rs422_ts_de ,
|
||||
output rs422_ts_txd ,
|
||||
// by - backup
|
||||
input rs485_by_rxd ,
|
||||
output rs485_by_reb ,
|
||||
output rs485_by_de ,
|
||||
output rs485_by_txd ,
|
||||
// int_mc - internal bus timing pulse
|
||||
input rs422_int_mc_rxd,
|
||||
output rs422_int_mc_reb,
|
||||
output rs422_int_mc_de ,
|
||||
output rs422_int_mc_txd,
|
||||
// int_dh - internal bus navigation
|
||||
input rs422_int_dh_rxd,
|
||||
output rs422_int_dh_reb,
|
||||
output rs422_int_dh_de ,
|
||||
output rs422_int_dh_txd,
|
||||
// *************************************************************************
|
||||
// *************************** Inter-board Ports ***************************
|
||||
// *************************************************************************
|
||||
// clocks
|
||||
input clk_s2p_0_p ,
|
||||
input clk_s2p_0_n ,
|
||||
input clk_s2p_1_p ,
|
||||
input clk_s2p_1_n ,
|
||||
// low speed
|
||||
inout [4:0] f1_lvds_io_p ,
|
||||
inout [4:0] f1_lvds_io_n ,
|
||||
inout [4:0] f2_lvds_io_p ,
|
||||
inout [4:0] f2_lvds_io_n ,
|
||||
// high speed
|
||||
input [3:0] f1_gtx_s2p_p ,
|
||||
input [3:0] f1_gtx_s2p_n ,
|
||||
// output [3:0] f1_gtx_p2s_p ,
|
||||
// output [3:0] f1_gtx_p2s_n ,
|
||||
input [3:0] f2_gtx_s2p_p ,
|
||||
// input [3:0] f2_gtx_s2p_n ,
|
||||
// output [3:0] f2_gtx_p2s_p ,
|
||||
// output [3:0] f2_gtx_p2s_n ,
|
||||
// *************************************************************************
|
||||
// ***************************** 3.3V Debug IO *****************************
|
||||
// *************************************************************************
|
||||
// uart
|
||||
output uart1_txd ,
|
||||
input uart1_rxd ,
|
||||
output uart2_txd ,
|
||||
input uart2_rxd ,
|
||||
output uart3_txd ,
|
||||
input uart3_rxd ,
|
||||
// gpio
|
||||
inout debug_io_1 ,
|
||||
inout debug_io_2 ,
|
||||
inout debug_io_3 ,
|
||||
inout debug_io_4 ,
|
||||
inout debug_io_5 ,
|
||||
inout debug_io_6 ,
|
||||
// *************************************************************************
|
||||
// ******************* DDR and Fixed-io (Do NOT Modify) ********************
|
||||
// *************************************************************************
|
||||
// ddr
|
||||
inout [14:0] ddr_addr ,
|
||||
inout [ 2:0] ddr_ba ,
|
||||
inout ddr_cas_n ,
|
||||
inout ddr_ck_n ,
|
||||
inout ddr_ck_p ,
|
||||
inout ddr_cke ,
|
||||
inout ddr_cs_n ,
|
||||
inout [ 3:0] ddr_dm ,
|
||||
inout [31:0] ddr_dq ,
|
||||
inout [ 3:0] ddr_dqs_n ,
|
||||
inout [ 3:0] ddr_dqs_p ,
|
||||
inout ddr_odt ,
|
||||
inout ddr_ras_n ,
|
||||
inout ddr_reset_n ,
|
||||
inout ddr_we_n ,
|
||||
// fixed-io
|
||||
inout fixed_io_ddr_vrn ,
|
||||
inout fixed_io_ddr_vrp ,
|
||||
inout [53:0] fixed_io_mio ,
|
||||
inout fixed_io_ps_clk ,
|
||||
inout fixed_io_ps_porb ,
|
||||
inout fixed_io_ps_srstb
|
||||
);
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//////////////////////////// Block Design Interface ////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
system_bd_wrapper system_bd
|
||||
(
|
||||
// ddr
|
||||
.ddr_addr (ddr_addr ), // inout [14:0]ddr_addr
|
||||
.ddr_ba (ddr_ba ), // inout [2:0]ddr_ba
|
||||
.ddr_cas_n (ddr_cas_n ), // inout ddr_cas_n
|
||||
.ddr_ck_n (ddr_ck_n ), // inout ddr_ck_n
|
||||
.ddr_ck_p (ddr_ck_p ), // inout ddr_ck_p
|
||||
.ddr_cke (ddr_cke ), // inout ddr_cke
|
||||
.ddr_cs_n (ddr_cs_n ), // inout ddr_cs_n
|
||||
.ddr_dm (ddr_dm ), // inout [3:0]ddr_dm
|
||||
.ddr_dq (ddr_dq ), // inout [31:0]ddr_dq
|
||||
.ddr_dqs_n (ddr_dqs_n ), // inout [3:0]ddr_dqs_n
|
||||
.ddr_dqs_p (ddr_dqs_p ), // inout [3:0]ddr_dqs_p
|
||||
.ddr_odt (ddr_odt ), // inout ddr_odt
|
||||
.ddr_ras_n (ddr_ras_n ), // inout ddr_ras_n
|
||||
.ddr_reset_n (ddr_reset_n ), // inout ddr_reset_n
|
||||
.ddr_we_n (ddr_we_n ), // inout ddr_we_n
|
||||
|
||||
// fixed-io
|
||||
.fixed_io_ddr_vrn (fixed_io_ddr_vrn ), // inout fixed_io_ddr_vrn
|
||||
.fixed_io_ddr_vrp (fixed_io_ddr_vrp ), // inout fixed_io_ddr_vrp
|
||||
.fixed_io_mio (fixed_io_mio ), // inout [53:0]fixed_io_mio
|
||||
.fixed_io_ps_clk (fixed_io_ps_clk ), // inout fixed_io_ps_clk
|
||||
.fixed_io_ps_porb (fixed_io_ps_porb ), // inout fixed_io_ps_porb
|
||||
.fixed_io_ps_srstb (fixed_io_ps_srstb ) // inout fixed_io_ps_srstb
|
||||
);
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/////////////////////////////////// KK LVDS ////////////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
wire clk_30m;
|
||||
wire clk_30m_rst;
|
||||
|
||||
lvds_clk_gen lvds_clk_gen
|
||||
(
|
||||
// Clock out ports
|
||||
.clk_out1 (clk_30m ), // output clk_out1
|
||||
// Status and control signals
|
||||
.locked (~clk_30m_rst ), // output locked
|
||||
// Clock in ports
|
||||
.clk_in1 (clk_lvds_30m ) // input clk_in1
|
||||
);
|
||||
|
||||
reg [31:0] cnt = 'b0;
|
||||
|
||||
always @(posedge clk_30m) begin
|
||||
if (clk_30m_rst) begin
|
||||
cnt <= 'b0;
|
||||
end
|
||||
else begin
|
||||
cnt <= cnt + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
ila_cnt u_ila_cnt
|
||||
(
|
||||
.clk (clk_30m ), // input wire clk
|
||||
.probe0 (cnt ) // input wire [31:0] probe0
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,356 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2024.1.2 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
|
||||
<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Workspace/vivado/brd_dx_ky/dx_pwr_basic/dx_pwr_basic.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="36333334a64546999938b88f368ce500"/>
|
||||
<Option Name="Part" Val="xc7z100ffg900-2"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorVersionXsim" Val="2024.1"/>
|
||||
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
|
||||
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
|
||||
<Option Name="SimulatorVersionRiviera" Val="2023.04"/>
|
||||
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
|
||||
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
|
||||
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="EnableResourceEstimation" Val="FALSE"/>
|
||||
<Option Name="SimCompileState" Val="TRUE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="3"/>
|
||||
<Option Name="WTModelSimExportSim" Val="3"/>
|
||||
<Option Name="WTQuestaExportSim" Val="3"/>
|
||||
<Option Name="WTIesExportSim" Val="3"/>
|
||||
<Option Name="WTVcsExportSim" Val="3"/>
|
||||
<Option Name="WTRivieraExportSim" Val="3"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="3"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
||||
<Option Name="ClassicSocBoot" Val="FALSE"/>
|
||||
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="32">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/bd/system_bd/system_bd.bd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
<CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_processing_system7_0_0/system_bd_processing_system7_0_0.xci">
|
||||
<Proxy FileSetName="system_bd_processing_system7_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
</File>
|
||||
<File Path="$PGENDIR/sources_1/bd/system_bd/hdl/system_bd_wrapper.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/system_top.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="system_top"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PSRCDIR/constrs_1/new/dx_z7100_pwr_inter_physical.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="system_top"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||
<Option Name="PamDesignTestbench" Val=""/>
|
||||
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
||||
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="system_bd_processing_system7_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_processing_system7_0_0" RelGenDir="$PGENDIR/system_bd_processing_system7_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="system_bd_processing_system7_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="lvds_clk_gen" Type="BlockSrcs" RelSrcDir="$PSRCDIR/lvds_clk_gen" RelGenDir="$PGENDIR/lvds_clk_gen">
|
||||
<File Path="$PSRCDIR/sources_1/ip/lvds_clk_gen/lvds_clk_gen.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="ImportPath" Val="$PPRDIR/../../../vivado_all/vivado_pvt/projects/dx_pwr/dx_pwr_basic/dx_pwr_basic.srcs/sources_1/ip/lvds_clk_gen/lvds_clk_gen.xci"/>
|
||||
<Attr Name="ImportTime" Val="1729586974"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="lvds_clk_gen"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="ila_cnt" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ila_cnt" RelGenDir="$PGENDIR/ila_cnt">
|
||||
<File Path="$PSRCDIR/sources_1/ip/ila_cnt/ila_cnt.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="ImportPath" Val="$PPRDIR/../../../vivado_all/vivado_pvt/projects/dx_pwr/dx_pwr_basic/dx_pwr_basic.srcs/sources_1/ip/ila_cnt/ila_cnt.xci"/>
|
||||
<Attr Name="ImportTime" Val="1729586974"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="ila_cnt"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="22">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z100ffg900-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_bd_processing_system7_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_processing_system7_0_0" Part="xc7z100ffg900-2" ConstrsSet="system_bd_processing_system7_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_processing_system7_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_processing_system7_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_processing_system7_0_0_synth_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="lvds_clk_gen_synth_1" Type="Ft3:Synth" SrcSet="lvds_clk_gen" Part="xc7z100ffg900-2" ConstrsSet="lvds_clk_gen" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/lvds_clk_gen_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/lvds_clk_gen_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/lvds_clk_gen_synth_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="ila_cnt_synth_1" Type="Ft3:Synth" SrcSet="ila_cnt" Part="xc7z100ffg900-2" ConstrsSet="ila_cnt" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ila_cnt_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_cnt_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ila_cnt_synth_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 16 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_bd_processing_system7_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="system_bd_processing_system7_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_processing_system7_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_processing_system7_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_processing_system7_0_0_impl_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="lvds_clk_gen_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="lvds_clk_gen" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="lvds_clk_gen_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/lvds_clk_gen_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/lvds_clk_gen_impl_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="ila_cnt_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="ila_cnt" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ila_cnt_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_cnt_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ila_cnt_impl_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
</Project>
|
||||
BIN
Binary file not shown.
@@ -0,0 +1,35 @@
|
||||
# keep compiled libs
|
||||
!*.a
|
||||
|
||||
# Buid folder
|
||||
build/
|
||||
|
||||
# Xilinx tools generated files
|
||||
.metadata/
|
||||
.settings/
|
||||
.wsdata/
|
||||
.Xil/
|
||||
logs/
|
||||
Packages/
|
||||
*.log*
|
||||
|
||||
# System generated files
|
||||
# -- macOS
|
||||
.DS_Store
|
||||
.AppleDouble
|
||||
.LSOverride
|
||||
._*
|
||||
|
||||
# -- Windows
|
||||
Thumbs.db
|
||||
ehthumbs.db
|
||||
Desktop.ini
|
||||
|
||||
# -- Linux
|
||||
*~
|
||||
|
||||
# IDEs and editors' files
|
||||
*.idea
|
||||
*.vscode
|
||||
*.sublime-workspace
|
||||
*.sublime-project
|
||||
@@ -0,0 +1,8 @@
|
||||
include ../../scripts/generic_variables.mk
|
||||
|
||||
PLATFORM := xilinx
|
||||
CONFIG_FILE := $(PROJECT)/config.json
|
||||
XILINX_VITIS_CLASSIC = y
|
||||
SCRIPT_DIR = ../../scripts
|
||||
|
||||
include ../../scripts/generic.mk
|
||||
@@ -0,0 +1,32 @@
|
||||
@echo off
|
||||
set "platform=xilinx"
|
||||
set "pltform_ver=2024.1"
|
||||
set "work_dir=%~dp0build"
|
||||
set "config=%~dp0config.json"
|
||||
set "tools_dir=%~dp0..\..\scripts\platform\%platform%"
|
||||
|
||||
REM Set up enviroment
|
||||
call "%tools_dir%\setenv.bat" "%pltform_ver%"
|
||||
if "%ERRORLEVEL%" neq "0" (
|
||||
echo Error: Failed to installize enviroment.
|
||||
pause >nul
|
||||
exit /b 1
|
||||
)
|
||||
|
||||
REM Build project
|
||||
call "%tools_dir%\build.bat" "%config%" "%work_dir%"
|
||||
if "%ERRORLEVEL%" neq "0" (
|
||||
echo Error: Failed to build project.
|
||||
pause >nul
|
||||
exit /b 1
|
||||
)
|
||||
|
||||
REM Lauch SDK
|
||||
call "%tools_dir%\launch.bat" "%pltform_ver%" "%work_dir%"
|
||||
if "%ERRORLEVEL%" neq "0" (
|
||||
echo Error: Failed to launch SDK.
|
||||
pause >nul
|
||||
exit /b 1
|
||||
)
|
||||
|
||||
exit /b 0
|
||||
@@ -0,0 +1,6 @@
|
||||
{
|
||||
"project_name": "dx_sig",
|
||||
"version": "1.1.0",
|
||||
"hw_design": "../system_top.xsa",
|
||||
"hw_version": "dx_sig-HW-1.1.0"
|
||||
}
|
||||
@@ -0,0 +1,178 @@
|
||||
proc getPresetInfo {} {
|
||||
return [dict create name {dx_pwr_preset} description {dx_pwr_preset} vlnv xilinx.com:ip:processing_system7:5.5 display_name {dx_pwr_preset} ]
|
||||
}
|
||||
|
||||
proc validate_preset {IPINST} { return true }
|
||||
|
||||
|
||||
proc apply_preset {IPINST} {
|
||||
return [dict create \
|
||||
CONFIG.PCW_DDR_RAM_HIGHADDR {0x1FFFFFFF} \
|
||||
CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \
|
||||
CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \
|
||||
CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \
|
||||
CONFIG.PCW_UIPARAM_DDR_CL {7} \
|
||||
CONFIG.PCW_UIPARAM_DDR_CWL {6} \
|
||||
CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \
|
||||
CONFIG.PCW_UIPARAM_DDR_T_RP {7} \
|
||||
CONFIG.PCW_UIPARAM_DDR_T_RC {48.91} \
|
||||
CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \
|
||||
CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \
|
||||
CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200} \
|
||||
CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \
|
||||
CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {25} \
|
||||
CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \
|
||||
CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \
|
||||
CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \
|
||||
CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \
|
||||
CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \
|
||||
CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \
|
||||
CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
|
||||
CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
|
||||
CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {50.000000} \
|
||||
CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
|
||||
CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
|
||||
CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
|
||||
CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
|
||||
CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
|
||||
CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
|
||||
CONFIG.PCW_CLK0_FREQ {50000000} \
|
||||
CONFIG.PCW_CLK1_FREQ {10000000} \
|
||||
CONFIG.PCW_CLK2_FREQ {10000000} \
|
||||
CONFIG.PCW_CLK3_FREQ {10000000} \
|
||||
CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
|
||||
CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \
|
||||
CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {9} \
|
||||
CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {18} \
|
||||
CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
|
||||
CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {6} \
|
||||
CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {6} \
|
||||
CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \
|
||||
CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \
|
||||
CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
|
||||
CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
|
||||
CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
|
||||
CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \
|
||||
CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \
|
||||
CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {9} \
|
||||
CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \
|
||||
CONFIG.PCW_IOPLL_CTRL_FBDIV {54} \
|
||||
CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \
|
||||
CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \
|
||||
CONFIG.PCW_IO_IO_PLL_FREQMHZ {1800.000} \
|
||||
CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \
|
||||
CONFIG.PCW_UART_PERIPHERAL_VALID {1} \
|
||||
CONFIG.PCW_EN_QSPI {1} \
|
||||
CONFIG.PCW_EN_UART1 {1} \
|
||||
CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \
|
||||
CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit} \
|
||||
CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J256M16 RE-125} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \
|
||||
CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \
|
||||
CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \
|
||||
CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \
|
||||
CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \
|
||||
CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \
|
||||
CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \
|
||||
CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \
|
||||
CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \
|
||||
CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \
|
||||
CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \
|
||||
CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {0} \
|
||||
CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \
|
||||
CONFIG.PCW_DUAL_PARALLEL_QSPI_DATA_MODE {x8} \
|
||||
CONFIG.PCW_QSPI_GRP_IO1_ENABLE {1} \
|
||||
CONFIG.PCW_QSPI_GRP_IO1_IO {MIO 0 9 .. 13} \
|
||||
CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {0} \
|
||||
CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS {0xFDFFFFFF} \
|
||||
CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \
|
||||
CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49} \
|
||||
CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \
|
||||
CONFIG.PCW_MIO_0_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \
|
||||
CONFIG.PCW_MIO_0_DIRECTION {out} \
|
||||
CONFIG.PCW_MIO_0_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_1_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \
|
||||
CONFIG.PCW_MIO_1_DIRECTION {out} \
|
||||
CONFIG.PCW_MIO_1_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_2_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \
|
||||
CONFIG.PCW_MIO_2_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_2_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_3_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \
|
||||
CONFIG.PCW_MIO_3_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_3_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_4_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \
|
||||
CONFIG.PCW_MIO_4_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_4_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_5_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \
|
||||
CONFIG.PCW_MIO_5_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_5_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_6_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \
|
||||
CONFIG.PCW_MIO_6_DIRECTION {out} \
|
||||
CONFIG.PCW_MIO_6_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_9_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \
|
||||
CONFIG.PCW_MIO_9_DIRECTION {out} \
|
||||
CONFIG.PCW_MIO_9_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_10_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \
|
||||
CONFIG.PCW_MIO_10_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_10_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_11_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \
|
||||
CONFIG.PCW_MIO_11_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_11_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_12_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \
|
||||
CONFIG.PCW_MIO_12_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_12_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_13_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \
|
||||
CONFIG.PCW_MIO_13_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_13_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_48_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 3.3V} \
|
||||
CONFIG.PCW_MIO_48_DIRECTION {out} \
|
||||
CONFIG.PCW_MIO_48_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_49_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 3.3V} \
|
||||
CONFIG.PCW_MIO_49_DIRECTION {in} \
|
||||
CONFIG.PCW_MIO_49_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#unassigned#unassigned#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#UART 1#UART 1#unassigned#unassigned#unassigned#unassigned} \
|
||||
CONFIG.PCW_MIO_TREE_SIGNALS {qspi1_ss_b#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#unassigned#unassigned#qspi1_sclk#qspi1_io[0]#qspi1_io[1]#qspi1_io[2]#qspi1_io[3]#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#tx#rx#unassigned#unassigned#unassigned#unassigned} \
|
||||
CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
|
||||
CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \
|
||||
CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \
|
||||
CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \
|
||||
]
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user