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feat: 增加跨域电源接口板工程

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josh
2024-11-14 21:06:09 +08:00
parent ddb2992955
commit b56c7ad3be
19 changed files with 10286 additions and 0 deletions
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dx_pwr_basic/vitis_classic_autobuild/Makefile
+8
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@@ -0,0 +1,8 @@
include ../../scripts/generic_variables.mk
PLATFORM := xilinx
CONFIG_FILE := $(PROJECT)/config.json
XILINX_VITIS_CLASSIC = y
SCRIPT_DIR = ../../scripts
include ../../scripts/generic.mk