feat: 增加不同帧类型的发送功率控制,修改AD9361增益

src/dev_profile/ad9361_reg_profile.c

@@ -1535,10 +1535,10 @@ uint32_t ad9361_reg_config(struct ad9361_reg_dev *dev){
 		status = ad9361_reg_write(dev, 0x0105, 0x3A);	// ADC Large Overload Threshold
 		status = ad9361_reg_write(dev, 0x0107, 0x2B);	// Small LMT Overload Threshold
 		status = ad9361_reg_write(dev, 0x0108, 0x31);	// Large LMT Overload Threshold
-		status = ad9361_reg_write(dev, 0x0109, 0x00);	// Rx1 Full/LMT Gain Index
+		status = ad9361_reg_write(dev, 0x0109, 0x20);	// Rx1 Full/LMT Gain Index
 		status = ad9361_reg_write(dev, 0x010A, 0x58);	// Rx1 LPF Gain Index
 		status = ad9361_reg_write(dev, 0x010B, 0x00);	// Rx1 Digital Gain Index
-		status = ad9361_reg_write(dev, 0x010C, 0x00);	// Rx2 Full/LMT Gain Index
+		status = ad9361_reg_write(dev, 0x010C, 0x20);	// Rx2 Full/LMT Gain Index
 		status = ad9361_reg_write(dev, 0x010D, 0x18);	// Rx2 LPF Gain Index
 		status = ad9361_reg_write(dev, 0x010E, 0x00);	// Rx2 Digital Gain Index
 		status = ad9361_reg_write(dev, 0x0114, 0x30);	// Low Power Threshold

src/hwconfig.c

@@ -259,10 +259,10 @@ int32_t Hardware_Init(void)
 	//	Status = ad9361_reg_read(ad9361_1_reg_inst, 0x0002, &rd_back);
 	//	Status = ad9361_reg_read(ad9361_2_reg_inst, 0x0002, &rd_back);
 
-	Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0109, 0x00); // Rx Gain
-	Status = ad9361_reg_write(ad9361_1_reg_inst, 0x010C, 0x00); // Rx Gain
-	Status = ad9361_reg_write(ad9361_2_reg_inst, 0x0109, 0x00); // Rx Gain
-	Status = ad9361_reg_write(ad9361_2_reg_inst, 0x010C, 0x00); // Rx Gain
+	// Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0109, 0x00); // Rx Gain
+	// Status = ad9361_reg_write(ad9361_1_reg_inst, 0x010C, 0x00); // Rx Gain
+	// Status = ad9361_reg_write(ad9361_2_reg_inst, 0x0109, 0x00); // Rx Gain
+	// Status = ad9361_reg_write(ad9361_2_reg_inst, 0x010C, 0x00); // Rx Gain
 #endif
 
 #ifdef AD9653

src/networking/phy_layer/phy_layer.c

@@ -696,6 +696,7 @@ int32_t Phy_SetupNextSlot(PHY_INST *instPtr, PHY_TOR_TYPE txrxMode,
 	ASSERT(instPtr != NULL);
 	int32_t Status;
 	uint32_t phyModeCtrl, hopNum;
+	uint16_t txMultifactor; // physical layer tx power digital attenuation
 	const uint8_t *hopPattern;
 	// Implement a ping-pong flow, offset always is 0 or half of buffer depth.
 	instPtr->antConfigOffset = (L1_ANTCONFIG_MAX_LEN >> 1) - instPtr->antConfigOffset;
@@ -721,26 +722,31 @@ int32_t Phy_SetupNextSlot(PHY_INST *instPtr, PHY_TOR_TYPE txrxMode,
 		phyModeCtrl |= PHY_MODE_CTRL_FRAME_ADV_24MS;
 		hopNum = L1_FRAME_ADV_24MS_HOPS;
 		hopPattern = hopPattern_ADV_24MS;
+		txMultifactor = 0x4023; // -12dB
 		break;
 	case L1_FRAME_ACK_8MS:
 		phyModeCtrl |= PHY_MODE_CTRL_FRAME_ACK_8MS;
 		hopNum = L1_FRAME_ACK_8MS_HOPS;
 		hopPattern = hopPattern_ACK_8MS;
+		txMultifactor = 0x4023; // -12dB
 		break;
 	case L1_FRAME_128KBPS_4MS:
 		phyModeCtrl |= PHY_MODE_CTRL_FRAME_128KBPS_4MS;
 		hopNum = L1_FRAME_128KBPS_4MS_HOPS;
 		hopPattern = hopPattern_128KBPS_4MS;
+		txMultifactor = 0x2D84; // -15dB
 		break;
 	case L1_FRAME_512KBPS_4MS:
 		phyModeCtrl |= PHY_MODE_CTRL_FRAME_512KBPS_4MS;
 		hopNum = L1_FRAME_512KBPS_4MS_HOPS;
 		hopPattern = hopPattern_512KBPS_4MS;
+		txMultifactor = 0x4023; // -12dB
 		break;
 	case L1_FRAME_2MBPS_4MS:
 		phyModeCtrl |= PHY_MODE_CTRL_FRAME_2MBPS_4MS;
 		hopNum = L1_FRAME_2MBPS_4MS_HOPS;
 		hopPattern = hopPattern_2MBPS_4MS;
+		txMultifactor = 0x8000; // -6dB, baseline
 		break;
 	default:
 		return EPARAM;
@@ -794,6 +800,9 @@ int32_t Phy_SetupNextSlot(PHY_INST *instPtr, PHY_TOR_TYPE txrxMode,
 		}
 	}
 
+	// Set tx multifactor
+	PhyWrite(instPtr, TX_MULFAC, txMultifactor);
+
 	// Trigger physical configuration.
 	// Indicate physical layer that all the configurations were done.
 	PhyWrite(instPtr, SLOT_CMD, SLOT_CMD_KEY);

src/networking/phy_layer/phy_reg.h

@@ -207,7 +207,7 @@
 /**
  * Register: TM_TARGET_L
  */
-#define TM_TARGET_L 0x00000064U
+#define TM_TARGET_L 0x00000034U
 #define TM_TARGET_L_SHIFT 0
 #define TM_TARGET_L_WIDTH 32
 #define TM_TARGET_L_MASK 0xFFFFFFFFU
@@ -260,6 +260,14 @@
 #define ANT_SELECT_INDEX_WIDTH 32
 #define ANT_SELECT_INDEX_MASK 0xFFFFFFFFU
 
+/**
+ * Register: TX_MULFAC
+ */
+#define TX_MULFAC 0x00000048U
+#define TX_MULFAC_SHIFT 0
+#define TX_MULFAC_WIDTH 16
+#define TX_MULFAC_MASK 0x0000FFFFU
+
 /**
  * Register: ANT_STATUS_1
  */
@@ -500,4 +508,4 @@
 
 /** @} PhysicalLayer_REG_Constants*/
 
-/** @} PhysicalLayer*/
+/** @} PhysicalLayer*/