forked from 0xha0/df_datalink
512 lines
13 KiB
C
512 lines
13 KiB
C
/*****************************************************************************/
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/**
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* @file phy_layer.h
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* @author FanHao ([email protected])
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* @brief Physical layer controller register definition
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* @version 0.0
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* @date 2023-04-24
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*
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* @copyright Copyright(c) 2024 Beijing Institute of Technology.\n
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* Lab of Communication and Network
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*
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******************************************************************************/
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/**
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* @defgroup PhysicalLayer
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* @{
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*/
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/**
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* @name PhysicalLayer_REG_Constants
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* @{
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*/
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#ifndef PHY_REG_H_
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#define PHY_REG_H_
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/***************************** Include Files *********************************/
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#include "util.h"
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/***************** Macros (Inline Functions) Definitions *********************/
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#define PhyRead(instPtr, addr) IO_In32((instPtr)->phyCofig.baseAddr + (addr))
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#define PhyWrite(instPtr, addr, value) IO_Out32((instPtr)->phyCofig.baseAddr + (addr), (value))
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/************************** Constant Definitions *****************************/
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/**
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* Register: PHY_MAIN_CTRL
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*/
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#define PHY_MAIN_CTRL 0x00000000U
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#define PHY_MAIN_CTRL_EN_SHIFT 0
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#define PHY_MAIN_CTRL_EN_WIDTH 1
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#define PHY_MAIN_CTRL_EN_MASK 0x00000001U
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#define PHY_MAIN_CTRL_MODE_SHIFT 8
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#define PHY_MAIN_CTRL_MODE_WIDTH 8
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#define PHY_MAIN_CTRL_MODE_MASK 0x0000FF00U
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#define PHY_MAIN_CTRL_NSCAN_SHIFT 16
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#define PHY_MAIN_CTRL_NSCAN_WIDTH 8
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#define PHY_MAIN_CTRL_NSCAN_MASK 0x00FF0000U
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#define PHY_MAIN_CTRL_EN_EN 0x00000001U
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#define PHY_MAIN_CTRL_EN_DSBL 0x00000000U
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#define PHY_MAIN_CTRL_MODE_NONE 0x00000000U
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#define PHY_MAIN_CTRL_MODE_LISTEN 0x00000100U
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#define PHY_MAIN_CTRL_MODE_SCHEDULE 0x00000200U // not used
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#define PHY_MAIN_CTRL_MODE_POLL 0x00000300U
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/**
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* Register: TXRX_CTRL
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*/
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#define PHY_MODE_CTRL 0x00000004U
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#define PHY_MODE_CTRL_TOR_SHIFT 0
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#define PHY_MODE_CTRL_TOR_WIDTH 8
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#define PHY_MODE_CTRL_TOR_MASK 0x000000FFU
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#define PHY_MODE_CTRL_FRAME_SHIFT 8
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#define PHY_MODE_CTRL_FRAME_WIDTH 8
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#define PHY_MODE_CTRL_FRAME_MASK 0x0000FF00U
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#define PHY_MODE_CTRL_CRC_SHIFT 8
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#define PHY_MODE_CTRL_CRC_WIDTH 16
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#define PHY_MODE_CTRL_CRC_MASK 0x00FF0000U
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#define PHY_MODE_CTRL_TOR_SUSPEND 0x00000000U
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#define PHY_MODE_CTRL_TOR_TX 0x00000001U
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#define PHY_MODE_CTRL_TOR_RX 0x00000002U
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#define PHY_MODE_CTRL_FRAME_NONE 0x00000000U
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#define PHY_MODE_CTRL_FRAME_ADV_24MS 0x00000100U
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#define PHY_MODE_CTRL_FRAME_ACK_8MS 0x00000200U
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#define PHY_MODE_CTRL_FRAME_128KBPS_4MS 0x00000300U
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#define PHY_MODE_CTRL_FRAME_512KBPS_4MS 0x00000400U
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#define PHY_MODE_CTRL_FRAME_2MBPS_4MS 0x00000500U
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#define PHY_MODE_CTRL_CRC_EN 0x00010000U
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#define PHY_MODE_CTRL_CRC_DSBL 0x00000000U
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/**
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* Register: POLLTIME_L
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*/
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#define POLLTIME_L 0x00000008U
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#define POLLTIME_L_SHIFT 0
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#define POLLTIME_L_WIDTH 32
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#define POLLTIME_L_MASK 0xFFFFFFFFU
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/**
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* Register: POLLTIME_H
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*/
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#define POLLTIME_H 0x0000000CU
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#define POLLTIME_H_SHIFT 0
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#define POLLTIME_H_WIDTH 32
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#define POLLTIME_H_MASK 0xFFFFFFFFU
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/**
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* Register: TIMEOUT_L
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*/
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#define LISTENTIMEOUT_L 0x00000010U
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#define LISTENTIMEOUT_L_SHIFT 0
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#define LISTENTIMEOUT_L_WIDTH 32
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#define LISTENTIMEOUT_L_MASK 0xFFFFFFFFU
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/**
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* Register: TIMEOUT_H
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*/
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#define LISTENTIMEOUT_H 0x00000014U
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#define LISTENTIMEOUT_H_SHIFT 0
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#define LISTENTIMEOUT_H_WIDTH 32
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#define LISTENTIMEOUT_H_MASK 0xFFFFFFFFU
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/**
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* Register: ANT_CTRL
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*/
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#define ANT_CONFIG 0x00000018U
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#define ANT_CONFIG_OFFSET_SHIFT 0
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#define ANT_CONFIG_OFFSET_WIDTH 16
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#define ANT_CONFIG_OFFSET_MASK 0x0000FFFFU
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#define ANT_CONFIG_LEN_SHIFT 16
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#define ANT_CONFIG_LEN_WIDTH 8
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#define ANT_CONFIG_LEN_MASK 0x00FF0000U
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#define ANT_CONFIG_NUM_SHIFT 24
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#define ANT_CONFIG_NUM_WIDTH 8
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#define ANT_CONFIG_NUM_MASK 0xFF000000U
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/**
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* Register: SEND_DATA_CMD
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*/
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#define SEND_DATA_CMD 0x0000001CU
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#define SEND_DATA_CMD_SHIFT 0
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#define SEND_DATA_CMD_WIDTH 32
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#define SEND_DATA_CMD_MASK 0xFFFFFFFFU
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#define SEND_DATA_CMD_LEN_SHIFT 0
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#define SEND_DATA_CMD_LEN_WIDTH 16
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#define SEND_DATA_CMD_LEN_MASK 0x0000FFFFU
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#define SEND_DATA_CMD_OFFSET_SHIFT 16
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#define SEND_DATA_CMD_OFFSET_WIDTH 16
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#define SEND_DATA_CMD_OFFSET_MASK 0xFFFF0000U
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/**
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* Register: SLOT_CONFIG_CMD
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*/
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#define SLOT_CMD 0x00000020U
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#define SLOT_CMD_SHIFT 0
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#define SLOT_CMD_WIDTH 32
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#define SLOT_CMD_MASK 0xFFFFFFFFU
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#define SLOT_CMD_KEY 0x434D442EU
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/**
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* Register: TXRX_STATE
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*/
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#define TXRX_STATE 0x00000024U
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#define TXRX_STATE_ACQ_SHIFT 0
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#define TXRX_STATE_ACQ_WIDTH 8
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#define TXRX_STATE_ACQ_MASK 0x000000FFU
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#define TXRX_STATE_ACQ_SUCCESS 0x00000001U
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#define TXRX_STATE_ACQ_FAIL 0x00000002U
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#define TXRX_STATE_FSYNC_SHIFT 8
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#define TXRX_STATE_FSYNC_WIDTH 8
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#define TXRX_STATE_FSYNC_MASK 0x0000FF00U
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#define TXRX_STATE_FSYNC_SUCCESS 0x00000100U
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#define TXRX_STATE_FSYNC_FAIL 0x00000200U
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#define TXRX_STATE_DECODE_SHIFT 16
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#define TXRX_STATE_DECODE_WIDTH 8
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#define TXRX_STATE_DECODE_MASK 0x00FF0000U
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#define TXRX_STATE_DECODE_SUCCESS 0x00010000U
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#define TXRX_STATE_DECODE_FAIL 0x00020000U
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#define TXRX_STATE_CRC_SHIFT 24
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#define TXRX_STATE_CRC_WIDTH 8
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#define TXRX_STATE_CRC_MASK 0xFF000000U
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#define TXRX_STATE_CRC_OK 0x01000000U
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#define TXRX_STATE_CRC_ERROR 0x02000000U
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/**
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* Register: RECVDATA_STATE
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*/
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#define RECVDATA_STATE 0x00000028U
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#define RECVDATA_STATE_LEN_SHIFT 0
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#define RECVDATA_STATE_LEN_WIDTH 16
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#define RECVDATA_STATE_LEN_MASK 0x0000FFFFU
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#define RECVDATA_STATE_OFFSET_SHIFT 16
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#define RECVDATA_STATE_OFFSET_WIDTH 16
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#define RECVDATA_STATE_OFFSET_MASK 0xFFFF0000U
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/**
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* Register: FSTIME_L
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*/
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#define FSTIME_L 0x0000002CU
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#define FSTIME_L_SHIFT 0
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#define FSTIME_L_WIDTH 32
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#define FSTIME_L_MASK 0xFFFFFFFFU
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/**
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* Register: FSTIME_INT1
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*/
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#define FSTIME_H 0x00000030U
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#define FSTIME_H_SHIFT 0
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#define FSTIME_H_WIDTH 32
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#define FSTIME_H_MASK 0xFFFFFFFFU
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/**
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* Register: TM_TARGET_L
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*/
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#define TM_TARGET_L 0x00000034U
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#define TM_TARGET_L_SHIFT 0
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#define TM_TARGET_L_WIDTH 32
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#define TM_TARGET_L_MASK 0xFFFFFFFFU
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/**
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* Register: TM_TARGET_H
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*/
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#define TM_TARGET_H 0x00000038U
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#define TM_TARGET_H_SHIFT 0
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#define TM_TARGET_H_WIDTH 32
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#define TM_TARGET_H_MASK 0xFFFFFFFFU
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/**
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* Register: COASEFREQEST
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*/
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#define COASE_FREQEST 0x0000003CU
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#define COASE_FREQEST_ACQ_SHIFT 0
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#define COASE_FREQEST_ACQ_WIDTH 8
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#define COASE_FREQEST_ACQ_MASK 0x000000FFU
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#define COASE_FREQEST_SYNC_SHIFT 8
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#define COASE_FREQEST_SYNC_WIDTH 8
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#define COASE_FREQEST_SYNC_MASK 0x0000FF00U
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#define COASE_TYPE_SHIFT 16
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#define COASE_TYPE_WIDTH 8
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#define COASE_TYPE_MASK 0x00FF0000U
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#define COASE_TYPE_ADV_24MS 0x00010000U
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#define COASE_TYPE_ACK_8MS 0x00020000U
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#define COASE_TYPE_128KBPS_4MS 0x00030000U
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#define COASE_TYPE_512KBPS_4MS 0x00040000U
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#define COASE_TYPE_2MBPS_4MS 0x00050000U
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/**
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* Register: FINE_FREQEST
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*/
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#define FINE_FREQEST 0x00000040U
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#define FINE_FREQEST_VAL_SHIFT 0
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#define FINE_FREQEST_VAL_WIDTH 24
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#define FINE_FREQEST_VAL_MASK 0x00FFFFFFU
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#define FINE_FREQEST_SIGN_SHIFT 24
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#define FINE_FREQEST_SIGN_WIDTH 8
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#define FINE_FREQEST_SIGN_MASK 0xFF000000U
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#define FINE_FREQEST_SIGN_POS 0x00000000U
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#define FINE_FREQEST_SIGN_NEG 0x01000000U
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/**
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* Register: ANT_SELECT
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*/
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#define ANT_SELECT_INDEX 0x00000044U
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#define ANT_SELECT_INDEX_SHIFT 0
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#define ANT_SELECT_INDEX_WIDTH 32
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#define ANT_SELECT_INDEX_MASK 0xFFFFFFFFU
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/**
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* Register: TX_MULFAC
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*/
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#define TX_MULFAC 0x00000048U
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#define TX_MULFAC_SHIFT 0
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#define TX_MULFAC_WIDTH 16
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#define TX_MULFAC_MASK 0x0000FFFFU
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/**
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* Register: ANT_STATUS_1
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*/
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#define ANT_STATUS_1 0x00000100U
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#define ANT_STATUS_1_ANT1_STATUS_SHIFT 0
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#define ANT_STATUS_1_ANT1_STATUS_WIDTH 16
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#define ANT_STATUS_1_ANT1_STATUS_MASK 0x0000FFFFU
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#define ANT_STATUS_1_ANT1_FREQ_SHIFT 0
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#define ANT_STATUS_1_ANT1_FREQ_WIDTH 15
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#define ANT_STATUS_1_ANT1_FREQ_MASK 0x00003FFFU
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#define ANT_STATUS_1_ANT1_PLL_SHIFT 15
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#define ANT_STATUS_1_ANT1_PLL_WIDTH 1
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#define ANT_STATUS_1_ANT1_PLL_MASK 0x00008000U
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#define ANT_STATUS_1_ANT2_STATUS_SHIFT 16
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#define ANT_STATUS_1_ANT2_STATUS_WIDTH 16
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#define ANT_STATUS_1_ANT2_STATUS_MASK 0x0000FFFFU
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#define ANT_STATUS_1_ANT2_FREQ_SHIFT 16
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#define ANT_STATUS_1_ANT2_FREQ_WIDTH 15
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#define ANT_STATUS_1_ANT2_FREQ_MASK 0x3FFF0000U
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#define ANT_STATUS_1_ANT2_PLL_SHIFT 31
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#define ANT_STATUS_1_ANT2_PLL_WIDTH 1
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#define ANT_STATUS_1_ANT2_PLL_MASK 0x80000000U
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/**
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* Register: ANT_STATUS_2
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*/
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#define ANT_STATUS_2 0x00000104U
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#define ANT_STATUS_2_ANT3_STATUS_SHIFT 0
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#define ANT_STATUS_2_ANT3_STATUS_WIDTH 16
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#define ANT_STATUS_2_ANT3_STATUS_MASK 0x0000FFFFU
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#define ANT_STATUS_2_ANT3_FREQ_SHIFT 0
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#define ANT_STATUS_2_ANT3_FREQ_WIDTH 15
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#define ANT_STATUS_2_ANT3_FREQ_MASK 0x00003FFFU
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#define ANT_STATUS_2_ANT3_PLL_SHIFT 15
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#define ANT_STATUS_2_ANT3_PLL_WIDTH 1
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#define ANT_STATUS_2_ANT3_PLL_MASK 0x00008000U
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#define ANT_STATUS_2_PLL_LK_SHIFT 16
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#define ANT_STATUS_2_PLL_LK_WIDTH 8
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#define ANT_STATUS_2_PLL_LK_MASK 0x00FF0000U
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#define ANT_STATUS_2_ANT3_PLL2_LK_SHIFT 16
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#define ANT_STATUS_2_ANT3_PLL2_LK_WIDTH 1
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#define ANT_STATUS_2_ANT3_PLL2_LK_MASK 0x00010000U
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#define ANT_STATUS_2_ANT3_PLL1_LK_SHIFT 17
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#define ANT_STATUS_2_ANT3_PLL1_LK_WIDTH 1
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#define ANT_STATUS_2_ANT3_PLL1_LK_MASK 0x00020000U
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#define ANT_STATUS_2_ANT2_PLL2_LK_SHIFT 18
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#define ANT_STATUS_2_ANT2_PLL2_LK_WIDTH 1
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#define ANT_STATUS_2_ANT2_PLL2_LK_MASK 0x00040000U
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#define ANT_STATUS_2_ANT2_PLL1_LK_SHIFT 19
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#define ANT_STATUS_2_ANT2_PLL1_LK_WIDTH 1
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#define ANT_STATUS_2_ANT2_PLL1_LK_MASK 0x00080000U
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#define ANT_STATUS_2_ANT1_PLL2_LK_SHIFT 20
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#define ANT_STATUS_2_ANT1_PLL2_LK_WIDTH 1
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#define ANT_STATUS_2_ANT1_PLL2_LK_MASK 0x00100000U
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#define ANT_STATUS_2_ANT1_PLL1_LK_SHIFT 21
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#define ANT_STATUS_2_ANT1_PLL1_LK_WIDTH 1
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#define ANT_STATUS_2_ANT1_PLL1_LK_MASK 0x00200000U
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#define ANT_STATUS_2_MODE_SHIFT 24
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#define ANT_STATUS_2_MODE_WIDTH 8
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#define ANT_STATUS_2_MODE_MASK 0xFF000000U
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#define ANT_STATUS_2_ANT1_MODE_SHIFT 24
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#define ANT_STATUS_2_ANT1_MODE_WIDTH 1
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#define ANT_STATUS_2_ANT1_MODE_MASK 0x01000000U
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#define ANT_STATUS_2_ANT2_MODE_SHIFT 25
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#define ANT_STATUS_2_ANT2_MODE_WIDTH 1
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#define ANT_STATUS_2_ANT2_MODE_MASK 0x02000000U
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#define ANT_STATUS_2_ANT3_MODE_SHIFT 26
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#define ANT_STATUS_2_ANT3_MODE_WIDTH 1
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#define ANT_STATUS_2_ANT3_MODE_MASK 0x04000000U
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/**
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* Register: ANT_STATUS_TEMP
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*/
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#define ANT_STATUS_TEMP 0x00000108U
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#define ANT_STATUS_TEMP_SHIFT 0
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#define ANT_STATUS_TEMP_WIDTH 8
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#define ANT_STATUS_TEMP_MASK 0x000000FFU
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#define ANT_STATUS_TEMP_RSVD_SHIFT 8
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#define ANT_STATUS_TEMP_RSVD_WIDTH 8
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#define ANT_STATUS_TEMP_RSVD_MASK 0x0000FF00U
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/**
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* Register: PHY_ACQ_CNT
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*/
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#define PHY_ACQ_CNT 0x00000114U
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#define PHY_ACQ_CNT_SHIFT 0
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#define PHY_ACQ_CNT_WIDTH 32
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#define PHY_ACQ_CNT_MASK 0xFFFFFFFFU
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/**
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* Register: PHY_FRAME_SYNC_CNT
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*/
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#define PHY_FRAME_SYNC_CNT 0x00000118U
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#define PHY_FRAME_SYNC_CNT_SHIFT 0
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#define PHY_FRAME_SYNC_CNT_WIDTH 32
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#define PHY_FRAME_SYNC_CNT_MASK 0xFFFFFFFFU
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/**
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* Register: PHY_DECODE_CNT
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*/
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#define PHY_DECODE_CNT 0x0000011CU
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#define PHY_DECODE_CNT_SHIFT 0
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#define PHY_DECODE_CNT_WIDTH 32
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#define PHY_DECODE_CNT_MASK 0xFFFFFFFFU
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/**
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* Register: PHY_CRC_OK_CNT
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*/
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#define PHY_CRC_OK_CNT 0x00000120U
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#define PHY_CRC_OK_CNT_SHIFT 0
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#define PHY_CRC_OK_CNT_WIDTH 32
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#define PHY_CRC_OK_CNT_MASK 0xFFFFFFFFU
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/**
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* Register: PHY_ACQ_PEAK_H
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*/
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#define PHY_ACQ_PEAK_H 0x00000124U
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#define PHY_ACQ_PEAK_H_SHIFT 0
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#define PHY_ACQ_PEAK_H_WIDTH 32
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#define PHY_ACQ_PEAK_H_MASK 0xFFFFFFFFU
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/**
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* Register: PHY_ACQ_PEAK_L
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*/
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#define PHY_ACQ_PEAK_L 0x00000128U
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#define PHY_ACQ_PEAK_L_SHIFT 0
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#define PHY_ACQ_PEAK_L_WIDTH 32
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#define PHY_ACQ_PEAK_L_MASK 0xFFFFFFFFU
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/**
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* Register: PHY_ACQ_MEAN_H
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*/
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#define PHY_ACQ_MEAN_H 0x0000012CU
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#define PHY_ACQ_MEAN_H_SHIFT 0
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#define PHY_ACQ_MEAN_H_WIDTH 32
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#define PHY_ACQ_MEAN_H_MASK 0xFFFFFFFFU
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/**
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* Register: PHY_ACQ_MEAN_L
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*/
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#define PHY_ACQ_MEAN_L 0x00000130U
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#define PHY_ACQ_MEAN_L_SHIFT 0
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#define PHY_ACQ_MEAN_L_WIDTH 32
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#define PHY_ACQ_MEAN_L_MASK 0xFFFFFFFFU
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/**
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* Register: PHY_ACQ_FREQEST
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*/
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#define PHY_ACQ_FREQEST 0x00000134U
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#define PHY_ACQ_FREQEST_SHIFT 0
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#define PHY_ACQ_FREQEST_WIDTH 32
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#define PHY_ACQ_FREQEST_MASK 0xFFFFFFFFU
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#define PHY_ACQ_FREQEST_PHASE_SHIFT 0
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#define PHY_ACQ_FREQEST_PHASE_WIDTH 8
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#define PHY_ACQ_FREQEST_PHASE_MASK 0x000000FFU
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#define PHY_ACQ_FREQEST_CHANNEL_SHIFT 8
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#define PHY_ACQ_FREQEST_CHANNEL_WIDTH 8
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#define PHY_ACQ_FREQEST_CHANNEL_MASK 0x0000FF00U
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/**
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* Register: PHY_FRAME_SYNC_PEAK_H
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*/
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#define PHY_FRAME_SYNC_PEAK_H 0x00000138U
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#define PHY_FRAME_SYNC_PEAK_H_SHIFT 0
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#define PHY_FRAME_SYNC_PEAK_H_WIDTH 32
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#define PHY_FRAME_SYNC_PEAK_H_MASK 0xFFFFFFFFU
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/**
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* Register: PHY_FRAME_SYNC_PEAK_L
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*/
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#define PHY_FRAME_SYNC_PEAK_L 0x0000013CU
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#define PHY_FRAME_SYNC_PEAK_L_SHIFT 0
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#define PHY_FRAME_SYNC_PEAK_L_WIDTH 32
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#define PHY_FRAME_SYNC_PEAK_L_MASK 0xFFFFFFFFU
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/**
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* Register: PHY_FRAME_SYNC_MEAN_H
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*/
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#define PHY_FRAME_SYNC_MEAN_H 0x00000140U
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#define PHY_FRAME_SYNC_MEAN_H_SHIFT 0
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#define PHY_FRAME_SYNC_MEAN_H_WIDTH 32
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#define PHY_FRAME_SYNC_MEAN_H_MASK 0xFFFFFFFFU
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/**
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* Register: PHY_FRAME_SYNC_MEAN_L
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*/
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#define PHY_FRAME_SYNC_MEAN_L 0x00000144U
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#define PHY_FRAME_SYNC_MEAN_L_SHIFT 0
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#define PHY_FRAME_SYNC_MEAN_L_WIDTH 32
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#define PHY_FRAME_SYNC_MEAN_L_MASK 0xFFFFFFFFU
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/**
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* Register: PHY_FRAME_SYNC_FREQEST
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*/
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#define PHY_FRAME_SYNC_FREQEST 0x00000148U
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#define PHY_FRAME_SYNC_FREQEST_SHIFT 0
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#define PHY_FRAME_SYNC_FREQEST_WIDTH 32
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#define PHY_FRAME_SYNC_FREQEST_MASK 0xFFFFFFFFU
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#define PHY_FRAME_SYNC_FREQEST_CHANNEL_SHIFT 0
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#define PHY_FRAME_SYNC_FREQEST_CHANNEL_WIDTH 8
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#define PHY_FRAME_SYNC_FREQEST_CHANNEL_MASK 0x000000FFU
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/**
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* Register: PHY_DEINTLV_AMPEST
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*/
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#define PHY_DEINTLV_AMPEST 0x0000014CU
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#define PHY_DEINTLV_AMPEST_SHIFT 0
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#define PHY_DEINTLV_AMPEST_WIDTH 16
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#define PHY_DEINTLV_AMPEST_MASK 0x0000FFFFU
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#endif /* PHY_REG_H_ */
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/** @} PhysicalLayer_REG_Constants*/
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/** @} PhysicalLayer*/
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