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Update gitignore, add dl814_z7 project

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gitignore structure is updated to work with single and multi project situation under a single project directory
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josh
2023-03-29 10:42:01 +08:00
parent b000e2702e
commit cd256a8cd6
2246 changed files with 7838223 additions and 86 deletions
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projects/datalink_814/dl814_z7/rtl/antenna_interface.v
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2022/09/01 14:39:50
// Design Name:
// Module Name: antenna_interface
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module antenna_interface
#(
parameter [15:0] FRAME_HEAD = 16'hCCCC,
parameter [15:0] FRAME_TAIL = 16'hF0F0,
parameter [15:0] FRAME_LENGTH = 16'h0100,//include frame_head and frame_tail
parameter [15:0] REST_LENGTH = 16'h0014,
parameter [15:0] FRAME_MAX_LENGTH = 16'h0200,
parameter [15:0] REST_MAX_LENGTH = 16'h0020
)
(
input clk_in ,
input data_in ,
input tr_in ,
input dary_in ,
input rst ,
output reg ant_clk ,
output en_out ,
input clk_out ,
output data_out ,
output tr_out ,
output dary_out ,
//debug
output reg [15:0] debug_freq ,
output reg debug_freq_change ,
output [63:0] debug_tr_count
);
reg fifo_data_in ;
wire fifo_data_out ;
reg fifo_wr_en ;
reg fifo_rd_en ;
wire fifo_full ;
wire fifo_empty ;
wire valid ;
fifo_en_creat u_fifo_en_creat (
.wr_clk(clk_in), // input wire wr_clk
.wr_rst(rst), // input wire wr_rst
.rd_clk(clk_out), // input wire rd_clk
.rd_rst(rst), // input wire rd_rst
.din(fifo_data_in), // input wire [0 : 0] din
.wr_en(fifo_wr_en), // input wire wr_en
.rd_en(fifo_rd_en), // input wire rd_en
.dout(fifo_data_out), // output wire [0 : 0] dout
.full(fifo_full), // output wire full
.empty(fifo_empty), // output wire empty
.valid(valid) // output wire valid
);
reg [3:0] rx_state_next;
reg [3:0] rx_state;
reg [3:0] tx_state_next;
reg [3:0] tx_state;
localparam WAIT = 4'd0;
localparam RECV = 4'd1;
localparam SEND = 4'd2;
localparam REST = 4'd3;
//1 to 8
reg [16:0] data_in_9;
always @ ( posedge clk_in or posedge rst) begin
if ( rst ) begin
data_in_9 <= 17'd0;
end
else begin
data_in_9 <= {data_in_9[15:0],data_in};
end
end
//cnt
reg [15:0] rx_bitcnt;
always @(posedge clk_in or posedge rst) begin
if(rst) begin
rx_bitcnt[15:0] <= 16'd0;
end
else if(rx_state == RECV) begin
rx_bitcnt[15:0] <= rx_bitcnt[15:0]+16'd1;
end
else begin
rx_bitcnt[15:0] <= 16'd0;
end
end
reg [15:0] tx_bitcnt;
always @(posedge clk_out or posedge rst) begin
if(rst) begin
tx_bitcnt[15:0] <= 16'd0;
end
else if(tx_state == SEND) begin
tx_bitcnt[15:0] <= tx_bitcnt[15:0]+16'd1;
end
else begin
tx_bitcnt[15:0] <= 16'd0;
end
end
reg [15:0] rest_cnt;
always @(posedge clk_out or posedge rst) begin
if(rst) begin
rest_cnt[15:0] <= 16'd0;
end
else if(tx_state == REST) begin
rest_cnt[15:0] <= rest_cnt[15:0]+16'd1;
end
else begin
rest_cnt[15:0] <= 16'd0;
end
end
// state machine
reg recv_down;
reg recv_down_d1;
reg recv_down_d2;
reg recv_down_d3;
//rx
always @ (*) begin
case (rx_state)
WAIT : begin
if ( data_in_9[15:0] == FRAME_HEAD) begin //can write
rx_state_next <= RECV;
end
else begin
rx_state_next <= WAIT;
end
end
RECV : begin // write
if(rx_bitcnt[15:0] == FRAME_LENGTH - 16'b1) begin//write end
rx_state_next <= WAIT;
end
else if(rx_bitcnt[15:0] > FRAME_MAX_LENGTH)begin //overtime
rx_state_next <= WAIT;
end
else begin
rx_state_next <= RECV;
end
end
default : begin
rx_state_next <= WAIT;
end
endcase
end
always @(posedge clk_in) begin
rx_state <= rx_state_next;
end
//tx
always @ (*) begin
case (tx_state)
WAIT : begin
if (recv_down_d2^recv_down_d3) begin //can write
tx_state_next <= SEND;
end
else begin
tx_state_next <= WAIT;
end
end
SEND : begin // read
if(tx_bitcnt[15:0] == FRAME_LENGTH - 16'b1) begin//read end
tx_state_next <= REST;
end
else if(tx_bitcnt[15:0] > FRAME_MAX_LENGTH)begin //overtime
tx_state_next <= WAIT;
end
else begin
tx_state_next <= SEND;
end
end
REST : begin // rest
if(rest_cnt[15:0] == REST_LENGTH - 16'b1) begin//rest end
tx_state_next <= WAIT;
end
else if(rest_cnt[15:0] > REST_MAX_LENGTH)begin //overtime
tx_state_next <= WAIT;
end
else begin
tx_state_next <= REST;
end
end
default : begin
tx_state_next <= WAIT;
end
endcase
end
always @(posedge clk_out) begin
tx_state <= tx_state_next;
end
//recv_down flag
always @ ( posedge clk_in or posedge rst) begin
if ( rst ) begin
recv_down <= 1'b0;
end
else if((rx_state == RECV)&&(rx_state_next == WAIT)) begin
recv_down <= ~recv_down;
end
else begin
recv_down <= recv_down;
end
end
always @ ( posedge clk_out or posedge rst) begin
if ( rst ) begin
recv_down_d1 <= 1'b0;
recv_down_d2 <= 1'b0;
recv_down_d3 <= 1'b0;
end
else begin
recv_down_d1 <= recv_down;
recv_down_d2 <= recv_down_d1;
recv_down_d3 <= recv_down_d2;
end
end
//fifo control
always @ ( posedge clk_in or posedge rst) begin
if ( rst ) begin
fifo_data_in <= 1'b0;
end
else if(rx_state == RECV) begin
fifo_data_in <= data_in_9[16];
end
else begin
fifo_data_in <= 1'b0;
end
end
always @ ( posedge clk_in or posedge rst) begin
if ( rst ) begin
fifo_wr_en <= 1'b0;
end
else if(rx_state == RECV ) begin
fifo_wr_en <= 1'b1;
end
else begin
fifo_wr_en <= 1'b0;
end
end
reg data_out_reg;
always @ ( posedge clk_out or posedge rst) begin
if ( rst ) begin
data_out_reg <= 1'b0;
end
else if(valid) begin
data_out_reg <= fifo_data_out;
end
else if(tx_state == REST) begin
data_out_reg <= 1'b0;
end
else begin
data_out_reg <= 1'b0;
end
end
assign data_out = data_out_reg;
always @ ( posedge clk_out or posedge rst) begin
if ( rst ) begin
fifo_rd_en <= 1'b0;
end
else if(tx_state == SEND) begin
fifo_rd_en <= 1'b1;
end
else begin
fifo_rd_en <= 1'b0;
end
end
//en create
reg en_out_reg;
reg en_out_reg_d1;
always @ ( posedge clk_out or posedge rst) begin
if ( rst ) begin
en_out_reg <= 1'b1;
en_out_reg_d1 <= 1'b1;
end
else begin
en_out_reg <= ~fifo_rd_en;
en_out_reg_d1 <= en_out_reg;
end
end
assign en_out = en_out_reg_d1;
//beam_clk
wire beam_clk;
reg beam_clk_reg;
reg beam_clk_reg_d1;
reg beam_clk_reg_d2;
always @ ( posedge clk_out or posedge rst) begin
if ( rst ) begin
beam_clk_reg <= 1'b0;
end
else if(tx_state == SEND || tx_state == REST) begin
beam_clk_reg <= 1'b1;
end
else begin
beam_clk_reg <= 1'b0;
end
end
always @ ( posedge clk_out or posedge rst) begin
if ( rst ) begin
beam_clk_reg_d1 <= 1'b0;
beam_clk_reg_d2 <= 1'b0;
end
else begin
beam_clk_reg_d1 <= beam_clk_reg;
beam_clk_reg_d2 <= beam_clk_reg_d1;
end
end
assign beam_clk = beam_clk_reg_d2;
//tr dary
reg tr_d1;
reg tr_d2;
always @ ( posedge clk_out or posedge rst) begin
if ( rst ) begin
tr_d1 <= 1'b0;
tr_d2 <= 1'b0;
end
else begin
tr_d1 <= tr_in;
tr_d2 <= tr_d1;
end
end
assign tr_out = tr_d2;
reg dary_d1;
reg dary_d2;
always @ ( posedge clk_out or posedge rst) begin
if ( rst ) begin
dary_d1 <= 1'b0;
dary_d2 <= 1'b0;
end
else begin
dary_d1 <= dary_in;
dary_d2 <= dary_d1;
end
end
assign dary_out = dary_d2;
//ant_clk
reg valid_d1;
always @ ( posedge clk_out or posedge rst) begin
if (rst ) begin
valid_d1 <= 1'b0;
end
else begin
valid_d1 <= valid;
end
end
always @ ( posedge clk_out or posedge rst) begin
if (rst ) begin
ant_clk <= 1'b1;
end
else if(~valid_d1 && valid) begin
ant_clk <= 1'b1;
end
else if(beam_clk) begin
ant_clk <= ~ant_clk;
end
else begin
ant_clk <= 1'b1;
end
end
//debug
reg [31:0] freq;
always @ ( posedge clk_out or posedge rst) begin
if (rst ) begin
freq[31:0] <= 32'b0;
end
else begin
freq[31:0] <= {freq[30:0],data_out_reg};
end
end
always @ ( posedge clk_out or posedge rst) begin
if (rst ) begin
debug_freq[15:0] <= 16'b0;
end
else if(tx_bitcnt == 16'h0092) begin
debug_freq[15:0] <= {freq[30],freq[28],freq[26],freq[24],freq[22],freq[20],freq[18],freq[16],freq[14],freq[12],freq[10],freq[8],freq[6],freq[4],freq[2],freq[0]};
end
else begin
debug_freq[15:0] <= debug_freq[15:0];
end
end
always @ ( posedge clk_out or posedge rst) begin
if (rst ) begin
debug_freq_change <= 1'b0;
end
else if(tx_bitcnt == 16'h0092 || tx_bitcnt == 16'h0093) begin
debug_freq_change <= 1'b1;
end
else begin
debug_freq_change <= 1'b0;
end
end
assign debug_tr_count = 64'b0;
// always @ ( posedge clk_out or posedge rst) begin
// if (rst ) begin
// debug_tr_count[63:0] <= 64'b0;
// end
// else if(tr_d1 != tr_d2) begin
// debug_tr_count[63:0] <= 64'b0;
// end
// else begin
// debug_tr_count[63:0] <= debug_tr_count[63:0] + 64'b1;
// end
// end
endmodule
projects/datalink_814/dl814_z7/rtl/c2c_bridge.v
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08/06/2022 04:29:04 PM
// Design Name:
// Module Name: c2c_bridge
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module c2c_bridge
#(
parameter [31:0] FRAME_HEAD = 31'h7E7E7E7E,
parameter [31:0] FRAME_MAX_LENGTH = 32'h00002000
)
(
input clk , // input clk, 100Mhz
input rst , // input rst, active high
//interface data
input c2c_clkin ,
output c2c_clkout,
input c2c_din ,
output c2c_dout ,
// bram interface
output tx_bram_clk , // output bram clk
output [31:0] tx_bram_addr , // output bram address[31:0]
input [31:0] tx_bram_dout , // input bram data[31:0]
output reg tx_bram_en , // output bram enable, active-high
output reg [3:0] tx_bram_we , // output bram write enable, active-high
output rx_bram_clk , // output bram clk
output reg [31:0] rx_bram_addr , // output bram address[31:0]
output reg [31:0] rx_bram_din , // output bram data[31:0]
output reg rx_bram_en , // output bram enable, active-high
output reg [3:0] rx_bram_we , // output bram write enable, active-high
// pl interrupt
output reg pl_rd_done , // output pl_rd_done, active-high
output reg pl_wr_done , // output pl_wr_done, active-high
// flag signal from ps to pl
input ps_rd_done , // input ps_rd_done, active-high
input ps_wr_done // input ps_wr_done, active-high
);
reg [31:0] c2c_in_32;
reg [39:0] tx_bitcnt;
reg [39:0] rx_bitcnt;
reg [31:0] tx_frame_length;//byte
reg [31:0] rx_frame_length;//byte
always @ ( posedge c2c_clkin or posedge rst) begin
if ( rst ) begin
c2c_in_32 <= 32'h00000000;
end
else begin
c2c_in_32 <= {c2c_in_32[30:0],c2c_din};
end
end
reg [31:0] c2c_out_32;
always @ ( posedge clk or posedge rst) begin
if ( rst ) begin
c2c_out_32 <= 32'h00000000;
end
else if(tx_bitcnt[4:0] == 5'd1) begin
c2c_out_32 <= tx_bram_dout;
end
else begin
c2c_out_32 <= {c2c_out_32[30:0],1'b0};
end
end
assign c2c_dout = c2c_out_32[31];
// dly
wire pl_read_start;
reg ps_rd_done_d0;
reg ps_rd_done_d1;
reg ps_rd_done_d2;
reg ps_wr_done_d0;
reg ps_wr_done_d1;
reg ps_wr_done_d2;
always @ ( posedge clk ) begin
if ( rst ) begin
ps_rd_done_d0 <= 1'b0;
ps_rd_done_d1 <= 1'b0;
ps_rd_done_d2 <= 1'b0;
ps_wr_done_d0 <= 1'b0;
ps_wr_done_d1 <= 1'b0;
ps_wr_done_d2 <= 1'b0;
end else begin
ps_rd_done_d0 <= ps_rd_done;
ps_rd_done_d1 <= ps_rd_done_d0;
ps_rd_done_d2 <= ps_rd_done_d1;
ps_wr_done_d0 <= ps_wr_done;
ps_wr_done_d1 <= ps_wr_done_d0;
ps_wr_done_d2 <= ps_wr_done_d1;
end
end
assign pl_read_start = ps_wr_done_d1 ^ ps_wr_done_d2;
////////////////// TX PORT /////////////////////
// state machine
reg [3:0] tx_state_next;
reg [3:0] tx_state;
localparam S_TX_WAIT = 4'd0;
localparam S_TX_PLREAD = 4'd1;
always @ (*) begin
case (tx_state)
S_TX_WAIT : begin
if ( pl_read_start ) begin //can read
tx_state_next <= S_TX_PLREAD;
end
else begin
tx_state_next <= S_TX_WAIT;
end
end
S_TX_PLREAD : begin // read bram
if(tx_bram_addr[31:0] >= tx_frame_length[31:0]) begin//frame end
tx_state_next <= S_TX_WAIT;
end
else if(tx_bram_addr > FRAME_MAX_LENGTH)begin //overtime
tx_state_next <= S_TX_WAIT;
end
else begin
tx_state_next <= S_TX_PLREAD;
end
end
default : begin
tx_state_next <= S_TX_WAIT;
end
endcase
end
always @(posedge clk) begin
tx_state <= tx_state_next;
end
//tx_bitcnt
always @(posedge clk) begin
if(rst) begin
tx_bitcnt[39:0] <= 40'd0;
end
else if(tx_state == S_TX_PLREAD) begin
tx_bitcnt[39:0] <= tx_bitcnt[39:0]+40'd1;
end
else begin
tx_bitcnt[39:0] <= 40'd0;
end
end
//tx_frame_length
always @(posedge clk) begin
if(rst) begin
tx_frame_length[31:0] <= 32'hFFFFFFFF;
end
else if(tx_bitcnt == 40'h0000000021) begin
tx_frame_length[31:0] <= tx_bram_dout;
end
else if(tx_state == S_TX_PLREAD) begin
tx_frame_length[31:0] <= tx_frame_length[31:0];
end
else begin
tx_frame_length[31:0] <= 32'hFFFFFFFF;
end
end
// tx_bram_en
// always enable
always @(posedge clk) begin
tx_bram_en <= 1'b1;
end
// tx_bram_we
// always disable
always @(posedge clk) begin
tx_bram_we[3:0] <= 4'h0;
end
//tx_bram_addr
assign tx_bram_addr = {tx_bitcnt[34:5],2'b0};
assign c2c_clkout = clk;
assign tx_bram_clk = clk;
////////////////// RX PORT /////////////////////
reg [3:0] rx_state_next;
reg [3:0] rx_state;
localparam S_RX_WAIT = 4'd0;
localparam S_RX_PLWRITE = 4'd1;
always @ (*) begin
case (rx_state)
S_TX_WAIT : begin
if ( c2c_in_32 == FRAME_HEAD ) begin //can write
rx_state_next <= S_RX_PLWRITE;
end
else begin
rx_state_next <= S_RX_WAIT;
end
end
S_RX_PLWRITE : begin // write bram
if(rx_bram_addr[31:0] >= rx_frame_length[31:0]) begin//frame end
rx_state_next <= S_RX_WAIT;
end
else if(rx_bram_addr > FRAME_MAX_LENGTH)begin //overtime
rx_state_next <= S_RX_WAIT;
end
else begin
rx_state_next <= S_RX_PLWRITE;
end
end
default : begin
rx_state_next <= S_RX_WAIT;
end
endcase
end
always @(posedge c2c_clkin) begin
rx_state <= rx_state_next;
end
//tx_bitcnt
always @(posedge c2c_clkin or posedge rst) begin
if(rst) begin
rx_bitcnt[39:0] <= 40'd0;
end
else if(rx_state == S_RX_PLWRITE) begin
rx_bitcnt[39:0] <= rx_bitcnt[39:0] + 40'd1;
end
else begin
rx_bitcnt <= 40'd0;
end
end
//rx_frame_length
always @(posedge c2c_clkin or posedge rst) begin
if(rst) begin
rx_frame_length[31:0] <= 32'hFFFFFFFF;
end
else if(rx_bitcnt == 40'h000000001F) begin
rx_frame_length[31:0] <= c2c_in_32;
end
else if(rx_state == S_RX_PLWRITE) begin
rx_frame_length[31:0] <= rx_frame_length[31:0];
end
else begin
rx_frame_length[31:0] <= 32'hFFFFFFFF;
end
end
// rx_bram_en
// always enable
always @(posedge c2c_clkin) begin
rx_bram_en <= 1'b1;
end
// rx_bram_we
// always disable
always @(posedge c2c_clkin or posedge rst) begin
if(rst) begin
rx_bram_we[3:0] <= 4'h0;
end
else if(rx_state_next == S_RX_PLWRITE) begin
rx_bram_we[3:0] <= 4'hF;
end
else begin
rx_bram_we[3:0] <= 4'h0;
end
end
//rx_bram_addr
always @(posedge c2c_clkin or posedge rst) begin
if(rst) begin
rx_bram_addr[31:0] <= 32'd0;
end
else if(rx_state == S_RX_PLWRITE) begin
rx_bram_addr = {rx_bitcnt[34:5],2'b0} + 32'd4;
end
else begin
rx_bram_addr[31:0] <= 32'b0;
end
end
reg [7:0] pl_wr_done_cnt;
always @(posedge c2c_clkin or posedge rst) begin
if(rst) begin
pl_wr_done_cnt <= 8'd0;
pl_wr_done <= 1'b0;
end
else if(rx_state == S_RX_PLWRITE
&& rx_state_next == S_RX_WAIT
&& rx_bram_addr <= FRAME_MAX_LENGTH) begin
pl_wr_done_cnt <= 8'd16;
pl_wr_done <= 1'b1;
end
else if(pl_wr_done_cnt > 0) begin
pl_wr_done_cnt <= pl_wr_done_cnt - 8'd1;
pl_wr_done <= 1'b1;
end
else begin
pl_wr_done_cnt <= 8'd0;
pl_wr_done <= 1'b0;
end
end
always @(posedge c2c_clkin or posedge rst) begin
if(rst) begin
rx_bram_din[31:0] <= 32'd0;
end
else begin
rx_bram_din <= c2c_in_32;
end
end
assign rx_bram_clk = c2c_clkin;
endmodule
projects/datalink_814/dl814_z7/rtl/c2c_bridge_dma.v
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2023/02/22 21:36:32
// Design Name:
// Module Name: c2c_bridge_dma
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
/////FRAME HEAD(32bit)/////FRAME LENGTH(32bit)/////DATA///////////////////////////
//////////////////////////////////////////////////////////////////////////////////
module c2c_bridge_dma
#(
parameter [31:0] FRAME_HEAD = 31'h7E7E7E7E,
parameter [31:0] FRAME_MAX_LENGTH = 31'h00000400
)
(
input clk , // input clk, 96Mhz
input rst , // input rst, active high
//interface data
input c2c_clkin ,
output c2c_clkout ,
input c2c_din ,
output c2c_dout ,
//dma fifo interface
input [31:0] c2c_tx_fifo_tdata ,
input c2c_tx_fifo_tlast ,
output reg c2c_tx_fifo_tready ,
input c2c_tx_fifo_tvalid ,
output reg [31:0] c2c_rx_fifo_tdata ,
output reg c2c_rx_fifo_tlast ,
input c2c_rx_fifo_tready ,
output reg c2c_rx_fifo_tvalid
);
//////////////////////////////////////////////////////////////////////////////////
/////TX ignore tlast, each 32 clk make ready on and get a 32bit data
//////////////////////////////////////////////////////////////////////////////////
reg [4:0] tx_cnt_32;
always @(posedge clk) begin
if(rst) begin
tx_cnt_32[4:0] <= 5'd0;
end
else begin
tx_cnt_32[4:0] <= tx_cnt_32[4:0] + 5'd1;
end
end
always @(posedge clk) begin
if(tx_cnt_32[4:0] == 5'd1) begin
c2c_tx_fifo_tready <= 1'b1;
end
else begin
c2c_tx_fifo_tready <= 1'b0;
end
end
reg [31:0] tx_data_32 = 32'b0;
always @(posedge clk) begin
if(c2c_tx_fifo_tready == 1'b1) begin
if(c2c_tx_fifo_tvalid == 1'b1) begin
tx_data_32 <= c2c_tx_fifo_tdata;
end
else begin
tx_data_32 <= 32'b0;
end
end
else begin
tx_data_32 <= {tx_data_32[30:0],1'b0};
end
end
assign c2c_clkout = clk;
assign c2c_dout = tx_data_32[31];
//////////////////////////////////////////////////////////////////////////////////
/////RX ignore tready, each 32 clk make valid on and send a 32bit data, final creat tlast
//////////////////////////////////////////////////////////////////////////////////
reg [31:0] rx_data_32 = 32'b0;
always @(posedge c2c_clkin) begin
rx_data_32 <= {rx_data_32[30:0],c2c_din};
end
// state machine
reg [3:0] rx_state_next;
reg [3:0] rx_state;
localparam RX_WAIT = 4'd0;
localparam RX_PLWRITE = 4'd1;
always @ (*) begin
case (rx_state)
RX_WAIT : begin //wait for frame head
if (rx_data_32 == FRAME_HEAD) begin
rx_state_next <= RX_PLWRITE;
end
else begin
rx_state_next <= RX_WAIT;
end
end
RX_PLWRITE : begin //
if(rx_data_cnt[36:5] == rx_frame_length[31:0] - 32'b1) begin
rx_state_next <= RX_WAIT;
end
else if(rx_data_cnt[36:5] > FRAME_MAX_LENGTH)begin //overtime
rx_state_next <= RX_WAIT;
end
else begin
rx_state_next <= RX_PLWRITE;
end
end
default : begin
rx_state_next <= RX_WAIT;
end
endcase
end
always @(posedge c2c_clkin) begin
rx_state <= rx_state_next;
end
//
reg [36:0] rx_data_cnt = 37'd0;
always @(posedge c2c_clkin) begin
if(rx_state == RX_WAIT) begin
rx_data_cnt[36:0] <= 37'd0;
end
else begin
rx_data_cnt[36:0] <= rx_data_cnt[36:0] + 37'd1;
end
end
reg [31:0] rx_frame_length = FRAME_MAX_LENGTH;
always @(posedge c2c_clkin) begin
if(rx_state == RX_WAIT)begin
rx_frame_length[31:0] <= FRAME_MAX_LENGTH;
end
else if(rx_data_cnt == 37'd31) begin
rx_frame_length[31:0] <= (rx_data_32[1:0] > 0) ? ({2'b0,rx_data_32[31:2]} + 32'b1) : ({2'b0,rx_data_32[31:2]});
end
else begin
rx_frame_length[31:0] <= rx_frame_length[31:0];
end
end
reg [31:0] rx_data_32_d1;
reg [31:0] rx_data_32_d2;
always @(posedge c2c_clkin) begin
rx_data_32_d1 <= rx_data_32;
rx_data_32_d2 <= rx_data_32_d1;
end
always @(posedge c2c_clkin) begin
c2c_rx_fifo_tdata <= rx_data_32_d2;
end
//fifo ctrl
always @(posedge c2c_clkin) begin
if(rx_data_cnt[4:0] == 5'd1) begin
c2c_rx_fifo_tvalid <= 1'b1;
end
else begin
c2c_rx_fifo_tvalid <= 1'b0;
end
end
reg c2c_rx_fifo_tlast_d0;
always @(posedge c2c_clkin) begin
if(rx_state == RX_PLWRITE && rx_state_next == RX_WAIT) begin
c2c_rx_fifo_tlast_d0 <= 1'b1;
end
else begin
c2c_rx_fifo_tlast_d0 <= 1'b0;
end
end
always @(posedge c2c_clkin) begin
c2c_rx_fifo_tlast <= c2c_rx_fifo_tlast_d0;
end
endmodule
projects/datalink_814/dl814_z7/rtl/ebey_glink_top_wrapper_k7_smartncnt.edf
+459187
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projects/datalink_814/dl814_z7/rtl/ebey_glink_top_wrapper_k7_smartncnt.v
+174
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2022/08/24 15:07:02
// Design Name:
// Module Name: ebey_glink_top_wrapper_k7_smartncnt
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ebey_glink_top_wrapper_k7_smartncnt(
clk_reconfig,
pll_inclk,
i_reset_p,
i_node_id,
i_node_id_par,
i_smartnc_2nd_cfg,
i_smartnc_3rd_cfg,
i_smartnt_cfg,
i_select_n,
i_strbd_n,
i_mem_access,
i_rd_access,
o_ready_n,
i_cpu_addr,
o_cpu_rdata,
o_cpu_rdata_oe,
i_cpu_wdata,
smartnc_trans_trig,
smartnc_trans_reset,
smartnc_trans_idle,
smartnc_trans_err,
smartnc_intf_tx_fifo_wdata,
smartnc_intf_tx_fifo_wr_en,
smartnc_intf_tx_fifo_afull,
smartnc_intf_rx_fifo_empty,
smartnc_intf_rx_fifo_rdata,
smartnc_intf_rx_fifo_rd_en,
smartnt_intf_cmd_proc_req,
smartnt_intf_cmd_proc_ack,
smartnt_intf_rx_fifo_empty,
smartnt_intf_rx_fifo_rdata,
smartnt_intf_rx_fifo_rd_en,
smartnt_intf_tx_fifo_wdata,
smartnt_intf_tx_fifo_wr_en,
rx_datain_p_ch_a,
rx_datain_n_ch_a,
rx_datain_p_ch_b,
rx_datain_n_ch_b,
tx_dataout_p_ch_a,
tx_dataout_n_ch_a,
tx_dataout_p_ch_b,
tx_dataout_n_ch_b,
clk_ip,
o_reset_n
);
input clk_reconfig;
input pll_inclk;
input i_reset_p;
input [11:0] i_node_id;
input i_node_id_par;
input [15:0] i_smartnc_2nd_cfg;
input [15:0] i_smartnc_3rd_cfg;
input [15:0] i_smartnt_cfg;
input i_select_n;
input i_strbd_n;
input i_mem_access;
input i_rd_access;
output o_ready_n;
input [17:0] i_cpu_addr;
output[15:0] o_cpu_rdata;
output o_cpu_rdata_oe;
input [15:0] i_cpu_wdata;
input smartnc_trans_trig;
input smartnc_trans_reset;
output smartnc_trans_idle;
output smartnc_trans_err;
input [15:0] smartnc_intf_tx_fifo_wdata;
input smartnc_intf_tx_fifo_wr_en;
output smartnc_intf_tx_fifo_afull;
output smartnc_intf_rx_fifo_empty;
output [15:0] smartnc_intf_rx_fifo_rdata;
input smartnc_intf_rx_fifo_rd_en;
output smartnt_intf_cmd_proc_req;
input smartnt_intf_cmd_proc_ack;
output smartnt_intf_rx_fifo_empty;
output [15:0] smartnt_intf_rx_fifo_rdata;
input smartnt_intf_rx_fifo_rd_en;
input [15:0] smartnt_intf_tx_fifo_wdata;
input smartnt_intf_tx_fifo_wr_en;
input rx_datain_p_ch_a;
input rx_datain_n_ch_a;
input rx_datain_p_ch_b;
input rx_datain_n_ch_b;
output tx_dataout_p_ch_a;
output tx_dataout_n_ch_a;
output tx_dataout_p_ch_b;
output tx_dataout_n_ch_b;
output clk_ip;
output o_reset_n;
wire clk_reconfig;
wire pll_inclk;
wire i_reset_p;
wire [11:0] i_node_id;
wire i_node_id_par;
wire [15:0] i_smartnc_2nd_cfg;
wire [15:0] i_smartnc_3rd_cfg;
wire [15:0] i_smartnt_cfg;
wire i_select_n;
wire i_strbd_n;
wire i_mem_access;
wire i_rd_access;
wire o_ready_n;
wire [17:0] i_cpu_addr;
wire [15:0] o_cpu_rdata;
wire o_cpu_rdata_oe;
wire [15:0] i_cpu_wdata;
wire smartnc_trans_trig;
wire smartnc_trans_reset;
wire smartnc_trans_idle;
wire smartnc_trans_err;
wire [15:0] smartnc_intf_tx_fifo_wdata;
wire smartnc_intf_tx_fifo_wr_en;
wire smartnc_intf_tx_fifo_afull;
wire smartnc_intf_rx_fifo_empty;
wire [15:0] smartnc_intf_rx_fifo_rdata;
wire smartnc_intf_rx_fifo_rd_en;
wire smartnt_intf_cmd_proc_req;
wire smartnt_intf_cmd_proc_ack;
wire smartnt_intf_rx_fifo_empty;
wire [15:0] smartnt_intf_rx_fifo_rdata;
wire smartnt_intf_rx_fifo_rd_en;
wire [15:0] smartnt_intf_tx_fifo_wdata;
wire smartnt_intf_tx_fifo_wr_en;
wire rx_datain_p_ch_a;
wire rx_datain_n_ch_a;
wire rx_datain_p_ch_b;
wire rx_datain_n_ch_b;
wire tx_dataout_p_ch_a;
wire tx_dataout_n_ch_a;
wire tx_dataout_p_ch_b;
wire tx_dataout_n_ch_b;
wire clk_ip;
wire o_reset_n;
endmodule
projects/datalink_814/dl814_z7/rtl/glink_rst.v
+63
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2022/08/26 16:14:01
// Design Name:
// Module Name: glink_rst_create
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module glink_rst_create(
input glink_logic_clk,
input i_reset_p,
output reset_p
);
wire rst_n_fil;
reset_filter
#(
.RESET_MANUAL_POL (0 ),
.RESET_POWER_POL (1 ),
.RESET_OUT_POL (0 ),
.FILTER_WIDTH (125),
.RESET_MANUAL_EN_POL (1 )
)
u_reset_filter
(
.clk (glink_logic_clk),
.i_reset_p (i_reset_p ),
.i_reset_m_en (1'b0 ),
.i_reset_m (1'b1 ),
.o_reset_p_syn ( ),
.o_reset_combo (rst_n_fil )
);
reset_pls_extend
#(
.IN_POLARITY (0 ),
.OUT_POLARITY (1 ),
.EXTEND_WIDTH (2500000)
)
u_reset_pls_extend
(
.clk (glink_logic_clk),
.i_reset (rst_n_fil ),
.o_reset (reset_p )
);
endmodule
projects/datalink_814/dl814_z7/rtl/glink_smartncnt_intf.v
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2022/08/26 14:27:08
// Design Name:
// Module Name: glink_smartncnt_intf
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module glink_smartncnt_intf(
input clk ,
input rst_n ,
output [31:0] glink_gpio_i_0 ,
output [31:0] glink_gpio_i_1 ,
input [31:0] glink_gpio_o_0 ,
input [31:0] glink_gpio_o_1 ,
output [11:0] i_node_id ,
output i_node_id_par ,
output [15:0] i_smartnc_2nd_cfg ,
output [15:0] i_smartnc_3rd_cfg ,
output [15:0] i_smartnt_cfg ,
output smartnc_trans_trig ,//gpio control
output smartnc_trans_reset ,//gpio control
input smartnc_trans_idle ,
input smartnc_trans_err ,//gpio control
output [15:0] smartnc_intf_tx_fifo_wdata ,
output smartnc_intf_tx_fifo_wr_en ,
input smartnc_intf_tx_fifo_afull ,
input smartnc_intf_rx_fifo_empty ,//useless
input [15:0] smartnc_intf_rx_fifo_rdata ,//useless
output smartnc_intf_rx_fifo_rd_en ,//useless
input smartnt_intf_cmd_proc_req ,
output smartnt_intf_cmd_proc_ack ,
input smartnt_intf_rx_fifo_empty ,
input [15:0] smartnt_intf_rx_fifo_rdata ,
output smartnt_intf_rx_fifo_rd_en ,
output [15:0] smartnt_intf_tx_fifo_wdata ,//useless
output smartnt_intf_tx_fifo_wr_en ,//useless
input [15:0] glink_tx_fifo_tdata ,
input glink_tx_fifo_tlast ,
output glink_tx_fifo_tready ,
input glink_tx_fifo_tvalid ,
output [15:0] glink_rx_fifo_tdata ,
output glink_rx_fifo_tlast ,
input glink_rx_fifo_tready ,
output glink_rx_fifo_tvalid
);
wire smartnc_trans_trig_d0;
//control
assign i_node_id[11:0] = glink_gpio_o_0[11:0];
assign i_node_id_par = ~(^i_node_id);
assign smartnc_trans_trig_d0 = glink_gpio_o_0[12];
assign smartnc_trans_reset = glink_gpio_o_0[13];
assign glink_gpio_i_0[14] = smartnc_trans_idle;
assign glink_gpio_i_0[15] = smartnc_trans_err;
assign i_smartnt_cfg = glink_gpio_o_0[31:16];
assign i_smartnc_2nd_cfg = glink_gpio_o_1[15:0];
assign i_smartnc_3rd_cfg = glink_gpio_o_1[31:16];
reg smartnc_trans_trig_d1;
reg smartnc_trans_trig_d2;
reg smartnc_trans_trig_d3;
always @(posedge clk) begin
if(~rst_n) begin
smartnc_trans_trig_d1 <= 1'd0;
smartnc_trans_trig_d2 <= 1'd0;
smartnc_trans_trig_d3 <= 1'd0;
end
else begin
smartnc_trans_trig_d1 <= smartnc_trans_trig_d0;
smartnc_trans_trig_d2 <= smartnc_trans_trig_d1;
smartnc_trans_trig_d3 <= smartnc_trans_trig_d2;
end
end
assign smartnc_trans_trig = smartnc_trans_trig_d3^smartnc_trans_trig_d2;
//useless interface
assign smartnc_intf_rx_fifo_rd_en = 1'b0;
assign smartnt_intf_tx_fifo_wdata = 16'b0;
assign smartnt_intf_tx_fifo_wr_en = 1'b0;
//stream_fifo_out to nc_tx_fifo
assign smartnc_intf_tx_fifo_wdata = glink_tx_fifo_tdata;
assign smartnc_intf_tx_fifo_wr_en = glink_tx_fifo_tvalid;
assign glink_tx_fifo_tready = ~smartnc_intf_tx_fifo_afull;
// nt_rx_fifo to stream_fifo_in
wire glink_recv_active;
reg glink_recv_active_d0;
reg glink_recv_active_d1;
reg glink_recv_active_d2;
assign glink_recv_active = smartnt_intf_cmd_proc_req & ~smartnt_intf_rx_fifo_empty & glink_rx_fifo_tready;
always @(posedge clk) begin
if(~rst_n) begin
glink_recv_active_d0 <= 1'b0;
glink_recv_active_d1 <= 1'b0;
glink_recv_active_d2 <= 1'b0;
end
else begin
glink_recv_active_d0 <= glink_recv_active ;
glink_recv_active_d1 <= glink_recv_active_d0 ;
glink_recv_active_d2 <= glink_recv_active_d1 ;
end
end
assign smartnt_intf_cmd_proc_ack = ~glink_recv_active_d1 & glink_recv_active_d2 ;
assign glink_rx_fifo_tlast = ~glink_recv_active_d0 & glink_recv_active_d1 ;
assign smartnt_intf_rx_fifo_rd_en = glink_recv_active_d1 ;
assign glink_rx_fifo_tvalid = glink_recv_active_d1 ;
assign glink_rx_fifo_tdata = smartnt_intf_rx_fifo_rdata ;
endmodule
projects/datalink_814/dl814_z7/rtl/glink_top.v
+205
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2022/08/27 15:30:06
// Design Name:
// Module Name: glink_top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module glink_top(
// glink gt reference clock
input glink_refclk_p , // generated by oscillator, 125mhz
input glink_refclk_n ,
// glink pk clock
input glink_logic_clk , // generated by oscillator, 25mhz
input pl_rst ,
input rx_datain_p_ch_a ,
input rx_datain_n_ch_a ,
input rx_datain_p_ch_b ,
input rx_datain_n_ch_b ,
output tx_dataout_p_ch_a ,
output tx_dataout_n_ch_a ,
output tx_dataout_p_ch_b ,
output tx_dataout_n_ch_b ,
//glink_ctrl
output [31:0] glink_gpio_i_0 ,
output [31:0] glink_gpio_i_1 ,
input [31:0] glink_gpio_o_0 ,
input [31:0] glink_gpio_o_1 ,
//DMA_send_fifo
input [15:0] glink_tx_fifo_tdata ,
input glink_tx_fifo_tlast ,
output glink_tx_fifo_tready,
input glink_tx_fifo_tvalid,
//DMA_recv_fifo
output [15:0] glink_rx_fifo_tdata ,
output glink_rx_fifo_tlast ,
input glink_rx_fifo_tready,
output glink_rx_fifo_tvalid,
output glink_ip_clk
);
wire glink_pll_inclk;
IBUFDS_GTE2 IBUFDS_GTE2_CLK1(
.I (glink_refclk_p ),
.IB (glink_refclk_n ),
.CEB (1'b0 ),
.O (glink_pll_inclk),
.ODIV2 ( )
);
wire glink_rst;
glink_rst_create u_glink_rst_create(
.glink_logic_clk(glink_logic_clk ),
.i_reset_p (pl_rst ),
.reset_p (glink_rst )
);
wire [11:0] i_node_id ;
wire i_node_id_par ;
wire [15:0] i_smartnc_2nd_cfg ;
wire [15:0] i_smartnc_3rd_cfg ;
wire [15:0] i_smartnt_cfg ;
wire smartnc_trans_trig ;
wire smartnc_trans_reset ;
wire smartnc_trans_idle ;
wire smartnc_trans_err ;
wire [15:0] smartnc_intf_tx_fifo_wdata ;
wire smartnc_intf_tx_fifo_wr_en ;
wire smartnc_intf_tx_fifo_afull ;
wire smartnc_intf_rx_fifo_empty ;
wire [15:0] smartnc_intf_rx_fifo_rdata ;
wire smartnc_intf_rx_fifo_rd_en ;
wire smartnt_intf_cmd_proc_req ;
wire smartnt_intf_cmd_proc_ack ;
wire smartnt_intf_rx_fifo_empty ;
wire [15:0] smartnt_intf_rx_fifo_rdata ;
wire smartnt_intf_rx_fifo_rd_en ;
wire [15:0] smartnt_intf_tx_fifo_wdata ;
wire smartnt_intf_tx_fifo_wr_en ;
wire glink_ip_rst_n ;
ebey_glink_top_wrapper_k7_smartncnt u_ebey_glink_top_wrapper_k7_smartncnt
( .clk_reconfig (glink_logic_clk ),
.pll_inclk (glink_pll_inclk ),
.i_reset_p (glink_rst ),
.i_node_id (i_node_id ),//�ڵ� ID12'h003
.i_node_id_par (i_node_id_par ),//��żУ�� 1'b1
.i_smartnc_2nd_cfg (i_smartnc_2nd_cfg ),//SMARTNC���䳬ʱΪ128us 16'h0003
.i_smartnc_3rd_cfg (i_smartnc_3rd_cfg ),//����Ϊ�̱��Ĺ���ģʽ 16'h0400
.i_smartnt_cfg (i_smartnt_cfg ),//����Ϊ�̱��Ĺ���ģʽ 16'h4000
.i_select_n (1'b1 ),
.i_strbd_n (1'b1 ),
.i_mem_access (1'b0 ),
.i_rd_access (1'b0 ),
.o_ready_n ( ),
.i_cpu_addr (18'b0 ),
.o_cpu_rdata ( ),
.o_cpu_rdata_oe ( ),
.i_cpu_wdata (16'b0 ),
.smartnc_trans_trig (smartnc_trans_trig ),
.smartnc_trans_reset (smartnc_trans_reset ),
.smartnc_trans_idle (smartnc_trans_idle ),
.smartnc_trans_err (smartnc_trans_err ),
.smartnc_intf_tx_fifo_wdata (smartnc_intf_tx_fifo_wdata ),
.smartnc_intf_tx_fifo_wr_en (smartnc_intf_tx_fifo_wr_en ),
.smartnc_intf_tx_fifo_afull (smartnc_intf_tx_fifo_afull ),
.smartnc_intf_rx_fifo_empty (smartnc_intf_rx_fifo_empty ),
.smartnc_intf_rx_fifo_rdata (smartnc_intf_rx_fifo_rdata ),
.smartnc_intf_rx_fifo_rd_en (smartnc_intf_rx_fifo_rd_en ),
.smartnt_intf_cmd_proc_req (smartnt_intf_cmd_proc_req ),
.smartnt_intf_cmd_proc_ack (smartnt_intf_cmd_proc_ack ),
.smartnt_intf_rx_fifo_empty (smartnt_intf_rx_fifo_empty ),
.smartnt_intf_rx_fifo_rdata (smartnt_intf_rx_fifo_rdata ),
.smartnt_intf_rx_fifo_rd_en (smartnt_intf_rx_fifo_rd_en ),
.smartnt_intf_tx_fifo_wdata (smartnt_intf_tx_fifo_wdata ),
.smartnt_intf_tx_fifo_wr_en (smartnt_intf_tx_fifo_wr_en ),
.rx_datain_p_ch_a (rx_datain_p_ch_a ),
.rx_datain_n_ch_a (rx_datain_n_ch_a ),
.rx_datain_p_ch_b (rx_datain_p_ch_b ),
.rx_datain_n_ch_b (rx_datain_n_ch_b ),
.tx_dataout_p_ch_a (tx_dataout_p_ch_a ),
.tx_dataout_n_ch_a (tx_dataout_n_ch_a ),
.tx_dataout_p_ch_b (tx_dataout_p_ch_b ),
.tx_dataout_n_ch_b (tx_dataout_n_ch_b ),
.clk_ip (glink_ip_clk ),
.o_reset_n (glink_ip_rst_n )
);
glink_smartncnt_intf u_glink_smartncnt_intf(
.clk (glink_ip_clk ),
.rst_n (glink_ip_rst_n ),
.glink_gpio_i_0 (glink_gpio_i_0 ), // PS <- Glink
.glink_gpio_i_1 (glink_gpio_i_1 ), // PS <- Glink
.glink_gpio_o_0 (glink_gpio_o_0 ), // PS -> Glink
.glink_gpio_o_1 (glink_gpio_o_1 ), // PS -> Glink
.i_node_id (i_node_id ),//�ڵ� ID12'h003
.i_node_id_par (i_node_id_par ),//��żУ�� 1'b1
.i_smartnc_2nd_cfg (i_smartnc_2nd_cfg ),//SMARTNC���䳬ʱΪ128us 16'h0003
.i_smartnc_3rd_cfg (i_smartnc_3rd_cfg ),//����Ϊ�̱��Ĺ���ģʽ 16'h0400
.i_smartnt_cfg (i_smartnt_cfg ),//����Ϊ�̱��Ĺ���ģʽ 16'h4000
.smartnc_trans_trig (smartnc_trans_trig ),//gpio control
.smartnc_trans_reset (smartnc_trans_reset ),//gpio control
.smartnc_trans_idle (smartnc_trans_idle ),
.smartnc_trans_err (smartnc_trans_err ),//gpio control
.smartnc_intf_tx_fifo_wdata (smartnc_intf_tx_fifo_wdata ),
.smartnc_intf_tx_fifo_wr_en (smartnc_intf_tx_fifo_wr_en ),
.smartnc_intf_tx_fifo_afull (smartnc_intf_tx_fifo_afull ),
.smartnc_intf_rx_fifo_empty (smartnc_intf_rx_fifo_empty ),
.smartnc_intf_rx_fifo_rdata (smartnc_intf_rx_fifo_rdata ),
.smartnc_intf_rx_fifo_rd_en (smartnc_intf_rx_fifo_rd_en ),
.smartnt_intf_cmd_proc_req (smartnt_intf_cmd_proc_req ),
.smartnt_intf_cmd_proc_ack (smartnt_intf_cmd_proc_ack ),
.smartnt_intf_rx_fifo_empty (smartnt_intf_rx_fifo_empty ),
.smartnt_intf_rx_fifo_rdata (smartnt_intf_rx_fifo_rdata ),
.smartnt_intf_rx_fifo_rd_en (smartnt_intf_rx_fifo_rd_en ),
.smartnt_intf_tx_fifo_wdata (smartnt_intf_tx_fifo_wdata ),
.smartnt_intf_tx_fifo_wr_en (smartnt_intf_tx_fifo_wr_en ),
.glink_tx_fifo_tdata (glink_tx_fifo_tdata[15:0] ),
.glink_tx_fifo_tlast (glink_tx_fifo_tlast ),
.glink_tx_fifo_tready (glink_tx_fifo_tready ),
.glink_tx_fifo_tvalid (glink_tx_fifo_tvalid ),
.glink_rx_fifo_tdata (glink_rx_fifo_tdata[15:0] ),
.glink_rx_fifo_tlast (glink_rx_fifo_tlast ),
.glink_rx_fifo_tready (glink_rx_fifo_tready ),
.glink_rx_fifo_tvalid (glink_rx_fifo_tvalid )
);
endmodule
projects/datalink_814/dl814_z7/rtl/reset_filter.vhd
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-------------------------------------------------------------------------------
-- Title : reset_filter
-- Project :
-------------------------------------------------------------------------------
-- File : reset_filter.vhd
-- Author : <zhanghb@ZHANGHONGBO>
-- Company :
-- Created : 2012-06-13
-- Last update: 2012-06-13
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-06-13 1.0 zhanghb Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity reset_filter is
generic (
RESET_MANUAL_POL : integer := 1; -- polarity of manual reset signal
RESET_POWER_POL : integer := 1; -- polarity of power reset signal
RESET_OUT_POL : integer := 1; -- polarity of reset output signal
FILTER_WIDTH : integer := 100; -- filter width, measured in clk unit
RESET_MANUAL_EN_POL : integer := 1 -- polarity of manual reset enable signal
);
port (
clk : in std_logic;
i_reset_p : in std_logic; -- power reset
i_reset_m_en : in std_logic; -- enalb control of manual reset,
-- active high
i_reset_m : in std_logic; -- manual reset signal
o_reset_p_syn : out std_logic; -- synchronzed power reset signal
o_reset_combo : out std_logic); -- reset output, combine manual
-- reset and power reset
end entity reset_filter;
architecture rtl of reset_filter is
signal reset_p_buf : std_logic_vector(2 downto 0); -- active low
signal reset_p_syn : std_logic; -- active low
signal reset_m_buf : std_logic_vector(2 downto 0); -- active low
signal reset_m_syn : std_logic; -- active low
signal reset_m_en_buf : std_logic_vector(2 downto 0); -- active high
signal reset_m_en_syn : std_logic; -- active high
signal reset_m_fil : std_logic; -- active low
signal reset_m_vld : std_logic; -- active high
signal counter : integer range 0 to FILTER_WIDTH;
begin -- architecture rtl
-----------------------------------------------------------------------------
-- purpose : power reset synchronization logic
-----------------------------------------------------------------------------
power_reset_syn_pol0 : if RESET_POWER_POL = 0 generate
process (clk, i_reset_p)
begin -- process
if i_reset_p = '0' then -- asynchronous reset (active low)
reset_p_buf <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
reset_p_buf <= reset_p_buf(1) & reset_p_buf(0) & '1';
end if;
end process;
end generate power_reset_syn_pol0;
power_reset_syn_pol1 : if RESET_POWER_POL = 1 generate
process (clk, i_reset_p)
begin -- process
if i_reset_p = '1' then -- asynchronous reset (active high)
reset_p_buf <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
reset_p_buf <= reset_p_buf(1) & reset_p_buf(0) & '1';
end if;
end process;
end generate power_reset_syn_pol1;
reset_p_syn <= reset_p_buf(2);
-------------------------------------------------------------------------------
-- purpose : generate output reset signal o_reset_p_syn
-------------------------------------------------------------------------------
reset_out_pol0_power : if RESET_OUT_POL = 0 generate
process (clk, reset_p_syn)
begin -- process
if reset_p_syn = '0' then -- asynchronous reset (active low)
o_reset_p_syn <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
o_reset_p_syn <= '1';
end if;
end process;
end generate reset_out_pol0_power;
reset_out_pol1_power : if RESET_OUT_POL = 1 generate
process (clk, reset_p_syn)
begin -- process
if reset_p_syn = '0' then -- asynchronous reset (active high)
o_reset_p_syn <= '1';
elsif clk'event and clk = '1' then -- rising clock edge
o_reset_p_syn <= '0';
end if;
end process;
end generate reset_out_pol1_power;
-----------------------------------------------------------------------------
-- purpose : manual reset synchronization logic
-----------------------------------------------------------------------------
manual_reset_syn_pol0 : if RESET_MANUAL_POL = 0 generate
process (clk, reset_p_syn)
begin -- process
if reset_p_syn = '0' then -- asynchronous reset (active low)
reset_m_buf <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
reset_m_buf <= reset_m_buf(1) & reset_m_buf(0) & i_reset_m;
end if;
end process;
end generate manual_reset_syn_pol0;
manual_reset_syn_pol1 : if RESET_MANUAL_POL = 1 generate
process (clk, reset_p_syn)
begin -- process
if reset_p_syn = '0' then -- asynchronous reset (active high)
reset_m_buf <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
reset_m_buf <= reset_m_buf(1) & reset_m_buf(0) & (not i_reset_m);
end if;
end process;
end generate manual_reset_syn_pol1;
reset_m_syn <= reset_m_buf(2);
-----------------------------------------------------------------------------
-- purpose : manual reset enable synchronization logic
-----------------------------------------------------------------------------
manual_reset_en_syn_pol0 : if RESET_MANUAL_EN_POL = 0 generate
process (clk, reset_p_syn)
begin -- process
if reset_p_syn = '0' then -- asynchronous reset (active low)
reset_m_en_buf <= (others => '1');
elsif clk'event and clk = '1' then -- rising clock edge
reset_m_en_buf <= reset_m_en_buf(1) & reset_m_en_buf(0) & (not i_reset_m_en);
end if;
end process;
end generate manual_reset_en_syn_pol0;
manual_reset_en_syn_pol1 : if RESET_MANUAL_EN_POL = 1 generate
process (clk, reset_p_syn)
begin -- process
if reset_p_syn = '0' then -- asynchronous reset (active low)
reset_m_en_buf <= (others => '1');
elsif clk'event and clk = '1' then -- rising clock edge
reset_m_en_buf <= reset_m_en_buf(1) & reset_m_en_buf(0) & i_reset_m_en;
end if;
end process;
end generate manual_reset_en_syn_pol1;
reset_m_en_syn <= reset_m_en_buf(2);
-----------------------------------------------------------------------------
-- purpose : manual reset valid logic
-----------------------------------------------------------------------------
reset_m_vld <= (not reset_m_syn) and reset_m_en_syn;
-----------------------------------------------------------------------------
-- purpose : manual reset counter
-----------------------------------------------------------------------------
process(clk, reset_p_syn)
begin
if reset_p_syn = '0' then
counter <= 0;
reset_m_fil <= '0';
elsif clk'event and clk = '1' then
if reset_m_vld = '1' then
if counter >= FILTER_WIDTH - 1 then
reset_m_fil <= '0';
else
counter <= counter + 1;
reset_m_fil <= '1';
end if;
else
counter <= 0;
reset_m_fil <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- purpose : generate output reset signal o_reset_p_syn
-------------------------------------------------------------------------------
reset_out_pol0_combo : if RESET_OUT_POL = 0 generate
process (clk, reset_p_syn)
begin -- process
if reset_p_syn = '0' then -- asynchronous reset
o_reset_combo <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
o_reset_combo <= reset_m_fil;
end if;
end process;
end generate reset_out_pol0_combo;
reset_out_pol1_combo : if RESET_OUT_POL = 1 generate
process (clk, reset_p_syn)
begin -- process
if reset_p_syn = '0' then -- asynchronous reset
o_reset_combo <= '1';
elsif clk'event and clk = '1' then -- rising clock edge
o_reset_combo <= not reset_m_fil;
end if;
end process;
end generate reset_out_pol1_combo;
end architecture rtl;
projects/datalink_814/dl814_z7/rtl/reset_pls_extend.vhd
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-------------------------------------------------------------------------------
-- Title : reset_pls_extend
-- Project :
-------------------------------------------------------------------------------
-- File : reset_pls_extend.vhd
-- Author : <zhanghb@ZHANGHONGBO>
-- Company :
-- Created : 2012-06-13
-- Last update: 2012-06-13
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: extend pulse width of reset signal
-- parameter : 1. polarity of input reset signal
-- 2. polarity of output reset signal
-- 3. pulse width of output reset signal, measured by clk.
-- 4. bit width of counter
-- To avoid problem when initiating reset_pls_extend module in verilog file,
-- IN_POLARITY and OUT_POLARITY are defined as integer type.
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-06-13 1.0 zhanghb Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity reset_pls_extend is
generic (
IN_POLARITY : integer := 0;
OUT_POLARITY : integer := 0;
EXTEND_WIDTH : integer := 8);
port (
clk : in std_logic;
i_reset : in std_logic;
o_reset : out std_logic);
end entity reset_pls_extend;
architecture rtl of reset_pls_extend is
signal counter : integer range 0 to EXTEND_WIDTH;
signal reset_reg : std_logic; -- drive o_reset
begin -- architecture rtl
polarity_00 : if IN_POLARITY = 0 and OUT_POLARITY = 0 generate
process (clk, i_reset) is
begin -- process
if i_reset = '0' then -- asynchronous reset
counter <= 0;
reset_reg <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if counter < EXTEND_WIDTH then
counter <= counter + 1;
reset_reg <= '0';
else
counter <= counter;
reset_reg <= '1';
end if;
end if;
end process;
end generate polarity_00;
polarity_01 : if IN_POLARITY = 0 and OUT_POLARITY = 1 generate
process (clk, i_reset) is
begin -- process
if i_reset = '0' then -- asynchronous reset
counter <= 0;
reset_reg <= '1';
elsif clk'event and clk = '1' then -- rising clock edge
if counter < EXTEND_WIDTH then
counter <= counter + 1;
reset_reg <= '1';
else
counter <= counter;
reset_reg <= '0';
end if;
end if;
end process;
end generate polarity_01;
polarity_10 : if IN_POLARITY = 1 and OUT_POLARITY = 0 generate
process (clk, i_reset) is
begin -- process
if i_reset = '1' then -- asynchronous reset
counter <= 0;
reset_reg <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if counter < EXTEND_WIDTH then
counter <= counter + 1;
reset_reg <= '0';
else
counter <= counter;
reset_reg <= '1';
end if;
end if;
end process;
end generate polarity_10;
polarity_11 : if IN_POLARITY = 1 and OUT_POLARITY = 1 generate
process (clk, i_reset) is
begin -- process
if i_reset = '1' then -- asynchronous reset
counter <= 0;
reset_reg <= '1';
elsif clk'event and clk = '1' then -- rising clock edge
if counter < EXTEND_WIDTH then
counter <= counter + 1;
reset_reg <= '1';
else
counter <= counter;
reset_reg <= '0';
end if;
end if;
end process;
end generate polarity_11;
o_reset <= reset_reg;
end architecture rtl;
projects/datalink_814/dl814_z7/rtl/system_top.v
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08/06/2022 04:20:01 PM
// Design Name:
// Module Name: system_top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module system_top(
/***************************************************************************
* Interface Content
* 01 - Clocks & Reset
* 02 - DDR and Fixed-io
***************************************************************************/
// *************************************************************************
// ***************************** PS Fixed IOs ******************************
// ************************************************************************
inout [14:0] DDR_addr ,
inout [2:0] DDR_ba ,
inout DDR_cas_n ,
inout DDR_ck_n ,
inout DDR_ck_p ,
inout DDR_cke ,
inout DDR_cs_n ,
inout [3:0] DDR_dm ,
inout [31:0] DDR_dq ,
inout [3:0] DDR_dqs_n ,
inout [3:0] DDR_dqs_p ,
inout DDR_odt ,
inout DDR_ras_n ,
inout DDR_reset_n ,
inout DDR_we_n ,
inout FIXED_IO_ddr_vrn ,
inout FIXED_IO_ddr_vrp ,
inout [53:0] FIXED_IO_mio ,
inout FIXED_IO_ps_clk ,
inout FIXED_IO_ps_porb ,
inout FIXED_IO_ps_srstb ,
// *************************************************************************
// *************************** Clocks and Resets ***************************
// *************************************************************************
input CLK_25M , // pl clock, 25mhz
// glink gt reference clock
input glink_refclk_p , // generated by oscillator, 125mhz
input glink_refclk_n ,
// *************************************************************************
// ************************************ LVDS *******************************
// *************************************************************************
input Din1 ,
output Dout1 ,
input Din2 ,
output Dout2 ,
input DCLK_in ,
output DCLK_out ,
input TR ,
input DARY ,
// *************************************************************************
// *********************************beam ctrl*******************************
// *************************************************************************
output [3:0] CLK_TR ,
output [3:0] TR_TR ,
output [3:0] DATA_TR ,
output [3:0] SYN_TR ,
output [3:0] SEL_TR ,
output [3:0] SEL4_TR ,
output [3:0] SEL3_TR ,
output [3:0] SEL2_TR ,
output [3:0] SEL1_TR ,
output T_DLY ,
output R_DLY ,
output PW_DOWN ,
// *************************************************************************
// ************************************ GLINK *******************************
// *************************************************************************
input rx_datain_p_ch_a ,
input rx_datain_n_ch_a ,
input rx_datain_p_ch_b ,
input rx_datain_n_ch_b ,
output tx_dataout_p_ch_a ,
output tx_dataout_n_ch_a ,
output tx_dataout_p_ch_b ,
output tx_dataout_n_ch_b
);
/*******************************************************************************
*******************************************************************************/
//supply1 const_high;
//assign PW_DOWN = const_high;
//******************************************************************************
//******************************* Clock & Reset *********************************
//******************************************************************************
wire CLK_25M_1;
wire CLK_25M_2;
wire CLK_25M_3;
clk_wiz_25m_1to3 u_clk_wiz_25m_1to3
(
// Clock out ports
.clk_out1(CLK_25M_1), // output clk_out1
.clk_out2(CLK_25M_2), // output clk_out2
.clk_out3(CLK_25M_3), // output clk_out3
// Clock in ports
.clk_in1(CLK_25M)); // input clk_in1
//////clk_lvds
wire pl_clk_96m;
wire lvds_rst;
wire lvds_locked;
clk_wiz_lvds u_clk_wiz_lvds
(
// Clock out ports
.clk_out1(pl_clk_96m), // output clk_out1
// Status and control signals
.locked(lvds_locked), // output locked
// Clock in ports
.clk_in1(CLK_25M_1)); // input clk_in1
assign lvds_rst = ~lvds_locked;
//////clk_glink
wire glink_logic_clk ;
wire glink_ila_clk ;
wire glink_rst;
wire glink_locked;
clk_wiz_glink u_clk_wiz_glink
(
// Clock out ports
.clk_out1(glink_logic_clk), // output clk_out1 25m
.clk_out2(glink_ila_clk), // output clk_out2 125m
// Status and control signals
.locked(glink_locked), // output locked
// Clock in ports
.clk_in1(CLK_25M_2)); // input clk_in1
assign glink_rst = ~glink_locked;
//////clk_beam
wire clk_beam_100m;
wire clk_beam_12_5m;
wire clk_beam_50m;
wire beam_locked;
clk_wiz_beam u_clk_wiz_beam
(
// Clock out ports
.clk_out1(clk_beam_100m), // output clk_out1
.clk_out2(clk_beam_12_5m), // output clk_out2
.clk_out3(clk_beam_50m), // output clk_out3
// Status and control signals
.locked(beam_locked), // output locked
// Clock in ports
.clk_in1(CLK_25M_3)); // input clk_in1
//******************************************************************************
//********************************* selectio ************************************
//******************************************************************************
wire lvds_clkin;
wire lvds_rx_clk;
clk_wiz_96m_1to1 u_clk_wiz_96m_1to1
(
// Clock out ports
.clk_out1(lvds_rx_clk), // output clk_out1
// Clock in ports
.clk_in1(lvds_clkin)); // input clk_in1
assign lvds_clkin = DCLK_in;
wire [3:0] lvds_din;
wire [3:0] lvds_rx_data;
selectio_lvds_rx u_selectio_lvds_rx
(
.data_in_from_pins(lvds_din), // input [3:0] data_in_from_pins
.data_in_to_device(lvds_rx_data), // output [3:0] data_in_to_device
.clk_in(lvds_rx_clk), // input clk_in
.io_reset(lvds_rst) // input io_reset
);
assign lvds_din[0] = Din1;
assign lvds_din[1] = Din2;
assign lvds_din[2] = TR;
assign lvds_din[3] = DARY;
wire lvds_dout;
wire lvds_tx_data;
wire lvds_clkout;
wire lvds_tx_clk;
selectio_lvds_tx u_selectio_lvds_tx
(
.data_out_from_device(lvds_tx_data), // input [0:0] data_out_from_device
.data_out_to_pins(lvds_dout), // output [0:0] data_out_to_pins
.clk_in(lvds_tx_clk), // input clk_in
.clk_out(lvds_clkout), // output clk_out
.io_reset(lvds_rst) // input io_reset
);
assign Dout1 = lvds_dout;
assign DCLK_out = lvds_clkout;
//******************************************************************************
//**************************** System Block Design ******************************
//******************************************************************************
wire c2c_rst_n ;
wire c2c_rx_clk ;
wire c2c_tx_clk ;
wire [31:0] c2c_tx_fifo_tdata ;
wire c2c_tx_fifo_tlast ;
wire c2c_tx_fifo_tready ;
wire c2c_tx_fifo_tvalid ;
wire [31:0] c2c_rx_fifo_tdata ;
wire c2c_rx_fifo_tlast ;
wire c2c_rx_fifo_tready ;
wire c2c_rx_fifo_tvalid ;
wire ps_clk ;
wire glink_ip_clk ;
wire [31:0] glink_gpio_i_0 ;
wire [31:0] glink_gpio_i_1 ;
wire [31:0] glink_gpio_o_0 ;
wire [31:0] glink_gpio_o_1 ;
wire [15:0] glink_tx_fifo_tdata ;
wire glink_tx_fifo_tlast ;
wire glink_tx_fifo_tready ;
wire glink_tx_fifo_tvalid ;
wire [15:0] glink_rx_fifo_tdata ;
wire glink_rx_fifo_tlast ;
wire glink_rx_fifo_tready ;
wire glink_rx_fifo_tvalid ;
wire pwdown_gpio_o ;
system_bd_wrapper u_system_bd_wrapper
(.DDR_addr (DDR_addr[14:0] ),
.DDR_ba (DDR_ba[2:0] ),
.DDR_cas_n (DDR_cas_n ),
.DDR_ck_n (DDR_ck_n ),
.DDR_ck_p (DDR_ck_p ),
.DDR_cke (DDR_cke ),
.DDR_cs_n (DDR_cs_n ),
.DDR_dm (DDR_dm[3:0] ),
.DDR_dq (DDR_dq[31:0] ),
.DDR_dqs_n (DDR_dqs_n[3:0] ),
.DDR_dqs_p (DDR_dqs_p[3:0] ),
.DDR_odt (DDR_odt ),
.DDR_ras_n (DDR_ras_n ),
.DDR_reset_n (DDR_reset_n ),
.DDR_we_n (DDR_we_n ),
.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn ),
.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp ),
.FIXED_IO_mio (FIXED_IO_mio[53:0] ),
.FIXED_IO_ps_clk (FIXED_IO_ps_clk ),
.FIXED_IO_ps_porb (FIXED_IO_ps_porb ),
.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb ),
//C2C
.c2c_rst_n (c2c_rst_n ),
.c2c_rx_clk (c2c_rx_clk ),
.c2c_tx_clk (c2c_tx_clk ),
.m_axis_fifo_c2c_out_tdata (c2c_tx_fifo_tdata[31:0] ),
.m_axis_fifo_c2c_out_tlast (c2c_tx_fifo_tlast ),
.m_axis_fifo_c2c_out_tready (c2c_tx_fifo_tready ),
.m_axis_fifo_c2c_out_tvalid (c2c_tx_fifo_tvalid ),
.s_axis_fifo_c2c_in_tdata (c2c_rx_fifo_tdata[31:0] ),
.s_axis_fifo_c2c_in_tlast (c2c_rx_fifo_tlast ),
.s_axis_fifo_c2c_in_tready (c2c_rx_fifo_tready ),
.s_axis_fifo_c2c_in_tvalid (c2c_rx_fifo_tvalid ),
//PS CLK
.ps_clk (ps_clk ),
// Glink Ports
.glink_ip_clk (glink_ip_clk ),
.glink_ip_rst_n (~glink_rst ),
.glink_gpio_i_0 (glink_gpio_i_0[31:0] ),// PS <- Glink
.glink_gpio_i_1 (glink_gpio_i_1[31:0] ),// PS <- Glink
.glink_gpio_o_0 (glink_gpio_o_0[31:0] ),// PS -> Glink
.glink_gpio_o_1 (glink_gpio_o_1[31:0] ),// PS -> Glink
.m_axis_fifo_glink_out_tdata (glink_tx_fifo_tdata[15:0] ),// PS -> Glink
.m_axis_fifo_glink_out_tlast (glink_tx_fifo_tlast ),// PS -> Glink
.m_axis_fifo_glink_out_tready (glink_tx_fifo_tready ),// PS -> Glink
.m_axis_fifo_glink_out_tvalid (glink_tx_fifo_tvalid ),// PS -> Glink
.s_axis_fifo_glink_in_tdata (glink_rx_fifo_tdata[15:0] ),// PS <- Glink
.s_axis_fifo_glink_in_tlast (glink_rx_fifo_tlast ),// PS <- Glink
.s_axis_fifo_glink_in_tready (glink_rx_fifo_tready ),// PS <- Glink
.s_axis_fifo_glink_in_tvalid (glink_rx_fifo_tvalid ),// PS <- Glink
.pwdown_gpio_o (pwdown_gpio_o )
);
assign c2c_rst_n = ~lvds_rst;
assign c2c_rx_clk = lvds_rx_clk;
assign c2c_tx_clk = lvds_tx_clk;
reg pwdown_gpio_o_100M_d1;
reg pwdown_gpio_o_100M_d2;
reg pwdown_gpio_o_100M_d3;
always @ ( posedge clk_beam_100m ) begin
if ( ~beam_locked ) begin
pwdown_gpio_o_100M_d1 <= 1'd0;
pwdown_gpio_o_100M_d2 <= 1'd0;
pwdown_gpio_o_100M_d3 <= 1'd0;
end
else begin
pwdown_gpio_o_100M_d1 <= pwdown_gpio_o;
pwdown_gpio_o_100M_d2 <= pwdown_gpio_o_100M_d1;
pwdown_gpio_o_100M_d3 <= pwdown_gpio_o_100M_d2;
end
end
assign PW_DOWN = pwdown_gpio_o_100M_d3;
//******************************************************************************
//*********************************** Glink *************************************
//******************************************************************************
glink_top u_glink_top(
// glink gt reference clock
.glink_refclk_p (glink_refclk_p ), //in,125mhz
.glink_refclk_n (glink_refclk_n ),
// glink pk clock
.glink_logic_clk (glink_logic_clk ), //in,25mhz
.pl_rst (glink_rst ),
.rx_datain_p_ch_a (rx_datain_p_ch_a ),
.rx_datain_n_ch_a (rx_datain_n_ch_a ),
.rx_datain_p_ch_b (rx_datain_p_ch_b ),
.rx_datain_n_ch_b (rx_datain_n_ch_b ),
.tx_dataout_p_ch_a (tx_dataout_p_ch_a ),
.tx_dataout_n_ch_a (tx_dataout_n_ch_a ),
.tx_dataout_p_ch_b (tx_dataout_p_ch_b ),
.tx_dataout_n_ch_b (tx_dataout_n_ch_b ),
//glink_ctrl
.glink_gpio_i_0 (glink_gpio_i_0 ),
.glink_gpio_i_1 (glink_gpio_i_1 ),
.glink_gpio_o_0 (glink_gpio_o_0 ),
.glink_gpio_o_1 (glink_gpio_o_1 ),
//DMA_send_fifo
.glink_tx_fifo_tdata (glink_tx_fifo_tdata ),
.glink_tx_fifo_tlast (glink_tx_fifo_tlast ),
.glink_tx_fifo_tready (glink_tx_fifo_tready ),
.glink_tx_fifo_tvalid (glink_tx_fifo_tvalid ),
//DMA_recv_fifo
.glink_rx_fifo_tdata (glink_rx_fifo_tdata ),
.glink_rx_fifo_tlast (glink_rx_fifo_tlast ),
.glink_rx_fifo_tready (glink_rx_fifo_tready ),
.glink_rx_fifo_tvalid (glink_rx_fifo_tvalid ),
.glink_ip_clk (glink_ip_clk )//out,31.25mhz
);
//******************************************************************************
//***************************** C2C DMA Control *******************************
//******************************************************************************
c2c_bridge_dma u_c2c_bridge_dma(
.clk (pl_clk_96m ), // input clk, 96Mhz
.rst (lvds_rst ), // input rst, active high
//interface data
.c2c_clkin (lvds_rx_clk ),
.c2c_clkout (lvds_tx_clk ),
.c2c_din (lvds_rx_data[0] ),
.c2c_dout (lvds_tx_data ),
//dma fifo interface
.c2c_tx_fifo_tdata (c2c_tx_fifo_tdata ),
.c2c_tx_fifo_tlast (c2c_tx_fifo_tlast ),
.c2c_tx_fifo_tready (c2c_tx_fifo_tready ),
.c2c_tx_fifo_tvalid (c2c_tx_fifo_tvalid ),
.c2c_rx_fifo_tdata (c2c_rx_fifo_tdata ),
.c2c_rx_fifo_tlast (c2c_rx_fifo_tlast ),
.c2c_rx_fifo_tready (c2c_rx_fifo_tready ),
.c2c_rx_fifo_tvalid (c2c_rx_fifo_tvalid )
);
//******************************************************************************
//************************************* beam ctrl*********************************
//******************************************************************************
wire beam_clk;
wire en_out;
wire data_out;
wire tr_out;
wire dary_out;
wire [15:0] debug_freq ;
wire debug_freq_change ;
wire [63:0] debug_tr_count ;
antenna_interface u_antenna_interface
(
.clk_in (lvds_rx_clk ),
.data_in (lvds_rx_data[1]),
.tr_in (lvds_rx_data[2]),
.dary_in (lvds_rx_data[3]),
.rst (lvds_rst ),
.ant_clk (beam_clk ),
.en_out (en_out ),
.clk_out (clk_beam_100m ),
.data_out (data_out ),
.tr_out (tr_out ),
.dary_out (dary_out ),
.debug_freq (debug_freq ),
.debug_freq_change (debug_freq_change),
.debug_tr_count (debug_tr_count )
);
ttop_S_005X u_ttop_S_005X(
.clock100 (clk_beam_100m ),
.clkdv (clk_beam_12_5m ),
.clk50 (clk_beam_50m ),
.n_rst (pwdown_gpio_o_100M_d3),
//interface Vio
.CLK (beam_clk ),
.DATA (data_out ),
.EN (en_out ),
.DARY (dary_out ),
.TR (tr_out ),
//TR Com_Tr_TR_N ,
.CLK_TR ({CLK_TR[0] ,CLK_TR[1] ,CLK_TR[2] ,CLK_TR[3] } ),
.DATA_TR ({DATA_TR[0],DATA_TR[1],DATA_TR[2],DATA_TR[3] } ),
.SYN_TR ({SYN_TR[0] ,SYN_TR[1] ,SYN_TR[2] ,SYN_TR[3] } ),
.SEL_TR ({SEL_TR[0] ,SEL_TR[1] ,SEL_TR[2] ,SEL_TR[3] } ),
.SEL4_TR ({SEL1_TR[3],SEL2_TR[3],SEL3_TR[3],SEL4_TR[3] } ),
.SEL3_TR ({SEL1_TR[2],SEL2_TR[2],SEL3_TR[2],SEL4_TR[2] } ),
.SEL2_TR ({SEL1_TR[1],SEL2_TR[1],SEL3_TR[1],SEL4_TR[1] } ),
.SEL1_TR ({SEL1_TR[0],SEL2_TR[0],SEL3_TR[0],SEL4_TR[0] } ),//sel4是高使
.TR_TR ({TR_TR[0],TR_TR[1],TR_TR[2],TR_TR[3] } ),
//DLY
.T_DLY(T_DLY),
.R_DLY(R_DLY),
//test
.LED0 ( ),
.LED1 ( ),
.test1( ),
.test2( ),
.test3( ),
.test4( ),
.test5( ),
.test6( ),
.test7( ),
.test8( )
);
//******************************************************************************
//******************************* ILAs and VIOs *******************************
//******************************************************************************
ila_c2c_dma_tx u_ila_c2c_dma_tx (
.clk (u_c2c_bridge_dma.clk ), // input wire clk
.probe0 (u_c2c_bridge_dma.c2c_tx_fifo_tdata ), // input wire [31:0] probe0
.probe1 (u_c2c_bridge_dma.c2c_tx_fifo_tlast ), // input wire [0:0] probe1
.probe2 (u_c2c_bridge_dma.c2c_tx_fifo_tready), // input wire [0:0] probe2
.probe3 (u_c2c_bridge_dma.c2c_tx_fifo_tvalid), // input wire [0:0] probe3
.probe4 (u_c2c_bridge_dma.rst ), // input wire [0:0] probe4
.probe5 (u_c2c_bridge_dma.c2c_dout ), // input wire [0:0] probe5
.probe6 (u_c2c_bridge_dma.tx_data_32 ) // input wire [31:0] probe6
);
ila_c2c_dma_rx u_ila_c2c_dma_rx (
.clk (u_c2c_bridge_dma.c2c_clkin ), // input wire clk
.probe0 (u_c2c_bridge_dma.c2c_rx_fifo_tdata ), // input wire [31:0] probe0
.probe1 (u_c2c_bridge_dma.c2c_rx_fifo_tlast ), // input wire [0:0] probe1
.probe2 (u_c2c_bridge_dma.c2c_rx_fifo_tready), // input wire [0:0] probe2
.probe3 (u_c2c_bridge_dma.c2c_rx_fifo_tvalid), // input wire [0:0] probe3
.probe4 (u_c2c_bridge_dma.rx_state ), // input wire [3:0] probe4
.probe5 (u_c2c_bridge_dma.rx_state_next ), // input wire [3:0] probe5
.probe6 (u_c2c_bridge_dma.rx_data_cnt ), // input wire [36:0] probe6
.probe7 (u_c2c_bridge_dma.rx_frame_length ), // input wire [31:0] probe7
.probe8 (u_c2c_bridge_dma.rx_data_32 ), // input wire [31:0] probe8
.probe9 (u_c2c_bridge_dma.c2c_din ) // input wire [0:0] probe9
);
ila_glink u_ila_glink (
.clk (glink_ila_clk ), // input wire clk
.probe0 (u_glink_top.glink_rst ), // input wire [0:0] probe0
.probe1 (u_glink_top.smartnc_trans_trig ), // input wire [0:0] probe1
.probe2 (u_glink_top.smartnc_trans_reset ), // input wire [0:0] probe2
.probe3 (u_glink_top.smartnc_trans_idle ), // input wire [0:0] probe3
.probe4 (u_glink_top.smartnc_trans_err ), // input wire [0:0] probe4
.probe5 (u_glink_top.smartnc_intf_tx_fifo_wdata ), // input wire [15:0] probe5
.probe6 (u_glink_top.smartnc_intf_tx_fifo_wr_en ), // input wire [0:0] probe6
.probe7 (u_glink_top.smartnc_intf_tx_fifo_afull ), // input wire [0:0] probe7
.probe8 (u_glink_top.smartnc_intf_rx_fifo_empty ), // input wire [0:0] probe8
.probe9 (u_glink_top.smartnc_intf_rx_fifo_rdata ), // input wire [15:0] probe9
.probe10(u_glink_top.smartnc_intf_rx_fifo_rd_en ), // input wire [0:0] probe10
.probe11(u_glink_top.smartnt_intf_cmd_proc_req ), // input wire [0:0] probe11
.probe12(u_glink_top.smartnt_intf_cmd_proc_ack ), // input wire [0:0] probe12
.probe13(u_glink_top.smartnt_intf_rx_fifo_empty ), // input wire [0:0] probe13
.probe14(u_glink_top.smartnt_intf_rx_fifo_rdata ), // input wire [15:0] probe14
.probe15(u_glink_top.smartnt_intf_rx_fifo_rd_en ), // input wire [0:0] probe15
.probe16(u_glink_top.smartnt_intf_tx_fifo_wdata ), // input wire [15:0] probe16
.probe17(u_glink_top.smartnt_intf_tx_fifo_wr_en ), // input wire [0:0] probe17
.probe18(u_glink_top.glink_ip_clk ), // input wire [0:0] probe18
.probe19(u_glink_top.glink_ip_rst_n ) // input wire [0:0] probe19
);
ila_glink_2 u_ila_glink_2 (
.clk (ps_clk ), // input wire clk
.probe0(u_glink_top.i_node_id ), // input wire [11:0] probe0
.probe1(u_glink_top.i_node_id_par ), // input wire [0:0] probe1
.probe2(u_glink_top.i_smartnc_2nd_cfg), // input wire [15:0] probe2
.probe3(u_glink_top.i_smartnc_3rd_cfg), // input wire [15:0] probe3
.probe4(u_glink_top.i_smartnt_cfg ) // input wire [15:0] probe4
);
ila_dma_fifo u_ila_dma_fifo (
.clk (glink_ip_clk ), // input wire clk
.probe0(glink_tx_fifo_tdata ), // input wire [15:0] probe0
.probe1(glink_tx_fifo_tlast ), // input wire [0:0] probe1
.probe2(glink_tx_fifo_tready), // input wire [0:0] probe2
.probe3(glink_tx_fifo_tvalid), // input wire [0:0] probe3
.probe4(glink_rx_fifo_tdata ), // input wire [15:0] probe4
.probe5(glink_rx_fifo_tlast ), // input wire [0:0] probe5
.probe6(glink_rx_fifo_tready), // input wire [0:0] probe6
.probe7(glink_rx_fifo_tvalid) // input wire [0:0] probe7
);
ila_beam u_ila_beam (
.clk (clk_beam_100m ), // input wire clk
.probe0 (clk_beam_12_5m ), // input wire [0:0] probe0
.probe1 (clk_beam_50m ), // input wire [0:0] probe1
.probe2 (beam_locked ), // input wire [0:0] probe2
.probe3 (beam_clk ), // input wire [0:0] probe3
.probe4 (data_out ), // input wire [0:0] probe4
.probe5 (en_out ), // input wire [0:0] probe5
.probe6 (dary_out ), // input wire [0:0] probe6
.probe7 (tr_out ), // input wire [0:0] probe7
.probe8 (CLK_TR ), // input wire [3:0] probe8
.probe9 (DATA_TR ), // input wire [3:0] probe9
.probe10(SYN_TR ), // input wire [3:0] probe10
.probe11(SEL_TR ), // input wire [3:0] probe11
.probe12(SEL1_TR ), // input wire [3:0] probe12
.probe13(SEL2_TR ), // input wire [3:0] probe13
.probe14(SEL3_TR ), // input wire [3:0] probe14
.probe15(SEL4_TR ), // input wire [3:0] probe15
.probe16(TR_TR ), // input wire [3:0] probe16
.probe17(T_DLY ), // input wire [0:0] probe17
.probe18(R_DLY ), // input wire [0:0] probe18
.probe19(debug_freq ), // input wire [15:0] probe19
.probe20(debug_freq_change), // input wire [0:0] probe20
.probe21(debug_tr_count ) // input wire [63:0] probe21
);
ila_en_creat_in u_ila_en_creat_in (
.clk (u_antenna_interface.clk_in ), // input wire clk
.probe0(u_antenna_interface.data_in ), // input wire [0:0] probe0
.probe1(u_antenna_interface.tr_in ), // input wire [0:0] probe1
.probe2(u_antenna_interface.dary_in ), // input wire [0:0] probe2
.probe3(u_antenna_interface.data_in_9 ), // input wire [8:0] probe0
.probe4(u_antenna_interface.rx_bitcnt ), // input wire [15:0] probe1
.probe5(u_antenna_interface.rx_state ), // input wire [3:0] probe4
.probe6(u_antenna_interface.recv_down ), // input wire [0:0] probe6
.probe7(u_antenna_interface.fifo_data_in), // input wire [0:0] probe8
.probe8(u_antenna_interface.fifo_wr_en ) // input wire [0:0] probe9
);
ila_en_creat_out u_ila_en_creat_out (
.clk (u_antenna_interface.clk_out ), // input wire clk
.probe0 (u_antenna_interface.en_out ), // input wire [0:0] probe0
.probe1 (u_antenna_interface.data_out ), // input wire [0:0] probe1
.probe2 (u_antenna_interface.tr_out ), // input wire [0:0] probe2
.probe3 (u_antenna_interface.dary_out ), // input wire [0:0] probe3
.probe4 (u_antenna_interface.tx_bitcnt ), // input wire [15:0] probe2
.probe5 (u_antenna_interface.rest_cnt ), // input wire [15:0] probe3
.probe6 (u_antenna_interface.tx_state ), // input wire [3:0] probe5
.probe7 (u_antenna_interface.recv_down_d3 ), // input wire [0:0] probe7
.probe8 (u_antenna_interface.data_out_reg ), // input wire [0:0] probe10
.probe9 (u_antenna_interface.fifo_rd_en ), // input wire [0:0] probe11
.probe10(u_antenna_interface.en_out_reg ), // input wire [0:0] probe12
.probe11(u_antenna_interface.beam_clk_reg ), // input wire [0:0] probe13
.probe12(u_antenna_interface.beam_clk_reg_d2) // input wire [0:0] probe14
);
endmodule
projects/datalink_814/dl814_z7/rtl/ttop_S_005X.edf
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// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Mon Sep 12 16:54:54 2022
// Host : Ksling-PC running 64-bit major release (build 9200)
// Command : write_verilog -mode synth_stub ttop_S_005X.v
// Design : ttop_S
// Purpose : Stub declaration of top-level module interface
// Device : xc7z045ffg900-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module ttop_S_005X(clock100, clkdv, clk50, n_rst, LED0, LED1, CLK, DATA, EN,
DARY, TR, CLK_TR, DATA_TR, SYN_TR, SEL_TR, SEL4_TR, SEL3_TR, SEL2_TR, SEL1_TR, TR_TR, T_DLY, R_DLY, test1,
test2, test3, test4, test5, test6, test7, test8)
/* synthesis syn_black_box black_box_pad_pin="clock100,clkdv,clk50,n_rst,LED0,LED1,CLK,DATA,EN,DARY,TR,CLK_TR[3:0],DATA_TR[3:0],SYN_TR[3:0],SEL_TR[3:0],SEL4_TR[3:0],SEL3_TR[3:0],SEL2_TR[3:0],SEL1_TR[3:0],TR_TR[3:0],T_DLY,R_DLY,test1,test2,test3,test4,test5,test6,test7,test8" */;
input clock100;
input clkdv;
input clk50;
input n_rst;
output LED0;
output LED1;
input CLK;
input DATA;
input EN;
input DARY;
input TR;
output [3:0]CLK_TR;
output [3:0]DATA_TR;
output [3:0]SYN_TR;
output [3:0]SEL_TR;
output [3:0]SEL4_TR;
output [3:0]SEL3_TR;
output [3:0]SEL2_TR;
output [3:0]SEL1_TR;
output [3:0]TR_TR;
output T_DLY;
output R_DLY;
output test1;
output test2;
output test3;
output test4;
output test5;
output test6;
output test7;
output test8;
endmodule