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major update to lcmv, to fit hop control

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1. 调零算法部分增加调零控制模块,用于各模块互联和状态控制以及数据存储,增加LCMV和DAS选通; 2. Cordic 旋转输入改为保留两个符号位,避免溢出; 3. LCMV快拍数修改为2048; 4. 修改功率计算模块,适配较小数据位宽; 5. 修改在线捕获校准程序自动校准部分VIO初值; 6. 地检新射频发端增加自动频点切换
This commit is contained in:
josh
2023-07-31 10:31:21 +08:00
parent a877802bdf
commit 365a132831
418 changed files with 14603 additions and 3824 deletions
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modules/xc7k410tffg900-2/var_cal/rtl/var_cal.v
+94 -48
View File
@@ -19,7 +19,9 @@
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Revision 0.01 - File Created
// 20230730-1427 - 修改输入位宽小于乘法器位宽时的处理，由补零变为符号位扩展；
// 修改；修改累加和输出截位方式，依托原始数据位宽进行处理。
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
@@ -30,7 +32,7 @@ module var_cal
parameter ACCUM_NUM = 16384,
parameter DATA_I_WIDTH = 30,
parameter DATA_O_WIDTH = 32,
parameter CMPY_WIDTH = 18
parameter CMPY_I_WIDTH = 18
)
(
input clk ,
@@ -50,11 +52,13 @@ module var_cal
integer i;
localparam CMPY_VALID_WIDTH = CMPY_WIDTH-1; // 17-bit valid data to protect cmpy from overflow
localparam DATA_MULT_FULL_WIDTH = 2*CMPY_VALID_WIDTH+1;
localparam DATA_MULT_VALID_WIDTH = 2*CMPY_VALID_WIDTH;
localparam AXIS_DATA_I_WIDTH = 8*((CMPY_VALID_WIDTH-1)/8+1) ; // axis data width of input real/image data
localparam AXIS_DATA_P_WIDTH = 8*((DATA_MULT_FULL_WIDTH-1)/8+1); // axis data width of cmpy output real/image data
localparam CMPY_P_WIDTH = 2*CMPY_I_WIDTH+1;
localparam AXIS_CMPY_I_WIDTH = 8*((CMPY_I_WIDTH-1)/8+1) ; // axis data width of input real/image data
localparam AXIS_CMPY_P_WIDTH = 8*((CMPY_P_WIDTH-1)/8+1); // axis data width of cmpy output real/image data
localparam CMPY_P_VALID_WIDTH = (DATA_I_WIDTH > CMPY_I_WIDTH) ? 2*CMPY_I_WIDTH : 2*DATA_I_WIDTH;
localparam ACCUM_WIDTH = CMPY_P_VALID_WIDTH + $clog2(ACCUM_NUM);
// status control
reg cal_start_auto = 'b0;
@@ -63,7 +67,7 @@ reg cal_start_d2 = 'b0;
reg cal_busy_buf = 'b0;
reg [$clog2(ACCUM_NUM)-1 : 0] cnt_accum = 'b0;
reg last_data = 'b0;
reg last_data_d [0:6]; // 6 for cmpy, 1 for register output
reg [6:0] last_data_d = 'b0; // 1 for register input, 6 for cmpy, 1 for register output
assign cal_busy = cal_busy_buf;
assign var_valid = last_data_d[6];
@@ -73,11 +77,16 @@ always @(posedge clk) begin
cal_start_auto <= 'b0;
end
else begin
if (~cal_busy_buf) begin
cal_start_auto = ~cal_start_auto;
if (cal_auto_en) begin
if (~cal_busy_buf) begin
cal_start_auto <= ~cal_start_auto;
end
else begin
cal_start_auto <= cal_start_auto;
end
end
else begin
cal_start_auto <= cal_start_auto;
cal_start_auto <= 'b0;
end
end
end
@@ -123,50 +132,72 @@ always @(posedge clk) begin
end
always @(posedge clk) begin
last_data_d[0] <= last_data;
for (i = 0; i < 6; i = i + 1) begin
last_data_d[i+1] <= last_data_d[i];
if (rst) begin
last_data_d[6:0] <= 'b0;
end
else begin
last_data_d[6:0] <= {last_data_d[5:0],last_data};
end
end
// cmpy
wire [AXIS_DATA_I_WIDTH-1 : 0] cmpy_i_real;
wire [AXIS_DATA_I_WIDTH-1 : 0] cmpy_i_imag;
wire [AXIS_DATA_P_WIDTH-1 : 0] cmpy_p_raw_real;
wire [AXIS_DATA_P_WIDTH-1 : 0] cmpy_p_raw_imag;
wire [DATA_O_WIDTH-1 : 0] cmpy_p_real;
wire [DATA_O_WIDTH-1 : 0] cmpy_p_imag;
reg [AXIS_CMPY_I_WIDTH-1 : 0] cmpy_a_real = 'b0;
reg [AXIS_CMPY_I_WIDTH-1 : 0] cmpy_a_imag = 'b0;
reg [AXIS_CMPY_I_WIDTH-1 : 0] cmpy_b_real = 'b0;
reg [AXIS_CMPY_I_WIDTH-1 : 0] cmpy_b_imag = 'b0;
wire [AXIS_CMPY_P_WIDTH-1 : 0] cmpy_p_raw_real;
wire [AXIS_CMPY_P_WIDTH-1 : 0] cmpy_p_raw_imag;
wire [CMPY_P_VALID_WIDTH-1 : 0] cmpy_p_real;
wire [CMPY_P_VALID_WIDTH-1 : 0] cmpy_p_imag;
if (CMPY_WIDTH > DATA_I_WIDTH) begin
// append zeros
assign cmpy_i_real = {{(AXIS_DATA_I_WIDTH-CMPY_VALID_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real,{(CMPY_VALID_WIDTH-DATA_I_WIDTH){1'b0}}};
assign cmpy_i_imag = {{(AXIS_DATA_I_WIDTH-CMPY_VALID_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag,{(CMPY_VALID_WIDTH-DATA_I_WIDTH){1'b0}}};
if (CMPY_I_WIDTH > DATA_I_WIDTH) begin
// sign-bit extension to fit cmpy input data width
always @(posedge clk) begin
if (rst) begin
cmpy_a_real <= 'b0;
cmpy_a_imag <= 'b0;
cmpy_b_real <= 'b0;
cmpy_b_imag <= 'b0;
end
else begin
cmpy_a_real <= {{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real};
cmpy_a_imag <= {{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag};
cmpy_b_real <= {{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real};
cmpy_b_imag <= (din_imag == {1'b1,{(DATA_I_WIDTH-1){1'b0}}}) ? {{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH+1){1'b0}},{(DATA_I_WIDTH-1){1'b1}}} : -{{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag};
end
end
end
else begin
// truncate msb
assign cmpy_i_real = {{(AXIS_DATA_I_WIDTH-CMPY_VALID_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real[DATA_I_WIDTH-1 -: CMPY_VALID_WIDTH]};
assign cmpy_i_imag = {{(AXIS_DATA_I_WIDTH-CMPY_VALID_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag[DATA_I_WIDTH-1 -: CMPY_VALID_WIDTH]};
always @(posedge clk) begin
if (rst) begin
cmpy_a_real <= 'b0;
cmpy_a_imag <= 'b0;
cmpy_b_real <= 'b0;
cmpy_b_imag <= 'b0;
end
else begin
cmpy_a_real <= {{(AXIS_CMPY_I_WIDTH-CMPY_I_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real[DATA_I_WIDTH-1 -: CMPY_I_WIDTH]};
cmpy_a_imag <= {{(AXIS_CMPY_I_WIDTH-CMPY_I_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag[DATA_I_WIDTH-1 -: CMPY_I_WIDTH]};
cmpy_b_real <= {{(AXIS_CMPY_I_WIDTH-CMPY_I_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real[DATA_I_WIDTH-1 -: CMPY_I_WIDTH]};
cmpy_b_imag <= (din_imag[DATA_I_WIDTH-1 -: CMPY_I_WIDTH] == {1'b1,{(CMPY_I_WIDTH-1){1'b0}}}) ? {{(AXIS_CMPY_I_WIDTH-CMPY_I_WIDTH+1){1'b0}},{(CMPY_I_WIDTH-1){1'b1}}} : -{{(AXIS_CMPY_I_WIDTH-CMPY_I_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag[DATA_I_WIDTH-1 -: CMPY_I_WIDTH]};
end
end
end
if (DATA_O_WIDTH > DATA_MULT_VALID_WIDTH) begin
// append zeros
assign cmpy_p_real = {cmpy_p_raw_real[0 +: DATA_MULT_VALID_WIDTH],{(DATA_O_WIDTH-DATA_MULT_VALID_WIDTH){1'b0}}};
assign cmpy_p_imag = {cmpy_p_raw_imag[0 +: DATA_MULT_VALID_WIDTH],{(DATA_O_WIDTH-DATA_MULT_VALID_WIDTH){1'b0}}};
end
else begin
// truncate msb
assign cmpy_p_real = cmpy_p_raw_real[DATA_MULT_VALID_WIDTH-1 -: DATA_O_WIDTH];
assign cmpy_p_imag = cmpy_p_raw_imag[DATA_MULT_VALID_WIDTH-1 -: DATA_O_WIDTH];
end
// truncate valid bits
assign cmpy_p_real = cmpy_p_raw_real[0 +: CMPY_P_VALID_WIDTH];
assign cmpy_p_imag = cmpy_p_raw_imag[0 +: CMPY_P_VALID_WIDTH];
wire [2*AXIS_DATA_I_WIDTH-1:0] cmpy_a;
wire [2*AXIS_DATA_I_WIDTH-1:0] cmpy_b;
wire [2*AXIS_DATA_P_WIDTH-1:0] cmpy_p;
wire [2*AXIS_CMPY_I_WIDTH-1:0] cmpy_a;
wire [2*AXIS_CMPY_I_WIDTH-1:0] cmpy_b;
wire [2*AXIS_CMPY_P_WIDTH-1:0] cmpy_p;
wire cmpy_p_vld;
assign cmpy_a = {cmpy_i_imag,cmpy_i_real};
assign cmpy_b = {-cmpy_i_imag,cmpy_i_real};
assign cmpy_a = {cmpy_a_imag,cmpy_a_real};
assign cmpy_b = {cmpy_b_imag,cmpy_b_real};
assign {cmpy_p_raw_imag,cmpy_p_raw_real} = cmpy_p;
cmpy_18x18_mult u_cmpy_18x18
@@ -180,8 +211,9 @@ cmpy_18x18_mult u_cmpy_18x18
.m_axis_dout_tdata (cmpy_p ) // output wire [63 : 0] m_axis_dout_tdata
);
// accumulation
reg [DATA_O_WIDTH+$clog2(ACCUM_NUM) : 0] accum = 'b0;
reg [ACCUM_WIDTH-1 : 0] accum = 'b0;
reg [DATA_O_WIDTH-1 : 0] var_buf = 'b0;
assign var = var_buf;
@@ -200,12 +232,26 @@ always @(posedge clk) begin
end
end
always @(posedge clk) begin
if (rst) begin
var_buf <= 'b0;
if (DATA_O_WIDTH > ACCUM_WIDTH) begin
// sign-bit extension to fit output data width
always @(posedge clk) begin
if (rst) begin
var_buf <= 'b0;
end
else if (last_data_d[5]) begin
var_buf <= {{(DATA_O_WIDTH-ACCUM_WIDTH){accum[ACCUM_WIDTH-1]}},accum};
end
end
else if (last_data_d[5]) begin
var_buf <= accum[DATA_O_WIDTH+$clog2(ACCUM_NUM) -: DATA_O_WIDTH];
end
else begin
// truncate msb
always @(posedge clk) begin
if (rst) begin
var_buf <= 'b0;
end
else if (last_data_d[5]) begin
var_buf <= accum[ACCUM_WIDTH-1 -: DATA_O_WIDTH];
end
end
end
modules/xc7k410tffg900-2/var_cal/testbenches/tb_var_cal.v
+21 -5
View File
@@ -22,7 +22,10 @@
module tb_var_cal;
localparam DATA_I_WIDTH = 30;
reg clk = 1'b1;
reg clk_init = 1'b1;
reg rst = 1'b1;
reg cal_start = 1'b0;
@@ -30,13 +33,22 @@ reg cal_auto_en = 1'b0;
wire cal_busy;
reg din_valid = 1'b0;
reg [29:0] din_real = 'b0;
reg [29:0] din_imag = 'b0;
reg [29:0] din_file_real = 'b0;
reg [29:0] din_file_imag = 'b0;
wire [DATA_I_WIDTH-1:0] din_real;
wire [DATA_I_WIDTH-1:0] din_imag;
assign din_real = din_file_real[29 -: DATA_I_WIDTH];
assign din_imag = din_file_imag[29 -: DATA_I_WIDTH];
wire var_valid;
wire [31:0] var;
var_cal u_var_cal
var_cal #(
.ACCUM_NUM (16384 ),
.DATA_I_WIDTH (DATA_I_WIDTH ),
.DATA_O_WIDTH (32 )
) u_var_cal
(
.clk (clk ),
.rst (rst ),
@@ -67,12 +79,16 @@ initial begin
r_file = $fopen("./../../../../../testbenches/singletone.csv","r");
for (i = 0; i <= 32768; i = i + 1) begin
@(posedge clk)
$fscanf(r_file,"%d,%d",din_real,din_imag);
$fscanf(r_file,"%d,%d",din_file_real,din_file_imag);
end
$fclose(r_file);
$stop;
end
always #10 clk = ~clk;
always #10 clk_init = ~clk_init;
always @(posedge clk_init) begin
clk <= ~clk;
end
endmodule