Archived
major update to lcmv, to fit hop control
1. 调零算法部分增加调零控制模块,用于各模块互联和状态控制以及数据存储,增加LCMV和DAS选通; 2. Cordic 旋转输入改为保留两个符号位,避免溢出; 3. LCMV快拍数修改为2048; 4. 修改功率计算模块,适配较小数据位宽; 5. 修改在线捕获校准程序自动校准部分VIO初值; 6. 地检新射频发端增加自动频点切换
This commit is contained in:
@@ -19,7 +19,9 @@
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// Dependencies:
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// Dependencies:
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//
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//
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// Revision:
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// Revision:
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// Revision 0.01 - File Created
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// Revision 0.01 - File Created
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// 20230730-1427 - 修改输入位宽小于乘法器位宽时的处理，由补零变为符号位扩展；
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// 修改；修改累加和输出截位方式，依托原始数据位宽进行处理。
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// Additional Comments:
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// Additional Comments:
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//
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//
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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@@ -30,7 +32,7 @@ module var_cal
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parameter ACCUM_NUM = 16384,
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parameter ACCUM_NUM = 16384,
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parameter DATA_I_WIDTH = 30,
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parameter DATA_I_WIDTH = 30,
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parameter DATA_O_WIDTH = 32,
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parameter DATA_O_WIDTH = 32,
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parameter CMPY_WIDTH = 18
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parameter CMPY_I_WIDTH = 18
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)
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)
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(
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(
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input clk ,
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input clk ,
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@@ -50,11 +52,13 @@ module var_cal
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integer i;
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integer i;
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localparam CMPY_VALID_WIDTH = CMPY_WIDTH-1; // 17-bit valid data to protect cmpy from overflow
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localparam CMPY_P_WIDTH = 2*CMPY_I_WIDTH+1;
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localparam DATA_MULT_FULL_WIDTH = 2*CMPY_VALID_WIDTH+1;
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localparam AXIS_CMPY_I_WIDTH = 8*((CMPY_I_WIDTH-1)/8+1) ; // axis data width of input real/image data
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localparam DATA_MULT_VALID_WIDTH = 2*CMPY_VALID_WIDTH;
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localparam AXIS_CMPY_P_WIDTH = 8*((CMPY_P_WIDTH-1)/8+1); // axis data width of cmpy output real/image data
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localparam AXIS_DATA_I_WIDTH = 8*((CMPY_VALID_WIDTH-1)/8+1) ; // axis data width of input real/image data
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localparam CMPY_P_VALID_WIDTH = (DATA_I_WIDTH > CMPY_I_WIDTH) ? 2*CMPY_I_WIDTH : 2*DATA_I_WIDTH;
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localparam AXIS_DATA_P_WIDTH = 8*((DATA_MULT_FULL_WIDTH-1)/8+1); // axis data width of cmpy output real/image data
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localparam ACCUM_WIDTH = CMPY_P_VALID_WIDTH + $clog2(ACCUM_NUM);
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// status control
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// status control
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reg cal_start_auto = 'b0;
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reg cal_start_auto = 'b0;
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@@ -63,7 +67,7 @@ reg cal_start_d2 = 'b0;
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reg cal_busy_buf = 'b0;
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reg cal_busy_buf = 'b0;
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reg [$clog2(ACCUM_NUM)-1 : 0] cnt_accum = 'b0;
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reg [$clog2(ACCUM_NUM)-1 : 0] cnt_accum = 'b0;
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reg last_data = 'b0;
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reg last_data = 'b0;
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reg last_data_d [0:6]; // 6 for cmpy, 1 for register output
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reg [6:0] last_data_d = 'b0; // 1 for register input, 6 for cmpy, 1 for register output
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assign cal_busy = cal_busy_buf;
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assign cal_busy = cal_busy_buf;
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assign var_valid = last_data_d[6];
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assign var_valid = last_data_d[6];
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@@ -73,11 +77,16 @@ always @(posedge clk) begin
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cal_start_auto <= 'b0;
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cal_start_auto <= 'b0;
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end
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end
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else begin
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else begin
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if (~cal_busy_buf) begin
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if (cal_auto_en) begin
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cal_start_auto = ~cal_start_auto;
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if (~cal_busy_buf) begin
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cal_start_auto <= ~cal_start_auto;
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end
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else begin
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cal_start_auto <= cal_start_auto;
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end
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end
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end
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else begin
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else begin
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cal_start_auto <= cal_start_auto;
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cal_start_auto <= 'b0;
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end
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end
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end
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end
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end
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end
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@@ -123,50 +132,72 @@ always @(posedge clk) begin
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end
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end
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always @(posedge clk) begin
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always @(posedge clk) begin
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last_data_d[0] <= last_data;
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if (rst) begin
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last_data_d[6:0] <= 'b0;
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for (i = 0; i < 6; i = i + 1) begin
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end
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last_data_d[i+1] <= last_data_d[i];
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else begin
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last_data_d[6:0] <= {last_data_d[5:0],last_data};
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end
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end
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end
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end
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// cmpy
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// cmpy
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wire [AXIS_DATA_I_WIDTH-1 : 0] cmpy_i_real;
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reg [AXIS_CMPY_I_WIDTH-1 : 0] cmpy_a_real = 'b0;
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wire [AXIS_DATA_I_WIDTH-1 : 0] cmpy_i_imag;
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reg [AXIS_CMPY_I_WIDTH-1 : 0] cmpy_a_imag = 'b0;
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wire [AXIS_DATA_P_WIDTH-1 : 0] cmpy_p_raw_real;
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reg [AXIS_CMPY_I_WIDTH-1 : 0] cmpy_b_real = 'b0;
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wire [AXIS_DATA_P_WIDTH-1 : 0] cmpy_p_raw_imag;
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reg [AXIS_CMPY_I_WIDTH-1 : 0] cmpy_b_imag = 'b0;
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wire [DATA_O_WIDTH-1 : 0] cmpy_p_real;
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wire [AXIS_CMPY_P_WIDTH-1 : 0] cmpy_p_raw_real;
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wire [DATA_O_WIDTH-1 : 0] cmpy_p_imag;
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wire [AXIS_CMPY_P_WIDTH-1 : 0] cmpy_p_raw_imag;
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wire [CMPY_P_VALID_WIDTH-1 : 0] cmpy_p_real;
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wire [CMPY_P_VALID_WIDTH-1 : 0] cmpy_p_imag;
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if (CMPY_WIDTH > DATA_I_WIDTH) begin
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if (CMPY_I_WIDTH > DATA_I_WIDTH) begin
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// append zeros
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// sign-bit extension to fit cmpy input data width
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assign cmpy_i_real = {{(AXIS_DATA_I_WIDTH-CMPY_VALID_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real,{(CMPY_VALID_WIDTH-DATA_I_WIDTH){1'b0}}};
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always @(posedge clk) begin
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assign cmpy_i_imag = {{(AXIS_DATA_I_WIDTH-CMPY_VALID_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag,{(CMPY_VALID_WIDTH-DATA_I_WIDTH){1'b0}}};
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if (rst) begin
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cmpy_a_real <= 'b0;
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cmpy_a_imag <= 'b0;
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cmpy_b_real <= 'b0;
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cmpy_b_imag <= 'b0;
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end
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else begin
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cmpy_a_real <= {{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real};
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cmpy_a_imag <= {{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag};
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cmpy_b_real <= {{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real};
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cmpy_b_imag <= (din_imag == {1'b1,{(DATA_I_WIDTH-1){1'b0}}}) ? {{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH+1){1'b0}},{(DATA_I_WIDTH-1){1'b1}}} : -{{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag};
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end
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end
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end
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end
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else begin
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else begin
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// truncate msb
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// truncate msb
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assign cmpy_i_real = {{(AXIS_DATA_I_WIDTH-CMPY_VALID_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real[DATA_I_WIDTH-1 -: CMPY_VALID_WIDTH]};
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always @(posedge clk) begin
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assign cmpy_i_imag = {{(AXIS_DATA_I_WIDTH-CMPY_VALID_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag[DATA_I_WIDTH-1 -: CMPY_VALID_WIDTH]};
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if (rst) begin
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cmpy_a_real <= 'b0;
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cmpy_a_imag <= 'b0;
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cmpy_b_real <= 'b0;
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cmpy_b_imag <= 'b0;
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end
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else begin
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cmpy_a_real <= {{(AXIS_CMPY_I_WIDTH-CMPY_I_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real[DATA_I_WIDTH-1 -: CMPY_I_WIDTH]};
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cmpy_a_imag <= {{(AXIS_CMPY_I_WIDTH-CMPY_I_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag[DATA_I_WIDTH-1 -: CMPY_I_WIDTH]};
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cmpy_b_real <= {{(AXIS_CMPY_I_WIDTH-CMPY_I_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real[DATA_I_WIDTH-1 -: CMPY_I_WIDTH]};
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cmpy_b_imag <= (din_imag[DATA_I_WIDTH-1 -: CMPY_I_WIDTH] == {1'b1,{(CMPY_I_WIDTH-1){1'b0}}}) ? {{(AXIS_CMPY_I_WIDTH-CMPY_I_WIDTH+1){1'b0}},{(CMPY_I_WIDTH-1){1'b1}}} : -{{(AXIS_CMPY_I_WIDTH-CMPY_I_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag[DATA_I_WIDTH-1 -: CMPY_I_WIDTH]};
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end
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end
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end
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end
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if (DATA_O_WIDTH > DATA_MULT_VALID_WIDTH) begin
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// truncate valid bits
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// append zeros
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assign cmpy_p_real = cmpy_p_raw_real[0 +: CMPY_P_VALID_WIDTH];
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assign cmpy_p_real = {cmpy_p_raw_real[0 +: DATA_MULT_VALID_WIDTH],{(DATA_O_WIDTH-DATA_MULT_VALID_WIDTH){1'b0}}};
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assign cmpy_p_imag = cmpy_p_raw_imag[0 +: CMPY_P_VALID_WIDTH];
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assign cmpy_p_imag = {cmpy_p_raw_imag[0 +: DATA_MULT_VALID_WIDTH],{(DATA_O_WIDTH-DATA_MULT_VALID_WIDTH){1'b0}}};
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end
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else begin
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// truncate msb
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assign cmpy_p_real = cmpy_p_raw_real[DATA_MULT_VALID_WIDTH-1 -: DATA_O_WIDTH];
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assign cmpy_p_imag = cmpy_p_raw_imag[DATA_MULT_VALID_WIDTH-1 -: DATA_O_WIDTH];
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end
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wire [2*AXIS_DATA_I_WIDTH-1:0] cmpy_a;
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wire [2*AXIS_DATA_I_WIDTH-1:0] cmpy_b;
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wire [2*AXIS_CMPY_I_WIDTH-1:0] cmpy_a;
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wire [2*AXIS_DATA_P_WIDTH-1:0] cmpy_p;
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wire [2*AXIS_CMPY_I_WIDTH-1:0] cmpy_b;
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wire [2*AXIS_CMPY_P_WIDTH-1:0] cmpy_p;
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wire cmpy_p_vld;
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wire cmpy_p_vld;
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assign cmpy_a = {cmpy_i_imag,cmpy_i_real};
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assign cmpy_a = {cmpy_a_imag,cmpy_a_real};
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assign cmpy_b = {-cmpy_i_imag,cmpy_i_real};
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assign cmpy_b = {cmpy_b_imag,cmpy_b_real};
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assign {cmpy_p_raw_imag,cmpy_p_raw_real} = cmpy_p;
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assign {cmpy_p_raw_imag,cmpy_p_raw_real} = cmpy_p;
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cmpy_18x18_mult u_cmpy_18x18
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cmpy_18x18_mult u_cmpy_18x18
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@@ -180,8 +211,9 @@ cmpy_18x18_mult u_cmpy_18x18
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.m_axis_dout_tdata (cmpy_p ) // output wire [63 : 0] m_axis_dout_tdata
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.m_axis_dout_tdata (cmpy_p ) // output wire [63 : 0] m_axis_dout_tdata
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);
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);
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// accumulation
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// accumulation
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reg [DATA_O_WIDTH+$clog2(ACCUM_NUM) : 0] accum = 'b0;
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reg [ACCUM_WIDTH-1 : 0] accum = 'b0;
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reg [DATA_O_WIDTH-1 : 0] var_buf = 'b0;
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reg [DATA_O_WIDTH-1 : 0] var_buf = 'b0;
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assign var = var_buf;
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assign var = var_buf;
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@@ -200,12 +232,26 @@ always @(posedge clk) begin
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end
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end
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end
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end
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always @(posedge clk) begin
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if (DATA_O_WIDTH > ACCUM_WIDTH) begin
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if (rst) begin
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// sign-bit extension to fit output data width
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var_buf <= 'b0;
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always @(posedge clk) begin
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if (rst) begin
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var_buf <= 'b0;
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end
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else if (last_data_d[5]) begin
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var_buf <= {{(DATA_O_WIDTH-ACCUM_WIDTH){accum[ACCUM_WIDTH-1]}},accum};
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end
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end
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end
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else if (last_data_d[5]) begin
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end
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var_buf <= accum[DATA_O_WIDTH+$clog2(ACCUM_NUM) -: DATA_O_WIDTH];
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else begin
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// truncate msb
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always @(posedge clk) begin
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if (rst) begin
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var_buf <= 'b0;
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end
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else if (last_data_d[5]) begin
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var_buf <= accum[ACCUM_WIDTH-1 -: DATA_O_WIDTH];
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end
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end
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end
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end
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end
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@@ -22,7 +22,10 @@
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module tb_var_cal;
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module tb_var_cal;
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localparam DATA_I_WIDTH = 30;
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reg clk = 1'b1;
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reg clk = 1'b1;
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reg clk_init = 1'b1;
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reg rst = 1'b1;
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reg rst = 1'b1;
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reg cal_start = 1'b0;
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reg cal_start = 1'b0;
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@@ -30,13 +33,22 @@ reg cal_auto_en = 1'b0;
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wire cal_busy;
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wire cal_busy;
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reg din_valid = 1'b0;
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reg din_valid = 1'b0;
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reg [29:0] din_real = 'b0;
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reg [29:0] din_file_real = 'b0;
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reg [29:0] din_imag = 'b0;
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reg [29:0] din_file_imag = 'b0;
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wire [DATA_I_WIDTH-1:0] din_real;
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wire [DATA_I_WIDTH-1:0] din_imag;
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assign din_real = din_file_real[29 -: DATA_I_WIDTH];
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assign din_imag = din_file_imag[29 -: DATA_I_WIDTH];
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wire var_valid;
|
wire var_valid;
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wire [31:0] var;
|
wire [31:0] var;
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|
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var_cal u_var_cal
|
var_cal #(
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|
.ACCUM_NUM (16384 ),
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|
.DATA_I_WIDTH (DATA_I_WIDTH ),
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|
.DATA_O_WIDTH (32 )
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|
) u_var_cal
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(
|
(
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.clk (clk ),
|
.clk (clk ),
|
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.rst (rst ),
|
.rst (rst ),
|
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@@ -67,12 +79,16 @@ initial begin
|
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r_file = $fopen("./../../../../../testbenches/singletone.csv","r");
|
r_file = $fopen("./../../../../../testbenches/singletone.csv","r");
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for (i = 0; i <= 32768; i = i + 1) begin
|
for (i = 0; i <= 32768; i = i + 1) begin
|
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@(posedge clk)
|
@(posedge clk)
|
||||||
$fscanf(r_file,"%d,%d",din_real,din_imag);
|
$fscanf(r_file,"%d,%d",din_file_real,din_file_imag);
|
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end
|
end
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$fclose(r_file);
|
$fclose(r_file);
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$stop;
|
$stop;
|
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end
|
end
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||||||
|
|
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always #10 clk = ~clk;
|
always #10 clk_init = ~clk_init;
|
||||||
|
|
||||||
|
always @(posedge clk_init) begin
|
||||||
|
clk <= ~clk;
|
||||||
|
end
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||||||
|
|
||||||
endmodule
|
endmodule
|
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|
|||||||
@@ -59,5 +59,5 @@ set_property -dict {PACKAGE_PIN V23 IOSTANDARD LVCMOS25} [get_ports hop_wor
|
|||||||
set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVCMOS25} [get_ports freq_hop_switch ]
|
set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVCMOS25} [get_ports freq_hop_switch ]
|
||||||
|
|
||||||
# Sync Signal
|
# Sync Signal
|
||||||
# set_property -dict {PACKAGE_PIN AD19 IOSTANDARD LVCMOS25} [get_ports sync_signal_out ] ;# Bank9, not used before
|
set_property -dict {PACKAGE_PIN AD19 IOSTANDARD LVCMOS25} [get_ports sync_signal_out ] ;# Bank9, not used before
|
||||||
# set_property -dict {PACKAGE_PIN AD18 IOSTANDARD LVCMOS25} [get_ports sync_gnd ] ;# Bank9, not used before
|
set_property -dict {PACKAGE_PIN AD18 IOSTANDARD LVCMOS25} [get_ports sync_gnd ] ;# Bank9, not used before
|
||||||
@@ -1,83 +1,83 @@
|
|||||||
MEMORY_INITIALIZATION_RADIX = 10;
|
MEMORY_INITIALIZATION_RADIX = 10;
|
||||||
MEMORY_INITIALIZATION_VECTOR =
|
MEMORY_INITIALIZATION_VECTOR =
|
||||||
1624,
|
2124,
|
||||||
1611,
|
2111,
|
||||||
1598,
|
2098,
|
||||||
1585,
|
2085,
|
||||||
1572,
|
2072,
|
||||||
1559,
|
2059,
|
||||||
1546,
|
2046,
|
||||||
1533,
|
2033,
|
||||||
1520,
|
2020,
|
||||||
1507,
|
2007,
|
||||||
1494,
|
1994,
|
||||||
1481,
|
1981,
|
||||||
1468,
|
1968,
|
||||||
1455,
|
1955,
|
||||||
1442,
|
1942,
|
||||||
1429,
|
1929,
|
||||||
1416,
|
1916,
|
||||||
1403,
|
1903,
|
||||||
1390,
|
1890,
|
||||||
1377,
|
1877,
|
||||||
1364,
|
1864,
|
||||||
1351,
|
1851,
|
||||||
1338,
|
1838,
|
||||||
1325,
|
1825,
|
||||||
1312,
|
1812,
|
||||||
1299,
|
1799,
|
||||||
1286,
|
1786,
|
||||||
1273,
|
1773,
|
||||||
1260,
|
1760,
|
||||||
1247,
|
1747,
|
||||||
1234,
|
1734,
|
||||||
1221,
|
1721,
|
||||||
1208,
|
1708,
|
||||||
1195,
|
1695,
|
||||||
1182,
|
1682,
|
||||||
1169,
|
1669,
|
||||||
1156,
|
1656,
|
||||||
1143,
|
1643,
|
||||||
1130,
|
1630,
|
||||||
1117,
|
1617,
|
||||||
1104,
|
1604,
|
||||||
1091,
|
1591,
|
||||||
1078,
|
1578,
|
||||||
1065,
|
1565,
|
||||||
1052,
|
1552,
|
||||||
1039,
|
1539,
|
||||||
1026,
|
1526,
|
||||||
1013,
|
1513,
|
||||||
1000,
|
1500,
|
||||||
987,
|
1487,
|
||||||
974,
|
1474,
|
||||||
961,
|
1461,
|
||||||
948,
|
1448,
|
||||||
935,
|
1435,
|
||||||
922,
|
1422,
|
||||||
909,
|
1409,
|
||||||
896,
|
1396,
|
||||||
883,
|
1383,
|
||||||
870,
|
1370,
|
||||||
857,
|
1357,
|
||||||
844,
|
1344,
|
||||||
831,
|
1331,
|
||||||
818,
|
1318,
|
||||||
805,
|
1305,
|
||||||
792,
|
1292,
|
||||||
779,
|
1279,
|
||||||
766,
|
1266,
|
||||||
753,
|
1253,
|
||||||
740,
|
1240,
|
||||||
727,
|
1227,
|
||||||
714,
|
1214,
|
||||||
701,
|
1201,
|
||||||
688,
|
1188,
|
||||||
675,
|
1175,
|
||||||
662,
|
1162,
|
||||||
649,
|
1149,
|
||||||
636,
|
1136,
|
||||||
623,
|
1123,
|
||||||
610,
|
1110,
|
||||||
597,
|
1097,
|
||||||
584,
|
1084,
|
||||||
|
|||||||
+1
-1
@@ -57,7 +57,7 @@
|
|||||||
rom_freq_word your_instance_name (
|
rom_freq_word your_instance_name (
|
||||||
.clka(clka), // input wire clka
|
.clka(clka), // input wire clka
|
||||||
.addra(addra), // input wire [6 : 0] addra
|
.addra(addra), // input wire [6 : 0] addra
|
||||||
.douta(douta) // output wire [10 : 0] douta
|
.douta(douta) // output wire [11 : 0] douta
|
||||||
);
|
);
|
||||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||||
|
|
||||||
|
|||||||
+1
-1
@@ -56,7 +56,7 @@ COMPONENT rom_freq_word
|
|||||||
PORT (
|
PORT (
|
||||||
clka : IN STD_LOGIC;
|
clka : IN STD_LOGIC;
|
||||||
addra : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
|
addra : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
|
||||||
douta : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
|
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
|
||||||
);
|
);
|
||||||
END COMPONENT;
|
END COMPONENT;
|
||||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||||
|
|||||||
LFS
BIN
Binary file not shown.
LFS
BIN
Binary file not shown.
+5
-5
@@ -1,10 +1,10 @@
|
|||||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
// --------------------------------------------------------------------------------
|
// --------------------------------------------------------------------------------
|
||||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||||
// Date : Mon May 8 18:56:10 2023
|
// Date : Sun Jul 30 18:06:27 2023
|
||||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||||
// Command : write_verilog -force -mode synth_stub -rename_top rom_freq_word -prefix
|
// Command : write_verilog -force -mode synth_stub
|
||||||
// rom_freq_word_ rom_freq_word_stub.v
|
// /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.v
|
||||||
// Design : rom_freq_word
|
// Design : rom_freq_word
|
||||||
// Purpose : Stub declaration of top-level module interface
|
// Purpose : Stub declaration of top-level module interface
|
||||||
// Device : xc7z100ffg900-2
|
// Device : xc7z100ffg900-2
|
||||||
@@ -15,8 +15,8 @@
|
|||||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||||
(* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *)
|
(* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *)
|
||||||
module rom_freq_word(clka, addra, douta)
|
module rom_freq_word(clka, addra, douta)
|
||||||
/* synthesis syn_black_box black_box_pad_pin="clka,addra[6:0],douta[10:0]" */;
|
/* synthesis syn_black_box black_box_pad_pin="clka,addra[6:0],douta[11:0]" */;
|
||||||
input clka;
|
input clka;
|
||||||
input [6:0]addra;
|
input [6:0]addra;
|
||||||
output [10:0]douta;
|
output [11:0]douta;
|
||||||
endmodule
|
endmodule
|
||||||
|
|||||||
+5
-5
@@ -1,10 +1,10 @@
|
|||||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
-- --------------------------------------------------------------------------------
|
-- --------------------------------------------------------------------------------
|
||||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||||
-- Date : Mon May 8 18:56:10 2023
|
-- Date : Sun Jul 30 18:06:27 2023
|
||||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||||
-- Command : write_vhdl -force -mode synth_stub -rename_top rom_freq_word -prefix
|
-- Command : write_vhdl -force -mode synth_stub
|
||||||
-- rom_freq_word_ rom_freq_word_stub.vhdl
|
-- /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.vhdl
|
||||||
-- Design : rom_freq_word
|
-- Design : rom_freq_word
|
||||||
-- Purpose : Stub declaration of top-level module interface
|
-- Purpose : Stub declaration of top-level module interface
|
||||||
-- Device : xc7z100ffg900-2
|
-- Device : xc7z100ffg900-2
|
||||||
@@ -16,7 +16,7 @@ entity rom_freq_word is
|
|||||||
Port (
|
Port (
|
||||||
clka : in STD_LOGIC;
|
clka : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 6 downto 0 );
|
addra : in STD_LOGIC_VECTOR ( 6 downto 0 );
|
||||||
douta : out STD_LOGIC_VECTOR ( 10 downto 0 )
|
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
|
||||||
);
|
);
|
||||||
|
|
||||||
end rom_freq_word;
|
end rom_freq_word;
|
||||||
@@ -25,7 +25,7 @@ architecture stub of rom_freq_word is
|
|||||||
attribute syn_black_box : boolean;
|
attribute syn_black_box : boolean;
|
||||||
attribute black_box_pad_pin : string;
|
attribute black_box_pad_pin : string;
|
||||||
attribute syn_black_box of stub : architecture is true;
|
attribute syn_black_box of stub : architecture is true;
|
||||||
attribute black_box_pad_pin of stub : architecture is "clka,addra[6:0],douta[10:0]";
|
attribute black_box_pad_pin of stub : architecture is "clka,addra[6:0],douta[11:0]";
|
||||||
attribute x_core_info : string;
|
attribute x_core_info : string;
|
||||||
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_3,Vivado 2019.1.3";
|
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_3,Vivado 2019.1.3";
|
||||||
begin
|
begin
|
||||||
|
|||||||
+9
-9
@@ -65,7 +65,7 @@ input wire clka;
|
|||||||
input wire [6 : 0] addra;
|
input wire [6 : 0] addra;
|
||||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *)
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *)
|
||||||
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
|
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
|
||||||
output wire [10 : 0] douta;
|
output wire [11 : 0] douta;
|
||||||
|
|
||||||
blk_mem_gen_v8_4_3 #(
|
blk_mem_gen_v8_4_3 #(
|
||||||
.C_FAMILY("zynq"),
|
.C_FAMILY("zynq"),
|
||||||
@@ -97,8 +97,8 @@ output wire [10 : 0] douta;
|
|||||||
.C_USE_BYTE_WEA(0),
|
.C_USE_BYTE_WEA(0),
|
||||||
.C_WEA_WIDTH(1),
|
.C_WEA_WIDTH(1),
|
||||||
.C_WRITE_MODE_A("WRITE_FIRST"),
|
.C_WRITE_MODE_A("WRITE_FIRST"),
|
||||||
.C_WRITE_WIDTH_A(11),
|
.C_WRITE_WIDTH_A(12),
|
||||||
.C_READ_WIDTH_A(11),
|
.C_READ_WIDTH_A(12),
|
||||||
.C_WRITE_DEPTH_A(81),
|
.C_WRITE_DEPTH_A(81),
|
||||||
.C_READ_DEPTH_A(81),
|
.C_READ_DEPTH_A(81),
|
||||||
.C_ADDRA_WIDTH(7),
|
.C_ADDRA_WIDTH(7),
|
||||||
@@ -111,8 +111,8 @@ output wire [10 : 0] douta;
|
|||||||
.C_USE_BYTE_WEB(0),
|
.C_USE_BYTE_WEB(0),
|
||||||
.C_WEB_WIDTH(1),
|
.C_WEB_WIDTH(1),
|
||||||
.C_WRITE_MODE_B("WRITE_FIRST"),
|
.C_WRITE_MODE_B("WRITE_FIRST"),
|
||||||
.C_WRITE_WIDTH_B(11),
|
.C_WRITE_WIDTH_B(12),
|
||||||
.C_READ_WIDTH_B(11),
|
.C_READ_WIDTH_B(12),
|
||||||
.C_WRITE_DEPTH_B(81),
|
.C_WRITE_DEPTH_B(81),
|
||||||
.C_READ_DEPTH_B(81),
|
.C_READ_DEPTH_B(81),
|
||||||
.C_ADDRB_WIDTH(7),
|
.C_ADDRB_WIDTH(7),
|
||||||
@@ -142,7 +142,7 @@ output wire [10 : 0] douta;
|
|||||||
.C_DISABLE_WARN_BHV_RANGE(0),
|
.C_DISABLE_WARN_BHV_RANGE(0),
|
||||||
.C_COUNT_36K_BRAM("0"),
|
.C_COUNT_36K_BRAM("0"),
|
||||||
.C_COUNT_18K_BRAM("1"),
|
.C_COUNT_18K_BRAM("1"),
|
||||||
.C_EST_POWER_SUMMARY("Estimated Power for IP : 2.5016 mW")
|
.C_EST_POWER_SUMMARY("Estimated Power for IP : 2.5432 mW")
|
||||||
) inst (
|
) inst (
|
||||||
.clka(clka),
|
.clka(clka),
|
||||||
.rsta(1'D0),
|
.rsta(1'D0),
|
||||||
@@ -150,7 +150,7 @@ output wire [10 : 0] douta;
|
|||||||
.regcea(1'D0),
|
.regcea(1'D0),
|
||||||
.wea(1'B0),
|
.wea(1'B0),
|
||||||
.addra(addra),
|
.addra(addra),
|
||||||
.dina(11'B0),
|
.dina(12'B0),
|
||||||
.douta(douta),
|
.douta(douta),
|
||||||
.clkb(1'D0),
|
.clkb(1'D0),
|
||||||
.rstb(1'D0),
|
.rstb(1'D0),
|
||||||
@@ -158,7 +158,7 @@ output wire [10 : 0] douta;
|
|||||||
.regceb(1'D0),
|
.regceb(1'D0),
|
||||||
.web(1'B0),
|
.web(1'B0),
|
||||||
.addrb(7'B0),
|
.addrb(7'B0),
|
||||||
.dinb(11'B0),
|
.dinb(12'B0),
|
||||||
.doutb(),
|
.doutb(),
|
||||||
.injectsbiterr(1'D0),
|
.injectsbiterr(1'D0),
|
||||||
.injectdbiterr(1'D0),
|
.injectdbiterr(1'D0),
|
||||||
@@ -180,7 +180,7 @@ output wire [10 : 0] douta;
|
|||||||
.s_axi_awburst(2'B0),
|
.s_axi_awburst(2'B0),
|
||||||
.s_axi_awvalid(1'D0),
|
.s_axi_awvalid(1'D0),
|
||||||
.s_axi_awready(),
|
.s_axi_awready(),
|
||||||
.s_axi_wdata(11'B0),
|
.s_axi_wdata(12'B0),
|
||||||
.s_axi_wstrb(1'B0),
|
.s_axi_wstrb(1'B0),
|
||||||
.s_axi_wlast(1'D0),
|
.s_axi_wlast(1'D0),
|
||||||
.s_axi_wvalid(1'D0),
|
.s_axi_wvalid(1'D0),
|
||||||
|
|||||||
+17
-2
@@ -48,7 +48,7 @@
|
|||||||
`timescale 1ns / 1ps
|
`timescale 1ns / 1ps
|
||||||
module vio_RF_control (
|
module vio_RF_control (
|
||||||
clk,
|
clk,
|
||||||
|
probe_in0,
|
||||||
probe_out0,
|
probe_out0,
|
||||||
probe_out1,
|
probe_out1,
|
||||||
probe_out2,
|
probe_out2,
|
||||||
@@ -57,10 +57,18 @@ probe_out4,
|
|||||||
probe_out5,
|
probe_out5,
|
||||||
probe_out6,
|
probe_out6,
|
||||||
probe_out7,
|
probe_out7,
|
||||||
probe_out8
|
probe_out8,
|
||||||
|
probe_out9,
|
||||||
|
probe_out10,
|
||||||
|
probe_out11,
|
||||||
|
probe_out12,
|
||||||
|
probe_out13,
|
||||||
|
probe_out14,
|
||||||
|
probe_out15
|
||||||
);
|
);
|
||||||
|
|
||||||
input clk;
|
input clk;
|
||||||
|
input [11 : 0] probe_in0;
|
||||||
|
|
||||||
output reg [0 : 0] probe_out0 = 'h0 ;
|
output reg [0 : 0] probe_out0 = 'h0 ;
|
||||||
output reg [1 : 0] probe_out1 = 'h0 ;
|
output reg [1 : 0] probe_out1 = 'h0 ;
|
||||||
@@ -71,6 +79,13 @@ output reg [11 : 0] probe_out5 = 'h3E8 ;
|
|||||||
output reg [0 : 0] probe_out6 = 'h0 ;
|
output reg [0 : 0] probe_out6 = 'h0 ;
|
||||||
output reg [0 : 0] probe_out7 = 'h0 ;
|
output reg [0 : 0] probe_out7 = 'h0 ;
|
||||||
output reg [0 : 0] probe_out8 = 'h0 ;
|
output reg [0 : 0] probe_out8 = 'h0 ;
|
||||||
|
output reg [0 : 0] probe_out9 = 'h0 ;
|
||||||
|
output reg [0 : 0] probe_out10 = 'h0 ;
|
||||||
|
output reg [0 : 0] probe_out11 = 'h0 ;
|
||||||
|
output reg [0 : 0] probe_out12 = 'h0 ;
|
||||||
|
output reg [31 : 0] probe_out13 = 'h0002EE00 ;
|
||||||
|
output reg [0 : 0] probe_out14 = 'h0 ;
|
||||||
|
output reg [31 : 0] probe_out15 = 'h0B71B000 ;
|
||||||
|
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|||||||
+18
-10
@@ -55,16 +55,24 @@
|
|||||||
|
|
||||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||||
vio_RF_control your_instance_name (
|
vio_RF_control your_instance_name (
|
||||||
.clk(clk), // input wire clk
|
.clk(clk), // input wire clk
|
||||||
.probe_out0(probe_out0), // output wire [0 : 0] probe_out0
|
.probe_in0(probe_in0), // input wire [11 : 0] probe_in0
|
||||||
.probe_out1(probe_out1), // output wire [1 : 0] probe_out1
|
.probe_out0(probe_out0), // output wire [0 : 0] probe_out0
|
||||||
.probe_out2(probe_out2), // output wire [0 : 0] probe_out2
|
.probe_out1(probe_out1), // output wire [1 : 0] probe_out1
|
||||||
.probe_out3(probe_out3), // output wire [7 : 0] probe_out3
|
.probe_out2(probe_out2), // output wire [0 : 0] probe_out2
|
||||||
.probe_out4(probe_out4), // output wire [7 : 0] probe_out4
|
.probe_out3(probe_out3), // output wire [7 : 0] probe_out3
|
||||||
.probe_out5(probe_out5), // output wire [11 : 0] probe_out5
|
.probe_out4(probe_out4), // output wire [7 : 0] probe_out4
|
||||||
.probe_out6(probe_out6), // output wire [0 : 0] probe_out6
|
.probe_out5(probe_out5), // output wire [11 : 0] probe_out5
|
||||||
.probe_out7(probe_out7), // output wire [0 : 0] probe_out7
|
.probe_out6(probe_out6), // output wire [0 : 0] probe_out6
|
||||||
.probe_out8(probe_out8) // output wire [0 : 0] probe_out8
|
.probe_out7(probe_out7), // output wire [0 : 0] probe_out7
|
||||||
|
.probe_out8(probe_out8), // output wire [0 : 0] probe_out8
|
||||||
|
.probe_out9(probe_out9), // output wire [0 : 0] probe_out9
|
||||||
|
.probe_out10(probe_out10), // output wire [0 : 0] probe_out10
|
||||||
|
.probe_out11(probe_out11), // output wire [0 : 0] probe_out11
|
||||||
|
.probe_out12(probe_out12), // output wire [0 : 0] probe_out12
|
||||||
|
.probe_out13(probe_out13), // output wire [31 : 0] probe_out13
|
||||||
|
.probe_out14(probe_out14), // output wire [0 : 0] probe_out14
|
||||||
|
.probe_out15(probe_out15) // output wire [31 : 0] probe_out15
|
||||||
);
|
);
|
||||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||||
|
|
||||||
|
|||||||
+18
-2
@@ -55,6 +55,7 @@
|
|||||||
COMPONENT vio_RF_control
|
COMPONENT vio_RF_control
|
||||||
PORT (
|
PORT (
|
||||||
clk : IN STD_LOGIC;
|
clk : IN STD_LOGIC;
|
||||||
|
probe_in0 : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
|
||||||
probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||||
probe_out1 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
probe_out1 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||||
probe_out2 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
probe_out2 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||||
@@ -63,7 +64,14 @@ COMPONENT vio_RF_control
|
|||||||
probe_out5 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
|
probe_out5 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
|
||||||
probe_out6 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
probe_out6 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||||
probe_out7 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
probe_out7 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||||
probe_out8 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
probe_out8 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||||
|
probe_out9 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||||
|
probe_out10 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||||
|
probe_out11 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||||
|
probe_out12 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||||
|
probe_out13 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||||
|
probe_out14 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||||
|
probe_out15 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||||
);
|
);
|
||||||
END COMPONENT;
|
END COMPONENT;
|
||||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||||
@@ -75,6 +83,7 @@ END COMPONENT;
|
|||||||
your_instance_name : vio_RF_control
|
your_instance_name : vio_RF_control
|
||||||
PORT MAP (
|
PORT MAP (
|
||||||
clk => clk,
|
clk => clk,
|
||||||
|
probe_in0 => probe_in0,
|
||||||
probe_out0 => probe_out0,
|
probe_out0 => probe_out0,
|
||||||
probe_out1 => probe_out1,
|
probe_out1 => probe_out1,
|
||||||
probe_out2 => probe_out2,
|
probe_out2 => probe_out2,
|
||||||
@@ -83,7 +92,14 @@ your_instance_name : vio_RF_control
|
|||||||
probe_out5 => probe_out5,
|
probe_out5 => probe_out5,
|
||||||
probe_out6 => probe_out6,
|
probe_out6 => probe_out6,
|
||||||
probe_out7 => probe_out7,
|
probe_out7 => probe_out7,
|
||||||
probe_out8 => probe_out8
|
probe_out8 => probe_out8,
|
||||||
|
probe_out9 => probe_out9,
|
||||||
|
probe_out10 => probe_out10,
|
||||||
|
probe_out11 => probe_out11,
|
||||||
|
probe_out12 => probe_out12,
|
||||||
|
probe_out13 => probe_out13,
|
||||||
|
probe_out14 => probe_out14,
|
||||||
|
probe_out15 => probe_out15
|
||||||
);
|
);
|
||||||
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||||
|
|
||||||
|
|||||||
LFS
BIN
Binary file not shown.
BIN
Binary file not shown.
+14
-5
@@ -1,10 +1,10 @@
|
|||||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
// --------------------------------------------------------------------------------
|
// --------------------------------------------------------------------------------
|
||||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||||
// Date : Tue Jun 27 16:05:58 2023
|
// Date : Sun Jul 30 18:20:42 2023
|
||||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||||
// Command : write_verilog -force -mode synth_stub
|
// Command : write_verilog -force -mode synth_stub
|
||||||
// /home/josh/Workspace/datalink_814/phy/dl814_dj_phy_ber/dl814_dj_phy_ber.runs/vio_RF_control_synth_1/vio_RF_control_stub.v
|
// /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control_stub.v
|
||||||
// Design : vio_RF_control
|
// Design : vio_RF_control
|
||||||
// Purpose : Stub declaration of top-level module interface
|
// Purpose : Stub declaration of top-level module interface
|
||||||
// Device : xc7z100ffg900-2
|
// Device : xc7z100ffg900-2
|
||||||
@@ -14,10 +14,12 @@
|
|||||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||||
(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
|
(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
|
||||||
module vio_RF_control(clk, probe_out0, probe_out1, probe_out2,
|
module vio_RF_control(clk, probe_in0, probe_out0, probe_out1,
|
||||||
probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8)
|
probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, probe_out9,
|
||||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[7:0],probe_out4[7:0],probe_out5[11:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0]" */;
|
probe_out10, probe_out11, probe_out12, probe_out13, probe_out14, probe_out15)
|
||||||
|
/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[11:0],probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[7:0],probe_out4[7:0],probe_out5[11:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0],probe_out9[0:0],probe_out10[0:0],probe_out11[0:0],probe_out12[0:0],probe_out13[31:0],probe_out14[0:0],probe_out15[31:0]" */;
|
||||||
input clk;
|
input clk;
|
||||||
|
input [11:0]probe_in0;
|
||||||
output [0:0]probe_out0;
|
output [0:0]probe_out0;
|
||||||
output [1:0]probe_out1;
|
output [1:0]probe_out1;
|
||||||
output [0:0]probe_out2;
|
output [0:0]probe_out2;
|
||||||
@@ -27,4 +29,11 @@ module vio_RF_control(clk, probe_out0, probe_out1, probe_out2,
|
|||||||
output [0:0]probe_out6;
|
output [0:0]probe_out6;
|
||||||
output [0:0]probe_out7;
|
output [0:0]probe_out7;
|
||||||
output [0:0]probe_out8;
|
output [0:0]probe_out8;
|
||||||
|
output [0:0]probe_out9;
|
||||||
|
output [0:0]probe_out10;
|
||||||
|
output [0:0]probe_out11;
|
||||||
|
output [0:0]probe_out12;
|
||||||
|
output [31:0]probe_out13;
|
||||||
|
output [0:0]probe_out14;
|
||||||
|
output [31:0]probe_out15;
|
||||||
endmodule
|
endmodule
|
||||||
|
|||||||
+12
-4
@@ -1,10 +1,10 @@
|
|||||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
-- --------------------------------------------------------------------------------
|
-- --------------------------------------------------------------------------------
|
||||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||||
-- Date : Tue Jun 27 16:05:58 2023
|
-- Date : Sun Jul 30 18:20:42 2023
|
||||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||||
-- Command : write_vhdl -force -mode synth_stub
|
-- Command : write_vhdl -force -mode synth_stub
|
||||||
-- /home/josh/Workspace/datalink_814/phy/dl814_dj_phy_ber/dl814_dj_phy_ber.runs/vio_RF_control_synth_1/vio_RF_control_stub.vhdl
|
-- /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control_stub.vhdl
|
||||||
-- Design : vio_RF_control
|
-- Design : vio_RF_control
|
||||||
-- Purpose : Stub declaration of top-level module interface
|
-- Purpose : Stub declaration of top-level module interface
|
||||||
-- Device : xc7z100ffg900-2
|
-- Device : xc7z100ffg900-2
|
||||||
@@ -15,6 +15,7 @@ use IEEE.STD_LOGIC_1164.ALL;
|
|||||||
entity vio_RF_control is
|
entity vio_RF_control is
|
||||||
Port (
|
Port (
|
||||||
clk : in STD_LOGIC;
|
clk : in STD_LOGIC;
|
||||||
|
probe_in0 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||||
probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
probe_out1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
probe_out1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||||
probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
@@ -23,7 +24,14 @@ entity vio_RF_control is
|
|||||||
probe_out5 : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
probe_out5 : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||||
probe_out6 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
probe_out6 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
probe_out7 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
probe_out7 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
probe_out8 : out STD_LOGIC_VECTOR ( 0 to 0 )
|
probe_out8 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
|
probe_out9 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
|
probe_out10 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
|
probe_out11 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
|
probe_out12 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
|
probe_out13 : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||||
|
probe_out14 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
|
probe_out15 : out STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||||
);
|
);
|
||||||
|
|
||||||
end vio_RF_control;
|
end vio_RF_control;
|
||||||
@@ -32,7 +40,7 @@ architecture stub of vio_RF_control is
|
|||||||
attribute syn_black_box : boolean;
|
attribute syn_black_box : boolean;
|
||||||
attribute black_box_pad_pin : string;
|
attribute black_box_pad_pin : string;
|
||||||
attribute syn_black_box of stub : architecture is true;
|
attribute syn_black_box of stub : architecture is true;
|
||||||
attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[7:0],probe_out4[7:0],probe_out5[11:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0]";
|
attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[11:0],probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[7:0],probe_out4[7:0],probe_out5[11:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0],probe_out9[0:0],probe_out10[0:0],probe_out11[0:0],probe_out12[0:0],probe_out13[31:0],probe_out14[0:0],probe_out15[31:0]";
|
||||||
attribute X_CORE_INFO : string;
|
attribute X_CORE_INFO : string;
|
||||||
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
|
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
|
||||||
begin
|
begin
|
||||||
|
|||||||
@@ -1,83 +1,83 @@
|
|||||||
MEMORY_INITIALIZATION_RADIX = 10;
|
MEMORY_INITIALIZATION_RADIX = 10;
|
||||||
MEMORY_INITIALIZATION_VECTOR =
|
MEMORY_INITIALIZATION_VECTOR =
|
||||||
1624,
|
2124,
|
||||||
1611,
|
2111,
|
||||||
1598,
|
2098,
|
||||||
1585,
|
2085,
|
||||||
1572,
|
2072,
|
||||||
1559,
|
2059,
|
||||||
1546,
|
2046,
|
||||||
1533,
|
2033,
|
||||||
1520,
|
2020,
|
||||||
1507,
|
2007,
|
||||||
1494,
|
1994,
|
||||||
1481,
|
1981,
|
||||||
1468,
|
1968,
|
||||||
1455,
|
1955,
|
||||||
1442,
|
1942,
|
||||||
1429,
|
1929,
|
||||||
1416,
|
1916,
|
||||||
1403,
|
1903,
|
||||||
1390,
|
1890,
|
||||||
1377,
|
1877,
|
||||||
1364,
|
1864,
|
||||||
1351,
|
1851,
|
||||||
1338,
|
1838,
|
||||||
1325,
|
1825,
|
||||||
1312,
|
1812,
|
||||||
1299,
|
1799,
|
||||||
1286,
|
1786,
|
||||||
1273,
|
1773,
|
||||||
1260,
|
1760,
|
||||||
1247,
|
1747,
|
||||||
1234,
|
1734,
|
||||||
1221,
|
1721,
|
||||||
1208,
|
1708,
|
||||||
1195,
|
1695,
|
||||||
1182,
|
1682,
|
||||||
1169,
|
1669,
|
||||||
1156,
|
1656,
|
||||||
1143,
|
1643,
|
||||||
1130,
|
1630,
|
||||||
1117,
|
1617,
|
||||||
1104,
|
1604,
|
||||||
1091,
|
1591,
|
||||||
1078,
|
1578,
|
||||||
1065,
|
1565,
|
||||||
1052,
|
1552,
|
||||||
1039,
|
1539,
|
||||||
1026,
|
1526,
|
||||||
1013,
|
1513,
|
||||||
1000,
|
1500,
|
||||||
987,
|
1487,
|
||||||
974,
|
1474,
|
||||||
961,
|
1461,
|
||||||
948,
|
1448,
|
||||||
935,
|
1435,
|
||||||
922,
|
1422,
|
||||||
909,
|
1409,
|
||||||
896,
|
1396,
|
||||||
883,
|
1383,
|
||||||
870,
|
1370,
|
||||||
857,
|
1357,
|
||||||
844,
|
1344,
|
||||||
831,
|
1331,
|
||||||
818,
|
1318,
|
||||||
805,
|
1305,
|
||||||
792,
|
1292,
|
||||||
779,
|
1279,
|
||||||
766,
|
1266,
|
||||||
753,
|
1253,
|
||||||
740,
|
1240,
|
||||||
727,
|
1227,
|
||||||
714,
|
1214,
|
||||||
701,
|
1201,
|
||||||
688,
|
1188,
|
||||||
675,
|
1175,
|
||||||
662,
|
1162,
|
||||||
649,
|
1149,
|
||||||
636,
|
1136,
|
||||||
623,
|
1123,
|
||||||
610,
|
1110,
|
||||||
597,
|
1097,
|
||||||
584,
|
1084,
|
||||||
|
|||||||
+81
-81
@@ -1,81 +1,81 @@
|
|||||||
11001011000
|
100001001100
|
||||||
11001001011
|
100000111111
|
||||||
11000111110
|
100000110010
|
||||||
11000110001
|
100000100101
|
||||||
11000100100
|
100000011000
|
||||||
11000010111
|
100000001011
|
||||||
11000001010
|
011111111110
|
||||||
10111111101
|
011111110001
|
||||||
10111110000
|
011111100100
|
||||||
10111100011
|
011111010111
|
||||||
10111010110
|
011111001010
|
||||||
10111001001
|
011110111101
|
||||||
10110111100
|
011110110000
|
||||||
10110101111
|
011110100011
|
||||||
10110100010
|
011110010110
|
||||||
10110010101
|
011110001001
|
||||||
10110001000
|
011101111100
|
||||||
10101111011
|
011101101111
|
||||||
10101101110
|
011101100010
|
||||||
10101100001
|
011101010101
|
||||||
10101010100
|
011101001000
|
||||||
10101000111
|
011100111011
|
||||||
10100111010
|
011100101110
|
||||||
10100101101
|
011100100001
|
||||||
10100100000
|
011100010100
|
||||||
10100010011
|
011100000111
|
||||||
10100000110
|
011011111010
|
||||||
10011111001
|
011011101101
|
||||||
10011101100
|
011011100000
|
||||||
10011011111
|
011011010011
|
||||||
10011010010
|
011011000110
|
||||||
10011000101
|
011010111001
|
||||||
10010111000
|
011010101100
|
||||||
10010101011
|
011010011111
|
||||||
10010011110
|
011010010010
|
||||||
10010010001
|
011010000101
|
||||||
10010000100
|
011001111000
|
||||||
10001110111
|
011001101011
|
||||||
10001101010
|
011001011110
|
||||||
10001011101
|
011001010001
|
||||||
10001010000
|
011001000100
|
||||||
10001000011
|
011000110111
|
||||||
10000110110
|
011000101010
|
||||||
10000101001
|
011000011101
|
||||||
10000011100
|
011000010000
|
||||||
10000001111
|
011000000011
|
||||||
10000000010
|
010111110110
|
||||||
01111110101
|
010111101001
|
||||||
01111101000
|
010111011100
|
||||||
01111011011
|
010111001111
|
||||||
01111001110
|
010111000010
|
||||||
01111000001
|
010110110101
|
||||||
01110110100
|
010110101000
|
||||||
01110100111
|
010110011011
|
||||||
01110011010
|
010110001110
|
||||||
01110001101
|
010110000001
|
||||||
01110000000
|
010101110100
|
||||||
01101110011
|
010101100111
|
||||||
01101100110
|
010101011010
|
||||||
01101011001
|
010101001101
|
||||||
01101001100
|
010101000000
|
||||||
01100111111
|
010100110011
|
||||||
01100110010
|
010100100110
|
||||||
01100100101
|
010100011001
|
||||||
01100011000
|
010100001100
|
||||||
01100001011
|
010011111111
|
||||||
01011111110
|
010011110010
|
||||||
01011110001
|
010011100101
|
||||||
01011100100
|
010011011000
|
||||||
01011010111
|
010011001011
|
||||||
01011001010
|
010010111110
|
||||||
01010111101
|
010010110001
|
||||||
01010110000
|
010010100100
|
||||||
01010100011
|
010010010111
|
||||||
01010010110
|
010010001010
|
||||||
01010001001
|
010001111101
|
||||||
01001111100
|
010001110000
|
||||||
01001101111
|
010001100011
|
||||||
01001100010
|
010001010110
|
||||||
01001010101
|
010001001001
|
||||||
01001001000
|
010000111100
|
||||||
|
|||||||
+1
-1
@@ -4,7 +4,7 @@
|
|||||||
# README.txt: Please read the sections below to understand the steps required to
|
# README.txt: Please read the sections below to understand the steps required to
|
||||||
# run the exported script and information about the source files.
|
# run the exported script and information about the source files.
|
||||||
#
|
#
|
||||||
# Generated by export_simulation on Thu May 18 11:49:45 CST 2023
|
# Generated by export_simulation on Sun Jul 30 18:05:42 CST 2023
|
||||||
#
|
#
|
||||||
################################################################################
|
################################################################################
|
||||||
|
|
||||||
|
|||||||
+3
-3
@@ -10,11 +10,11 @@ vmap xpm activehdl/xpm
|
|||||||
vmap blk_mem_gen_v8_4_3 activehdl/blk_mem_gen_v8_4_3
|
vmap blk_mem_gen_v8_4_3 activehdl/blk_mem_gen_v8_4_3
|
||||||
|
|
||||||
vlog -work xil_defaultlib -sv2k12 \
|
vlog -work xil_defaultlib -sv2k12 \
|
||||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||||
|
|
||||||
vcom -work xpm -93 \
|
vcom -work xpm -93 \
|
||||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||||
|
|
||||||
vlog -work blk_mem_gen_v8_4_3 -v2k5 \
|
vlog -work blk_mem_gen_v8_4_3 -v2k5 \
|
||||||
"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
|
"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
|
||||||
|
|||||||
+3
-3
@@ -1,6 +1,6 @@
|
|||||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||||
blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
|
blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
|
||||||
rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v,
|
rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v,
|
||||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||||
|
|||||||
+81
-81
@@ -1,83 +1,83 @@
|
|||||||
MEMORY_INITIALIZATION_RADIX = 10;
|
MEMORY_INITIALIZATION_RADIX = 10;
|
||||||
MEMORY_INITIALIZATION_VECTOR =
|
MEMORY_INITIALIZATION_VECTOR =
|
||||||
1624,
|
2124,
|
||||||
1611,
|
2111,
|
||||||
1598,
|
2098,
|
||||||
1585,
|
2085,
|
||||||
1572,
|
2072,
|
||||||
1559,
|
2059,
|
||||||
1546,
|
2046,
|
||||||
1533,
|
2033,
|
||||||
1520,
|
2020,
|
||||||
1507,
|
2007,
|
||||||
1494,
|
1994,
|
||||||
1481,
|
1981,
|
||||||
1468,
|
1968,
|
||||||
1455,
|
1955,
|
||||||
1442,
|
1942,
|
||||||
1429,
|
1929,
|
||||||
1416,
|
1916,
|
||||||
1403,
|
1903,
|
||||||
1390,
|
1890,
|
||||||
1377,
|
1877,
|
||||||
1364,
|
1864,
|
||||||
1351,
|
1851,
|
||||||
1338,
|
1838,
|
||||||
1325,
|
1825,
|
||||||
1312,
|
1812,
|
||||||
1299,
|
1799,
|
||||||
1286,
|
1786,
|
||||||
1273,
|
1773,
|
||||||
1260,
|
1760,
|
||||||
1247,
|
1747,
|
||||||
1234,
|
1734,
|
||||||
1221,
|
1721,
|
||||||
1208,
|
1708,
|
||||||
1195,
|
1695,
|
||||||
1182,
|
1682,
|
||||||
1169,
|
1669,
|
||||||
1156,
|
1656,
|
||||||
1143,
|
1643,
|
||||||
1130,
|
1630,
|
||||||
1117,
|
1617,
|
||||||
1104,
|
1604,
|
||||||
1091,
|
1591,
|
||||||
1078,
|
1578,
|
||||||
1065,
|
1565,
|
||||||
1052,
|
1552,
|
||||||
1039,
|
1539,
|
||||||
1026,
|
1526,
|
||||||
1013,
|
1513,
|
||||||
1000,
|
1500,
|
||||||
987,
|
1487,
|
||||||
974,
|
1474,
|
||||||
961,
|
1461,
|
||||||
948,
|
1448,
|
||||||
935,
|
1435,
|
||||||
922,
|
1422,
|
||||||
909,
|
1409,
|
||||||
896,
|
1396,
|
||||||
883,
|
1383,
|
||||||
870,
|
1370,
|
||||||
857,
|
1357,
|
||||||
844,
|
1344,
|
||||||
831,
|
1331,
|
||||||
818,
|
1318,
|
||||||
805,
|
1305,
|
||||||
792,
|
1292,
|
||||||
779,
|
1279,
|
||||||
766,
|
1266,
|
||||||
753,
|
1253,
|
||||||
740,
|
1240,
|
||||||
727,
|
1227,
|
||||||
714,
|
1214,
|
||||||
701,
|
1201,
|
||||||
688,
|
1188,
|
||||||
675,
|
1175,
|
||||||
662,
|
1162,
|
||||||
649,
|
1149,
|
||||||
636,
|
1136,
|
||||||
623,
|
1123,
|
||||||
610,
|
1110,
|
||||||
597,
|
1097,
|
||||||
584,
|
1084,
|
||||||
|
|||||||
+81
-81
@@ -1,81 +1,81 @@
|
|||||||
11001011000
|
100001001100
|
||||||
11001001011
|
100000111111
|
||||||
11000111110
|
100000110010
|
||||||
11000110001
|
100000100101
|
||||||
11000100100
|
100000011000
|
||||||
11000010111
|
100000001011
|
||||||
11000001010
|
011111111110
|
||||||
10111111101
|
011111110001
|
||||||
10111110000
|
011111100100
|
||||||
10111100011
|
011111010111
|
||||||
10111010110
|
011111001010
|
||||||
10111001001
|
011110111101
|
||||||
10110111100
|
011110110000
|
||||||
10110101111
|
011110100011
|
||||||
10110100010
|
011110010110
|
||||||
10110010101
|
011110001001
|
||||||
10110001000
|
011101111100
|
||||||
10101111011
|
011101101111
|
||||||
10101101110
|
011101100010
|
||||||
10101100001
|
011101010101
|
||||||
10101010100
|
011101001000
|
||||||
10101000111
|
011100111011
|
||||||
10100111010
|
011100101110
|
||||||
10100101101
|
011100100001
|
||||||
10100100000
|
011100010100
|
||||||
10100010011
|
011100000111
|
||||||
10100000110
|
011011111010
|
||||||
10011111001
|
011011101101
|
||||||
10011101100
|
011011100000
|
||||||
10011011111
|
011011010011
|
||||||
10011010010
|
011011000110
|
||||||
10011000101
|
011010111001
|
||||||
10010111000
|
011010101100
|
||||||
10010101011
|
011010011111
|
||||||
10010011110
|
011010010010
|
||||||
10010010001
|
011010000101
|
||||||
10010000100
|
011001111000
|
||||||
10001110111
|
011001101011
|
||||||
10001101010
|
011001011110
|
||||||
10001011101
|
011001010001
|
||||||
10001010000
|
011001000100
|
||||||
10001000011
|
011000110111
|
||||||
10000110110
|
011000101010
|
||||||
10000101001
|
011000011101
|
||||||
10000011100
|
011000010000
|
||||||
10000001111
|
011000000011
|
||||||
10000000010
|
010111110110
|
||||||
01111110101
|
010111101001
|
||||||
01111101000
|
010111011100
|
||||||
01111011011
|
010111001111
|
||||||
01111001110
|
010111000010
|
||||||
01111000001
|
010110110101
|
||||||
01110110100
|
010110101000
|
||||||
01110100111
|
010110011011
|
||||||
01110011010
|
010110001110
|
||||||
01110001101
|
010110000001
|
||||||
01110000000
|
010101110100
|
||||||
01101110011
|
010101100111
|
||||||
01101100110
|
010101011010
|
||||||
01101011001
|
010101001101
|
||||||
01101001100
|
010101000000
|
||||||
01100111111
|
010100110011
|
||||||
01100110010
|
010100100110
|
||||||
01100100101
|
010100011001
|
||||||
01100011000
|
010100001100
|
||||||
01100001011
|
010011111111
|
||||||
01011111110
|
010011110010
|
||||||
01011110001
|
010011100101
|
||||||
01011100100
|
010011011000
|
||||||
01011010111
|
010011001011
|
||||||
01011001010
|
010010111110
|
||||||
01010111101
|
010010110001
|
||||||
01010110000
|
010010100100
|
||||||
01010100011
|
010010010111
|
||||||
01010010110
|
010010001010
|
||||||
01010001001
|
010001111101
|
||||||
01001111100
|
010001110000
|
||||||
01001101111
|
010001100011
|
||||||
01001100010
|
010001010110
|
||||||
01001010101
|
010001001001
|
||||||
01001001000
|
010000111100
|
||||||
|
|||||||
+1
-1
@@ -9,7 +9,7 @@
|
|||||||
# directory, add the library logical mappings in the simulator setup file, create default
|
# directory, add the library logical mappings in the simulator setup file, create default
|
||||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||||
#
|
#
|
||||||
# Generated by Vivado on Thu May 18 11:49:45 CST 2023
|
# Generated by Vivado on Sun Jul 30 18:05:42 CST 2023
|
||||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||||
#
|
#
|
||||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
|||||||
+1
-1
@@ -4,7 +4,7 @@
|
|||||||
# README.txt: Please read the sections below to understand the steps required to
|
# README.txt: Please read the sections below to understand the steps required to
|
||||||
# run the exported script and information about the source files.
|
# run the exported script and information about the source files.
|
||||||
#
|
#
|
||||||
# Generated by export_simulation on Thu May 18 11:49:45 CST 2023
|
# Generated by export_simulation on Sun Jul 30 18:05:42 CST 2023
|
||||||
#
|
#
|
||||||
################################################################################
|
################################################################################
|
||||||
|
|
||||||
|
|||||||
+3
-3
@@ -1,6 +1,6 @@
|
|||||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||||
blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
|
blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
|
||||||
rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v,
|
rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v,
|
||||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||||
|
|||||||
+81
-81
@@ -1,83 +1,83 @@
|
|||||||
MEMORY_INITIALIZATION_RADIX = 10;
|
MEMORY_INITIALIZATION_RADIX = 10;
|
||||||
MEMORY_INITIALIZATION_VECTOR =
|
MEMORY_INITIALIZATION_VECTOR =
|
||||||
1624,
|
2124,
|
||||||
1611,
|
2111,
|
||||||
1598,
|
2098,
|
||||||
1585,
|
2085,
|
||||||
1572,
|
2072,
|
||||||
1559,
|
2059,
|
||||||
1546,
|
2046,
|
||||||
1533,
|
2033,
|
||||||
1520,
|
2020,
|
||||||
1507,
|
2007,
|
||||||
1494,
|
1994,
|
||||||
1481,
|
1981,
|
||||||
1468,
|
1968,
|
||||||
1455,
|
1955,
|
||||||
1442,
|
1942,
|
||||||
1429,
|
1929,
|
||||||
1416,
|
1916,
|
||||||
1403,
|
1903,
|
||||||
1390,
|
1890,
|
||||||
1377,
|
1877,
|
||||||
1364,
|
1864,
|
||||||
1351,
|
1851,
|
||||||
1338,
|
1838,
|
||||||
1325,
|
1825,
|
||||||
1312,
|
1812,
|
||||||
1299,
|
1799,
|
||||||
1286,
|
1786,
|
||||||
1273,
|
1773,
|
||||||
1260,
|
1760,
|
||||||
1247,
|
1747,
|
||||||
1234,
|
1734,
|
||||||
1221,
|
1721,
|
||||||
1208,
|
1708,
|
||||||
1195,
|
1695,
|
||||||
1182,
|
1682,
|
||||||
1169,
|
1669,
|
||||||
1156,
|
1656,
|
||||||
1143,
|
1643,
|
||||||
1130,
|
1630,
|
||||||
1117,
|
1617,
|
||||||
1104,
|
1604,
|
||||||
1091,
|
1591,
|
||||||
1078,
|
1578,
|
||||||
1065,
|
1565,
|
||||||
1052,
|
1552,
|
||||||
1039,
|
1539,
|
||||||
1026,
|
1526,
|
||||||
1013,
|
1513,
|
||||||
1000,
|
1500,
|
||||||
987,
|
1487,
|
||||||
974,
|
1474,
|
||||||
961,
|
1461,
|
||||||
948,
|
1448,
|
||||||
935,
|
1435,
|
||||||
922,
|
1422,
|
||||||
909,
|
1409,
|
||||||
896,
|
1396,
|
||||||
883,
|
1383,
|
||||||
870,
|
1370,
|
||||||
857,
|
1357,
|
||||||
844,
|
1344,
|
||||||
831,
|
1331,
|
||||||
818,
|
1318,
|
||||||
805,
|
1305,
|
||||||
792,
|
1292,
|
||||||
779,
|
1279,
|
||||||
766,
|
1266,
|
||||||
753,
|
1253,
|
||||||
740,
|
1240,
|
||||||
727,
|
1227,
|
||||||
714,
|
1214,
|
||||||
701,
|
1201,
|
||||||
688,
|
1188,
|
||||||
675,
|
1175,
|
||||||
662,
|
1162,
|
||||||
649,
|
1149,
|
||||||
636,
|
1136,
|
||||||
623,
|
1123,
|
||||||
610,
|
1110,
|
||||||
597,
|
1097,
|
||||||
584,
|
1084,
|
||||||
|
|||||||
+81
-81
@@ -1,81 +1,81 @@
|
|||||||
11001011000
|
100001001100
|
||||||
11001001011
|
100000111111
|
||||||
11000111110
|
100000110010
|
||||||
11000110001
|
100000100101
|
||||||
11000100100
|
100000011000
|
||||||
11000010111
|
100000001011
|
||||||
11000001010
|
011111111110
|
||||||
10111111101
|
011111110001
|
||||||
10111110000
|
011111100100
|
||||||
10111100011
|
011111010111
|
||||||
10111010110
|
011111001010
|
||||||
10111001001
|
011110111101
|
||||||
10110111100
|
011110110000
|
||||||
10110101111
|
011110100011
|
||||||
10110100010
|
011110010110
|
||||||
10110010101
|
011110001001
|
||||||
10110001000
|
011101111100
|
||||||
10101111011
|
011101101111
|
||||||
10101101110
|
011101100010
|
||||||
10101100001
|
011101010101
|
||||||
10101010100
|
011101001000
|
||||||
10101000111
|
011100111011
|
||||||
10100111010
|
011100101110
|
||||||
10100101101
|
011100100001
|
||||||
10100100000
|
011100010100
|
||||||
10100010011
|
011100000111
|
||||||
10100000110
|
011011111010
|
||||||
10011111001
|
011011101101
|
||||||
10011101100
|
011011100000
|
||||||
10011011111
|
011011010011
|
||||||
10011010010
|
011011000110
|
||||||
10011000101
|
011010111001
|
||||||
10010111000
|
011010101100
|
||||||
10010101011
|
011010011111
|
||||||
10010011110
|
011010010010
|
||||||
10010010001
|
011010000101
|
||||||
10010000100
|
011001111000
|
||||||
10001110111
|
011001101011
|
||||||
10001101010
|
011001011110
|
||||||
10001011101
|
011001010001
|
||||||
10001010000
|
011001000100
|
||||||
10001000011
|
011000110111
|
||||||
10000110110
|
011000101010
|
||||||
10000101001
|
011000011101
|
||||||
10000011100
|
011000010000
|
||||||
10000001111
|
011000000011
|
||||||
10000000010
|
010111110110
|
||||||
01111110101
|
010111101001
|
||||||
01111101000
|
010111011100
|
||||||
01111011011
|
010111001111
|
||||||
01111001110
|
010111000010
|
||||||
01111000001
|
010110110101
|
||||||
01110110100
|
010110101000
|
||||||
01110100111
|
010110011011
|
||||||
01110011010
|
010110001110
|
||||||
01110001101
|
010110000001
|
||||||
01110000000
|
010101110100
|
||||||
01101110011
|
010101100111
|
||||||
01101100110
|
010101011010
|
||||||
01101011001
|
010101001101
|
||||||
01101001100
|
010101000000
|
||||||
01100111111
|
010100110011
|
||||||
01100110010
|
010100100110
|
||||||
01100100101
|
010100011001
|
||||||
01100011000
|
010100001100
|
||||||
01100001011
|
010011111111
|
||||||
01011111110
|
010011110010
|
||||||
01011110001
|
010011100101
|
||||||
01011100100
|
010011011000
|
||||||
01011010111
|
010011001011
|
||||||
01011001010
|
010010111110
|
||||||
01010111101
|
010010110001
|
||||||
01010110000
|
010010100100
|
||||||
01010100011
|
010010010111
|
||||||
01010010110
|
010010001010
|
||||||
01010001001
|
010001111101
|
||||||
01001111100
|
010001110000
|
||||||
01001101111
|
010001100011
|
||||||
01001100010
|
010001010110
|
||||||
01001010101
|
010001001001
|
||||||
01001001000
|
010000111100
|
||||||
|
|||||||
+1
-1
@@ -9,7 +9,7 @@
|
|||||||
# directory, add the library logical mappings in the simulator setup file, create default
|
# directory, add the library logical mappings in the simulator setup file, create default
|
||||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||||
#
|
#
|
||||||
# Generated by Vivado on Thu May 18 11:49:45 CST 2023
|
# Generated by Vivado on Sun Jul 30 18:05:42 CST 2023
|
||||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||||
#
|
#
|
||||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
|||||||
+3
-3
@@ -1,9 +1,9 @@
|
|||||||
-makelib ies_lib/xil_defaultlib -sv \
|
-makelib ies_lib/xil_defaultlib -sv \
|
||||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||||
-endlib
|
-endlib
|
||||||
-makelib ies_lib/xpm \
|
-makelib ies_lib/xpm \
|
||||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||||
-endlib
|
-endlib
|
||||||
-makelib ies_lib/blk_mem_gen_v8_4_3 \
|
-makelib ies_lib/blk_mem_gen_v8_4_3 \
|
||||||
"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
|
"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
|
||||||
|
|||||||
+1
-1
@@ -4,7 +4,7 @@
|
|||||||
# README.txt: Please read the sections below to understand the steps required to
|
# README.txt: Please read the sections below to understand the steps required to
|
||||||
# run the exported script and information about the source files.
|
# run the exported script and information about the source files.
|
||||||
#
|
#
|
||||||
# Generated by export_simulation on Thu May 18 11:49:45 CST 2023
|
# Generated by export_simulation on Sun Jul 30 18:05:42 CST 2023
|
||||||
#
|
#
|
||||||
################################################################################
|
################################################################################
|
||||||
|
|
||||||
|
|||||||
+81
-81
@@ -1,83 +1,83 @@
|
|||||||
MEMORY_INITIALIZATION_RADIX = 10;
|
MEMORY_INITIALIZATION_RADIX = 10;
|
||||||
MEMORY_INITIALIZATION_VECTOR =
|
MEMORY_INITIALIZATION_VECTOR =
|
||||||
1624,
|
2124,
|
||||||
1611,
|
2111,
|
||||||
1598,
|
2098,
|
||||||
1585,
|
2085,
|
||||||
1572,
|
2072,
|
||||||
1559,
|
2059,
|
||||||
1546,
|
2046,
|
||||||
1533,
|
2033,
|
||||||
1520,
|
2020,
|
||||||
1507,
|
2007,
|
||||||
1494,
|
1994,
|
||||||
1481,
|
1981,
|
||||||
1468,
|
1968,
|
||||||
1455,
|
1955,
|
||||||
1442,
|
1942,
|
||||||
1429,
|
1929,
|
||||||
1416,
|
1916,
|
||||||
1403,
|
1903,
|
||||||
1390,
|
1890,
|
||||||
1377,
|
1877,
|
||||||
1364,
|
1864,
|
||||||
1351,
|
1851,
|
||||||
1338,
|
1838,
|
||||||
1325,
|
1825,
|
||||||
1312,
|
1812,
|
||||||
1299,
|
1799,
|
||||||
1286,
|
1786,
|
||||||
1273,
|
1773,
|
||||||
1260,
|
1760,
|
||||||
1247,
|
1747,
|
||||||
1234,
|
1734,
|
||||||
1221,
|
1721,
|
||||||
1208,
|
1708,
|
||||||
1195,
|
1695,
|
||||||
1182,
|
1682,
|
||||||
1169,
|
1669,
|
||||||
1156,
|
1656,
|
||||||
1143,
|
1643,
|
||||||
1130,
|
1630,
|
||||||
1117,
|
1617,
|
||||||
1104,
|
1604,
|
||||||
1091,
|
1591,
|
||||||
1078,
|
1578,
|
||||||
1065,
|
1565,
|
||||||
1052,
|
1552,
|
||||||
1039,
|
1539,
|
||||||
1026,
|
1526,
|
||||||
1013,
|
1513,
|
||||||
1000,
|
1500,
|
||||||
987,
|
1487,
|
||||||
974,
|
1474,
|
||||||
961,
|
1461,
|
||||||
948,
|
1448,
|
||||||
935,
|
1435,
|
||||||
922,
|
1422,
|
||||||
909,
|
1409,
|
||||||
896,
|
1396,
|
||||||
883,
|
1383,
|
||||||
870,
|
1370,
|
||||||
857,
|
1357,
|
||||||
844,
|
1344,
|
||||||
831,
|
1331,
|
||||||
818,
|
1318,
|
||||||
805,
|
1305,
|
||||||
792,
|
1292,
|
||||||
779,
|
1279,
|
||||||
766,
|
1266,
|
||||||
753,
|
1253,
|
||||||
740,
|
1240,
|
||||||
727,
|
1227,
|
||||||
714,
|
1214,
|
||||||
701,
|
1201,
|
||||||
688,
|
1188,
|
||||||
675,
|
1175,
|
||||||
662,
|
1162,
|
||||||
649,
|
1149,
|
||||||
636,
|
1136,
|
||||||
623,
|
1123,
|
||||||
610,
|
1110,
|
||||||
597,
|
1097,
|
||||||
584,
|
1084,
|
||||||
|
|||||||
+81
-81
@@ -1,81 +1,81 @@
|
|||||||
11001011000
|
100001001100
|
||||||
11001001011
|
100000111111
|
||||||
11000111110
|
100000110010
|
||||||
11000110001
|
100000100101
|
||||||
11000100100
|
100000011000
|
||||||
11000010111
|
100000001011
|
||||||
11000001010
|
011111111110
|
||||||
10111111101
|
011111110001
|
||||||
10111110000
|
011111100100
|
||||||
10111100011
|
011111010111
|
||||||
10111010110
|
011111001010
|
||||||
10111001001
|
011110111101
|
||||||
10110111100
|
011110110000
|
||||||
10110101111
|
011110100011
|
||||||
10110100010
|
011110010110
|
||||||
10110010101
|
011110001001
|
||||||
10110001000
|
011101111100
|
||||||
10101111011
|
011101101111
|
||||||
10101101110
|
011101100010
|
||||||
10101100001
|
011101010101
|
||||||
10101010100
|
011101001000
|
||||||
10101000111
|
011100111011
|
||||||
10100111010
|
011100101110
|
||||||
10100101101
|
011100100001
|
||||||
10100100000
|
011100010100
|
||||||
10100010011
|
011100000111
|
||||||
10100000110
|
011011111010
|
||||||
10011111001
|
011011101101
|
||||||
10011101100
|
011011100000
|
||||||
10011011111
|
011011010011
|
||||||
10011010010
|
011011000110
|
||||||
10011000101
|
011010111001
|
||||||
10010111000
|
011010101100
|
||||||
10010101011
|
011010011111
|
||||||
10010011110
|
011010010010
|
||||||
10010010001
|
011010000101
|
||||||
10010000100
|
011001111000
|
||||||
10001110111
|
011001101011
|
||||||
10001101010
|
011001011110
|
||||||
10001011101
|
011001010001
|
||||||
10001010000
|
011001000100
|
||||||
10001000011
|
011000110111
|
||||||
10000110110
|
011000101010
|
||||||
10000101001
|
011000011101
|
||||||
10000011100
|
011000010000
|
||||||
10000001111
|
011000000011
|
||||||
10000000010
|
010111110110
|
||||||
01111110101
|
010111101001
|
||||||
01111101000
|
010111011100
|
||||||
01111011011
|
010111001111
|
||||||
01111001110
|
010111000010
|
||||||
01111000001
|
010110110101
|
||||||
01110110100
|
010110101000
|
||||||
01110100111
|
010110011011
|
||||||
01110011010
|
010110001110
|
||||||
01110001101
|
010110000001
|
||||||
01110000000
|
010101110100
|
||||||
01101110011
|
010101100111
|
||||||
01101100110
|
010101011010
|
||||||
01101011001
|
010101001101
|
||||||
01101001100
|
010101000000
|
||||||
01100111111
|
010100110011
|
||||||
01100110010
|
010100100110
|
||||||
01100100101
|
010100011001
|
||||||
01100011000
|
010100001100
|
||||||
01100001011
|
010011111111
|
||||||
01011111110
|
010011110010
|
||||||
01011110001
|
010011100101
|
||||||
01011100100
|
010011011000
|
||||||
01011010111
|
010011001011
|
||||||
01011001010
|
010010111110
|
||||||
01010111101
|
010010110001
|
||||||
01010110000
|
010010100100
|
||||||
01010100011
|
010010010111
|
||||||
01010010110
|
010010001010
|
||||||
01010001001
|
010001111101
|
||||||
01001111100
|
010001110000
|
||||||
01001101111
|
010001100011
|
||||||
01001100010
|
010001010110
|
||||||
01001010101
|
010001001001
|
||||||
01001001000
|
010000111100
|
||||||
|
|||||||
+1
-1
@@ -9,7 +9,7 @@
|
|||||||
# directory, add the library logical mappings in the simulator setup file, create default
|
# directory, add the library logical mappings in the simulator setup file, create default
|
||||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||||
#
|
#
|
||||||
# Generated by Vivado on Thu May 18 11:49:45 CST 2023
|
# Generated by Vivado on Sun Jul 30 18:05:42 CST 2023
|
||||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||||
#
|
#
|
||||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
|||||||
+1
-1
@@ -4,7 +4,7 @@
|
|||||||
# README.txt: Please read the sections below to understand the steps required to
|
# README.txt: Please read the sections below to understand the steps required to
|
||||||
# run the exported script and information about the source files.
|
# run the exported script and information about the source files.
|
||||||
#
|
#
|
||||||
# Generated by export_simulation on Thu May 18 11:49:45 CST 2023
|
# Generated by export_simulation on Sun Jul 30 18:05:42 CST 2023
|
||||||
#
|
#
|
||||||
################################################################################
|
################################################################################
|
||||||
|
|
||||||
|
|||||||
+3
-3
@@ -10,11 +10,11 @@ vmap xpm questa_lib/msim/xpm
|
|||||||
vmap blk_mem_gen_v8_4_3 questa_lib/msim/blk_mem_gen_v8_4_3
|
vmap blk_mem_gen_v8_4_3 questa_lib/msim/blk_mem_gen_v8_4_3
|
||||||
|
|
||||||
vlog -work xil_defaultlib -64 -sv \
|
vlog -work xil_defaultlib -64 -sv \
|
||||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||||
|
|
||||||
vcom -work xpm -64 -93 \
|
vcom -work xpm -64 -93 \
|
||||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||||
|
|
||||||
vlog -work blk_mem_gen_v8_4_3 -64 \
|
vlog -work blk_mem_gen_v8_4_3 -64 \
|
||||||
"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
|
"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
|
||||||
|
|||||||
+3
-3
@@ -1,6 +1,6 @@
|
|||||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||||
blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
|
blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
|
||||||
rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v,
|
rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v,
|
||||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||||
|
|||||||
+81
-81
@@ -1,83 +1,83 @@
|
|||||||
MEMORY_INITIALIZATION_RADIX = 10;
|
MEMORY_INITIALIZATION_RADIX = 10;
|
||||||
MEMORY_INITIALIZATION_VECTOR =
|
MEMORY_INITIALIZATION_VECTOR =
|
||||||
1624,
|
2124,
|
||||||
1611,
|
2111,
|
||||||
1598,
|
2098,
|
||||||
1585,
|
2085,
|
||||||
1572,
|
2072,
|
||||||
1559,
|
2059,
|
||||||
1546,
|
2046,
|
||||||
1533,
|
2033,
|
||||||
1520,
|
2020,
|
||||||
1507,
|
2007,
|
||||||
1494,
|
1994,
|
||||||
1481,
|
1981,
|
||||||
1468,
|
1968,
|
||||||
1455,
|
1955,
|
||||||
1442,
|
1942,
|
||||||
1429,
|
1929,
|
||||||
1416,
|
1916,
|
||||||
1403,
|
1903,
|
||||||
1390,
|
1890,
|
||||||
1377,
|
1877,
|
||||||
1364,
|
1864,
|
||||||
1351,
|
1851,
|
||||||
1338,
|
1838,
|
||||||
1325,
|
1825,
|
||||||
1312,
|
1812,
|
||||||
1299,
|
1799,
|
||||||
1286,
|
1786,
|
||||||
1273,
|
1773,
|
||||||
1260,
|
1760,
|
||||||
1247,
|
1747,
|
||||||
1234,
|
1734,
|
||||||
1221,
|
1721,
|
||||||
1208,
|
1708,
|
||||||
1195,
|
1695,
|
||||||
1182,
|
1682,
|
||||||
1169,
|
1669,
|
||||||
1156,
|
1656,
|
||||||
1143,
|
1643,
|
||||||
1130,
|
1630,
|
||||||
1117,
|
1617,
|
||||||
1104,
|
1604,
|
||||||
1091,
|
1591,
|
||||||
1078,
|
1578,
|
||||||
1065,
|
1565,
|
||||||
1052,
|
1552,
|
||||||
1039,
|
1539,
|
||||||
1026,
|
1526,
|
||||||
1013,
|
1513,
|
||||||
1000,
|
1500,
|
||||||
987,
|
1487,
|
||||||
974,
|
1474,
|
||||||
961,
|
1461,
|
||||||
948,
|
1448,
|
||||||
935,
|
1435,
|
||||||
922,
|
1422,
|
||||||
909,
|
1409,
|
||||||
896,
|
1396,
|
||||||
883,
|
1383,
|
||||||
870,
|
1370,
|
||||||
857,
|
1357,
|
||||||
844,
|
1344,
|
||||||
831,
|
1331,
|
||||||
818,
|
1318,
|
||||||
805,
|
1305,
|
||||||
792,
|
1292,
|
||||||
779,
|
1279,
|
||||||
766,
|
1266,
|
||||||
753,
|
1253,
|
||||||
740,
|
1240,
|
||||||
727,
|
1227,
|
||||||
714,
|
1214,
|
||||||
701,
|
1201,
|
||||||
688,
|
1188,
|
||||||
675,
|
1175,
|
||||||
662,
|
1162,
|
||||||
649,
|
1149,
|
||||||
636,
|
1136,
|
||||||
623,
|
1123,
|
||||||
610,
|
1110,
|
||||||
597,
|
1097,
|
||||||
584,
|
1084,
|
||||||
|
|||||||
+81
-81
@@ -1,81 +1,81 @@
|
|||||||
11001011000
|
100001001100
|
||||||
11001001011
|
100000111111
|
||||||
11000111110
|
100000110010
|
||||||
11000110001
|
100000100101
|
||||||
11000100100
|
100000011000
|
||||||
11000010111
|
100000001011
|
||||||
11000001010
|
011111111110
|
||||||
10111111101
|
011111110001
|
||||||
10111110000
|
011111100100
|
||||||
10111100011
|
011111010111
|
||||||
10111010110
|
011111001010
|
||||||
10111001001
|
011110111101
|
||||||
10110111100
|
011110110000
|
||||||
10110101111
|
011110100011
|
||||||
10110100010
|
011110010110
|
||||||
10110010101
|
011110001001
|
||||||
10110001000
|
011101111100
|
||||||
10101111011
|
011101101111
|
||||||
10101101110
|
011101100010
|
||||||
10101100001
|
011101010101
|
||||||
10101010100
|
011101001000
|
||||||
10101000111
|
011100111011
|
||||||
10100111010
|
011100101110
|
||||||
10100101101
|
011100100001
|
||||||
10100100000
|
011100010100
|
||||||
10100010011
|
011100000111
|
||||||
10100000110
|
011011111010
|
||||||
10011111001
|
011011101101
|
||||||
10011101100
|
011011100000
|
||||||
10011011111
|
011011010011
|
||||||
10011010010
|
011011000110
|
||||||
10011000101
|
011010111001
|
||||||
10010111000
|
011010101100
|
||||||
10010101011
|
011010011111
|
||||||
10010011110
|
011010010010
|
||||||
10010010001
|
011010000101
|
||||||
10010000100
|
011001111000
|
||||||
10001110111
|
011001101011
|
||||||
10001101010
|
011001011110
|
||||||
10001011101
|
011001010001
|
||||||
10001010000
|
011001000100
|
||||||
10001000011
|
011000110111
|
||||||
10000110110
|
011000101010
|
||||||
10000101001
|
011000011101
|
||||||
10000011100
|
011000010000
|
||||||
10000001111
|
011000000011
|
||||||
10000000010
|
010111110110
|
||||||
01111110101
|
010111101001
|
||||||
01111101000
|
010111011100
|
||||||
01111011011
|
010111001111
|
||||||
01111001110
|
010111000010
|
||||||
01111000001
|
010110110101
|
||||||
01110110100
|
010110101000
|
||||||
01110100111
|
010110011011
|
||||||
01110011010
|
010110001110
|
||||||
01110001101
|
010110000001
|
||||||
01110000000
|
010101110100
|
||||||
01101110011
|
010101100111
|
||||||
01101100110
|
010101011010
|
||||||
01101011001
|
010101001101
|
||||||
01101001100
|
010101000000
|
||||||
01100111111
|
010100110011
|
||||||
01100110010
|
010100100110
|
||||||
01100100101
|
010100011001
|
||||||
01100011000
|
010100001100
|
||||||
01100001011
|
010011111111
|
||||||
01011111110
|
010011110010
|
||||||
01011110001
|
010011100101
|
||||||
01011100100
|
010011011000
|
||||||
01011010111
|
010011001011
|
||||||
01011001010
|
010010111110
|
||||||
01010111101
|
010010110001
|
||||||
01010110000
|
010010100100
|
||||||
01010100011
|
010010010111
|
||||||
01010010110
|
010010001010
|
||||||
01010001001
|
010001111101
|
||||||
01001111100
|
010001110000
|
||||||
01001101111
|
010001100011
|
||||||
01001100010
|
010001010110
|
||||||
01001010101
|
010001001001
|
||||||
01001001000
|
010000111100
|
||||||
|
|||||||
+1
-1
@@ -9,7 +9,7 @@
|
|||||||
# directory, add the library logical mappings in the simulator setup file, create default
|
# directory, add the library logical mappings in the simulator setup file, create default
|
||||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||||
#
|
#
|
||||||
# Generated by Vivado on Thu May 18 11:49:45 CST 2023
|
# Generated by Vivado on Sun Jul 30 18:05:42 CST 2023
|
||||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||||
#
|
#
|
||||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
|||||||
+1
-1
@@ -4,7 +4,7 @@
|
|||||||
# README.txt: Please read the sections below to understand the steps required to
|
# README.txt: Please read the sections below to understand the steps required to
|
||||||
# run the exported script and information about the source files.
|
# run the exported script and information about the source files.
|
||||||
#
|
#
|
||||||
# Generated by export_simulation on Thu May 18 11:49:45 CST 2023
|
# Generated by export_simulation on Sun Jul 30 18:05:42 CST 2023
|
||||||
#
|
#
|
||||||
################################################################################
|
################################################################################
|
||||||
|
|
||||||
|
|||||||
+3
-3
@@ -10,11 +10,11 @@ vmap xpm riviera/xpm
|
|||||||
vmap blk_mem_gen_v8_4_3 riviera/blk_mem_gen_v8_4_3
|
vmap blk_mem_gen_v8_4_3 riviera/blk_mem_gen_v8_4_3
|
||||||
|
|
||||||
vlog -work xil_defaultlib -sv2k12 \
|
vlog -work xil_defaultlib -sv2k12 \
|
||||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||||
|
|
||||||
vcom -work xpm -93 \
|
vcom -work xpm -93 \
|
||||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||||
|
|
||||||
vlog -work blk_mem_gen_v8_4_3 -v2k5 \
|
vlog -work blk_mem_gen_v8_4_3 -v2k5 \
|
||||||
"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
|
"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
|
||||||
|
|||||||
+3
-3
@@ -1,6 +1,6 @@
|
|||||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||||
blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
|
blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
|
||||||
rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v,
|
rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v,
|
||||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||||
|
|||||||
+81
-81
@@ -1,83 +1,83 @@
|
|||||||
MEMORY_INITIALIZATION_RADIX = 10;
|
MEMORY_INITIALIZATION_RADIX = 10;
|
||||||
MEMORY_INITIALIZATION_VECTOR =
|
MEMORY_INITIALIZATION_VECTOR =
|
||||||
1624,
|
2124,
|
||||||
1611,
|
2111,
|
||||||
1598,
|
2098,
|
||||||
1585,
|
2085,
|
||||||
1572,
|
2072,
|
||||||
1559,
|
2059,
|
||||||
1546,
|
2046,
|
||||||
1533,
|
2033,
|
||||||
1520,
|
2020,
|
||||||
1507,
|
2007,
|
||||||
1494,
|
1994,
|
||||||
1481,
|
1981,
|
||||||
1468,
|
1968,
|
||||||
1455,
|
1955,
|
||||||
1442,
|
1942,
|
||||||
1429,
|
1929,
|
||||||
1416,
|
1916,
|
||||||
1403,
|
1903,
|
||||||
1390,
|
1890,
|
||||||
1377,
|
1877,
|
||||||
1364,
|
1864,
|
||||||
1351,
|
1851,
|
||||||
1338,
|
1838,
|
||||||
1325,
|
1825,
|
||||||
1312,
|
1812,
|
||||||
1299,
|
1799,
|
||||||
1286,
|
1786,
|
||||||
1273,
|
1773,
|
||||||
1260,
|
1760,
|
||||||
1247,
|
1747,
|
||||||
1234,
|
1734,
|
||||||
1221,
|
1721,
|
||||||
1208,
|
1708,
|
||||||
1195,
|
1695,
|
||||||
1182,
|
1682,
|
||||||
1169,
|
1669,
|
||||||
1156,
|
1656,
|
||||||
1143,
|
1643,
|
||||||
1130,
|
1630,
|
||||||
1117,
|
1617,
|
||||||
1104,
|
1604,
|
||||||
1091,
|
1591,
|
||||||
1078,
|
1578,
|
||||||
1065,
|
1565,
|
||||||
1052,
|
1552,
|
||||||
1039,
|
1539,
|
||||||
1026,
|
1526,
|
||||||
1013,
|
1513,
|
||||||
1000,
|
1500,
|
||||||
987,
|
1487,
|
||||||
974,
|
1474,
|
||||||
961,
|
1461,
|
||||||
948,
|
1448,
|
||||||
935,
|
1435,
|
||||||
922,
|
1422,
|
||||||
909,
|
1409,
|
||||||
896,
|
1396,
|
||||||
883,
|
1383,
|
||||||
870,
|
1370,
|
||||||
857,
|
1357,
|
||||||
844,
|
1344,
|
||||||
831,
|
1331,
|
||||||
818,
|
1318,
|
||||||
805,
|
1305,
|
||||||
792,
|
1292,
|
||||||
779,
|
1279,
|
||||||
766,
|
1266,
|
||||||
753,
|
1253,
|
||||||
740,
|
1240,
|
||||||
727,
|
1227,
|
||||||
714,
|
1214,
|
||||||
701,
|
1201,
|
||||||
688,
|
1188,
|
||||||
675,
|
1175,
|
||||||
662,
|
1162,
|
||||||
649,
|
1149,
|
||||||
636,
|
1136,
|
||||||
623,
|
1123,
|
||||||
610,
|
1110,
|
||||||
597,
|
1097,
|
||||||
584,
|
1084,
|
||||||
|
|||||||
+81
-81
@@ -1,81 +1,81 @@
|
|||||||
11001011000
|
100001001100
|
||||||
11001001011
|
100000111111
|
||||||
11000111110
|
100000110010
|
||||||
11000110001
|
100000100101
|
||||||
11000100100
|
100000011000
|
||||||
11000010111
|
100000001011
|
||||||
11000001010
|
011111111110
|
||||||
10111111101
|
011111110001
|
||||||
10111110000
|
011111100100
|
||||||
10111100011
|
011111010111
|
||||||
10111010110
|
011111001010
|
||||||
10111001001
|
011110111101
|
||||||
10110111100
|
011110110000
|
||||||
10110101111
|
011110100011
|
||||||
10110100010
|
011110010110
|
||||||
10110010101
|
011110001001
|
||||||
10110001000
|
011101111100
|
||||||
10101111011
|
011101101111
|
||||||
10101101110
|
011101100010
|
||||||
10101100001
|
011101010101
|
||||||
10101010100
|
011101001000
|
||||||
10101000111
|
011100111011
|
||||||
10100111010
|
011100101110
|
||||||
10100101101
|
011100100001
|
||||||
10100100000
|
011100010100
|
||||||
10100010011
|
011100000111
|
||||||
10100000110
|
011011111010
|
||||||
10011111001
|
011011101101
|
||||||
10011101100
|
011011100000
|
||||||
10011011111
|
011011010011
|
||||||
10011010010
|
011011000110
|
||||||
10011000101
|
011010111001
|
||||||
10010111000
|
011010101100
|
||||||
10010101011
|
011010011111
|
||||||
10010011110
|
011010010010
|
||||||
10010010001
|
011010000101
|
||||||
10010000100
|
011001111000
|
||||||
10001110111
|
011001101011
|
||||||
10001101010
|
011001011110
|
||||||
10001011101
|
011001010001
|
||||||
10001010000
|
011001000100
|
||||||
10001000011
|
011000110111
|
||||||
10000110110
|
011000101010
|
||||||
10000101001
|
011000011101
|
||||||
10000011100
|
011000010000
|
||||||
10000001111
|
011000000011
|
||||||
10000000010
|
010111110110
|
||||||
01111110101
|
010111101001
|
||||||
01111101000
|
010111011100
|
||||||
01111011011
|
010111001111
|
||||||
01111001110
|
010111000010
|
||||||
01111000001
|
010110110101
|
||||||
01110110100
|
010110101000
|
||||||
01110100111
|
010110011011
|
||||||
01110011010
|
010110001110
|
||||||
01110001101
|
010110000001
|
||||||
01110000000
|
010101110100
|
||||||
01101110011
|
010101100111
|
||||||
01101100110
|
010101011010
|
||||||
01101011001
|
010101001101
|
||||||
01101001100
|
010101000000
|
||||||
01100111111
|
010100110011
|
||||||
01100110010
|
010100100110
|
||||||
01100100101
|
010100011001
|
||||||
01100011000
|
010100001100
|
||||||
01100001011
|
010011111111
|
||||||
01011111110
|
010011110010
|
||||||
01011110001
|
010011100101
|
||||||
01011100100
|
010011011000
|
||||||
01011010111
|
010011001011
|
||||||
01011001010
|
010010111110
|
||||||
01010111101
|
010010110001
|
||||||
01010110000
|
010010100100
|
||||||
01010100011
|
010010010111
|
||||||
01010010110
|
010010001010
|
||||||
01010001001
|
010001111101
|
||||||
01001111100
|
010001110000
|
||||||
01001101111
|
010001100011
|
||||||
01001100010
|
010001010110
|
||||||
01001010101
|
010001001001
|
||||||
01001001000
|
010000111100
|
||||||
|
|||||||
+1
-1
@@ -9,7 +9,7 @@
|
|||||||
# directory, add the library logical mappings in the simulator setup file, create default
|
# directory, add the library logical mappings in the simulator setup file, create default
|
||||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||||
#
|
#
|
||||||
# Generated by Vivado on Thu May 18 11:49:45 CST 2023
|
# Generated by Vivado on Sun Jul 30 18:05:42 CST 2023
|
||||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||||
#
|
#
|
||||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
|||||||
+1
-1
@@ -4,7 +4,7 @@
|
|||||||
# README.txt: Please read the sections below to understand the steps required to
|
# README.txt: Please read the sections below to understand the steps required to
|
||||||
# run the exported script and information about the source files.
|
# run the exported script and information about the source files.
|
||||||
#
|
#
|
||||||
# Generated by export_simulation on Thu May 18 11:49:45 CST 2023
|
# Generated by export_simulation on Sun Jul 30 18:05:42 CST 2023
|
||||||
#
|
#
|
||||||
################################################################################
|
################################################################################
|
||||||
|
|
||||||
|
|||||||
+81
-81
@@ -1,83 +1,83 @@
|
|||||||
MEMORY_INITIALIZATION_RADIX = 10;
|
MEMORY_INITIALIZATION_RADIX = 10;
|
||||||
MEMORY_INITIALIZATION_VECTOR =
|
MEMORY_INITIALIZATION_VECTOR =
|
||||||
1624,
|
2124,
|
||||||
1611,
|
2111,
|
||||||
1598,
|
2098,
|
||||||
1585,
|
2085,
|
||||||
1572,
|
2072,
|
||||||
1559,
|
2059,
|
||||||
1546,
|
2046,
|
||||||
1533,
|
2033,
|
||||||
1520,
|
2020,
|
||||||
1507,
|
2007,
|
||||||
1494,
|
1994,
|
||||||
1481,
|
1981,
|
||||||
1468,
|
1968,
|
||||||
1455,
|
1955,
|
||||||
1442,
|
1942,
|
||||||
1429,
|
1929,
|
||||||
1416,
|
1916,
|
||||||
1403,
|
1903,
|
||||||
1390,
|
1890,
|
||||||
1377,
|
1877,
|
||||||
1364,
|
1864,
|
||||||
1351,
|
1851,
|
||||||
1338,
|
1838,
|
||||||
1325,
|
1825,
|
||||||
1312,
|
1812,
|
||||||
1299,
|
1799,
|
||||||
1286,
|
1786,
|
||||||
1273,
|
1773,
|
||||||
1260,
|
1760,
|
||||||
1247,
|
1747,
|
||||||
1234,
|
1734,
|
||||||
1221,
|
1721,
|
||||||
1208,
|
1708,
|
||||||
1195,
|
1695,
|
||||||
1182,
|
1682,
|
||||||
1169,
|
1669,
|
||||||
1156,
|
1656,
|
||||||
1143,
|
1643,
|
||||||
1130,
|
1630,
|
||||||
1117,
|
1617,
|
||||||
1104,
|
1604,
|
||||||
1091,
|
1591,
|
||||||
1078,
|
1578,
|
||||||
1065,
|
1565,
|
||||||
1052,
|
1552,
|
||||||
1039,
|
1539,
|
||||||
1026,
|
1526,
|
||||||
1013,
|
1513,
|
||||||
1000,
|
1500,
|
||||||
987,
|
1487,
|
||||||
974,
|
1474,
|
||||||
961,
|
1461,
|
||||||
948,
|
1448,
|
||||||
935,
|
1435,
|
||||||
922,
|
1422,
|
||||||
909,
|
1409,
|
||||||
896,
|
1396,
|
||||||
883,
|
1383,
|
||||||
870,
|
1370,
|
||||||
857,
|
1357,
|
||||||
844,
|
1344,
|
||||||
831,
|
1331,
|
||||||
818,
|
1318,
|
||||||
805,
|
1305,
|
||||||
792,
|
1292,
|
||||||
779,
|
1279,
|
||||||
766,
|
1266,
|
||||||
753,
|
1253,
|
||||||
740,
|
1240,
|
||||||
727,
|
1227,
|
||||||
714,
|
1214,
|
||||||
701,
|
1201,
|
||||||
688,
|
1188,
|
||||||
675,
|
1175,
|
||||||
662,
|
1162,
|
||||||
649,
|
1149,
|
||||||
636,
|
1136,
|
||||||
623,
|
1123,
|
||||||
610,
|
1110,
|
||||||
597,
|
1097,
|
||||||
584,
|
1084,
|
||||||
|
|||||||
+81
-81
@@ -1,81 +1,81 @@
|
|||||||
11001011000
|
100001001100
|
||||||
11001001011
|
100000111111
|
||||||
11000111110
|
100000110010
|
||||||
11000110001
|
100000100101
|
||||||
11000100100
|
100000011000
|
||||||
11000010111
|
100000001011
|
||||||
11000001010
|
011111111110
|
||||||
10111111101
|
011111110001
|
||||||
10111110000
|
011111100100
|
||||||
10111100011
|
011111010111
|
||||||
10111010110
|
011111001010
|
||||||
10111001001
|
011110111101
|
||||||
10110111100
|
011110110000
|
||||||
10110101111
|
011110100011
|
||||||
10110100010
|
011110010110
|
||||||
10110010101
|
011110001001
|
||||||
10110001000
|
011101111100
|
||||||
10101111011
|
011101101111
|
||||||
10101101110
|
011101100010
|
||||||
10101100001
|
011101010101
|
||||||
10101010100
|
011101001000
|
||||||
10101000111
|
011100111011
|
||||||
10100111010
|
011100101110
|
||||||
10100101101
|
011100100001
|
||||||
10100100000
|
011100010100
|
||||||
10100010011
|
011100000111
|
||||||
10100000110
|
011011111010
|
||||||
10011111001
|
011011101101
|
||||||
10011101100
|
011011100000
|
||||||
10011011111
|
011011010011
|
||||||
10011010010
|
011011000110
|
||||||
10011000101
|
011010111001
|
||||||
10010111000
|
011010101100
|
||||||
10010101011
|
011010011111
|
||||||
10010011110
|
011010010010
|
||||||
10010010001
|
011010000101
|
||||||
10010000100
|
011001111000
|
||||||
10001110111
|
011001101011
|
||||||
10001101010
|
011001011110
|
||||||
10001011101
|
011001010001
|
||||||
10001010000
|
011001000100
|
||||||
10001000011
|
011000110111
|
||||||
10000110110
|
011000101010
|
||||||
10000101001
|
011000011101
|
||||||
10000011100
|
011000010000
|
||||||
10000001111
|
011000000011
|
||||||
10000000010
|
010111110110
|
||||||
01111110101
|
010111101001
|
||||||
01111101000
|
010111011100
|
||||||
01111011011
|
010111001111
|
||||||
01111001110
|
010111000010
|
||||||
01111000001
|
010110110101
|
||||||
01110110100
|
010110101000
|
||||||
01110100111
|
010110011011
|
||||||
01110011010
|
010110001110
|
||||||
01110001101
|
010110000001
|
||||||
01110000000
|
010101110100
|
||||||
01101110011
|
010101100111
|
||||||
01101100110
|
010101011010
|
||||||
01101011001
|
010101001101
|
||||||
01101001100
|
010101000000
|
||||||
01100111111
|
010100110011
|
||||||
01100110010
|
010100100110
|
||||||
01100100101
|
010100011001
|
||||||
01100011000
|
010100001100
|
||||||
01100001011
|
010011111111
|
||||||
01011111110
|
010011110010
|
||||||
01011110001
|
010011100101
|
||||||
01011100100
|
010011011000
|
||||||
01011010111
|
010011001011
|
||||||
01011001010
|
010010111110
|
||||||
01010111101
|
010010110001
|
||||||
01010110000
|
010010100100
|
||||||
01010100011
|
010010010111
|
||||||
01010010110
|
010010001010
|
||||||
01010001001
|
010001111101
|
||||||
01001111100
|
010001110000
|
||||||
01001101111
|
010001100011
|
||||||
01001100010
|
010001010110
|
||||||
01001010101
|
010001001001
|
||||||
01001001000
|
010000111100
|
||||||
|
|||||||
+1
-1
@@ -9,7 +9,7 @@
|
|||||||
# directory, add the library logical mappings in the simulator setup file, create default
|
# directory, add the library logical mappings in the simulator setup file, create default
|
||||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||||
#
|
#
|
||||||
# Generated by Vivado on Thu May 18 11:49:45 CST 2023
|
# Generated by Vivado on Sun Jul 30 18:05:42 CST 2023
|
||||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||||
#
|
#
|
||||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
|||||||
+1
-1
@@ -4,7 +4,7 @@
|
|||||||
# README.txt: Please read the sections below to understand the steps required to
|
# README.txt: Please read the sections below to understand the steps required to
|
||||||
# run the exported script and information about the source files.
|
# run the exported script and information about the source files.
|
||||||
#
|
#
|
||||||
# Generated by export_simulation on Thu May 18 11:49:45 CST 2023
|
# Generated by export_simulation on Sun Jul 30 18:05:42 CST 2023
|
||||||
#
|
#
|
||||||
################################################################################
|
################################################################################
|
||||||
|
|
||||||
|
|||||||
+3
-3
@@ -1,6 +1,6 @@
|
|||||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||||
blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
|
blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
|
||||||
rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v,
|
rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v,
|
||||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||||
|
|||||||
+81
-81
@@ -1,83 +1,83 @@
|
|||||||
MEMORY_INITIALIZATION_RADIX = 10;
|
MEMORY_INITIALIZATION_RADIX = 10;
|
||||||
MEMORY_INITIALIZATION_VECTOR =
|
MEMORY_INITIALIZATION_VECTOR =
|
||||||
1624,
|
2124,
|
||||||
1611,
|
2111,
|
||||||
1598,
|
2098,
|
||||||
1585,
|
2085,
|
||||||
1572,
|
2072,
|
||||||
1559,
|
2059,
|
||||||
1546,
|
2046,
|
||||||
1533,
|
2033,
|
||||||
1520,
|
2020,
|
||||||
1507,
|
2007,
|
||||||
1494,
|
1994,
|
||||||
1481,
|
1981,
|
||||||
1468,
|
1968,
|
||||||
1455,
|
1955,
|
||||||
1442,
|
1942,
|
||||||
1429,
|
1929,
|
||||||
1416,
|
1916,
|
||||||
1403,
|
1903,
|
||||||
1390,
|
1890,
|
||||||
1377,
|
1877,
|
||||||
1364,
|
1864,
|
||||||
1351,
|
1851,
|
||||||
1338,
|
1838,
|
||||||
1325,
|
1825,
|
||||||
1312,
|
1812,
|
||||||
1299,
|
1799,
|
||||||
1286,
|
1786,
|
||||||
1273,
|
1773,
|
||||||
1260,
|
1760,
|
||||||
1247,
|
1747,
|
||||||
1234,
|
1734,
|
||||||
1221,
|
1721,
|
||||||
1208,
|
1708,
|
||||||
1195,
|
1695,
|
||||||
1182,
|
1682,
|
||||||
1169,
|
1669,
|
||||||
1156,
|
1656,
|
||||||
1143,
|
1643,
|
||||||
1130,
|
1630,
|
||||||
1117,
|
1617,
|
||||||
1104,
|
1604,
|
||||||
1091,
|
1591,
|
||||||
1078,
|
1578,
|
||||||
1065,
|
1565,
|
||||||
1052,
|
1552,
|
||||||
1039,
|
1539,
|
||||||
1026,
|
1526,
|
||||||
1013,
|
1513,
|
||||||
1000,
|
1500,
|
||||||
987,
|
1487,
|
||||||
974,
|
1474,
|
||||||
961,
|
1461,
|
||||||
948,
|
1448,
|
||||||
935,
|
1435,
|
||||||
922,
|
1422,
|
||||||
909,
|
1409,
|
||||||
896,
|
1396,
|
||||||
883,
|
1383,
|
||||||
870,
|
1370,
|
||||||
857,
|
1357,
|
||||||
844,
|
1344,
|
||||||
831,
|
1331,
|
||||||
818,
|
1318,
|
||||||
805,
|
1305,
|
||||||
792,
|
1292,
|
||||||
779,
|
1279,
|
||||||
766,
|
1266,
|
||||||
753,
|
1253,
|
||||||
740,
|
1240,
|
||||||
727,
|
1227,
|
||||||
714,
|
1214,
|
||||||
701,
|
1201,
|
||||||
688,
|
1188,
|
||||||
675,
|
1175,
|
||||||
662,
|
1162,
|
||||||
649,
|
1149,
|
||||||
636,
|
1136,
|
||||||
623,
|
1123,
|
||||||
610,
|
1110,
|
||||||
597,
|
1097,
|
||||||
584,
|
1084,
|
||||||
|
|||||||
+81
-81
@@ -1,81 +1,81 @@
|
|||||||
11001011000
|
100001001100
|
||||||
11001001011
|
100000111111
|
||||||
11000111110
|
100000110010
|
||||||
11000110001
|
100000100101
|
||||||
11000100100
|
100000011000
|
||||||
11000010111
|
100000001011
|
||||||
11000001010
|
011111111110
|
||||||
10111111101
|
011111110001
|
||||||
10111110000
|
011111100100
|
||||||
10111100011
|
011111010111
|
||||||
10111010110
|
011111001010
|
||||||
10111001001
|
011110111101
|
||||||
10110111100
|
011110110000
|
||||||
10110101111
|
011110100011
|
||||||
10110100010
|
011110010110
|
||||||
10110010101
|
011110001001
|
||||||
10110001000
|
011101111100
|
||||||
10101111011
|
011101101111
|
||||||
10101101110
|
011101100010
|
||||||
10101100001
|
011101010101
|
||||||
10101010100
|
011101001000
|
||||||
10101000111
|
011100111011
|
||||||
10100111010
|
011100101110
|
||||||
10100101101
|
011100100001
|
||||||
10100100000
|
011100010100
|
||||||
10100010011
|
011100000111
|
||||||
10100000110
|
011011111010
|
||||||
10011111001
|
011011101101
|
||||||
10011101100
|
011011100000
|
||||||
10011011111
|
011011010011
|
||||||
10011010010
|
011011000110
|
||||||
10011000101
|
011010111001
|
||||||
10010111000
|
011010101100
|
||||||
10010101011
|
011010011111
|
||||||
10010011110
|
011010010010
|
||||||
10010010001
|
011010000101
|
||||||
10010000100
|
011001111000
|
||||||
10001110111
|
011001101011
|
||||||
10001101010
|
011001011110
|
||||||
10001011101
|
011001010001
|
||||||
10001010000
|
011001000100
|
||||||
10001000011
|
011000110111
|
||||||
10000110110
|
011000101010
|
||||||
10000101001
|
011000011101
|
||||||
10000011100
|
011000010000
|
||||||
10000001111
|
011000000011
|
||||||
10000000010
|
010111110110
|
||||||
01111110101
|
010111101001
|
||||||
01111101000
|
010111011100
|
||||||
01111011011
|
010111001111
|
||||||
01111001110
|
010111000010
|
||||||
01111000001
|
010110110101
|
||||||
01110110100
|
010110101000
|
||||||
01110100111
|
010110011011
|
||||||
01110011010
|
010110001110
|
||||||
01110001101
|
010110000001
|
||||||
01110000000
|
010101110100
|
||||||
01101110011
|
010101100111
|
||||||
01101100110
|
010101011010
|
||||||
01101011001
|
010101001101
|
||||||
01101001100
|
010101000000
|
||||||
01100111111
|
010100110011
|
||||||
01100110010
|
010100100110
|
||||||
01100100101
|
010100011001
|
||||||
01100011000
|
010100001100
|
||||||
01100001011
|
010011111111
|
||||||
01011111110
|
010011110010
|
||||||
01011110001
|
010011100101
|
||||||
01011100100
|
010011011000
|
||||||
01011010111
|
010011001011
|
||||||
01011001010
|
010010111110
|
||||||
01010111101
|
010010110001
|
||||||
01010110000
|
010010100100
|
||||||
01010100011
|
010010010111
|
||||||
01010010110
|
010010001010
|
||||||
01010001001
|
010001111101
|
||||||
01001111100
|
010001110000
|
||||||
01001101111
|
010001100011
|
||||||
01001100010
|
010001010110
|
||||||
01001010101
|
010001001001
|
||||||
01001001000
|
010000111100
|
||||||
|
|||||||
+1
-1
@@ -9,7 +9,7 @@
|
|||||||
# directory, add the library logical mappings in the simulator setup file, create default
|
# directory, add the library logical mappings in the simulator setup file, create default
|
||||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||||
#
|
#
|
||||||
# Generated by Vivado on Thu May 18 11:49:45 CST 2023
|
# Generated by Vivado on Sun Jul 30 18:05:42 CST 2023
|
||||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||||
#
|
#
|
||||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
|||||||
+3
-3
@@ -1,9 +1,9 @@
|
|||||||
-makelib xcelium_lib/xil_defaultlib -sv \
|
-makelib xcelium_lib/xil_defaultlib -sv \
|
||||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||||
-endlib
|
-endlib
|
||||||
-makelib xcelium_lib/xpm \
|
-makelib xcelium_lib/xpm \
|
||||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||||
-endlib
|
-endlib
|
||||||
-makelib xcelium_lib/blk_mem_gen_v8_4_3 \
|
-makelib xcelium_lib/blk_mem_gen_v8_4_3 \
|
||||||
"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
|
"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
|
||||||
|
|||||||
+1
-1
@@ -4,7 +4,7 @@
|
|||||||
# README.txt: Please read the sections below to understand the steps required to
|
# README.txt: Please read the sections below to understand the steps required to
|
||||||
# run the exported script and information about the source files.
|
# run the exported script and information about the source files.
|
||||||
#
|
#
|
||||||
# Generated by export_simulation on Thu May 18 11:49:45 CST 2023
|
# Generated by export_simulation on Sun Jul 30 18:05:42 CST 2023
|
||||||
#
|
#
|
||||||
################################################################################
|
################################################################################
|
||||||
|
|
||||||
|
|||||||
+81
-81
@@ -1,83 +1,83 @@
|
|||||||
MEMORY_INITIALIZATION_RADIX = 10;
|
MEMORY_INITIALIZATION_RADIX = 10;
|
||||||
MEMORY_INITIALIZATION_VECTOR =
|
MEMORY_INITIALIZATION_VECTOR =
|
||||||
1624,
|
2124,
|
||||||
1611,
|
2111,
|
||||||
1598,
|
2098,
|
||||||
1585,
|
2085,
|
||||||
1572,
|
2072,
|
||||||
1559,
|
2059,
|
||||||
1546,
|
2046,
|
||||||
1533,
|
2033,
|
||||||
1520,
|
2020,
|
||||||
1507,
|
2007,
|
||||||
1494,
|
1994,
|
||||||
1481,
|
1981,
|
||||||
1468,
|
1968,
|
||||||
1455,
|
1955,
|
||||||
1442,
|
1942,
|
||||||
1429,
|
1929,
|
||||||
1416,
|
1916,
|
||||||
1403,
|
1903,
|
||||||
1390,
|
1890,
|
||||||
1377,
|
1877,
|
||||||
1364,
|
1864,
|
||||||
1351,
|
1851,
|
||||||
1338,
|
1838,
|
||||||
1325,
|
1825,
|
||||||
1312,
|
1812,
|
||||||
1299,
|
1799,
|
||||||
1286,
|
1786,
|
||||||
1273,
|
1773,
|
||||||
1260,
|
1760,
|
||||||
1247,
|
1747,
|
||||||
1234,
|
1734,
|
||||||
1221,
|
1721,
|
||||||
1208,
|
1708,
|
||||||
1195,
|
1695,
|
||||||
1182,
|
1682,
|
||||||
1169,
|
1669,
|
||||||
1156,
|
1656,
|
||||||
1143,
|
1643,
|
||||||
1130,
|
1630,
|
||||||
1117,
|
1617,
|
||||||
1104,
|
1604,
|
||||||
1091,
|
1591,
|
||||||
1078,
|
1578,
|
||||||
1065,
|
1565,
|
||||||
1052,
|
1552,
|
||||||
1039,
|
1539,
|
||||||
1026,
|
1526,
|
||||||
1013,
|
1513,
|
||||||
1000,
|
1500,
|
||||||
987,
|
1487,
|
||||||
974,
|
1474,
|
||||||
961,
|
1461,
|
||||||
948,
|
1448,
|
||||||
935,
|
1435,
|
||||||
922,
|
1422,
|
||||||
909,
|
1409,
|
||||||
896,
|
1396,
|
||||||
883,
|
1383,
|
||||||
870,
|
1370,
|
||||||
857,
|
1357,
|
||||||
844,
|
1344,
|
||||||
831,
|
1331,
|
||||||
818,
|
1318,
|
||||||
805,
|
1305,
|
||||||
792,
|
1292,
|
||||||
779,
|
1279,
|
||||||
766,
|
1266,
|
||||||
753,
|
1253,
|
||||||
740,
|
1240,
|
||||||
727,
|
1227,
|
||||||
714,
|
1214,
|
||||||
701,
|
1201,
|
||||||
688,
|
1188,
|
||||||
675,
|
1175,
|
||||||
662,
|
1162,
|
||||||
649,
|
1149,
|
||||||
636,
|
1136,
|
||||||
623,
|
1123,
|
||||||
610,
|
1110,
|
||||||
597,
|
1097,
|
||||||
584,
|
1084,
|
||||||
|
|||||||
+81
-81
@@ -1,81 +1,81 @@
|
|||||||
11001011000
|
100001001100
|
||||||
11001001011
|
100000111111
|
||||||
11000111110
|
100000110010
|
||||||
11000110001
|
100000100101
|
||||||
11000100100
|
100000011000
|
||||||
11000010111
|
100000001011
|
||||||
11000001010
|
011111111110
|
||||||
10111111101
|
011111110001
|
||||||
10111110000
|
011111100100
|
||||||
10111100011
|
011111010111
|
||||||
10111010110
|
011111001010
|
||||||
10111001001
|
011110111101
|
||||||
10110111100
|
011110110000
|
||||||
10110101111
|
011110100011
|
||||||
10110100010
|
011110010110
|
||||||
10110010101
|
011110001001
|
||||||
10110001000
|
011101111100
|
||||||
10101111011
|
011101101111
|
||||||
10101101110
|
011101100010
|
||||||
10101100001
|
011101010101
|
||||||
10101010100
|
011101001000
|
||||||
10101000111
|
011100111011
|
||||||
10100111010
|
011100101110
|
||||||
10100101101
|
011100100001
|
||||||
10100100000
|
011100010100
|
||||||
10100010011
|
011100000111
|
||||||
10100000110
|
011011111010
|
||||||
10011111001
|
011011101101
|
||||||
10011101100
|
011011100000
|
||||||
10011011111
|
011011010011
|
||||||
10011010010
|
011011000110
|
||||||
10011000101
|
011010111001
|
||||||
10010111000
|
011010101100
|
||||||
10010101011
|
011010011111
|
||||||
10010011110
|
011010010010
|
||||||
10010010001
|
011010000101
|
||||||
10010000100
|
011001111000
|
||||||
10001110111
|
011001101011
|
||||||
10001101010
|
011001011110
|
||||||
10001011101
|
011001010001
|
||||||
10001010000
|
011001000100
|
||||||
10001000011
|
011000110111
|
||||||
10000110110
|
011000101010
|
||||||
10000101001
|
011000011101
|
||||||
10000011100
|
011000010000
|
||||||
10000001111
|
011000000011
|
||||||
10000000010
|
010111110110
|
||||||
01111110101
|
010111101001
|
||||||
01111101000
|
010111011100
|
||||||
01111011011
|
010111001111
|
||||||
01111001110
|
010111000010
|
||||||
01111000001
|
010110110101
|
||||||
01110110100
|
010110101000
|
||||||
01110100111
|
010110011011
|
||||||
01110011010
|
010110001110
|
||||||
01110001101
|
010110000001
|
||||||
01110000000
|
010101110100
|
||||||
01101110011
|
010101100111
|
||||||
01101100110
|
010101011010
|
||||||
01101011001
|
010101001101
|
||||||
01101001100
|
010101000000
|
||||||
01100111111
|
010100110011
|
||||||
01100110010
|
010100100110
|
||||||
01100100101
|
010100011001
|
||||||
01100011000
|
010100001100
|
||||||
01100001011
|
010011111111
|
||||||
01011111110
|
010011110010
|
||||||
01011110001
|
010011100101
|
||||||
01011100100
|
010011011000
|
||||||
01011010111
|
010011001011
|
||||||
01011001010
|
010010111110
|
||||||
01010111101
|
010010110001
|
||||||
01010110000
|
010010100100
|
||||||
01010100011
|
010010010111
|
||||||
01010010110
|
010010001010
|
||||||
01010001001
|
010001111101
|
||||||
01001111100
|
010001110000
|
||||||
01001101111
|
010001100011
|
||||||
01001100010
|
010001010110
|
||||||
01001010101
|
010001001001
|
||||||
01001001000
|
010000111100
|
||||||
|
|||||||
+3
-3
@@ -9,7 +9,7 @@
|
|||||||
# directory, add the library logical mappings in the simulator setup file, create default
|
# directory, add the library logical mappings in the simulator setup file, create default
|
||||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||||
#
|
#
|
||||||
# Generated by Vivado on Thu May 18 11:49:45 CST 2023
|
# Generated by Vivado on Sun Jul 30 18:05:42 CST 2023
|
||||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||||
#
|
#
|
||||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
@@ -22,7 +22,7 @@
|
|||||||
#*********************************************************************************************************
|
#*********************************************************************************************************
|
||||||
|
|
||||||
# Command line options
|
# Command line options
|
||||||
xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0
|
xv_boost_lib_path=/home/josh/Software/Xilinx/Vivado/2019.1/tps/boost_1_64_0
|
||||||
xvlog_opts="--relax"
|
xvlog_opts="--relax"
|
||||||
|
|
||||||
|
|
||||||
@@ -92,7 +92,7 @@ setup()
|
|||||||
copy_setup_file()
|
copy_setup_file()
|
||||||
{
|
{
|
||||||
file="xsim.ini"
|
file="xsim.ini"
|
||||||
lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim"
|
lib_map_path="/home/josh/Software/Xilinx/Vivado/2019.1/data/xsim"
|
||||||
if [[ ($1 != "") ]]; then
|
if [[ ($1 != "") ]]; then
|
||||||
lib_map_path="$1"
|
lib_map_path="$1"
|
||||||
fi
|
fi
|
||||||
|
|||||||
+1
-1
@@ -4,7 +4,7 @@
|
|||||||
# README.txt: Please read the sections below to understand the steps required to
|
# README.txt: Please read the sections below to understand the steps required to
|
||||||
# run the exported script and information about the source files.
|
# run the exported script and information about the source files.
|
||||||
#
|
#
|
||||||
# Generated by export_simulation on Mon Jul 03 19:45:40 CST 2023
|
# Generated by export_simulation on Sun Jul 30 18:20:24 CST 2023
|
||||||
#
|
#
|
||||||
################################################################################
|
################################################################################
|
||||||
|
|
||||||
|
|||||||
+1
-1
@@ -9,7 +9,7 @@
|
|||||||
# directory, add the library logical mappings in the simulator setup file, create default
|
# directory, add the library logical mappings in the simulator setup file, create default
|
||||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||||
#
|
#
|
||||||
# Generated by Vivado on Mon Jul 03 19:45:40 CST 2023
|
# Generated by Vivado on Sun Jul 30 18:20:24 CST 2023
|
||||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||||
#
|
#
|
||||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
|||||||
+1
-1
@@ -4,7 +4,7 @@
|
|||||||
# README.txt: Please read the sections below to understand the steps required to
|
# README.txt: Please read the sections below to understand the steps required to
|
||||||
# run the exported script and information about the source files.
|
# run the exported script and information about the source files.
|
||||||
#
|
#
|
||||||
# Generated by export_simulation on Mon Jul 03 19:45:40 CST 2023
|
# Generated by export_simulation on Sun Jul 30 18:20:24 CST 2023
|
||||||
#
|
#
|
||||||
################################################################################
|
################################################################################
|
||||||
|
|
||||||
|
|||||||
+1
-1
@@ -9,7 +9,7 @@
|
|||||||
# directory, add the library logical mappings in the simulator setup file, create default
|
# directory, add the library logical mappings in the simulator setup file, create default
|
||||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||||
#
|
#
|
||||||
# Generated by Vivado on Mon Jul 03 19:45:40 CST 2023
|
# Generated by Vivado on Sun Jul 30 18:20:24 CST 2023
|
||||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||||
#
|
#
|
||||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
|||||||
+1
-1
@@ -4,7 +4,7 @@
|
|||||||
# README.txt: Please read the sections below to understand the steps required to
|
# README.txt: Please read the sections below to understand the steps required to
|
||||||
# run the exported script and information about the source files.
|
# run the exported script and information about the source files.
|
||||||
#
|
#
|
||||||
# Generated by export_simulation on Mon Jul 03 19:45:40 CST 2023
|
# Generated by export_simulation on Sun Jul 30 18:20:24 CST 2023
|
||||||
#
|
#
|
||||||
################################################################################
|
################################################################################
|
||||||
|
|
||||||
|
|||||||
+1
-1
@@ -9,7 +9,7 @@
|
|||||||
# directory, add the library logical mappings in the simulator setup file, create default
|
# directory, add the library logical mappings in the simulator setup file, create default
|
||||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||||
#
|
#
|
||||||
# Generated by Vivado on Mon Jul 03 19:45:40 CST 2023
|
# Generated by Vivado on Sun Jul 30 18:20:24 CST 2023
|
||||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||||
#
|
#
|
||||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
|||||||
+1
-1
@@ -4,7 +4,7 @@
|
|||||||
# README.txt: Please read the sections below to understand the steps required to
|
# README.txt: Please read the sections below to understand the steps required to
|
||||||
# run the exported script and information about the source files.
|
# run the exported script and information about the source files.
|
||||||
#
|
#
|
||||||
# Generated by export_simulation on Mon Jul 03 19:45:40 CST 2023
|
# Generated by export_simulation on Sun Jul 30 18:20:24 CST 2023
|
||||||
#
|
#
|
||||||
################################################################################
|
################################################################################
|
||||||
|
|
||||||
|
|||||||
+1
-1
@@ -9,7 +9,7 @@
|
|||||||
# directory, add the library logical mappings in the simulator setup file, create default
|
# directory, add the library logical mappings in the simulator setup file, create default
|
||||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||||
#
|
#
|
||||||
# Generated by Vivado on Mon Jul 03 19:45:40 CST 2023
|
# Generated by Vivado on Sun Jul 30 18:20:24 CST 2023
|
||||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||||
#
|
#
|
||||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
|||||||
+1
-1
@@ -4,7 +4,7 @@
|
|||||||
# README.txt: Please read the sections below to understand the steps required to
|
# README.txt: Please read the sections below to understand the steps required to
|
||||||
# run the exported script and information about the source files.
|
# run the exported script and information about the source files.
|
||||||
#
|
#
|
||||||
# Generated by export_simulation on Mon Jul 03 19:45:40 CST 2023
|
# Generated by export_simulation on Sun Jul 30 18:20:24 CST 2023
|
||||||
#
|
#
|
||||||
################################################################################
|
################################################################################
|
||||||
|
|
||||||
|
|||||||
+1
-1
@@ -9,7 +9,7 @@
|
|||||||
# directory, add the library logical mappings in the simulator setup file, create default
|
# directory, add the library logical mappings in the simulator setup file, create default
|
||||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||||
#
|
#
|
||||||
# Generated by Vivado on Mon Jul 03 19:45:40 CST 2023
|
# Generated by Vivado on Sun Jul 30 18:20:24 CST 2023
|
||||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||||
#
|
#
|
||||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
|||||||
+1
-1
@@ -4,7 +4,7 @@
|
|||||||
# README.txt: Please read the sections below to understand the steps required to
|
# README.txt: Please read the sections below to understand the steps required to
|
||||||
# run the exported script and information about the source files.
|
# run the exported script and information about the source files.
|
||||||
#
|
#
|
||||||
# Generated by export_simulation on Mon Jul 03 19:45:40 CST 2023
|
# Generated by export_simulation on Sun Jul 30 18:20:24 CST 2023
|
||||||
#
|
#
|
||||||
################################################################################
|
################################################################################
|
||||||
|
|
||||||
|
|||||||
+1
-1
@@ -9,7 +9,7 @@
|
|||||||
# directory, add the library logical mappings in the simulator setup file, create default
|
# directory, add the library logical mappings in the simulator setup file, create default
|
||||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||||
#
|
#
|
||||||
# Generated by Vivado on Mon Jul 03 19:45:40 CST 2023
|
# Generated by Vivado on Sun Jul 30 18:20:24 CST 2023
|
||||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||||
#
|
#
|
||||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
|||||||
+1
-1
@@ -4,7 +4,7 @@
|
|||||||
# README.txt: Please read the sections below to understand the steps required to
|
# README.txt: Please read the sections below to understand the steps required to
|
||||||
# run the exported script and information about the source files.
|
# run the exported script and information about the source files.
|
||||||
#
|
#
|
||||||
# Generated by export_simulation on Mon Jul 03 19:45:40 CST 2023
|
# Generated by export_simulation on Sun Jul 30 18:20:24 CST 2023
|
||||||
#
|
#
|
||||||
################################################################################
|
################################################################################
|
||||||
|
|
||||||
|
|||||||
+1
-1
@@ -9,7 +9,7 @@
|
|||||||
# directory, add the library logical mappings in the simulator setup file, create default
|
# directory, add the library logical mappings in the simulator setup file, create default
|
||||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||||
#
|
#
|
||||||
# Generated by Vivado on Mon Jul 03 19:45:40 CST 2023
|
# Generated by Vivado on Sun Jul 30 18:20:24 CST 2023
|
||||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||||
#
|
#
|
||||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
|||||||
+1
-1
@@ -4,7 +4,7 @@
|
|||||||
# README.txt: Please read the sections below to understand the steps required to
|
# README.txt: Please read the sections below to understand the steps required to
|
||||||
# run the exported script and information about the source files.
|
# run the exported script and information about the source files.
|
||||||
#
|
#
|
||||||
# Generated by export_simulation on Mon Jul 03 19:45:40 CST 2023
|
# Generated by export_simulation on Sun Jul 30 18:20:24 CST 2023
|
||||||
#
|
#
|
||||||
################################################################################
|
################################################################################
|
||||||
|
|
||||||
|
|||||||
+1
-1
@@ -9,7 +9,7 @@
|
|||||||
# directory, add the library logical mappings in the simulator setup file, create default
|
# directory, add the library logical mappings in the simulator setup file, create default
|
||||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||||
#
|
#
|
||||||
# Generated by Vivado on Mon Jul 03 19:45:40 CST 2023
|
# Generated by Vivado on Sun Jul 30 18:20:24 CST 2023
|
||||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||||
#
|
#
|
||||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
|||||||
+109
@@ -0,0 +1,109 @@
|
|||||||
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
|
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||||
|
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||||
|
<spirit:library>ipcache</spirit:library>
|
||||||
|
<spirit:name>7727187e03eca7b1</spirit:name>
|
||||||
|
<spirit:version>0</spirit:version>
|
||||||
|
<spirit:componentInstances>
|
||||||
|
<spirit:componentInstance>
|
||||||
|
<spirit:instanceName>rom_freq_word</spirit:instanceName>
|
||||||
|
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="blk_mem_gen" spirit:version="8.4"/>
|
||||||
|
<spirit:configurableElementValues>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_ID_Width">4</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Slave_Type">Memory_Slave</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Type">AXI4_Full</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Additional_Inputs_for_Power_Estimation">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Algorithm">Minimum_Area</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Assume_Synchronous_Clk">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Byte_Size">9</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coe_File">../coe/freq_word.coe</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Collision_Warnings">ALL</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">rom_freq_word</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Collision_Warnings">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Out_of_Range_Warnings">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ECC">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_DEEPSLEEP_PIN">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_ECC_PIPE">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SAFETY_CKT">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SHUTDOWN_PIN">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SLEEP_PIN">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_32bit_Address">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_A">Always_Enabled</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_B">Always_Enabled</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Error_Injection_Type">Single_Bit_Error_Injection</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fill_Remaining_Memory_Locations">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interface_Type">Native</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Load_Init_File">true</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MEM_FILE">no_mem_loaded</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Memory_Type">Single_Port_ROM</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_A">WRITE_FIRST</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_B">WRITE_FIRST</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_A">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_B">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_type_to_Implement">BRAM</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pipeline_Stages">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Clock">100</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Enable_Rate">100</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Write_Rate">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Clock">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Enable_Rate">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Write_Rate">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Primitive">8kx2</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_A">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_B">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_LATENCY_A">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_LATENCY_B">1</spirit:configurableElementValue>
|
||||||
|
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</spirit:design>
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||||||
BIN
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BIN
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BIN
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+22
@@ -0,0 +1,22 @@
|
|||||||
|
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||||
|
// Date : Sun Jul 30 18:06:27 2023
|
||||||
|
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||||
|
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||||
|
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rom_freq_word_stub.v
|
||||||
|
// Design : rom_freq_word
|
||||||
|
// Purpose : Stub declaration of top-level module interface
|
||||||
|
// Device : xc7z100ffg900-2
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||||
|
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||||
|
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||||
|
(* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *)
|
||||||
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clka, addra, douta)
|
||||||
|
/* synthesis syn_black_box black_box_pad_pin="clka,addra[6:0],douta[11:0]" */;
|
||||||
|
input clka;
|
||||||
|
input [6:0]addra;
|
||||||
|
output [11:0]douta;
|
||||||
|
endmodule
|
||||||
+32
@@ -0,0 +1,32 @@
|
|||||||
|
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
-- --------------------------------------------------------------------------------
|
||||||
|
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||||
|
-- Date : Sun Jul 30 18:06:27 2023
|
||||||
|
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||||
|
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||||
|
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rom_freq_word_stub.vhdl
|
||||||
|
-- Design : rom_freq_word
|
||||||
|
-- Purpose : Stub declaration of top-level module interface
|
||||||
|
-- Device : xc7z100ffg900-2
|
||||||
|
-- --------------------------------------------------------------------------------
|
||||||
|
library IEEE;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
|
||||||
|
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||||
|
Port (
|
||||||
|
clka : in STD_LOGIC;
|
||||||
|
addra : in STD_LOGIC_VECTOR ( 6 downto 0 );
|
||||||
|
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
|
||||||
|
);
|
||||||
|
|
||||||
|
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||||
|
|
||||||
|
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||||
|
attribute syn_black_box : boolean;
|
||||||
|
attribute black_box_pad_pin : string;
|
||||||
|
attribute syn_black_box of stub : architecture is true;
|
||||||
|
attribute black_box_pad_pin of stub : architecture is "clka,addra[6:0],douta[11:0]";
|
||||||
|
attribute x_core_info : string;
|
||||||
|
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_3,Vivado 2019.1.3";
|
||||||
|
begin
|
||||||
|
end;
|
||||||
+810
@@ -0,0 +1,810 @@
|
|||||||
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
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|
||||||
|
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||||
|
<spirit:library>ipcache</spirit:library>
|
||||||
|
<spirit:name>e8e950360ca1fe60</spirit:name>
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|
<spirit:version>0</spirit:version>
|
||||||
|
<spirit:componentInstances>
|
||||||
|
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|
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT85_WIDTH">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT86_INIT_VAL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT86_WIDTH">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT87_INIT_VAL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT87_WIDTH">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT88_INIT_VAL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT88_WIDTH">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT89_INIT_VAL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT89_WIDTH">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT8_INIT_VAL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT8_WIDTH">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT90_INIT_VAL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT90_WIDTH">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT91_INIT_VAL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT91_WIDTH">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT92_INIT_VAL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT92_WIDTH">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT93_INIT_VAL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT93_WIDTH">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT94_INIT_VAL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT94_WIDTH">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT95_INIT_VAL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT95_WIDTH">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT96_INIT_VAL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT96_WIDTH">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT97_INIT_VAL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT97_WIDTH">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT98_INIT_VAL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT98_WIDTH">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT99_INIT_VAL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT99_WIDTH">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT9_INIT_VAL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT9_WIDTH">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">vio_RF_control</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z100</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">e8e950360ca1fe60</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">9a10a187</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">14</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">20</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.3</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||||
|
</spirit:configurableElementValues>
|
||||||
|
</spirit:componentInstance>
|
||||||
|
</spirit:componentInstances>
|
||||||
|
</spirit:design>
|
||||||
BIN
Binary file not shown.
BIN
Binary file not shown.
BIN
Binary file not shown.
+39
@@ -0,0 +1,39 @@
|
|||||||
|
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||||
|
// Date : Sun Jul 30 18:20:41 2023
|
||||||
|
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||||
|
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||||
|
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_RF_control_stub.v
|
||||||
|
// Design : vio_RF_control
|
||||||
|
// Purpose : Stub declaration of top-level module interface
|
||||||
|
// Device : xc7z100ffg900-2
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||||
|
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||||
|
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||||
|
(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
|
||||||
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe_in0, probe_out0, probe_out1,
|
||||||
|
probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, probe_out9,
|
||||||
|
probe_out10, probe_out11, probe_out12, probe_out13, probe_out14, probe_out15)
|
||||||
|
/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[11:0],probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[7:0],probe_out4[7:0],probe_out5[11:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0],probe_out9[0:0],probe_out10[0:0],probe_out11[0:0],probe_out12[0:0],probe_out13[31:0],probe_out14[0:0],probe_out15[31:0]" */;
|
||||||
|
input clk;
|
||||||
|
input [11:0]probe_in0;
|
||||||
|
output [0:0]probe_out0;
|
||||||
|
output [1:0]probe_out1;
|
||||||
|
output [0:0]probe_out2;
|
||||||
|
output [7:0]probe_out3;
|
||||||
|
output [7:0]probe_out4;
|
||||||
|
output [11:0]probe_out5;
|
||||||
|
output [0:0]probe_out6;
|
||||||
|
output [0:0]probe_out7;
|
||||||
|
output [0:0]probe_out8;
|
||||||
|
output [0:0]probe_out9;
|
||||||
|
output [0:0]probe_out10;
|
||||||
|
output [0:0]probe_out11;
|
||||||
|
output [0:0]probe_out12;
|
||||||
|
output [31:0]probe_out13;
|
||||||
|
output [0:0]probe_out14;
|
||||||
|
output [31:0]probe_out15;
|
||||||
|
endmodule
|
||||||
+47
@@ -0,0 +1,47 @@
|
|||||||
|
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
-- --------------------------------------------------------------------------------
|
||||||
|
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||||
|
-- Date : Sun Jul 30 18:20:41 2023
|
||||||
|
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||||
|
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||||
|
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_RF_control_stub.vhdl
|
||||||
|
-- Design : vio_RF_control
|
||||||
|
-- Purpose : Stub declaration of top-level module interface
|
||||||
|
-- Device : xc7z100ffg900-2
|
||||||
|
-- --------------------------------------------------------------------------------
|
||||||
|
library IEEE;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
|
||||||
|
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||||
|
Port (
|
||||||
|
clk : in STD_LOGIC;
|
||||||
|
probe_in0 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||||
|
probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
|
probe_out1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||||
|
probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
|
probe_out3 : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||||
|
probe_out4 : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||||
|
probe_out5 : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||||
|
probe_out6 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
|
probe_out7 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
|
probe_out8 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
|
probe_out9 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
|
probe_out10 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
|
probe_out11 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
|
probe_out12 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
|
probe_out13 : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||||
|
probe_out14 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
|
probe_out15 : out STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||||
|
);
|
||||||
|
|
||||||
|
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||||
|
|
||||||
|
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||||
|
attribute syn_black_box : boolean;
|
||||||
|
attribute black_box_pad_pin : string;
|
||||||
|
attribute syn_black_box of stub : architecture is true;
|
||||||
|
attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[11:0],probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[7:0],probe_out4[7:0],probe_out5[11:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0],probe_out9[0:0],probe_out10[0:0],probe_out11[0:0],probe_out12[0:0],probe_out13[31:0],probe_out14[0:0],probe_out15[31:0]";
|
||||||
|
attribute X_CORE_INFO : string;
|
||||||
|
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
|
||||||
|
begin
|
||||||
|
end;
|
||||||
+11
-8
@@ -1,13 +1,14 @@
|
|||||||
version:1
|
version:1
|
||||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:34:00:00
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:34:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3234:00:00
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3236:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:34:00:00
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:34:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:65787072756e6d656e755f72657365745f616e645f67656e65726174655f6f75747075745f70726f6475637473:31:00:00
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:65787072756e6d656e755f72657365745f616e645f67656e65726174655f6f75747075745f70726f6475637473:31:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:65787072756e7472656570616e656c5f6578705f72756e5f747265655f7461626c65:39:00:00
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:65787072756e7472656570616e656c5f6578705f72756e5f747265655f7461626c65:3133:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:3638:00:00
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:3739:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6d616e6167655f6970:33:00:00
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6d616e6167655f6970:35:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f73746172745f7573696e675f76697661646f5f776974685f69705f636174616c6f67:31:00:00
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f73746172745f7573696e675f76697661646f5f776974685f69705f636174616c6f67:31:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6861636763636f6566696c657769646765745f62726f777365:34:00:00
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6861636763636f6566696c657769646765745f62726f777365:35:00:00
|
||||||
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68666f6c64657263686f6f73657268656c706572735f6a756d705f746f5f726563656e745f70726f6a6563745f6469726563746f7279:31:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:686a66696c6563686f6f73657268656c706572735f6a756d705f746f5f726563656e745f70726f6a6563745f6469726563746f7279:33:00:00
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:686a66696c6563686f6f73657268656c706572735f6a756d705f746f5f726563656e745f70726f6a6563745f6469726563746f7279:33:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f65646974:32:00:00
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f65646974:32:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f6578706f7274:33:00:00
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f6578706f7274:33:00:00
|
||||||
@@ -24,14 +25,16 @@ version:1
|
|||||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f6578697374696e675f6970:38:00:00
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f6578697374696e675f6970:38:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f636c6f73655f70726f6a656374:35:00:00
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f636c6f73655f70726f6a656374:35:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f67656e65726174655f636f6d706f736974655f66696c65:35:00:00
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f67656e65726174655f636f6d706f736974655f66696c65:35:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6f70656e5f69705f6c6f636174696f6e:32:00:00
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6f70656e5f69705f6c6f636174696f6e:34:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f72657365745f636f6d706f736974655f66696c65:32:00:00
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f72657365745f636f6d706f736974655f66696c65:32:00:00
|
||||||
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f67726573736469616c6f675f63616e63656c:31:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f64656c657465:31:00:00
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f64656c657465:31:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72656d6f7665736f75726365736469616c6f675f616c736f5f64656c657465:35:00:00
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72656d6f7665736f75726365736469616c6f675f616c736f5f64656c657465:35:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d706c656f757470757470726f647563746469616c6f675f67656e65726174655f6f75747075745f70726f64756374735f696d6d6564696174656c79:3133:00:00
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d706c656f757470757470726f647563746469616c6f675f67656e65726174655f6f75747075745f70726f64756374735f696d6d6564696174656c79:3135:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d706c656f757470757470726f647563746469616c6f675f72657365745f6f75747075745f70726f6475637473:33:00:00
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d706c656f757470757470726f647563746469616c6f675f72657365745f6f75747075745f70726f6475637473:33:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f636f6e666967757261626c655f69705f66696c6573:38:00:00
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f636f6e666967757261626c655f69705f66696c6573:38:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6d616b655f6c6f63616c5f636f70795f6f665f74686573655f66696c65735f696e746f:32:00:00
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6d616b655f6c6f63616c5f636f70795f6f665f74686573655f66696c65735f696e746f:32:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f69705f646f63756d656e746174696f6e:32:00:00
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f69705f646f63756d656e746174696f6e:32:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636167657474696e6773746172746564766965775f726563656e745f69705f6c6f636174696f6e73:38:00:00
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636167657474696e6773746172746564766965775f726563656e745f69705f6c6f636174696f6e73:38:00:00
|
||||||
eof:3676694193
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636167657474696e6773746172746564766965775f726563656e745f70726f6a65637473:31:00:00
|
||||||
|
eof:3632338426
|
||||||
|
|||||||
+3
-3
@@ -4,7 +4,7 @@ version:1
|
|||||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:34:00:00
|
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:34:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6d616e616765636f6d706f7369746574617267657473:37:00:00
|
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6d616e616765636f6d706f7369746574617267657473:37:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657769706c6f636174696f6e68616e646c6572:31:00:00
|
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657769706c6f636174696f6e68616e646c6572:31:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e69706c6f636174696f6e68616e646c6572:32:00:00
|
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e69706c6f636174696f6e68616e646c6572:34:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726576696f7573697068616e646c6572:38:00:00
|
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726576696f7573697068616e646c6572:38:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265637573746f6d697a65636f7265:3131:00:00
|
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265637573746f6d697a65636f7265:3134:00:00
|
||||||
eof:2683708577
|
eof:309752714
|
||||||
|
|||||||
+1
-1
@@ -1,3 +1,3 @@
|
|||||||
version:1
|
version:1
|
||||||
6d6f64655f636f756e7465727c4755494d6f6465:11
|
6d6f64655f636f756e7465727c4755494d6f6465:13
|
||||||
eof:
|
eof:
|
||||||
|
|||||||
+5
-5
@@ -1,7 +1,7 @@
|
|||||||
version:1
|
version:1
|
||||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:7863377a3130306666673930302d32:00:00
|
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:7863377a3130306666673930302d32:00:00
|
||||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:696c615f72665f74657374:00:00
|
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:76696f5f52465f636f6e74726f6c:00:00
|
||||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||||
@@ -33,7 +33,7 @@ version:1
|
|||||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||||
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a343973:00:00
|
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a313173:00:00
|
||||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323332392e3038364d42:00:00
|
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323131342e3039384d42:00:00
|
||||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3931312e3232334d42:00:00
|
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3730392e3733304d42:00:00
|
||||||
eof:2301228565
|
eof:1038723330
|
||||||
|
|||||||
+15
-12
@@ -3,7 +3,7 @@
|
|||||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||||
The structure and the elements are likely to change over the next few releases.
|
The structure and the elements are likely to change over the next few releases.
|
||||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||||
<application name="pa" timeStamp="Mon Jul 3 19:45:47 2023">
|
<application name="pa" timeStamp="Sun Jul 30 18:42:58 2023">
|
||||||
<section name="Project Information" visible="false">
|
<section name="Project Information" visible="false">
|
||||||
<property name="ProjectID" value="b252a1e4ed8d4787b074893bfbb0dee3" type="ProjectID"/>
|
<property name="ProjectID" value="b252a1e4ed8d4787b074893bfbb0dee3" type="ProjectID"/>
|
||||||
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
|
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
|
||||||
@@ -22,20 +22,21 @@ This means code written to parse this file will need to be revisited each subseq
|
|||||||
<property name="EditDelete" value="4" type="JavaHandler"/>
|
<property name="EditDelete" value="4" type="JavaHandler"/>
|
||||||
<property name="ManageCompositeTargets" value="7" type="JavaHandler"/>
|
<property name="ManageCompositeTargets" value="7" type="JavaHandler"/>
|
||||||
<property name="NewIPLocationHandler" value="1" type="JavaHandler"/>
|
<property name="NewIPLocationHandler" value="1" type="JavaHandler"/>
|
||||||
<property name="OpenIPLocationHandler" value="2" type="JavaHandler"/>
|
<property name="OpenIPLocationHandler" value="4" type="JavaHandler"/>
|
||||||
<property name="OpenPreviousIPHandler" value="8" type="JavaHandler"/>
|
<property name="OpenPreviousIPHandler" value="8" type="JavaHandler"/>
|
||||||
<property name="RecustomizeCore" value="11" type="JavaHandler"/>
|
<property name="RecustomizeCore" value="14" type="JavaHandler"/>
|
||||||
</item>
|
</item>
|
||||||
<item name="Gui Handlers">
|
<item name="Gui Handlers">
|
||||||
<property name="BaseDialog_CANCEL" value="4" type="GuiHandlerData"/>
|
<property name="BaseDialog_CANCEL" value="4" type="GuiHandlerData"/>
|
||||||
<property name="BaseDialog_OK" value="24" type="GuiHandlerData"/>
|
<property name="BaseDialog_OK" value="26" type="GuiHandlerData"/>
|
||||||
<property name="CmdMsgDialog_OK" value="4" type="GuiHandlerData"/>
|
<property name="CmdMsgDialog_OK" value="4" type="GuiHandlerData"/>
|
||||||
<property name="ExpRunMenu_RESET_AND_GENERATE_OUTPUT_PRODUCTS" value="1" type="GuiHandlerData"/>
|
<property name="ExpRunMenu_RESET_AND_GENERATE_OUTPUT_PRODUCTS" value="1" type="GuiHandlerData"/>
|
||||||
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="9" type="GuiHandlerData"/>
|
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="13" type="GuiHandlerData"/>
|
||||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="68" type="GuiHandlerData"/>
|
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="79" type="GuiHandlerData"/>
|
||||||
<property name="GettingStartedView_MANAGE_IP" value="3" type="GuiHandlerData"/>
|
<property name="GettingStartedView_MANAGE_IP" value="5" type="GuiHandlerData"/>
|
||||||
<property name="GettingStartedView_START_USING_VIVADO_WITH_IP_CATALOG" value="1" type="GuiHandlerData"/>
|
<property name="GettingStartedView_START_USING_VIVADO_WITH_IP_CATALOG" value="1" type="GuiHandlerData"/>
|
||||||
<property name="HACGCCoeFileWidget_BROWSE" value="4" type="GuiHandlerData"/>
|
<property name="HACGCCoeFileWidget_BROWSE" value="5" type="GuiHandlerData"/>
|
||||||
|
<property name="HFolderChooserHelpers_JUMP_TO_RECENT_PROJECT_DIRECTORY" value="1" type="GuiHandlerData"/>
|
||||||
<property name="HJFileChooserHelpers_JUMP_TO_RECENT_PROJECT_DIRECTORY" value="3" type="GuiHandlerData"/>
|
<property name="HJFileChooserHelpers_JUMP_TO_RECENT_PROJECT_DIRECTORY" value="3" type="GuiHandlerData"/>
|
||||||
<property name="MainMenuMgr_EDIT" value="2" type="GuiHandlerData"/>
|
<property name="MainMenuMgr_EDIT" value="2" type="GuiHandlerData"/>
|
||||||
<property name="MainMenuMgr_EXPORT" value="3" type="GuiHandlerData"/>
|
<property name="MainMenuMgr_EXPORT" value="3" type="GuiHandlerData"/>
|
||||||
@@ -52,21 +53,23 @@ This means code written to parse this file will need to be revisited each subseq
|
|||||||
<property name="PACommandNames_ADD_EXISTING_IP" value="8" type="GuiHandlerData"/>
|
<property name="PACommandNames_ADD_EXISTING_IP" value="8" type="GuiHandlerData"/>
|
||||||
<property name="PACommandNames_CLOSE_PROJECT" value="5" type="GuiHandlerData"/>
|
<property name="PACommandNames_CLOSE_PROJECT" value="5" type="GuiHandlerData"/>
|
||||||
<property name="PACommandNames_GENERATE_COMPOSITE_FILE" value="5" type="GuiHandlerData"/>
|
<property name="PACommandNames_GENERATE_COMPOSITE_FILE" value="5" type="GuiHandlerData"/>
|
||||||
<property name="PACommandNames_OPEN_IP_LOCATION" value="2" type="GuiHandlerData"/>
|
<property name="PACommandNames_OPEN_IP_LOCATION" value="4" type="GuiHandlerData"/>
|
||||||
<property name="PACommandNames_RESET_COMPOSITE_FILE" value="2" type="GuiHandlerData"/>
|
<property name="PACommandNames_RESET_COMPOSITE_FILE" value="2" type="GuiHandlerData"/>
|
||||||
|
<property name="ProgressDialog_CANCEL" value="1" type="GuiHandlerData"/>
|
||||||
<property name="RDICommands_DELETE" value="1" type="GuiHandlerData"/>
|
<property name="RDICommands_DELETE" value="1" type="GuiHandlerData"/>
|
||||||
<property name="RemoveSourcesDialog_ALSO_DELETE" value="5" type="GuiHandlerData"/>
|
<property name="RemoveSourcesDialog_ALSO_DELETE" value="5" type="GuiHandlerData"/>
|
||||||
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="13" type="GuiHandlerData"/>
|
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="15" type="GuiHandlerData"/>
|
||||||
<property name="SimpleOutputProductDialog_RESET_OUTPUT_PRODUCTS" value="3" type="GuiHandlerData"/>
|
<property name="SimpleOutputProductDialog_RESET_OUTPUT_PRODUCTS" value="3" type="GuiHandlerData"/>
|
||||||
<property name="SrcChooserPanel_ADD_CONFIGURABLE_IP_FILES" value="8" type="GuiHandlerData"/>
|
<property name="SrcChooserPanel_ADD_CONFIGURABLE_IP_FILES" value="8" type="GuiHandlerData"/>
|
||||||
<property name="SrcChooserPanel_MAKE_LOCAL_COPY_OF_THESE_FILES_INTO" value="2" type="GuiHandlerData"/>
|
<property name="SrcChooserPanel_MAKE_LOCAL_COPY_OF_THESE_FILES_INTO" value="2" type="GuiHandlerData"/>
|
||||||
<property name="SrcMenu_IP_DOCUMENTATION" value="2" type="GuiHandlerData"/>
|
<property name="SrcMenu_IP_DOCUMENTATION" value="2" type="GuiHandlerData"/>
|
||||||
<property name="SyntheticaGettingStartedView_RECENT_IP_LOCATIONS" value="8" type="GuiHandlerData"/>
|
<property name="SyntheticaGettingStartedView_RECENT_IP_LOCATIONS" value="8" type="GuiHandlerData"/>
|
||||||
|
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="1" type="GuiHandlerData"/>
|
||||||
</item>
|
</item>
|
||||||
<item name="Other">
|
<item name="Other">
|
||||||
<property name="GuiMode" value="23" type="GuiMode"/>
|
<property name="GuiMode" value="40" type="GuiMode"/>
|
||||||
<property name="BatchMode" value="0" type="BatchMode"/>
|
<property name="BatchMode" value="0" type="BatchMode"/>
|
||||||
<property name="TclMode" value="11" type="TclMode"/>
|
<property name="TclMode" value="20" type="TclMode"/>
|
||||||
</item>
|
</item>
|
||||||
</section>
|
</section>
|
||||||
</application>
|
</application>
|
||||||
|
|||||||
+8
@@ -0,0 +1,8 @@
|
|||||||
|
<?xml version="1.0"?>
|
||||||
|
<Runs Version="1" Minor="0">
|
||||||
|
<Run Id="rom_freq_word_synth_1" LaunchDir="/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||||
|
<Parameters>
|
||||||
|
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||||
|
</Parameters>
|
||||||
|
</Runs>
|
||||||
|
|
||||||
+8
@@ -0,0 +1,8 @@
|
|||||||
|
<?xml version="1.0"?>
|
||||||
|
<Runs Version="1" Minor="0">
|
||||||
|
<Run Id="vio_RF_control_synth_1" LaunchDir="/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||||
|
<Parameters>
|
||||||
|
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||||
|
</Parameters>
|
||||||
|
</Runs>
|
||||||
|
|
||||||
+1
-1
@@ -1,5 +1,5 @@
|
|||||||
<?xml version="1.0"?>
|
<?xml version="1.0"?>
|
||||||
<ProcessHandle Version="1" Minor="0">
|
<ProcessHandle Version="1" Minor="0">
|
||||||
<Process Command="vivado" Owner="josh" Host="JOSH-ASUS-Z690" Pid="1476074" HostCore="20" HostMemory="65588992">
|
<Process Command="vivado" Owner="josh" Host="JOSH-ASUS-Z690" Pid="1394906" HostCore="20" HostMemory="65576700">
|
||||||
</Process>
|
</Process>
|
||||||
</ProcessHandle>
|
</ProcessHandle>
|
||||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user