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major update to lcmv, to fit hop control

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1. 调零算法部分增加调零控制模块,用于各模块互联和状态控制以及数据存储,增加LCMV和DAS选通; 2. Cordic 旋转输入改为保留两个符号位,避免溢出; 3. LCMV快拍数修改为2048; 4. 修改功率计算模块,适配较小数据位宽; 5. 修改在线捕获校准程序自动校准部分VIO初值; 6. 地检新射频发端增加自动频点切换
This commit is contained in:
josh
2023-07-31 10:31:21 +08:00
parent a877802bdf
commit 365a132831
418 changed files with 14603 additions and 3824 deletions
Download Patch File Download Diff File Expand all files Collapse all files
modules/xc7k410tffg900-2/var_cal/rtl/var_cal.v
+94 -48
View File
@@ -19,7 +19,9 @@
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Revision 0.01 - File Created
// 20230730-1427 - 修改输入位宽小于乘法器位宽时的处理，由补零变为符号位扩展；
// 修改；修改累加和输出截位方式，依托原始数据位宽进行处理。
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
@@ -30,7 +32,7 @@ module var_cal
parameter ACCUM_NUM = 16384,
parameter DATA_I_WIDTH = 30,
parameter DATA_O_WIDTH = 32,
parameter CMPY_WIDTH = 18
parameter CMPY_I_WIDTH = 18
)
(
input clk ,
@@ -50,11 +52,13 @@ module var_cal
integer i;
localparam CMPY_VALID_WIDTH = CMPY_WIDTH-1; // 17-bit valid data to protect cmpy from overflow
localparam DATA_MULT_FULL_WIDTH = 2*CMPY_VALID_WIDTH+1;
localparam DATA_MULT_VALID_WIDTH = 2*CMPY_VALID_WIDTH;
localparam AXIS_DATA_I_WIDTH = 8*((CMPY_VALID_WIDTH-1)/8+1) ; // axis data width of input real/image data
localparam AXIS_DATA_P_WIDTH = 8*((DATA_MULT_FULL_WIDTH-1)/8+1); // axis data width of cmpy output real/image data
localparam CMPY_P_WIDTH = 2*CMPY_I_WIDTH+1;
localparam AXIS_CMPY_I_WIDTH = 8*((CMPY_I_WIDTH-1)/8+1) ; // axis data width of input real/image data
localparam AXIS_CMPY_P_WIDTH = 8*((CMPY_P_WIDTH-1)/8+1); // axis data width of cmpy output real/image data
localparam CMPY_P_VALID_WIDTH = (DATA_I_WIDTH > CMPY_I_WIDTH) ? 2*CMPY_I_WIDTH : 2*DATA_I_WIDTH;
localparam ACCUM_WIDTH = CMPY_P_VALID_WIDTH + $clog2(ACCUM_NUM);
// status control
reg cal_start_auto = 'b0;
@@ -63,7 +67,7 @@ reg cal_start_d2 = 'b0;
reg cal_busy_buf = 'b0;
reg [$clog2(ACCUM_NUM)-1 : 0] cnt_accum = 'b0;
reg last_data = 'b0;
reg last_data_d [0:6]; // 6 for cmpy, 1 for register output
reg [6:0] last_data_d = 'b0; // 1 for register input, 6 for cmpy, 1 for register output
assign cal_busy = cal_busy_buf;
assign var_valid = last_data_d[6];
@@ -73,11 +77,16 @@ always @(posedge clk) begin
cal_start_auto <= 'b0;
end
else begin
if (~cal_busy_buf) begin
cal_start_auto = ~cal_start_auto;
if (cal_auto_en) begin
if (~cal_busy_buf) begin
cal_start_auto <= ~cal_start_auto;
end
else begin
cal_start_auto <= cal_start_auto;
end
end
else begin
cal_start_auto <= cal_start_auto;
cal_start_auto <= 'b0;
end
end
end
@@ -123,50 +132,72 @@ always @(posedge clk) begin
end
always @(posedge clk) begin
last_data_d[0] <= last_data;
for (i = 0; i < 6; i = i + 1) begin
last_data_d[i+1] <= last_data_d[i];
if (rst) begin
last_data_d[6:0] <= 'b0;
end
else begin
last_data_d[6:0] <= {last_data_d[5:0],last_data};
end
end
// cmpy
wire [AXIS_DATA_I_WIDTH-1 : 0] cmpy_i_real;
wire [AXIS_DATA_I_WIDTH-1 : 0] cmpy_i_imag;
wire [AXIS_DATA_P_WIDTH-1 : 0] cmpy_p_raw_real;
wire [AXIS_DATA_P_WIDTH-1 : 0] cmpy_p_raw_imag;
wire [DATA_O_WIDTH-1 : 0] cmpy_p_real;
wire [DATA_O_WIDTH-1 : 0] cmpy_p_imag;
reg [AXIS_CMPY_I_WIDTH-1 : 0] cmpy_a_real = 'b0;
reg [AXIS_CMPY_I_WIDTH-1 : 0] cmpy_a_imag = 'b0;
reg [AXIS_CMPY_I_WIDTH-1 : 0] cmpy_b_real = 'b0;
reg [AXIS_CMPY_I_WIDTH-1 : 0] cmpy_b_imag = 'b0;
wire [AXIS_CMPY_P_WIDTH-1 : 0] cmpy_p_raw_real;
wire [AXIS_CMPY_P_WIDTH-1 : 0] cmpy_p_raw_imag;
wire [CMPY_P_VALID_WIDTH-1 : 0] cmpy_p_real;
wire [CMPY_P_VALID_WIDTH-1 : 0] cmpy_p_imag;
if (CMPY_WIDTH > DATA_I_WIDTH) begin
// append zeros
assign cmpy_i_real = {{(AXIS_DATA_I_WIDTH-CMPY_VALID_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real,{(CMPY_VALID_WIDTH-DATA_I_WIDTH){1'b0}}};
assign cmpy_i_imag = {{(AXIS_DATA_I_WIDTH-CMPY_VALID_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag,{(CMPY_VALID_WIDTH-DATA_I_WIDTH){1'b0}}};
if (CMPY_I_WIDTH > DATA_I_WIDTH) begin
// sign-bit extension to fit cmpy input data width
always @(posedge clk) begin
if (rst) begin
cmpy_a_real <= 'b0;
cmpy_a_imag <= 'b0;
cmpy_b_real <= 'b0;
cmpy_b_imag <= 'b0;
end
else begin
cmpy_a_real <= {{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real};
cmpy_a_imag <= {{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag};
cmpy_b_real <= {{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real};
cmpy_b_imag <= (din_imag == {1'b1,{(DATA_I_WIDTH-1){1'b0}}}) ? {{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH+1){1'b0}},{(DATA_I_WIDTH-1){1'b1}}} : -{{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag};
end
end
end
else begin
// truncate msb
assign cmpy_i_real = {{(AXIS_DATA_I_WIDTH-CMPY_VALID_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real[DATA_I_WIDTH-1 -: CMPY_VALID_WIDTH]};
assign cmpy_i_imag = {{(AXIS_DATA_I_WIDTH-CMPY_VALID_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag[DATA_I_WIDTH-1 -: CMPY_VALID_WIDTH]};
always @(posedge clk) begin
if (rst) begin
cmpy_a_real <= 'b0;
cmpy_a_imag <= 'b0;
cmpy_b_real <= 'b0;
cmpy_b_imag <= 'b0;
end
else begin
cmpy_a_real <= {{(AXIS_CMPY_I_WIDTH-CMPY_I_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real[DATA_I_WIDTH-1 -: CMPY_I_WIDTH]};
cmpy_a_imag <= {{(AXIS_CMPY_I_WIDTH-CMPY_I_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag[DATA_I_WIDTH-1 -: CMPY_I_WIDTH]};
cmpy_b_real <= {{(AXIS_CMPY_I_WIDTH-CMPY_I_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real[DATA_I_WIDTH-1 -: CMPY_I_WIDTH]};
cmpy_b_imag <= (din_imag[DATA_I_WIDTH-1 -: CMPY_I_WIDTH] == {1'b1,{(CMPY_I_WIDTH-1){1'b0}}}) ? {{(AXIS_CMPY_I_WIDTH-CMPY_I_WIDTH+1){1'b0}},{(CMPY_I_WIDTH-1){1'b1}}} : -{{(AXIS_CMPY_I_WIDTH-CMPY_I_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag[DATA_I_WIDTH-1 -: CMPY_I_WIDTH]};
end
end
end
if (DATA_O_WIDTH > DATA_MULT_VALID_WIDTH) begin
// append zeros
assign cmpy_p_real = {cmpy_p_raw_real[0 +: DATA_MULT_VALID_WIDTH],{(DATA_O_WIDTH-DATA_MULT_VALID_WIDTH){1'b0}}};
assign cmpy_p_imag = {cmpy_p_raw_imag[0 +: DATA_MULT_VALID_WIDTH],{(DATA_O_WIDTH-DATA_MULT_VALID_WIDTH){1'b0}}};
end
else begin
// truncate msb
assign cmpy_p_real = cmpy_p_raw_real[DATA_MULT_VALID_WIDTH-1 -: DATA_O_WIDTH];
assign cmpy_p_imag = cmpy_p_raw_imag[DATA_MULT_VALID_WIDTH-1 -: DATA_O_WIDTH];
end
// truncate valid bits
assign cmpy_p_real = cmpy_p_raw_real[0 +: CMPY_P_VALID_WIDTH];
assign cmpy_p_imag = cmpy_p_raw_imag[0 +: CMPY_P_VALID_WIDTH];
wire [2*AXIS_DATA_I_WIDTH-1:0] cmpy_a;
wire [2*AXIS_DATA_I_WIDTH-1:0] cmpy_b;
wire [2*AXIS_DATA_P_WIDTH-1:0] cmpy_p;
wire [2*AXIS_CMPY_I_WIDTH-1:0] cmpy_a;
wire [2*AXIS_CMPY_I_WIDTH-1:0] cmpy_b;
wire [2*AXIS_CMPY_P_WIDTH-1:0] cmpy_p;
wire cmpy_p_vld;
assign cmpy_a = {cmpy_i_imag,cmpy_i_real};
assign cmpy_b = {-cmpy_i_imag,cmpy_i_real};
assign cmpy_a = {cmpy_a_imag,cmpy_a_real};
assign cmpy_b = {cmpy_b_imag,cmpy_b_real};
assign {cmpy_p_raw_imag,cmpy_p_raw_real} = cmpy_p;
cmpy_18x18_mult u_cmpy_18x18
@@ -180,8 +211,9 @@ cmpy_18x18_mult u_cmpy_18x18
.m_axis_dout_tdata (cmpy_p ) // output wire [63 : 0] m_axis_dout_tdata
);
// accumulation
reg [DATA_O_WIDTH+$clog2(ACCUM_NUM) : 0] accum = 'b0;
reg [ACCUM_WIDTH-1 : 0] accum = 'b0;
reg [DATA_O_WIDTH-1 : 0] var_buf = 'b0;
assign var = var_buf;
@@ -200,12 +232,26 @@ always @(posedge clk) begin
end
end
always @(posedge clk) begin
if (rst) begin
var_buf <= 'b0;
if (DATA_O_WIDTH > ACCUM_WIDTH) begin
// sign-bit extension to fit output data width
always @(posedge clk) begin
if (rst) begin
var_buf <= 'b0;
end
else if (last_data_d[5]) begin
var_buf <= {{(DATA_O_WIDTH-ACCUM_WIDTH){accum[ACCUM_WIDTH-1]}},accum};
end
end
else if (last_data_d[5]) begin
var_buf <= accum[DATA_O_WIDTH+$clog2(ACCUM_NUM) -: DATA_O_WIDTH];
end
else begin
// truncate msb
always @(posedge clk) begin
if (rst) begin
var_buf <= 'b0;
end
else if (last_data_d[5]) begin
var_buf <= accum[ACCUM_WIDTH-1 -: DATA_O_WIDTH];
end
end
end
modules/xc7k410tffg900-2/var_cal/testbenches/tb_var_cal.v
+21 -5
View File
@@ -22,7 +22,10 @@
module tb_var_cal;
localparam DATA_I_WIDTH = 30;
reg clk = 1'b1;
reg clk_init = 1'b1;
reg rst = 1'b1;
reg cal_start = 1'b0;
@@ -30,13 +33,22 @@ reg cal_auto_en = 1'b0;
wire cal_busy;
reg din_valid = 1'b0;
reg [29:0] din_real = 'b0;
reg [29:0] din_imag = 'b0;
reg [29:0] din_file_real = 'b0;
reg [29:0] din_file_imag = 'b0;
wire [DATA_I_WIDTH-1:0] din_real;
wire [DATA_I_WIDTH-1:0] din_imag;
assign din_real = din_file_real[29 -: DATA_I_WIDTH];
assign din_imag = din_file_imag[29 -: DATA_I_WIDTH];
wire var_valid;
wire [31:0] var;
var_cal u_var_cal
var_cal #(
.ACCUM_NUM (16384 ),
.DATA_I_WIDTH (DATA_I_WIDTH ),
.DATA_O_WIDTH (32 )
) u_var_cal
(
.clk (clk ),
.rst (rst ),
@@ -67,12 +79,16 @@ initial begin
r_file = $fopen("./../../../../../testbenches/singletone.csv","r");
for (i = 0; i <= 32768; i = i + 1) begin
@(posedge clk)
$fscanf(r_file,"%d,%d",din_real,din_imag);
$fscanf(r_file,"%d,%d",din_file_real,din_file_imag);
end
$fclose(r_file);
$stop;
end
always #10 clk = ~clk;
always #10 clk_init = ~clk_init;
always @(posedge clk_init) begin
clk <= ~clk;
end
endmodule
projects/dl814_dj/dl814_dj_new_48m/constraints/z7100_ad9528_ad9371.xdc
+2 -2
View File
@@ -59,5 +59,5 @@ set_property -dict {PACKAGE_PIN V23 IOSTANDARD LVCMOS25} [get_ports hop_wor
set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVCMOS25} [get_ports freq_hop_switch ]
# Sync Signal
# set_property -dict {PACKAGE_PIN AD19 IOSTANDARD LVCMOS25} [get_ports sync_signal_out ] ;# Bank9, not used before
# set_property -dict {PACKAGE_PIN AD18 IOSTANDARD LVCMOS25} [get_ports sync_gnd ] ;# Bank9, not used before
set_property -dict {PACKAGE_PIN AD19 IOSTANDARD LVCMOS25} [get_ports sync_signal_out ] ;# Bank9, not used before
set_property -dict {PACKAGE_PIN AD18 IOSTANDARD LVCMOS25} [get_ports sync_gnd ] ;# Bank9, not used before
projects/dl814_dj/dl814_dj_new_48m/ip/coe/freq_word.coe
+81 -81
View File
@@ -1,83 +1,83 @@
MEMORY_INITIALIZATION_RADIX = 10;
MEMORY_INITIALIZATION_VECTOR =
1624,
1611,
1598,
1585,
1572,
1559,
1546,
1533,
1520,
1507,
1494,
1481,
1468,
1455,
1442,
1429,
1416,
1403,
1390,
1377,
1364,
1351,
1338,
1325,
1312,
1299,
1286,
1273,
1260,
1247,
1234,
1221,
1208,
1195,
1182,
1169,
1156,
1143,
1130,
1117,
1104,
1091,
1078,
1065,
1052,
1039,
1026,
1013,
1000,
987,
974,
961,
948,
935,
922,
909,
896,
883,
870,
857,
844,
831,
818,
805,
792,
779,
766,
753,
740,
727,
714,
701,
688,
675,
662,
649,
636,
623,
610,
597,
584,
2124,
2111,
2098,
2085,
2072,
2059,
2046,
2033,
2020,
2007,
1994,
1981,
1968,
1955,
1942,
1929,
1916,
1903,
1890,
1877,
1864,
1851,
1838,
1825,
1812,
1799,
1786,
1773,
1760,
1747,
1734,
1721,
1708,
1695,
1682,
1669,
1656,
1643,
1630,
1617,
1604,
1591,
1578,
1565,
1552,
1539,
1526,
1513,
1500,
1487,
1474,
1461,
1448,
1435,
1422,
1409,
1396,
1383,
1370,
1357,
1344,
1331,
1318,
1305,
1292,
1279,
1266,
1253,
1240,
1227,
1214,
1201,
1188,
1175,
1162,
1149,
1136,
1123,
1110,
1097,
1084,
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word.veo
+1 -1
View File
@@ -57,7 +57,7 @@
rom_freq_word your_instance_name (
.clka(clka), // input wire clka
.addra(addra), // input wire [6 : 0] addra
.douta(douta) // output wire [10 : 0] douta
.douta(douta) // output wire [11 : 0] douta
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word.vho
+1 -1
View File
@@ -56,7 +56,7 @@ COMPONENT rom_freq_word
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END COMPONENT;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_sim_netlist.v
LFS
BIN
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projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_sim_netlist.vhdl
LFS
BIN
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projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_stub.v
+5 -5
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@@ -1,10 +1,10 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
// Date : Mon May 8 18:56:10 2023
// Date : Sun Jul 30 18:06:27 2023
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
// Command : write_verilog -force -mode synth_stub -rename_top rom_freq_word -prefix
// rom_freq_word_ rom_freq_word_stub.v
// Command : write_verilog -force -mode synth_stub
// /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.v
// Design : rom_freq_word
// Purpose : Stub declaration of top-level module interface
// Device : xc7z100ffg900-2
@@ -15,8 +15,8 @@
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *)
module rom_freq_word(clka, addra, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,addra[6:0],douta[10:0]" */;
/* synthesis syn_black_box black_box_pad_pin="clka,addra[6:0],douta[11:0]" */;
input clka;
input [6:0]addra;
output [10:0]douta;
output [11:0]douta;
endmodule
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_stub.vhdl
+5 -5
View File
@@ -1,10 +1,10 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
-- Date : Mon May 8 18:56:10 2023
-- Date : Sun Jul 30 18:06:27 2023
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
-- Command : write_vhdl -force -mode synth_stub -rename_top rom_freq_word -prefix
-- rom_freq_word_ rom_freq_word_stub.vhdl
-- Command : write_vhdl -force -mode synth_stub
-- /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.vhdl
-- Design : rom_freq_word
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z100ffg900-2
@@ -16,7 +16,7 @@ entity rom_freq_word is
Port (
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 6 downto 0 );
douta : out STD_LOGIC_VECTOR ( 10 downto 0 )
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
end rom_freq_word;
@@ -25,7 +25,7 @@ architecture stub of rom_freq_word is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,addra[6:0],douta[10:0]";
attribute black_box_pad_pin of stub : architecture is "clka,addra[6:0],douta[11:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_3,Vivado 2019.1.3";
begin
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/sim/rom_freq_word.v
+9 -9
View File
@@ -65,7 +65,7 @@ input wire clka;
input wire [6 : 0] addra;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [10 : 0] douta;
output wire [11 : 0] douta;
blk_mem_gen_v8_4_3 #(
.C_FAMILY("zynq"),
@@ -97,8 +97,8 @@ output wire [10 : 0] douta;
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(11),
.C_READ_WIDTH_A(11),
.C_WRITE_WIDTH_A(12),
.C_READ_WIDTH_A(12),
.C_WRITE_DEPTH_A(81),
.C_READ_DEPTH_A(81),
.C_ADDRA_WIDTH(7),
@@ -111,8 +111,8 @@ output wire [10 : 0] douta;
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(11),
.C_READ_WIDTH_B(11),
.C_WRITE_WIDTH_B(12),
.C_READ_WIDTH_B(12),
.C_WRITE_DEPTH_B(81),
.C_READ_DEPTH_B(81),
.C_ADDRB_WIDTH(7),
@@ -142,7 +142,7 @@ output wire [10 : 0] douta;
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("0"),
.C_COUNT_18K_BRAM("1"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 2.5016 mW")
.C_EST_POWER_SUMMARY("Estimated Power for IP : 2.5432 mW")
) inst (
.clka(clka),
.rsta(1'D0),
@@ -150,7 +150,7 @@ output wire [10 : 0] douta;
.regcea(1'D0),
.wea(1'B0),
.addra(addra),
.dina(11'B0),
.dina(12'B0),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
@@ -158,7 +158,7 @@ output wire [10 : 0] douta;
.regceb(1'D0),
.web(1'B0),
.addrb(7'B0),
.dinb(11'B0),
.dinb(12'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
@@ -180,7 +180,7 @@ output wire [10 : 0] douta;
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(11'B0),
.s_axi_wdata(12'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/sim/vio_RF_control.v
+17 -2
View File
@@ -48,7 +48,7 @@
`timescale 1ns / 1ps
module vio_RF_control (
clk,
probe_in0,
probe_out0,
probe_out1,
probe_out2,
@@ -57,10 +57,18 @@ probe_out4,
probe_out5,
probe_out6,
probe_out7,
probe_out8
probe_out8,
probe_out9,
probe_out10,
probe_out11,
probe_out12,
probe_out13,
probe_out14,
probe_out15
);
input clk;
input [11 : 0] probe_in0;
output reg [0 : 0] probe_out0 = 'h0 ;
output reg [1 : 0] probe_out1 = 'h0 ;
@@ -71,6 +79,13 @@ output reg [11 : 0] probe_out5 = 'h3E8 ;
output reg [0 : 0] probe_out6 = 'h0 ;
output reg [0 : 0] probe_out7 = 'h0 ;
output reg [0 : 0] probe_out8 = 'h0 ;
output reg [0 : 0] probe_out9 = 'h0 ;
output reg [0 : 0] probe_out10 = 'h0 ;
output reg [0 : 0] probe_out11 = 'h0 ;
output reg [0 : 0] probe_out12 = 'h0 ;
output reg [31 : 0] probe_out13 = 'h0002EE00 ;
output reg [0 : 0] probe_out14 = 'h0 ;
output reg [31 : 0] probe_out15 = 'h0B71B000 ;
endmodule
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control.veo
+18 -10
View File
@@ -55,16 +55,24 @@
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
vio_RF_control your_instance_name (
.clk(clk), // input wire clk
.probe_out0(probe_out0), // output wire [0 : 0] probe_out0
.probe_out1(probe_out1), // output wire [1 : 0] probe_out1
.probe_out2(probe_out2), // output wire [0 : 0] probe_out2
.probe_out3(probe_out3), // output wire [7 : 0] probe_out3
.probe_out4(probe_out4), // output wire [7 : 0] probe_out4
.probe_out5(probe_out5), // output wire [11 : 0] probe_out5
.probe_out6(probe_out6), // output wire [0 : 0] probe_out6
.probe_out7(probe_out7), // output wire [0 : 0] probe_out7
.probe_out8(probe_out8) // output wire [0 : 0] probe_out8
.clk(clk), // input wire clk
.probe_in0(probe_in0), // input wire [11 : 0] probe_in0
.probe_out0(probe_out0), // output wire [0 : 0] probe_out0
.probe_out1(probe_out1), // output wire [1 : 0] probe_out1
.probe_out2(probe_out2), // output wire [0 : 0] probe_out2
.probe_out3(probe_out3), // output wire [7 : 0] probe_out3
.probe_out4(probe_out4), // output wire [7 : 0] probe_out4
.probe_out5(probe_out5), // output wire [11 : 0] probe_out5
.probe_out6(probe_out6), // output wire [0 : 0] probe_out6
.probe_out7(probe_out7), // output wire [0 : 0] probe_out7
.probe_out8(probe_out8), // output wire [0 : 0] probe_out8
.probe_out9(probe_out9), // output wire [0 : 0] probe_out9
.probe_out10(probe_out10), // output wire [0 : 0] probe_out10
.probe_out11(probe_out11), // output wire [0 : 0] probe_out11
.probe_out12(probe_out12), // output wire [0 : 0] probe_out12
.probe_out13(probe_out13), // output wire [31 : 0] probe_out13
.probe_out14(probe_out14), // output wire [0 : 0] probe_out14
.probe_out15(probe_out15) // output wire [31 : 0] probe_out15
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control.vho
+18 -2
View File
@@ -55,6 +55,7 @@
COMPONENT vio_RF_control
PORT (
clk : IN STD_LOGIC;
probe_in0 : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
probe_out1 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
probe_out2 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
@@ -63,7 +64,14 @@ COMPONENT vio_RF_control
probe_out5 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
probe_out6 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
probe_out7 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
probe_out8 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
probe_out8 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
probe_out9 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
probe_out10 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
probe_out11 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
probe_out12 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
probe_out13 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
probe_out14 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
probe_out15 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
@@ -75,6 +83,7 @@ END COMPONENT;
your_instance_name : vio_RF_control
PORT MAP (
clk => clk,
probe_in0 => probe_in0,
probe_out0 => probe_out0,
probe_out1 => probe_out1,
probe_out2 => probe_out2,
@@ -83,7 +92,14 @@ your_instance_name : vio_RF_control
probe_out5 => probe_out5,
probe_out6 => probe_out6,
probe_out7 => probe_out7,
probe_out8 => probe_out8
probe_out8 => probe_out8,
probe_out9 => probe_out9,
probe_out10 => probe_out10,
probe_out11 => probe_out11,
probe_out12 => probe_out12,
probe_out13 => probe_out13,
probe_out14 => probe_out14,
probe_out15 => probe_out15
);
-- INST_TAG_END ------ End INSTANTIATION Template ---------
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control_sim_netlist.v
LFS
BIN
View File
Binary file not shown.
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control_sim_netlist.vhdl
LFS
BIN
View File
Binary file not shown.
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control_stub.v
+14 -5
View File
@@ -1,10 +1,10 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
// Date : Tue Jun 27 16:05:58 2023
// Date : Sun Jul 30 18:20:42 2023
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
// Command : write_verilog -force -mode synth_stub
// /home/josh/Workspace/datalink_814/phy/dl814_dj_phy_ber/dl814_dj_phy_ber.runs/vio_RF_control_synth_1/vio_RF_control_stub.v
// /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control_stub.v
// Design : vio_RF_control
// Purpose : Stub declaration of top-level module interface
// Device : xc7z100ffg900-2
@@ -14,10 +14,12 @@
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
module vio_RF_control(clk, probe_out0, probe_out1, probe_out2,
probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8)
/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[7:0],probe_out4[7:0],probe_out5[11:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0]" */;
module vio_RF_control(clk, probe_in0, probe_out0, probe_out1,
probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, probe_out9,
probe_out10, probe_out11, probe_out12, probe_out13, probe_out14, probe_out15)
/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[11:0],probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[7:0],probe_out4[7:0],probe_out5[11:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0],probe_out9[0:0],probe_out10[0:0],probe_out11[0:0],probe_out12[0:0],probe_out13[31:0],probe_out14[0:0],probe_out15[31:0]" */;
input clk;
input [11:0]probe_in0;
output [0:0]probe_out0;
output [1:0]probe_out1;
output [0:0]probe_out2;
@@ -27,4 +29,11 @@ module vio_RF_control(clk, probe_out0, probe_out1, probe_out2,
output [0:0]probe_out6;
output [0:0]probe_out7;
output [0:0]probe_out8;
output [0:0]probe_out9;
output [0:0]probe_out10;
output [0:0]probe_out11;
output [0:0]probe_out12;
output [31:0]probe_out13;
output [0:0]probe_out14;
output [31:0]probe_out15;
endmodule
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control_stub.vhdl
+12 -4
View File
@@ -1,10 +1,10 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
-- Date : Tue Jun 27 16:05:58 2023
-- Date : Sun Jul 30 18:20:42 2023
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
-- Command : write_vhdl -force -mode synth_stub
-- /home/josh/Workspace/datalink_814/phy/dl814_dj_phy_ber/dl814_dj_phy_ber.runs/vio_RF_control_synth_1/vio_RF_control_stub.vhdl
-- /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control_stub.vhdl
-- Design : vio_RF_control
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z100ffg900-2
@@ -15,6 +15,7 @@ use IEEE.STD_LOGIC_1164.ALL;
entity vio_RF_control is
Port (
clk : in STD_LOGIC;
probe_in0 : in STD_LOGIC_VECTOR ( 11 downto 0 );
probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 );
@@ -23,7 +24,14 @@ entity vio_RF_control is
probe_out5 : out STD_LOGIC_VECTOR ( 11 downto 0 );
probe_out6 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out7 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out8 : out STD_LOGIC_VECTOR ( 0 to 0 )
probe_out8 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out9 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out10 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out11 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out12 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out13 : out STD_LOGIC_VECTOR ( 31 downto 0 );
probe_out14 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out15 : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end vio_RF_control;
@@ -32,7 +40,7 @@ architecture stub of vio_RF_control is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[7:0],probe_out4[7:0],probe_out5[11:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0]";
attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[11:0],probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[7:0],probe_out4[7:0],probe_out5[11:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0],probe_out9[0:0],probe_out10[0:0],probe_out11[0:0],probe_out12[0:0],probe_out13[31:0],probe_out14[0:0],probe_out15[31:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
begin
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/mem_init_files/freq_word.coe
+81 -81
View File
@@ -1,83 +1,83 @@
MEMORY_INITIALIZATION_RADIX = 10;
MEMORY_INITIALIZATION_VECTOR =
1624,
1611,
1598,
1585,
1572,
1559,
1546,
1533,
1520,
1507,
1494,
1481,
1468,
1455,
1442,
1429,
1416,
1403,
1390,
1377,
1364,
1351,
1338,
1325,
1312,
1299,
1286,
1273,
1260,
1247,
1234,
1221,
1208,
1195,
1182,
1169,
1156,
1143,
1130,
1117,
1104,
1091,
1078,
1065,
1052,
1039,
1026,
1013,
1000,
987,
974,
961,
948,
935,
922,
909,
896,
883,
870,
857,
844,
831,
818,
805,
792,
779,
766,
753,
740,
727,
714,
701,
688,
675,
662,
649,
636,
623,
610,
597,
584,
2124,
2111,
2098,
2085,
2072,
2059,
2046,
2033,
2020,
2007,
1994,
1981,
1968,
1955,
1942,
1929,
1916,
1903,
1890,
1877,
1864,
1851,
1838,
1825,
1812,
1799,
1786,
1773,
1760,
1747,
1734,
1721,
1708,
1695,
1682,
1669,
1656,
1643,
1630,
1617,
1604,
1591,
1578,
1565,
1552,
1539,
1526,
1513,
1500,
1487,
1474,
1461,
1448,
1435,
1422,
1409,
1396,
1383,
1370,
1357,
1344,
1331,
1318,
1305,
1292,
1279,
1266,
1253,
1240,
1227,
1214,
1201,
1188,
1175,
1162,
1149,
1136,
1123,
1110,
1097,
1084,
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/mem_init_files/rom_freq_word.mif
+81 -81
View File
@@ -1,81 +1,81 @@
11001011000
11001001011
11000111110
11000110001
11000100100
11000010111
11000001010
10111111101
10111110000
10111100011
10111010110
10111001001
10110111100
10110101111
10110100010
10110010101
10110001000
10101111011
10101101110
10101100001
10101010100
10101000111
10100111010
10100101101
10100100000
10100010011
10100000110
10011111001
10011101100
10011011111
10011010010
10011000101
10010111000
10010101011
10010011110
10010010001
10010000100
10001110111
10001101010
10001011101
10001010000
10001000011
10000110110
10000101001
10000011100
10000001111
10000000010
01111110101
01111101000
01111011011
01111001110
01111000001
01110110100
01110100111
01110011010
01110001101
01110000000
01101110011
01101100110
01101011001
01101001100
01100111111
01100110010
01100100101
01100011000
01100001011
01011111110
01011110001
01011100100
01011010111
01011001010
01010111101
01010110000
01010100011
01010010110
01010001001
01001111100
01001101111
01001100010
01001010101
01001001000
100001001100
100000111111
100000110010
100000100101
100000011000
100000001011
011111111110
011111110001
011111100100
011111010111
011111001010
011110111101
011110110000
011110100011
011110010110
011110001001
011101111100
011101101111
011101100010
011101010101
011101001000
011100111011
011100101110
011100100001
011100010100
011100000111
011011111010
011011101101
011011100000
011011010011
011011000110
011010111001
011010101100
011010011111
011010010010
011010000101
011001111000
011001101011
011001011110
011001010001
011001000100
011000110111
011000101010
011000011101
011000010000
011000000011
010111110110
010111101001
010111011100
010111001111
010111000010
010110110101
010110101000
010110011011
010110001110
010110000001
010101110100
010101100111
010101011010
010101001101
010101000000
010100110011
010100100110
010100011001
010100001100
010011111111
010011110010
010011100101
010011011000
010011001011
010010111110
010010110001
010010100100
010010010111
010010001010
010001111101
010001110000
010001100011
010001010110
010001001001
010000111100
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/README.txt
+1 -1
View File
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Thu May 18 11:49:45 CST 2023
# Generated by export_simulation on Sun Jul 30 18:05:42 CST 2023
#
################################################################################
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/compile.do
+3 -3
View File
@@ -10,11 +10,11 @@ vmap xpm activehdl/xpm
vmap blk_mem_gen_v8_4_3 activehdl/blk_mem_gen_v8_4_3
vlog -work xil_defaultlib -sv2k12 \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
vcom -work xpm -93 \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
vlog -work blk_mem_gen_v8_4_3 -v2k5 \
"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/file_info.txt
+3 -3
View File
@@ -1,6 +1,6 @@
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v,
glbl.v,Verilog,xil_defaultlib,glbl.v
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/freq_word.coe
+81 -81
View File
@@ -1,83 +1,83 @@
MEMORY_INITIALIZATION_RADIX = 10;
MEMORY_INITIALIZATION_VECTOR =
1624,
1611,
1598,
1585,
1572,
1559,
1546,
1533,
1520,
1507,
1494,
1481,
1468,
1455,
1442,
1429,
1416,
1403,
1390,
1377,
1364,
1351,
1338,
1325,
1312,
1299,
1286,
1273,
1260,
1247,
1234,
1221,
1208,
1195,
1182,
1169,
1156,
1143,
1130,
1117,
1104,
1091,
1078,
1065,
1052,
1039,
1026,
1013,
1000,
987,
974,
961,
948,
935,
922,
909,
896,
883,
870,
857,
844,
831,
818,
805,
792,
779,
766,
753,
740,
727,
714,
701,
688,
675,
662,
649,
636,
623,
610,
597,
584,
2124,
2111,
2098,
2085,
2072,
2059,
2046,
2033,
2020,
2007,
1994,
1981,
1968,
1955,
1942,
1929,
1916,
1903,
1890,
1877,
1864,
1851,
1838,
1825,
1812,
1799,
1786,
1773,
1760,
1747,
1734,
1721,
1708,
1695,
1682,
1669,
1656,
1643,
1630,
1617,
1604,
1591,
1578,
1565,
1552,
1539,
1526,
1513,
1500,
1487,
1474,
1461,
1448,
1435,
1422,
1409,
1396,
1383,
1370,
1357,
1344,
1331,
1318,
1305,
1292,
1279,
1266,
1253,
1240,
1227,
1214,
1201,
1188,
1175,
1162,
1149,
1136,
1123,
1110,
1097,
1084,
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/rom_freq_word.mif
+81 -81
View File
@@ -1,81 +1,81 @@
11001011000
11001001011
11000111110
11000110001
11000100100
11000010111
11000001010
10111111101
10111110000
10111100011
10111010110
10111001001
10110111100
10110101111
10110100010
10110010101
10110001000
10101111011
10101101110
10101100001
10101010100
10101000111
10100111010
10100101101
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10100000110
10011111001
10011101100
10011011111
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10010011110
10010010001
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10001110111
10001101010
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10000001111
10000000010
01111110101
01111101000
01111011011
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01111000001
01110110100
01110100111
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01110001101
01110000000
01101110011
01101100110
01101011001
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01010111101
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01010100011
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01001101111
01001100010
01001010101
01001001000
100001001100
100000111111
100000110010
100000100101
100000011000
100000001011
011111111110
011111110001
011111100100
011111010111
011111001010
011110111101
011110110000
011110100011
011110010110
011110001001
011101111100
011101101111
011101100010
011101010101
011101001000
011100111011
011100101110
011100100001
011100010100
011100000111
011011111010
011011101101
011011100000
011011010011
011011000110
011010111001
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011010011111
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011000000011
010111110110
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010110001110
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010101110100
010101100111
010101011010
010101001101
010101000000
010100110011
010100100110
010100011001
010100001100
010011111111
010011110010
010011100101
010011011000
010011001011
010010111110
010010110001
010010100100
010010010111
010010001010
010001111101
010001110000
010001100011
010001010110
010001001001
010000111100
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/rom_freq_word.sh
+1 -1
View File
@@ -9,7 +9,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Thu May 18 11:49:45 CST 2023
# Generated by Vivado on Sun Jul 30 18:05:42 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/README.txt
+1 -1
View File
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Thu May 18 11:49:45 CST 2023
# Generated by export_simulation on Sun Jul 30 18:05:42 CST 2023
#
################################################################################
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/file_info.txt
+3 -3
View File
@@ -1,6 +1,6 @@
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v,
glbl.v,Verilog,xil_defaultlib,glbl.v
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/freq_word.coe
+81 -81
View File
@@ -1,83 +1,83 @@
MEMORY_INITIALIZATION_RADIX = 10;
MEMORY_INITIALIZATION_VECTOR =
1624,
1611,
1598,
1585,
1572,
1559,
1546,
1533,
1520,
1507,
1494,
1481,
1468,
1455,
1442,
1429,
1416,
1403,
1390,
1377,
1364,
1351,
1338,
1325,
1312,
1299,
1286,
1273,
1260,
1247,
1234,
1221,
1208,
1195,
1182,
1169,
1156,
1143,
1130,
1117,
1104,
1091,
1078,
1065,
1052,
1039,
1026,
1013,
1000,
987,
974,
961,
948,
935,
922,
909,
896,
883,
870,
857,
844,
831,
818,
805,
792,
779,
766,
753,
740,
727,
714,
701,
688,
675,
662,
649,
636,
623,
610,
597,
584,
2124,
2111,
2098,
2085,
2072,
2059,
2046,
2033,
2020,
2007,
1994,
1981,
1968,
1955,
1942,
1929,
1916,
1903,
1890,
1877,
1864,
1851,
1838,
1825,
1812,
1799,
1786,
1773,
1760,
1747,
1734,
1721,
1708,
1695,
1682,
1669,
1656,
1643,
1630,
1617,
1604,
1591,
1578,
1565,
1552,
1539,
1526,
1513,
1500,
1487,
1474,
1461,
1448,
1435,
1422,
1409,
1396,
1383,
1370,
1357,
1344,
1331,
1318,
1305,
1292,
1279,
1266,
1253,
1240,
1227,
1214,
1201,
1188,
1175,
1162,
1149,
1136,
1123,
1110,
1097,
1084,
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/rom_freq_word.mif
+81 -81
View File
@@ -1,81 +1,81 @@
11001011000
11001001011
11000111110
11000110001
11000100100
11000010111
11000001010
10111111101
10111110000
10111100011
10111010110
10111001001
10110111100
10110101111
10110100010
10110010101
10110001000
10101111011
10101101110
10101100001
10101010100
10101000111
10100111010
10100101101
10100100000
10100010011
10100000110
10011111001
10011101100
10011011111
10011010010
10011000101
10010111000
10010101011
10010011110
10010010001
10010000100
10001110111
10001101010
10001011101
10001010000
10001000011
10000110110
10000101001
10000011100
10000001111
10000000010
01111110101
01111101000
01111011011
01111001110
01111000001
01110110100
01110100111
01110011010
01110001101
01110000000
01101110011
01101100110
01101011001
01101001100
01100111111
01100110010
01100100101
01100011000
01100001011
01011111110
01011110001
01011100100
01011010111
01011001010
01010111101
01010110000
01010100011
01010010110
01010001001
01001111100
01001101111
01001100010
01001010101
01001001000
100001001100
100000111111
100000110010
100000100101
100000011000
100000001011
011111111110
011111110001
011111100100
011111010111
011111001010
011110111101
011110110000
011110100011
011110010110
011110001001
011101111100
011101101111
011101100010
011101010101
011101001000
011100111011
011100101110
011100100001
011100010100
011100000111
011011111010
011011101101
011011100000
011011010011
011011000110
011010111001
011010101100
011010011111
011010010010
011010000101
011001111000
011001101011
011001011110
011001010001
011001000100
011000110111
011000101010
011000011101
011000010000
011000000011
010111110110
010111101001
010111011100
010111001111
010111000010
010110110101
010110101000
010110011011
010110001110
010110000001
010101110100
010101100111
010101011010
010101001101
010101000000
010100110011
010100100110
010100011001
010100001100
010011111111
010011110010
010011100101
010011011000
010011001011
010010111110
010010110001
010010100100
010010010111
010010001010
010001111101
010001110000
010001100011
010001010110
010001001001
010000111100
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/rom_freq_word.sh
+1 -1
View File
@@ -9,7 +9,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Thu May 18 11:49:45 CST 2023
# Generated by Vivado on Sun Jul 30 18:05:42 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/run.f
+3 -3
View File
@@ -1,9 +1,9 @@
-makelib ies_lib/xil_defaultlib -sv \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
-endlib
-makelib ies_lib/xpm \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
-endlib
-makelib ies_lib/blk_mem_gen_v8_4_3 \
"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/README.txt
+1 -1
View File
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Thu May 18 11:49:45 CST 2023
# Generated by export_simulation on Sun Jul 30 18:05:42 CST 2023
#
################################################################################
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/freq_word.coe
+81 -81
View File
@@ -1,83 +1,83 @@
MEMORY_INITIALIZATION_RADIX = 10;
MEMORY_INITIALIZATION_VECTOR =
1624,
1611,
1598,
1585,
1572,
1559,
1546,
1533,
1520,
1507,
1494,
1481,
1468,
1455,
1442,
1429,
1416,
1403,
1390,
1377,
1364,
1351,
1338,
1325,
1312,
1299,
1286,
1273,
1260,
1247,
1234,
1221,
1208,
1195,
1182,
1169,
1156,
1143,
1130,
1117,
1104,
1091,
1078,
1065,
1052,
1039,
1026,
1013,
1000,
987,
974,
961,
948,
935,
922,
909,
896,
883,
870,
857,
844,
831,
818,
805,
792,
779,
766,
753,
740,
727,
714,
701,
688,
675,
662,
649,
636,
623,
610,
597,
584,
2124,
2111,
2098,
2085,
2072,
2059,
2046,
2033,
2020,
2007,
1994,
1981,
1968,
1955,
1942,
1929,
1916,
1903,
1890,
1877,
1864,
1851,
1838,
1825,
1812,
1799,
1786,
1773,
1760,
1747,
1734,
1721,
1708,
1695,
1682,
1669,
1656,
1643,
1630,
1617,
1604,
1591,
1578,
1565,
1552,
1539,
1526,
1513,
1500,
1487,
1474,
1461,
1448,
1435,
1422,
1409,
1396,
1383,
1370,
1357,
1344,
1331,
1318,
1305,
1292,
1279,
1266,
1253,
1240,
1227,
1214,
1201,
1188,
1175,
1162,
1149,
1136,
1123,
1110,
1097,
1084,
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/rom_freq_word.mif
+81 -81
View File
@@ -1,81 +1,81 @@
11001011000
11001001011
11000111110
11000110001
11000100100
11000010111
11000001010
10111111101
10111110000
10111100011
10111010110
10111001001
10110111100
10110101111
10110100010
10110010101
10110001000
10101111011
10101101110
10101100001
10101010100
10101000111
10100111010
10100101101
10100100000
10100010011
10100000110
10011111001
10011101100
10011011111
10011010010
10011000101
10010111000
10010101011
10010011110
10010010001
10010000100
10001110111
10001101010
10001011101
10001010000
10001000011
10000110110
10000101001
10000011100
10000001111
10000000010
01111110101
01111101000
01111011011
01111001110
01111000001
01110110100
01110100111
01110011010
01110001101
01110000000
01101110011
01101100110
01101011001
01101001100
01100111111
01100110010
01100100101
01100011000
01100001011
01011111110
01011110001
01011100100
01011010111
01011001010
01010111101
01010110000
01010100011
01010010110
01010001001
01001111100
01001101111
01001100010
01001010101
01001001000
100001001100
100000111111
100000110010
100000100101
100000011000
100000001011
011111111110
011111110001
011111100100
011111010111
011111001010
011110111101
011110110000
011110100011
011110010110
011110001001
011101111100
011101101111
011101100010
011101010101
011101001000
011100111011
011100101110
011100100001
011100010100
011100000111
011011111010
011011101101
011011100000
011011010011
011011000110
011010111001
011010101100
011010011111
011010010010
011010000101
011001111000
011001101011
011001011110
011001010001
011001000100
011000110111
011000101010
011000011101
011000010000
011000000011
010111110110
010111101001
010111011100
010111001111
010111000010
010110110101
010110101000
010110011011
010110001110
010110000001
010101110100
010101100111
010101011010
010101001101
010101000000
010100110011
010100100110
010100011001
010100001100
010011111111
010011110010
010011100101
010011011000
010011001011
010010111110
010010110001
010010100100
010010010111
010010001010
010001111101
010001110000
010001100011
010001010110
010001001001
010000111100
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/rom_freq_word.sh
+1 -1
View File
@@ -9,7 +9,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Thu May 18 11:49:45 CST 2023
# Generated by Vivado on Sun Jul 30 18:05:42 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/README.txt
+1 -1
View File
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Thu May 18 11:49:45 CST 2023
# Generated by export_simulation on Sun Jul 30 18:05:42 CST 2023
#
################################################################################
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/compile.do
+3 -3
View File
@@ -10,11 +10,11 @@ vmap xpm questa_lib/msim/xpm
vmap blk_mem_gen_v8_4_3 questa_lib/msim/blk_mem_gen_v8_4_3
vlog -work xil_defaultlib -64 -sv \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
vcom -work xpm -64 -93 \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
vlog -work blk_mem_gen_v8_4_3 -64 \
"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/file_info.txt
+3 -3
View File
@@ -1,6 +1,6 @@
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v,
glbl.v,Verilog,xil_defaultlib,glbl.v
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/freq_word.coe
+81 -81
View File
@@ -1,83 +1,83 @@
MEMORY_INITIALIZATION_RADIX = 10;
MEMORY_INITIALIZATION_VECTOR =
1624,
1611,
1598,
1585,
1572,
1559,
1546,
1533,
1520,
1507,
1494,
1481,
1468,
1455,
1442,
1429,
1416,
1403,
1390,
1377,
1364,
1351,
1338,
1325,
1312,
1299,
1286,
1273,
1260,
1247,
1234,
1221,
1208,
1195,
1182,
1169,
1156,
1143,
1130,
1117,
1104,
1091,
1078,
1065,
1052,
1039,
1026,
1013,
1000,
987,
974,
961,
948,
935,
922,
909,
896,
883,
870,
857,
844,
831,
818,
805,
792,
779,
766,
753,
740,
727,
714,
701,
688,
675,
662,
649,
636,
623,
610,
597,
584,
2124,
2111,
2098,
2085,
2072,
2059,
2046,
2033,
2020,
2007,
1994,
1981,
1968,
1955,
1942,
1929,
1916,
1903,
1890,
1877,
1864,
1851,
1838,
1825,
1812,
1799,
1786,
1773,
1760,
1747,
1734,
1721,
1708,
1695,
1682,
1669,
1656,
1643,
1630,
1617,
1604,
1591,
1578,
1565,
1552,
1539,
1526,
1513,
1500,
1487,
1474,
1461,
1448,
1435,
1422,
1409,
1396,
1383,
1370,
1357,
1344,
1331,
1318,
1305,
1292,
1279,
1266,
1253,
1240,
1227,
1214,
1201,
1188,
1175,
1162,
1149,
1136,
1123,
1110,
1097,
1084,
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/rom_freq_word.mif
+81 -81
View File
@@ -1,81 +1,81 @@
11001011000
11001001011
11000111110
11000110001
11000100100
11000010111
11000001010
10111111101
10111110000
10111100011
10111010110
10111001001
10110111100
10110101111
10110100010
10110010101
10110001000
10101111011
10101101110
10101100001
10101010100
10101000111
10100111010
10100101101
10100100000
10100010011
10100000110
10011111001
10011101100
10011011111
10011010010
10011000101
10010111000
10010101011
10010011110
10010010001
10010000100
10001110111
10001101010
10001011101
10001010000
10001000011
10000110110
10000101001
10000011100
10000001111
10000000010
01111110101
01111101000
01111011011
01111001110
01111000001
01110110100
01110100111
01110011010
01110001101
01110000000
01101110011
01101100110
01101011001
01101001100
01100111111
01100110010
01100100101
01100011000
01100001011
01011111110
01011110001
01011100100
01011010111
01011001010
01010111101
01010110000
01010100011
01010010110
01010001001
01001111100
01001101111
01001100010
01001010101
01001001000
100001001100
100000111111
100000110010
100000100101
100000011000
100000001011
011111111110
011111110001
011111100100
011111010111
011111001010
011110111101
011110110000
011110100011
011110010110
011110001001
011101111100
011101101111
011101100010
011101010101
011101001000
011100111011
011100101110
011100100001
011100010100
011100000111
011011111010
011011101101
011011100000
011011010011
011011000110
011010111001
011010101100
011010011111
011010010010
011010000101
011001111000
011001101011
011001011110
011001010001
011001000100
011000110111
011000101010
011000011101
011000010000
011000000011
010111110110
010111101001
010111011100
010111001111
010111000010
010110110101
010110101000
010110011011
010110001110
010110000001
010101110100
010101100111
010101011010
010101001101
010101000000
010100110011
010100100110
010100011001
010100001100
010011111111
010011110010
010011100101
010011011000
010011001011
010010111110
010010110001
010010100100
010010010111
010010001010
010001111101
010001110000
010001100011
010001010110
010001001001
010000111100
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/rom_freq_word.sh
+1 -1
View File
@@ -9,7 +9,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Thu May 18 11:49:45 CST 2023
# Generated by Vivado on Sun Jul 30 18:05:42 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/README.txt
+1 -1
View File
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Thu May 18 11:49:45 CST 2023
# Generated by export_simulation on Sun Jul 30 18:05:42 CST 2023
#
################################################################################
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/compile.do
+3 -3
View File
@@ -10,11 +10,11 @@ vmap xpm riviera/xpm
vmap blk_mem_gen_v8_4_3 riviera/blk_mem_gen_v8_4_3
vlog -work xil_defaultlib -sv2k12 \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
vcom -work xpm -93 \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
vlog -work blk_mem_gen_v8_4_3 -v2k5 \
"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/file_info.txt
+3 -3
View File
@@ -1,6 +1,6 @@
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v,
glbl.v,Verilog,xil_defaultlib,glbl.v
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/freq_word.coe
+81 -81
View File
@@ -1,83 +1,83 @@
MEMORY_INITIALIZATION_RADIX = 10;
MEMORY_INITIALIZATION_VECTOR =
1624,
1611,
1598,
1585,
1572,
1559,
1546,
1533,
1520,
1507,
1494,
1481,
1468,
1455,
1442,
1429,
1416,
1403,
1390,
1377,
1364,
1351,
1338,
1325,
1312,
1299,
1286,
1273,
1260,
1247,
1234,
1221,
1208,
1195,
1182,
1169,
1156,
1143,
1130,
1117,
1104,
1091,
1078,
1065,
1052,
1039,
1026,
1013,
1000,
987,
974,
961,
948,
935,
922,
909,
896,
883,
870,
857,
844,
831,
818,
805,
792,
779,
766,
753,
740,
727,
714,
701,
688,
675,
662,
649,
636,
623,
610,
597,
584,
2124,
2111,
2098,
2085,
2072,
2059,
2046,
2033,
2020,
2007,
1994,
1981,
1968,
1955,
1942,
1929,
1916,
1903,
1890,
1877,
1864,
1851,
1838,
1825,
1812,
1799,
1786,
1773,
1760,
1747,
1734,
1721,
1708,
1695,
1682,
1669,
1656,
1643,
1630,
1617,
1604,
1591,
1578,
1565,
1552,
1539,
1526,
1513,
1500,
1487,
1474,
1461,
1448,
1435,
1422,
1409,
1396,
1383,
1370,
1357,
1344,
1331,
1318,
1305,
1292,
1279,
1266,
1253,
1240,
1227,
1214,
1201,
1188,
1175,
1162,
1149,
1136,
1123,
1110,
1097,
1084,
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/rom_freq_word.mif
+81 -81
View File
@@ -1,81 +1,81 @@
11001011000
11001001011
11000111110
11000110001
11000100100
11000010111
11000001010
10111111101
10111110000
10111100011
10111010110
10111001001
10110111100
10110101111
10110100010
10110010101
10110001000
10101111011
10101101110
10101100001
10101010100
10101000111
10100111010
10100101101
10100100000
10100010011
10100000110
10011111001
10011101100
10011011111
10011010010
10011000101
10010111000
10010101011
10010011110
10010010001
10010000100
10001110111
10001101010
10001011101
10001010000
10001000011
10000110110
10000101001
10000011100
10000001111
10000000010
01111110101
01111101000
01111011011
01111001110
01111000001
01110110100
01110100111
01110011010
01110001101
01110000000
01101110011
01101100110
01101011001
01101001100
01100111111
01100110010
01100100101
01100011000
01100001011
01011111110
01011110001
01011100100
01011010111
01011001010
01010111101
01010110000
01010100011
01010010110
01010001001
01001111100
01001101111
01001100010
01001010101
01001001000
100001001100
100000111111
100000110010
100000100101
100000011000
100000001011
011111111110
011111110001
011111100100
011111010111
011111001010
011110111101
011110110000
011110100011
011110010110
011110001001
011101111100
011101101111
011101100010
011101010101
011101001000
011100111011
011100101110
011100100001
011100010100
011100000111
011011111010
011011101101
011011100000
011011010011
011011000110
011010111001
011010101100
011010011111
011010010010
011010000101
011001111000
011001101011
011001011110
011001010001
011001000100
011000110111
011000101010
011000011101
011000010000
011000000011
010111110110
010111101001
010111011100
010111001111
010111000010
010110110101
010110101000
010110011011
010110001110
010110000001
010101110100
010101100111
010101011010
010101001101
010101000000
010100110011
010100100110
010100011001
010100001100
010011111111
010011110010
010011100101
010011011000
010011001011
010010111110
010010110001
010010100100
010010010111
010010001010
010001111101
010001110000
010001100011
010001010110
010001001001
010000111100
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/rom_freq_word.sh
+1 -1
View File
@@ -9,7 +9,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Thu May 18 11:49:45 CST 2023
# Generated by Vivado on Sun Jul 30 18:05:42 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/README.txt
+1 -1
View File
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Thu May 18 11:49:45 CST 2023
# Generated by export_simulation on Sun Jul 30 18:05:42 CST 2023
#
################################################################################
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/freq_word.coe
+81 -81
View File
@@ -1,83 +1,83 @@
MEMORY_INITIALIZATION_RADIX = 10;
MEMORY_INITIALIZATION_VECTOR =
1624,
1611,
1598,
1585,
1572,
1559,
1546,
1533,
1520,
1507,
1494,
1481,
1468,
1455,
1442,
1429,
1416,
1403,
1390,
1377,
1364,
1351,
1338,
1325,
1312,
1299,
1286,
1273,
1260,
1247,
1234,
1221,
1208,
1195,
1182,
1169,
1156,
1143,
1130,
1117,
1104,
1091,
1078,
1065,
1052,
1039,
1026,
1013,
1000,
987,
974,
961,
948,
935,
922,
909,
896,
883,
870,
857,
844,
831,
818,
805,
792,
779,
766,
753,
740,
727,
714,
701,
688,
675,
662,
649,
636,
623,
610,
597,
584,
2124,
2111,
2098,
2085,
2072,
2059,
2046,
2033,
2020,
2007,
1994,
1981,
1968,
1955,
1942,
1929,
1916,
1903,
1890,
1877,
1864,
1851,
1838,
1825,
1812,
1799,
1786,
1773,
1760,
1747,
1734,
1721,
1708,
1695,
1682,
1669,
1656,
1643,
1630,
1617,
1604,
1591,
1578,
1565,
1552,
1539,
1526,
1513,
1500,
1487,
1474,
1461,
1448,
1435,
1422,
1409,
1396,
1383,
1370,
1357,
1344,
1331,
1318,
1305,
1292,
1279,
1266,
1253,
1240,
1227,
1214,
1201,
1188,
1175,
1162,
1149,
1136,
1123,
1110,
1097,
1084,
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/rom_freq_word.mif
+81 -81
View File
@@ -1,81 +1,81 @@
11001011000
11001001011
11000111110
11000110001
11000100100
11000010111
11000001010
10111111101
10111110000
10111100011
10111010110
10111001001
10110111100
10110101111
10110100010
10110010101
10110001000
10101111011
10101101110
10101100001
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10100000110
10011111001
10011101100
10011011111
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10010101011
10010011110
10010010001
10010000100
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10001101010
10001011101
10001010000
10001000011
10000110110
10000101001
10000011100
10000001111
10000000010
01111110101
01111101000
01111011011
01111001110
01111000001
01110110100
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01110011010
01110001101
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01101110011
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01100111111
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01100100101
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01100001011
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01011110001
01011100100
01011010111
01011001010
01010111101
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01010100011
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01001111100
01001101111
01001100010
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01001001000
100001001100
100000111111
100000110010
100000100101
100000011000
100000001011
011111111110
011111110001
011111100100
011111010111
011111001010
011110111101
011110110000
011110100011
011110010110
011110001001
011101111100
011101101111
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011000101010
011000011101
011000010000
011000000011
010111110110
010111101001
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010111000010
010110110101
010110101000
010110011011
010110001110
010110000001
010101110100
010101100111
010101011010
010101001101
010101000000
010100110011
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010100011001
010100001100
010011111111
010011110010
010011100101
010011011000
010011001011
010010111110
010010110001
010010100100
010010010111
010010001010
010001111101
010001110000
010001100011
010001010110
010001001001
010000111100
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/rom_freq_word.sh
+1 -1
View File
@@ -9,7 +9,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Thu May 18 11:49:45 CST 2023
# Generated by Vivado on Sun Jul 30 18:05:42 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/README.txt
+1 -1
View File
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Thu May 18 11:49:45 CST 2023
# Generated by export_simulation on Sun Jul 30 18:05:42 CST 2023
#
################################################################################
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/file_info.txt
+3 -3
View File
@@ -1,6 +1,6 @@
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v,
glbl.v,Verilog,xil_defaultlib,glbl.v
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/freq_word.coe
+81 -81
View File
@@ -1,83 +1,83 @@
MEMORY_INITIALIZATION_RADIX = 10;
MEMORY_INITIALIZATION_VECTOR =
1624,
1611,
1598,
1585,
1572,
1559,
1546,
1533,
1520,
1507,
1494,
1481,
1468,
1455,
1442,
1429,
1416,
1403,
1390,
1377,
1364,
1351,
1338,
1325,
1312,
1299,
1286,
1273,
1260,
1247,
1234,
1221,
1208,
1195,
1182,
1169,
1156,
1143,
1130,
1117,
1104,
1091,
1078,
1065,
1052,
1039,
1026,
1013,
1000,
987,
974,
961,
948,
935,
922,
909,
896,
883,
870,
857,
844,
831,
818,
805,
792,
779,
766,
753,
740,
727,
714,
701,
688,
675,
662,
649,
636,
623,
610,
597,
584,
2124,
2111,
2098,
2085,
2072,
2059,
2046,
2033,
2020,
2007,
1994,
1981,
1968,
1955,
1942,
1929,
1916,
1903,
1890,
1877,
1864,
1851,
1838,
1825,
1812,
1799,
1786,
1773,
1760,
1747,
1734,
1721,
1708,
1695,
1682,
1669,
1656,
1643,
1630,
1617,
1604,
1591,
1578,
1565,
1552,
1539,
1526,
1513,
1500,
1487,
1474,
1461,
1448,
1435,
1422,
1409,
1396,
1383,
1370,
1357,
1344,
1331,
1318,
1305,
1292,
1279,
1266,
1253,
1240,
1227,
1214,
1201,
1188,
1175,
1162,
1149,
1136,
1123,
1110,
1097,
1084,
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/rom_freq_word.mif
+81 -81
View File
@@ -1,81 +1,81 @@
11001011000
11001001011
11000111110
11000110001
11000100100
11000010111
11000001010
10111111101
10111110000
10111100011
10111010110
10111001001
10110111100
10110101111
10110100010
10110010101
10110001000
10101111011
10101101110
10101100001
10101010100
10101000111
10100111010
10100101101
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10100000110
10011111001
10011101100
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10010111000
10010101011
10010011110
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10000001111
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01111110101
01111101000
01111011011
01111001110
01111000001
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01110100111
01110011010
01110001101
01110000000
01101110011
01101100110
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01101001100
01100111111
01100110010
01100100101
01100011000
01100001011
01011111110
01011110001
01011100100
01011010111
01011001010
01010111101
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01010100011
01010010110
01010001001
01001111100
01001101111
01001100010
01001010101
01001001000
100001001100
100000111111
100000110010
100000100101
100000011000
100000001011
011111111110
011111110001
011111100100
011111010111
011111001010
011110111101
011110110000
011110100011
011110010110
011110001001
011101111100
011101101111
011101100010
011101010101
011101001000
011100111011
011100101110
011100100001
011100010100
011100000111
011011111010
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011011100000
011011010011
011011000110
011010111001
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011010011111
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011010000101
011001111000
011001101011
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011001000100
011000110111
011000101010
011000011101
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011000000011
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010111000010
010110110101
010110101000
010110011011
010110001110
010110000001
010101110100
010101100111
010101011010
010101001101
010101000000
010100110011
010100100110
010100011001
010100001100
010011111111
010011110010
010011100101
010011011000
010011001011
010010111110
010010110001
010010100100
010010010111
010010001010
010001111101
010001110000
010001100011
010001010110
010001001001
010000111100
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/rom_freq_word.sh
+1 -1
View File
@@ -9,7 +9,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Thu May 18 11:49:45 CST 2023
# Generated by Vivado on Sun Jul 30 18:05:42 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/run.f
+3 -3
View File
@@ -1,9 +1,9 @@
-makelib xcelium_lib/xil_defaultlib -sv \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
-endlib
-makelib xcelium_lib/xpm \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
-endlib
-makelib xcelium_lib/blk_mem_gen_v8_4_3 \
"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/README.txt
+1 -1
View File
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Thu May 18 11:49:45 CST 2023
# Generated by export_simulation on Sun Jul 30 18:05:42 CST 2023
#
################################################################################
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/freq_word.coe
+81 -81
View File
@@ -1,83 +1,83 @@
MEMORY_INITIALIZATION_RADIX = 10;
MEMORY_INITIALIZATION_VECTOR =
1624,
1611,
1598,
1585,
1572,
1559,
1546,
1533,
1520,
1507,
1494,
1481,
1468,
1455,
1442,
1429,
1416,
1403,
1390,
1377,
1364,
1351,
1338,
1325,
1312,
1299,
1286,
1273,
1260,
1247,
1234,
1221,
1208,
1195,
1182,
1169,
1156,
1143,
1130,
1117,
1104,
1091,
1078,
1065,
1052,
1039,
1026,
1013,
1000,
987,
974,
961,
948,
935,
922,
909,
896,
883,
870,
857,
844,
831,
818,
805,
792,
779,
766,
753,
740,
727,
714,
701,
688,
675,
662,
649,
636,
623,
610,
597,
584,
2124,
2111,
2098,
2085,
2072,
2059,
2046,
2033,
2020,
2007,
1994,
1981,
1968,
1955,
1942,
1929,
1916,
1903,
1890,
1877,
1864,
1851,
1838,
1825,
1812,
1799,
1786,
1773,
1760,
1747,
1734,
1721,
1708,
1695,
1682,
1669,
1656,
1643,
1630,
1617,
1604,
1591,
1578,
1565,
1552,
1539,
1526,
1513,
1500,
1487,
1474,
1461,
1448,
1435,
1422,
1409,
1396,
1383,
1370,
1357,
1344,
1331,
1318,
1305,
1292,
1279,
1266,
1253,
1240,
1227,
1214,
1201,
1188,
1175,
1162,
1149,
1136,
1123,
1110,
1097,
1084,
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/rom_freq_word.mif
+81 -81
View File
@@ -1,81 +1,81 @@
11001011000
11001001011
11000111110
11000110001
11000100100
11000010111
11000001010
10111111101
10111110000
10111100011
10111010110
10111001001
10110111100
10110101111
10110100010
10110010101
10110001000
10101111011
10101101110
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10100101101
10100100000
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10100000110
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10011101100
10011011111
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10010101011
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10010010001
10010000100
10001110111
10001101010
10001011101
10001010000
10001000011
10000110110
10000101001
10000011100
10000001111
10000000010
01111110101
01111101000
01111011011
01111001110
01111000001
01110110100
01110100111
01110011010
01110001101
01110000000
01101110011
01101100110
01101011001
01101001100
01100111111
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01100100101
01100011000
01100001011
01011111110
01011110001
01011100100
01011010111
01011001010
01010111101
01010110000
01010100011
01010010110
01010001001
01001111100
01001101111
01001100010
01001010101
01001001000
100001001100
100000111111
100000110010
100000100101
100000011000
100000001011
011111111110
011111110001
011111100100
011111010111
011111001010
011110111101
011110110000
011110100011
011110010110
011110001001
011101111100
011101101111
011101100010
011101010101
011101001000
011100111011
011100101110
011100100001
011100010100
011100000111
011011111010
011011101101
011011100000
011011010011
011011000110
011010111001
011010101100
011010011111
011010010010
011010000101
011001111000
011001101011
011001011110
011001010001
011001000100
011000110111
011000101010
011000011101
011000010000
011000000011
010111110110
010111101001
010111011100
010111001111
010111000010
010110110101
010110101000
010110011011
010110001110
010110000001
010101110100
010101100111
010101011010
010101001101
010101000000
010100110011
010100100110
010100011001
010100001100
010011111111
010011110010
010011100101
010011011000
010011001011
010010111110
010010110001
010010100100
010010010111
010010001010
010001111101
010001110000
010001100011
010001010110
010001001001
010000111100
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/rom_freq_word.sh
+3 -3
View File
@@ -9,7 +9,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Thu May 18 11:49:45 CST 2023
# Generated by Vivado on Sun Jul 30 18:05:42 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
@@ -22,7 +22,7 @@
#*********************************************************************************************************
# Command line options
xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0
xv_boost_lib_path=/home/josh/Software/Xilinx/Vivado/2019.1/tps/boost_1_64_0
xvlog_opts="--relax"
@@ -92,7 +92,7 @@ setup()
copy_setup_file()
{
file="xsim.ini"
lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim"
lib_map_path="/home/josh/Software/Xilinx/Vivado/2019.1/data/xsim"
if [[ ($1 != "") ]]; then
lib_map_path="$1"
fi
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/activehdl/README.txt
+1 -1
View File
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Mon Jul 03 19:45:40 CST 2023
# Generated by export_simulation on Sun Jul 30 18:20:24 CST 2023
#
################################################################################
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/activehdl/vio_RF_control.sh
+1 -1
View File
@@ -9,7 +9,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Mon Jul 03 19:45:40 CST 2023
# Generated by Vivado on Sun Jul 30 18:20:24 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/ies/README.txt
+1 -1
View File
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Mon Jul 03 19:45:40 CST 2023
# Generated by export_simulation on Sun Jul 30 18:20:24 CST 2023
#
################################################################################
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/ies/vio_RF_control.sh
+1 -1
View File
@@ -9,7 +9,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Mon Jul 03 19:45:40 CST 2023
# Generated by Vivado on Sun Jul 30 18:20:24 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/modelsim/README.txt
+1 -1
View File
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Mon Jul 03 19:45:40 CST 2023
# Generated by export_simulation on Sun Jul 30 18:20:24 CST 2023
#
################################################################################
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/modelsim/vio_RF_control.sh
+1 -1
View File
@@ -9,7 +9,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Mon Jul 03 19:45:40 CST 2023
# Generated by Vivado on Sun Jul 30 18:20:24 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/questa/README.txt
+1 -1
View File
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Mon Jul 03 19:45:40 CST 2023
# Generated by export_simulation on Sun Jul 30 18:20:24 CST 2023
#
################################################################################
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/questa/vio_RF_control.sh
+1 -1
View File
@@ -9,7 +9,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Mon Jul 03 19:45:40 CST 2023
# Generated by Vivado on Sun Jul 30 18:20:24 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/riviera/README.txt
+1 -1
View File
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Mon Jul 03 19:45:40 CST 2023
# Generated by export_simulation on Sun Jul 30 18:20:24 CST 2023
#
################################################################################
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/riviera/vio_RF_control.sh
+1 -1
View File
@@ -9,7 +9,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Mon Jul 03 19:45:40 CST 2023
# Generated by Vivado on Sun Jul 30 18:20:24 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/vcs/README.txt
+1 -1
View File
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Mon Jul 03 19:45:40 CST 2023
# Generated by export_simulation on Sun Jul 30 18:20:24 CST 2023
#
################################################################################
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/vcs/vio_RF_control.sh
+1 -1
View File
@@ -9,7 +9,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Mon Jul 03 19:45:40 CST 2023
# Generated by Vivado on Sun Jul 30 18:20:24 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xcelium/README.txt
+1 -1
View File
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Mon Jul 03 19:45:40 CST 2023
# Generated by export_simulation on Sun Jul 30 18:20:24 CST 2023
#
################################################################################
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xcelium/vio_RF_control.sh
+1 -1
View File
@@ -9,7 +9,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Mon Jul 03 19:45:40 CST 2023
# Generated by Vivado on Sun Jul 30 18:20:24 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xsim/README.txt
+1 -1
View File
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Mon Jul 03 19:45:40 CST 2023
# Generated by export_simulation on Sun Jul 30 18:20:24 CST 2023
#
################################################################################
projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xsim/vio_RF_control.sh
+1 -1
View File
@@ -9,7 +9,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Mon Jul 03 19:45:40 CST 2023
# Generated by Vivado on Sun Jul 30 18:20:24 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/7727187e03eca7b1/7727187e03eca7b1.xci
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<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/7727187e03eca7b1/rom_freq_word.dcp
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projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/7727187e03eca7b1/rom_freq_word_sim_netlist.v
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projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/7727187e03eca7b1/rom_freq_word_sim_netlist.vhdl
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projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/7727187e03eca7b1/rom_freq_word_stub.v
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// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
// Date : Sun Jul 30 18:06:27 2023
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rom_freq_word_stub.v
// Design : rom_freq_word
// Purpose : Stub declaration of top-level module interface
// Device : xc7z100ffg900-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clka, addra, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,addra[6:0],douta[11:0]" */;
input clka;
input [6:0]addra;
output [11:0]douta;
endmodule
projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/7727187e03eca7b1/rom_freq_word_stub.vhdl
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-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
-- Date : Sun Jul 30 18:06:27 2023
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rom_freq_word_stub.vhdl
-- Design : rom_freq_word
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z100ffg900-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 6 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,addra[6:0],douta[11:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_3,Vivado 2019.1.3";
begin
end;
projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e8e950360ca1fe60/e8e950360ca1fe60.xci
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projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e8e950360ca1fe60/vio_RF_control.dcp
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projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e8e950360ca1fe60/vio_RF_control_sim_netlist.v
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projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e8e950360ca1fe60/vio_RF_control_sim_netlist.vhdl
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projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e8e950360ca1fe60/vio_RF_control_stub.v
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// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
// Date : Sun Jul 30 18:20:41 2023
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_RF_control_stub.v
// Design : vio_RF_control
// Purpose : Stub declaration of top-level module interface
// Device : xc7z100ffg900-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe_in0, probe_out0, probe_out1,
probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, probe_out9,
probe_out10, probe_out11, probe_out12, probe_out13, probe_out14, probe_out15)
/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[11:0],probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[7:0],probe_out4[7:0],probe_out5[11:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0],probe_out9[0:0],probe_out10[0:0],probe_out11[0:0],probe_out12[0:0],probe_out13[31:0],probe_out14[0:0],probe_out15[31:0]" */;
input clk;
input [11:0]probe_in0;
output [0:0]probe_out0;
output [1:0]probe_out1;
output [0:0]probe_out2;
output [7:0]probe_out3;
output [7:0]probe_out4;
output [11:0]probe_out5;
output [0:0]probe_out6;
output [0:0]probe_out7;
output [0:0]probe_out8;
output [0:0]probe_out9;
output [0:0]probe_out10;
output [0:0]probe_out11;
output [0:0]probe_out12;
output [31:0]probe_out13;
output [0:0]probe_out14;
output [31:0]probe_out15;
endmodule
projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e8e950360ca1fe60/vio_RF_control_stub.vhdl
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-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
-- Date : Sun Jul 30 18:20:41 2023
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_RF_control_stub.vhdl
-- Design : vio_RF_control
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z100ffg900-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
clk : in STD_LOGIC;
probe_in0 : in STD_LOGIC_VECTOR ( 11 downto 0 );
probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out3 : out STD_LOGIC_VECTOR ( 7 downto 0 );
probe_out4 : out STD_LOGIC_VECTOR ( 7 downto 0 );
probe_out5 : out STD_LOGIC_VECTOR ( 11 downto 0 );
probe_out6 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out7 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out8 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out9 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out10 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out11 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out12 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out13 : out STD_LOGIC_VECTOR ( 31 downto 0 );
probe_out14 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out15 : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[11:0],probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[7:0],probe_out4[7:0],probe_out5[11:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0],probe_out9[0:0],probe_out10[0:0],probe_out11[0:0],probe_out12[0:0],probe_out13[31:0],probe_out14[0:0],probe_out15[31:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
begin
end;
projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf
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projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt/java_command_handlers.wdf
+3 -3
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@@ -4,7 +4,7 @@ version:1
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eof:309752714
projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc
+1 -1
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@@ -1,3 +1,3 @@
version:1
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6d6f64655f636f756e7465727c4755494d6f6465:13
eof:
projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf
+5 -5
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@@ -1,7 +1,7 @@
version:1
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73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
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@@ -33,7 +33,7 @@ version:1
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eof:1038723330
projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml
+15 -12
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@@ -3,7 +3,7 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Mon Jul 3 19:45:47 2023">
<application name="pa" timeStamp="Sun Jul 30 18:42:58 2023">
<section name="Project Information" visible="false">
<property name="ProjectID" value="b252a1e4ed8d4787b074893bfbb0dee3" type="ProjectID"/>
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
@@ -22,20 +22,21 @@ This means code written to parse this file will need to be revisited each subseq
<property name="EditDelete" value="4" type="JavaHandler"/>
<property name="ManageCompositeTargets" value="7" type="JavaHandler"/>
<property name="NewIPLocationHandler" value="1" type="JavaHandler"/>
<property name="OpenIPLocationHandler" value="2" type="JavaHandler"/>
<property name="OpenIPLocationHandler" value="4" type="JavaHandler"/>
<property name="OpenPreviousIPHandler" value="8" type="JavaHandler"/>
<property name="RecustomizeCore" value="11" type="JavaHandler"/>
<property name="RecustomizeCore" value="14" type="JavaHandler"/>
</item>
<item name="Gui Handlers">
<property name="BaseDialog_CANCEL" value="4" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="24" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="26" type="GuiHandlerData"/>
<property name="CmdMsgDialog_OK" value="4" type="GuiHandlerData"/>
<property name="ExpRunMenu_RESET_AND_GENERATE_OUTPUT_PRODUCTS" value="1" type="GuiHandlerData"/>
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="9" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="68" type="GuiHandlerData"/>
<property name="GettingStartedView_MANAGE_IP" value="3" type="GuiHandlerData"/>
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="13" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="79" type="GuiHandlerData"/>
<property name="GettingStartedView_MANAGE_IP" value="5" type="GuiHandlerData"/>
<property name="GettingStartedView_START_USING_VIVADO_WITH_IP_CATALOG" value="1" type="GuiHandlerData"/>
<property name="HACGCCoeFileWidget_BROWSE" value="4" type="GuiHandlerData"/>
<property name="HACGCCoeFileWidget_BROWSE" value="5" type="GuiHandlerData"/>
<property name="HFolderChooserHelpers_JUMP_TO_RECENT_PROJECT_DIRECTORY" value="1" type="GuiHandlerData"/>
<property name="HJFileChooserHelpers_JUMP_TO_RECENT_PROJECT_DIRECTORY" value="3" type="GuiHandlerData"/>
<property name="MainMenuMgr_EDIT" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_EXPORT" value="3" type="GuiHandlerData"/>
@@ -52,21 +53,23 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PACommandNames_ADD_EXISTING_IP" value="8" type="GuiHandlerData"/>
<property name="PACommandNames_CLOSE_PROJECT" value="5" type="GuiHandlerData"/>
<property name="PACommandNames_GENERATE_COMPOSITE_FILE" value="5" type="GuiHandlerData"/>
<property name="PACommandNames_OPEN_IP_LOCATION" value="2" type="GuiHandlerData"/>
<property name="PACommandNames_OPEN_IP_LOCATION" value="4" type="GuiHandlerData"/>
<property name="PACommandNames_RESET_COMPOSITE_FILE" value="2" type="GuiHandlerData"/>
<property name="ProgressDialog_CANCEL" value="1" type="GuiHandlerData"/>
<property name="RDICommands_DELETE" value="1" type="GuiHandlerData"/>
<property name="RemoveSourcesDialog_ALSO_DELETE" value="5" type="GuiHandlerData"/>
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="13" type="GuiHandlerData"/>
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="15" type="GuiHandlerData"/>
<property name="SimpleOutputProductDialog_RESET_OUTPUT_PRODUCTS" value="3" type="GuiHandlerData"/>
<property name="SrcChooserPanel_ADD_CONFIGURABLE_IP_FILES" value="8" type="GuiHandlerData"/>
<property name="SrcChooserPanel_MAKE_LOCAL_COPY_OF_THESE_FILES_INTO" value="2" type="GuiHandlerData"/>
<property name="SrcMenu_IP_DOCUMENTATION" value="2" type="GuiHandlerData"/>
<property name="SyntheticaGettingStartedView_RECENT_IP_LOCATIONS" value="8" type="GuiHandlerData"/>
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="1" type="GuiHandlerData"/>
</item>
<item name="Other">
<property name="GuiMode" value="23" type="GuiMode"/>
<property name="GuiMode" value="40" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="11" type="TclMode"/>
<property name="TclMode" value="20" type="TclMode"/>
</item>
</section>
</application>
projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_8.xml
+8
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@@ -0,0 +1,8 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="rom_freq_word_synth_1" LaunchDir="/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>
projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_9.xml
+8
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@@ -0,0 +1,8 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="vio_RF_control_synth_1" LaunchDir="/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>
projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/.Vivado_Synthesis.queue.rst → projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/.Vivado_Synthesis.queue.rst
View File
projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/.vivado.begin.rst → projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/.vivado.begin.rst
+1 -1
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@@ -1,5 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command="vivado" Owner="josh" Host="JOSH-ASUS-Z690" Pid="1476074" HostCore="20" HostMemory="65588992">
<Process Command="vivado" Owner="josh" Host="JOSH-ASUS-Z690" Pid="1394906" HostCore="20" HostMemory="65576700">
</Process>
</ProcessHandle>
projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/.vivado.end.rst → projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/.vivado.end.rst
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