Archived
change online acq pn code length, change 814 online acq to the same
修改了在线捕获程序的PN码长和频偏搜索步进,修改了地检发送程序的PN码长,使用对飞相控阵进行了测试,得到正确结果;将程序移植到814平台,同样能够正常工作;对地检程序(20230512),对飞程序(20230512)和814程序(20230415)进行归档
This commit is contained in:
@@ -3,7 +3,7 @@
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#
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# project.tcl: Tcl script for re-creating project 'project'
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#
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||||
# Generated by Vivado on Thu May 11 19:05:20 CST 2023
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# Generated by Vivado on Fri May 12 10:01:28 CST 2023
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# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
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#
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# This file contains the Vivado Tcl commands for re-creating the project to the state*
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@@ -42,7 +42,9 @@ wire [15:0] tx_pn_seq_i;
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wire [15:0] tx_pn_seq_q;
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tx_pn_seq_6mcps #(
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.DATA_WIDTH (16)
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.DATA_WIDTH (16),
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.BIT_DATA (1024'b0000000100100010000011001001101000010010101000011110101110101101101100000000110000011011001100001010110101110001101111110001000111100111101101101000000010100001011010101000111110111100100101100000100110010001010001101101110000001111000111011111110010000110001011011101000011010101100111100101101100100000100010010011000000101100010100111011001110001011111101010001011101101011000011001101101010000011101001111010011010100100111000001111100111001101111010001010101101111100001001110100011101011111011010010000100001010010101100011100111111101100001000110100111001001111000011011101100011000111101111101001001010000001101000110010111010010110100010001011001101001010010001100001110110111100000101110010101110011101110111001100111010101110111101100101000100110110001000011100101111100101001100110010101010011111100110001101011110011010110100110001001011100001011110101010101111111101000001010100101111000101011110111010100110111001000111000111111111100000001110000111111011100010011111000110011111010110010110010010010000000001),
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.BIT_DATA_LEN (1024)
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) u_tx_pn_seq
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(
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.sys_clk (sys_clk ), // 122.88MHz
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Load Diff
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-239
@@ -1,239 +0,0 @@
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-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
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||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
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||||
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||||
-- IP VLNV: xilinx.com:ip:dds_compiler:6.0
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-- IP Revision: 18
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||||
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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LIBRARY dds_compiler_v6_0_18;
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USE dds_compiler_v6_0_18.dds_compiler_v6_0_18;
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ENTITY dds_32b_8b_comp IS
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PORT (
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aclk : IN STD_LOGIC;
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s_axis_config_tvalid : IN STD_LOGIC;
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s_axis_config_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
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m_axis_data_tvalid : OUT STD_LOGIC;
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m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
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m_axis_phase_tvalid : OUT STD_LOGIC;
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m_axis_phase_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
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);
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END dds_32b_8b_comp;
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||||
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||||
ARCHITECTURE dds_32b_8b_comp_arch OF dds_32b_8b_comp IS
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ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
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ATTRIBUTE DowngradeIPIdentifiedWarnings OF dds_32b_8b_comp_arch: ARCHITECTURE IS "yes";
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COMPONENT dds_compiler_v6_0_18 IS
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GENERIC (
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C_XDEVICEFAMILY : STRING;
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C_MODE_OF_OPERATION : INTEGER;
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C_MODULUS : INTEGER;
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C_ACCUMULATOR_WIDTH : INTEGER;
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C_CHANNELS : INTEGER;
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C_HAS_PHASE_OUT : INTEGER;
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C_HAS_PHASEGEN : INTEGER;
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C_HAS_SINCOS : INTEGER;
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C_LATENCY : INTEGER;
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C_MEM_TYPE : INTEGER;
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C_NEGATIVE_COSINE : INTEGER;
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C_NEGATIVE_SINE : INTEGER;
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C_NOISE_SHAPING : INTEGER;
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C_OUTPUTS_REQUIRED : INTEGER;
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C_OUTPUT_FORM : INTEGER;
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C_OUTPUT_WIDTH : INTEGER;
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C_PHASE_ANGLE_WIDTH : INTEGER;
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C_PHASE_INCREMENT : INTEGER;
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C_PHASE_INCREMENT_VALUE : STRING;
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C_RESYNC : INTEGER;
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C_PHASE_OFFSET : INTEGER;
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C_PHASE_OFFSET_VALUE : STRING;
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||||
C_OPTIMISE_GOAL : INTEGER;
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C_USE_DSP48 : INTEGER;
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C_POR_MODE : INTEGER;
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C_AMPLITUDE : INTEGER;
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C_HAS_ACLKEN : INTEGER;
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C_HAS_ARESETN : INTEGER;
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C_HAS_TLAST : INTEGER;
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C_HAS_TREADY : INTEGER;
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C_HAS_S_PHASE : INTEGER;
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C_S_PHASE_TDATA_WIDTH : INTEGER;
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C_S_PHASE_HAS_TUSER : INTEGER;
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C_S_PHASE_TUSER_WIDTH : INTEGER;
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C_HAS_S_CONFIG : INTEGER;
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C_S_CONFIG_SYNC_MODE : INTEGER;
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||||
C_S_CONFIG_TDATA_WIDTH : INTEGER;
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C_HAS_M_DATA : INTEGER;
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C_M_DATA_TDATA_WIDTH : INTEGER;
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C_M_DATA_HAS_TUSER : INTEGER;
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C_M_DATA_TUSER_WIDTH : INTEGER;
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C_HAS_M_PHASE : INTEGER;
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C_M_PHASE_TDATA_WIDTH : INTEGER;
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C_M_PHASE_HAS_TUSER : INTEGER;
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C_M_PHASE_TUSER_WIDTH : INTEGER;
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C_DEBUG_INTERFACE : INTEGER;
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C_CHAN_WIDTH : INTEGER
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||||
);
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PORT (
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aclk : IN STD_LOGIC;
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aclken : IN STD_LOGIC;
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aresetn : IN STD_LOGIC;
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s_axis_phase_tvalid : IN STD_LOGIC;
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s_axis_phase_tready : OUT STD_LOGIC;
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s_axis_phase_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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s_axis_phase_tlast : IN STD_LOGIC;
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s_axis_phase_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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s_axis_config_tvalid : IN STD_LOGIC;
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s_axis_config_tready : OUT STD_LOGIC;
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s_axis_config_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
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s_axis_config_tlast : IN STD_LOGIC;
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m_axis_data_tvalid : OUT STD_LOGIC;
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m_axis_data_tready : IN STD_LOGIC;
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m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
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m_axis_data_tlast : OUT STD_LOGIC;
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m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
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m_axis_phase_tvalid : OUT STD_LOGIC;
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m_axis_phase_tready : IN STD_LOGIC;
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m_axis_phase_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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m_axis_phase_tlast : OUT STD_LOGIC;
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m_axis_phase_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
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event_pinc_invalid : OUT STD_LOGIC;
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event_poff_invalid : OUT STD_LOGIC;
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event_phase_in_invalid : OUT STD_LOGIC;
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event_s_phase_tlast_missing : OUT STD_LOGIC;
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event_s_phase_tlast_unexpected : OUT STD_LOGIC;
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event_s_phase_chanid_incorrect : OUT STD_LOGIC;
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event_s_config_tlast_missing : OUT STD_LOGIC;
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event_s_config_tlast_unexpected : OUT STD_LOGIC
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);
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END COMPONENT dds_compiler_v6_0_18;
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ATTRIBUTE X_INTERFACE_INFO : STRING;
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ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
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ATTRIBUTE X_INTERFACE_INFO OF m_axis_phase_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_PHASE TDATA";
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ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_phase_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_PHASE, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
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ATTRIBUTE X_INTERFACE_INFO OF m_axis_phase_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_PHASE TVALID";
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||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
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ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_data_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_DATA, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
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ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
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ATTRIBUTE X_INTERFACE_INFO OF s_axis_config_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CONFIG TDATA";
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ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_config_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_CONFIG, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
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||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_config_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CONFIG TVALID";
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ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF M_AXIS_PHASE:S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_PHASE, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0";
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ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
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BEGIN
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U0 : dds_compiler_v6_0_18
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GENERIC MAP (
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C_XDEVICEFAMILY => "kintex7",
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C_MODE_OF_OPERATION => 0,
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C_MODULUS => 9,
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C_ACCUMULATOR_WIDTH => 32,
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C_CHANNELS => 1,
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C_HAS_PHASE_OUT => 1,
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C_HAS_PHASEGEN => 1,
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C_HAS_SINCOS => 1,
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C_LATENCY => 4,
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C_MEM_TYPE => 1,
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C_NEGATIVE_COSINE => 0,
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C_NEGATIVE_SINE => 0,
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C_NOISE_SHAPING => 0,
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C_OUTPUTS_REQUIRED => 2,
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||||
C_OUTPUT_FORM => 0,
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C_OUTPUT_WIDTH => 8,
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C_PHASE_ANGLE_WIDTH => 8,
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C_PHASE_INCREMENT => 1,
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C_PHASE_INCREMENT_VALUE => "1101000110110111,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",
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C_RESYNC => 0,
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C_PHASE_OFFSET => 1,
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||||
C_PHASE_OFFSET_VALUE => "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",
|
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C_OPTIMISE_GOAL => 0,
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||||
C_USE_DSP48 => 0,
|
||||
C_POR_MODE => 0,
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||||
C_AMPLITUDE => 0,
|
||||
C_HAS_ACLKEN => 0,
|
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C_HAS_ARESETN => 0,
|
||||
C_HAS_TLAST => 0,
|
||||
C_HAS_TREADY => 0,
|
||||
C_HAS_S_PHASE => 0,
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C_S_PHASE_TDATA_WIDTH => 1,
|
||||
C_S_PHASE_HAS_TUSER => 0,
|
||||
C_S_PHASE_TUSER_WIDTH => 1,
|
||||
C_HAS_S_CONFIG => 1,
|
||||
C_S_CONFIG_SYNC_MODE => 0,
|
||||
C_S_CONFIG_TDATA_WIDTH => 64,
|
||||
C_HAS_M_DATA => 1,
|
||||
C_M_DATA_TDATA_WIDTH => 16,
|
||||
C_M_DATA_HAS_TUSER => 0,
|
||||
C_M_DATA_TUSER_WIDTH => 1,
|
||||
C_HAS_M_PHASE => 1,
|
||||
C_M_PHASE_TDATA_WIDTH => 32,
|
||||
C_M_PHASE_HAS_TUSER => 0,
|
||||
C_M_PHASE_TUSER_WIDTH => 1,
|
||||
C_DEBUG_INTERFACE => 0,
|
||||
C_CHAN_WIDTH => 1
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||||
)
|
||||
PORT MAP (
|
||||
aclk => aclk,
|
||||
aclken => '1',
|
||||
aresetn => '1',
|
||||
s_axis_phase_tvalid => '0',
|
||||
s_axis_phase_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axis_phase_tlast => '0',
|
||||
s_axis_phase_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axis_config_tvalid => s_axis_config_tvalid,
|
||||
s_axis_config_tdata => s_axis_config_tdata,
|
||||
s_axis_config_tlast => '0',
|
||||
m_axis_data_tvalid => m_axis_data_tvalid,
|
||||
m_axis_data_tready => '0',
|
||||
m_axis_data_tdata => m_axis_data_tdata,
|
||||
m_axis_phase_tvalid => m_axis_phase_tvalid,
|
||||
m_axis_phase_tready => '0',
|
||||
m_axis_phase_tdata => m_axis_phase_tdata
|
||||
);
|
||||
END dds_32b_8b_comp_arch;
|
||||
+14
-12
@@ -46,26 +46,28 @@
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
// IP VLNV: xilinx.com:ip:dds_compiler:6.0
|
||||
// IP Revision: 18
|
||||
// IP VLNV: xilinx.com:ip:fifo_generator:13.2
|
||||
// IP Revision: 4
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
dds_32b_8b_comp your_instance_name (
|
||||
.aclk(aclk), // input wire aclk
|
||||
.s_axis_config_tvalid(s_axis_config_tvalid), // input wire s_axis_config_tvalid
|
||||
.s_axis_config_tdata(s_axis_config_tdata), // input wire [63 : 0] s_axis_config_tdata
|
||||
.m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid
|
||||
.m_axis_data_tdata(m_axis_data_tdata), // output wire [15 : 0] m_axis_data_tdata
|
||||
.m_axis_phase_tvalid(m_axis_phase_tvalid), // output wire m_axis_phase_tvalid
|
||||
.m_axis_phase_tdata(m_axis_phase_tdata) // output wire [31 : 0] m_axis_phase_tdata
|
||||
fifo_rx_data your_instance_name (
|
||||
.rst(rst), // input wire rst
|
||||
.wr_clk(wr_clk), // input wire wr_clk
|
||||
.rd_clk(rd_clk), // input wire rd_clk
|
||||
.din(din), // input wire [95 : 0] din
|
||||
.wr_en(wr_en), // input wire wr_en
|
||||
.rd_en(rd_en), // input wire rd_en
|
||||
.dout(dout), // output wire [95 : 0] dout
|
||||
.full(full), // output wire full
|
||||
.empty(empty) // output wire empty
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file dds_32b_8b_comp.v when simulating
|
||||
// the core, dds_32b_8b_comp. When compiling the wrapper file, be sure to
|
||||
// You must compile the wrapper file fifo_rx_data.v when simulating
|
||||
// the core, fifo_rx_data. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
+91
@@ -0,0 +1,91 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:fifo_generator:13.2
|
||||
-- IP Revision: 4
|
||||
|
||||
-- The following code must appear in the VHDL architecture header.
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
COMPONENT fifo_rx_data
|
||||
PORT (
|
||||
rst : IN STD_LOGIC;
|
||||
wr_clk : IN STD_LOGIC;
|
||||
rd_clk : IN STD_LOGIC;
|
||||
din : IN STD_LOGIC_VECTOR(95 DOWNTO 0);
|
||||
wr_en : IN STD_LOGIC;
|
||||
rd_en : IN STD_LOGIC;
|
||||
dout : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
|
||||
full : OUT STD_LOGIC;
|
||||
empty : OUT STD_LOGIC
|
||||
);
|
||||
END COMPONENT;
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
|
||||
-- The following code must appear in the VHDL architecture
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : fifo_rx_data
|
||||
PORT MAP (
|
||||
rst => rst,
|
||||
wr_clk => wr_clk,
|
||||
rd_clk => rd_clk,
|
||||
din => din,
|
||||
wr_en => wr_en,
|
||||
rd_en => rd_en,
|
||||
dout => dout,
|
||||
full => full,
|
||||
empty => empty
|
||||
);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
-- You must compile the wrapper file fifo_rx_data.vhd when simulating
|
||||
-- the core, fifo_rx_data. When compiling the wrapper file, be sure to
|
||||
-- reference the VHDL simulation library.
|
||||
|
||||
LFS
BIN
Binary file not shown.
projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/fifo_rx_data/fifo_rx_data_sim_netlist.vhdl
LFS
BIN
Binary file not shown.
+29
@@ -0,0 +1,29 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Fri May 12 16:08:03 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data_stub.v
|
||||
// Design : fifo_rx_data
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "fifo_generator_v13_2_4,Vivado 2019.1.3" *)
|
||||
module fifo_rx_data(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full,
|
||||
empty)
|
||||
/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[95:0],wr_en,rd_en,dout[95:0],full,empty" */;
|
||||
input rst;
|
||||
input wr_clk;
|
||||
input rd_clk;
|
||||
input [95:0]din;
|
||||
input wr_en;
|
||||
input rd_en;
|
||||
output [95:0]dout;
|
||||
output full;
|
||||
output empty;
|
||||
endmodule
|
||||
+38
@@ -0,0 +1,38 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Fri May 12 16:08:04 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data_stub.vhdl
|
||||
-- Design : fifo_rx_data
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity fifo_rx_data is
|
||||
Port (
|
||||
rst : in STD_LOGIC;
|
||||
wr_clk : in STD_LOGIC;
|
||||
rd_clk : in STD_LOGIC;
|
||||
din : in STD_LOGIC_VECTOR ( 95 downto 0 );
|
||||
wr_en : in STD_LOGIC;
|
||||
rd_en : in STD_LOGIC;
|
||||
dout : out STD_LOGIC_VECTOR ( 95 downto 0 );
|
||||
full : out STD_LOGIC;
|
||||
empty : out STD_LOGIC
|
||||
);
|
||||
|
||||
end fifo_rx_data;
|
||||
|
||||
architecture stub of fifo_rx_data is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "rst,wr_clk,rd_clk,din[95:0],wr_en,rd_en,dout[95:0],full,empty";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "fifo_generator_v13_2_4,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+524
@@ -0,0 +1,524 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:fifo_generator:13.2
|
||||
// IP Revision: 4
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module fifo_rx_data (
|
||||
rst,
|
||||
wr_clk,
|
||||
rd_clk,
|
||||
din,
|
||||
wr_en,
|
||||
rd_en,
|
||||
dout,
|
||||
full,
|
||||
empty
|
||||
);
|
||||
|
||||
input wire rst;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME write_clk, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 write_clk CLK" *)
|
||||
input wire wr_clk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME read_clk, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 read_clk CLK" *)
|
||||
input wire rd_clk;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *)
|
||||
input wire [95 : 0] din;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *)
|
||||
input wire wr_en;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *)
|
||||
input wire rd_en;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *)
|
||||
output wire [95 : 0] dout;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *)
|
||||
output wire full;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *)
|
||||
output wire empty;
|
||||
|
||||
fifo_generator_v13_2_4 #(
|
||||
.C_COMMON_CLOCK(0),
|
||||
.C_SELECT_XPM(0),
|
||||
.C_COUNT_TYPE(0),
|
||||
.C_DATA_COUNT_WIDTH(4),
|
||||
.C_DEFAULT_VALUE("BlankString"),
|
||||
.C_DIN_WIDTH(96),
|
||||
.C_DOUT_RST_VAL("0"),
|
||||
.C_DOUT_WIDTH(96),
|
||||
.C_ENABLE_RLOCS(0),
|
||||
.C_FAMILY("kintex7"),
|
||||
.C_FULL_FLAGS_RST_VAL(1),
|
||||
.C_HAS_ALMOST_EMPTY(0),
|
||||
.C_HAS_ALMOST_FULL(0),
|
||||
.C_HAS_BACKUP(0),
|
||||
.C_HAS_DATA_COUNT(0),
|
||||
.C_HAS_INT_CLK(0),
|
||||
.C_HAS_MEMINIT_FILE(0),
|
||||
.C_HAS_OVERFLOW(0),
|
||||
.C_HAS_RD_DATA_COUNT(0),
|
||||
.C_HAS_RD_RST(0),
|
||||
.C_HAS_RST(1),
|
||||
.C_HAS_SRST(0),
|
||||
.C_HAS_UNDERFLOW(0),
|
||||
.C_HAS_VALID(0),
|
||||
.C_HAS_WR_ACK(0),
|
||||
.C_HAS_WR_DATA_COUNT(0),
|
||||
.C_HAS_WR_RST(0),
|
||||
.C_IMPLEMENTATION_TYPE(2),
|
||||
.C_INIT_WR_PNTR_VAL(0),
|
||||
.C_MEMORY_TYPE(2),
|
||||
.C_MIF_FILE_NAME("BlankString"),
|
||||
.C_OPTIMIZATION_MODE(0),
|
||||
.C_OVERFLOW_LOW(0),
|
||||
.C_PRELOAD_LATENCY(1),
|
||||
.C_PRELOAD_REGS(0),
|
||||
.C_PRIM_FIFO_TYPE("512x72"),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
|
||||
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
|
||||
.C_PROG_EMPTY_TYPE(0),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL(13),
|
||||
.C_PROG_FULL_THRESH_NEGATE_VAL(12),
|
||||
.C_PROG_FULL_TYPE(0),
|
||||
.C_RD_DATA_COUNT_WIDTH(4),
|
||||
.C_RD_DEPTH(16),
|
||||
.C_RD_FREQ(1),
|
||||
.C_RD_PNTR_WIDTH(4),
|
||||
.C_UNDERFLOW_LOW(0),
|
||||
.C_USE_DOUT_RST(1),
|
||||
.C_USE_ECC(0),
|
||||
.C_USE_EMBEDDED_REG(0),
|
||||
.C_USE_PIPELINE_REG(0),
|
||||
.C_POWER_SAVING_MODE(0),
|
||||
.C_USE_FIFO16_FLAGS(0),
|
||||
.C_USE_FWFT_DATA_COUNT(0),
|
||||
.C_VALID_LOW(0),
|
||||
.C_WR_ACK_LOW(0),
|
||||
.C_WR_DATA_COUNT_WIDTH(4),
|
||||
.C_WR_DEPTH(16),
|
||||
.C_WR_FREQ(1),
|
||||
.C_WR_PNTR_WIDTH(4),
|
||||
.C_WR_RESPONSE_LATENCY(1),
|
||||
.C_MSGON_VAL(1),
|
||||
.C_ENABLE_RST_SYNC(1),
|
||||
.C_EN_SAFETY_CKT(0),
|
||||
.C_ERROR_INJECTION_TYPE(0),
|
||||
.C_SYNCHRONIZER_STAGE(3),
|
||||
.C_INTERFACE_TYPE(0),
|
||||
.C_AXI_TYPE(1),
|
||||
.C_HAS_AXI_WR_CHANNEL(1),
|
||||
.C_HAS_AXI_RD_CHANNEL(1),
|
||||
.C_HAS_SLAVE_CE(0),
|
||||
.C_HAS_MASTER_CE(0),
|
||||
.C_ADD_NGC_CONSTRAINT(0),
|
||||
.C_USE_COMMON_OVERFLOW(0),
|
||||
.C_USE_COMMON_UNDERFLOW(0),
|
||||
.C_USE_DEFAULT_SETTINGS(0),
|
||||
.C_AXI_ID_WIDTH(1),
|
||||
.C_AXI_ADDR_WIDTH(32),
|
||||
.C_AXI_DATA_WIDTH(64),
|
||||
.C_AXI_LEN_WIDTH(8),
|
||||
.C_AXI_LOCK_WIDTH(1),
|
||||
.C_HAS_AXI_ID(0),
|
||||
.C_HAS_AXI_AWUSER(0),
|
||||
.C_HAS_AXI_WUSER(0),
|
||||
.C_HAS_AXI_BUSER(0),
|
||||
.C_HAS_AXI_ARUSER(0),
|
||||
.C_HAS_AXI_RUSER(0),
|
||||
.C_AXI_ARUSER_WIDTH(1),
|
||||
.C_AXI_AWUSER_WIDTH(1),
|
||||
.C_AXI_WUSER_WIDTH(1),
|
||||
.C_AXI_BUSER_WIDTH(1),
|
||||
.C_AXI_RUSER_WIDTH(1),
|
||||
.C_HAS_AXIS_TDATA(1),
|
||||
.C_HAS_AXIS_TID(0),
|
||||
.C_HAS_AXIS_TDEST(0),
|
||||
.C_HAS_AXIS_TUSER(1),
|
||||
.C_HAS_AXIS_TREADY(1),
|
||||
.C_HAS_AXIS_TLAST(0),
|
||||
.C_HAS_AXIS_TSTRB(0),
|
||||
.C_HAS_AXIS_TKEEP(0),
|
||||
.C_AXIS_TDATA_WIDTH(8),
|
||||
.C_AXIS_TID_WIDTH(1),
|
||||
.C_AXIS_TDEST_WIDTH(1),
|
||||
.C_AXIS_TUSER_WIDTH(4),
|
||||
.C_AXIS_TSTRB_WIDTH(1),
|
||||
.C_AXIS_TKEEP_WIDTH(1),
|
||||
.C_WACH_TYPE(0),
|
||||
.C_WDCH_TYPE(0),
|
||||
.C_WRCH_TYPE(0),
|
||||
.C_RACH_TYPE(0),
|
||||
.C_RDCH_TYPE(0),
|
||||
.C_AXIS_TYPE(0),
|
||||
.C_IMPLEMENTATION_TYPE_WACH(1),
|
||||
.C_IMPLEMENTATION_TYPE_WDCH(1),
|
||||
.C_IMPLEMENTATION_TYPE_WRCH(1),
|
||||
.C_IMPLEMENTATION_TYPE_RACH(1),
|
||||
.C_IMPLEMENTATION_TYPE_RDCH(1),
|
||||
.C_IMPLEMENTATION_TYPE_AXIS(1),
|
||||
.C_APPLICATION_TYPE_WACH(0),
|
||||
.C_APPLICATION_TYPE_WDCH(0),
|
||||
.C_APPLICATION_TYPE_WRCH(0),
|
||||
.C_APPLICATION_TYPE_RACH(0),
|
||||
.C_APPLICATION_TYPE_RDCH(0),
|
||||
.C_APPLICATION_TYPE_AXIS(0),
|
||||
.C_PRIM_FIFO_TYPE_WACH("512x36"),
|
||||
.C_PRIM_FIFO_TYPE_WDCH("1kx36"),
|
||||
.C_PRIM_FIFO_TYPE_WRCH("512x36"),
|
||||
.C_PRIM_FIFO_TYPE_RACH("512x36"),
|
||||
.C_PRIM_FIFO_TYPE_RDCH("1kx36"),
|
||||
.C_PRIM_FIFO_TYPE_AXIS("1kx18"),
|
||||
.C_USE_ECC_WACH(0),
|
||||
.C_USE_ECC_WDCH(0),
|
||||
.C_USE_ECC_WRCH(0),
|
||||
.C_USE_ECC_RACH(0),
|
||||
.C_USE_ECC_RDCH(0),
|
||||
.C_USE_ECC_AXIS(0),
|
||||
.C_ERROR_INJECTION_TYPE_WACH(0),
|
||||
.C_ERROR_INJECTION_TYPE_WDCH(0),
|
||||
.C_ERROR_INJECTION_TYPE_WRCH(0),
|
||||
.C_ERROR_INJECTION_TYPE_RACH(0),
|
||||
.C_ERROR_INJECTION_TYPE_RDCH(0),
|
||||
.C_ERROR_INJECTION_TYPE_AXIS(0),
|
||||
.C_DIN_WIDTH_WACH(1),
|
||||
.C_DIN_WIDTH_WDCH(64),
|
||||
.C_DIN_WIDTH_WRCH(2),
|
||||
.C_DIN_WIDTH_RACH(32),
|
||||
.C_DIN_WIDTH_RDCH(64),
|
||||
.C_DIN_WIDTH_AXIS(1),
|
||||
.C_WR_DEPTH_WACH(16),
|
||||
.C_WR_DEPTH_WDCH(1024),
|
||||
.C_WR_DEPTH_WRCH(16),
|
||||
.C_WR_DEPTH_RACH(16),
|
||||
.C_WR_DEPTH_RDCH(1024),
|
||||
.C_WR_DEPTH_AXIS(1024),
|
||||
.C_WR_PNTR_WIDTH_WACH(4),
|
||||
.C_WR_PNTR_WIDTH_WDCH(10),
|
||||
.C_WR_PNTR_WIDTH_WRCH(4),
|
||||
.C_WR_PNTR_WIDTH_RACH(4),
|
||||
.C_WR_PNTR_WIDTH_RDCH(10),
|
||||
.C_WR_PNTR_WIDTH_AXIS(10),
|
||||
.C_HAS_DATA_COUNTS_WACH(0),
|
||||
.C_HAS_DATA_COUNTS_WDCH(0),
|
||||
.C_HAS_DATA_COUNTS_WRCH(0),
|
||||
.C_HAS_DATA_COUNTS_RACH(0),
|
||||
.C_HAS_DATA_COUNTS_RDCH(0),
|
||||
.C_HAS_DATA_COUNTS_AXIS(0),
|
||||
.C_HAS_PROG_FLAGS_WACH(0),
|
||||
.C_HAS_PROG_FLAGS_WDCH(0),
|
||||
.C_HAS_PROG_FLAGS_WRCH(0),
|
||||
.C_HAS_PROG_FLAGS_RACH(0),
|
||||
.C_HAS_PROG_FLAGS_RDCH(0),
|
||||
.C_HAS_PROG_FLAGS_AXIS(0),
|
||||
.C_PROG_FULL_TYPE_WACH(0),
|
||||
.C_PROG_FULL_TYPE_WDCH(0),
|
||||
.C_PROG_FULL_TYPE_WRCH(0),
|
||||
.C_PROG_FULL_TYPE_RACH(0),
|
||||
.C_PROG_FULL_TYPE_RDCH(0),
|
||||
.C_PROG_FULL_TYPE_AXIS(0),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
|
||||
.C_PROG_EMPTY_TYPE_WACH(0),
|
||||
.C_PROG_EMPTY_TYPE_WDCH(0),
|
||||
.C_PROG_EMPTY_TYPE_WRCH(0),
|
||||
.C_PROG_EMPTY_TYPE_RACH(0),
|
||||
.C_PROG_EMPTY_TYPE_RDCH(0),
|
||||
.C_PROG_EMPTY_TYPE_AXIS(0),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
|
||||
.C_REG_SLICE_MODE_WACH(0),
|
||||
.C_REG_SLICE_MODE_WDCH(0),
|
||||
.C_REG_SLICE_MODE_WRCH(0),
|
||||
.C_REG_SLICE_MODE_RACH(0),
|
||||
.C_REG_SLICE_MODE_RDCH(0),
|
||||
.C_REG_SLICE_MODE_AXIS(0)
|
||||
) inst (
|
||||
.backup(1'D0),
|
||||
.backup_marker(1'D0),
|
||||
.clk(1'D0),
|
||||
.rst(rst),
|
||||
.srst(1'D0),
|
||||
.wr_clk(wr_clk),
|
||||
.wr_rst(1'D0),
|
||||
.rd_clk(rd_clk),
|
||||
.rd_rst(1'D0),
|
||||
.din(din),
|
||||
.wr_en(wr_en),
|
||||
.rd_en(rd_en),
|
||||
.prog_empty_thresh(4'B0),
|
||||
.prog_empty_thresh_assert(4'B0),
|
||||
.prog_empty_thresh_negate(4'B0),
|
||||
.prog_full_thresh(4'B0),
|
||||
.prog_full_thresh_assert(4'B0),
|
||||
.prog_full_thresh_negate(4'B0),
|
||||
.int_clk(1'D0),
|
||||
.injectdbiterr(1'D0),
|
||||
.injectsbiterr(1'D0),
|
||||
.sleep(1'D0),
|
||||
.dout(dout),
|
||||
.full(full),
|
||||
.almost_full(),
|
||||
.wr_ack(),
|
||||
.overflow(),
|
||||
.empty(empty),
|
||||
.almost_empty(),
|
||||
.valid(),
|
||||
.underflow(),
|
||||
.data_count(),
|
||||
.rd_data_count(),
|
||||
.wr_data_count(),
|
||||
.prog_full(),
|
||||
.prog_empty(),
|
||||
.sbiterr(),
|
||||
.dbiterr(),
|
||||
.wr_rst_busy(),
|
||||
.rd_rst_busy(),
|
||||
.m_aclk(1'D0),
|
||||
.s_aclk(1'D0),
|
||||
.s_aresetn(1'D0),
|
||||
.m_aclk_en(1'D0),
|
||||
.s_aclk_en(1'D0),
|
||||
.s_axi_awid(1'B0),
|
||||
.s_axi_awaddr(32'B0),
|
||||
.s_axi_awlen(8'B0),
|
||||
.s_axi_awsize(3'B0),
|
||||
.s_axi_awburst(2'B0),
|
||||
.s_axi_awlock(1'B0),
|
||||
.s_axi_awcache(4'B0),
|
||||
.s_axi_awprot(3'B0),
|
||||
.s_axi_awqos(4'B0),
|
||||
.s_axi_awregion(4'B0),
|
||||
.s_axi_awuser(1'B0),
|
||||
.s_axi_awvalid(1'D0),
|
||||
.s_axi_awready(),
|
||||
.s_axi_wid(1'B0),
|
||||
.s_axi_wdata(64'B0),
|
||||
.s_axi_wstrb(8'B0),
|
||||
.s_axi_wlast(1'D0),
|
||||
.s_axi_wuser(1'B0),
|
||||
.s_axi_wvalid(1'D0),
|
||||
.s_axi_wready(),
|
||||
.s_axi_bid(),
|
||||
.s_axi_bresp(),
|
||||
.s_axi_buser(),
|
||||
.s_axi_bvalid(),
|
||||
.s_axi_bready(1'D0),
|
||||
.m_axi_awid(),
|
||||
.m_axi_awaddr(),
|
||||
.m_axi_awlen(),
|
||||
.m_axi_awsize(),
|
||||
.m_axi_awburst(),
|
||||
.m_axi_awlock(),
|
||||
.m_axi_awcache(),
|
||||
.m_axi_awprot(),
|
||||
.m_axi_awqos(),
|
||||
.m_axi_awregion(),
|
||||
.m_axi_awuser(),
|
||||
.m_axi_awvalid(),
|
||||
.m_axi_awready(1'D0),
|
||||
.m_axi_wid(),
|
||||
.m_axi_wdata(),
|
||||
.m_axi_wstrb(),
|
||||
.m_axi_wlast(),
|
||||
.m_axi_wuser(),
|
||||
.m_axi_wvalid(),
|
||||
.m_axi_wready(1'D0),
|
||||
.m_axi_bid(1'B0),
|
||||
.m_axi_bresp(2'B0),
|
||||
.m_axi_buser(1'B0),
|
||||
.m_axi_bvalid(1'D0),
|
||||
.m_axi_bready(),
|
||||
.s_axi_arid(1'B0),
|
||||
.s_axi_araddr(32'B0),
|
||||
.s_axi_arlen(8'B0),
|
||||
.s_axi_arsize(3'B0),
|
||||
.s_axi_arburst(2'B0),
|
||||
.s_axi_arlock(1'B0),
|
||||
.s_axi_arcache(4'B0),
|
||||
.s_axi_arprot(3'B0),
|
||||
.s_axi_arqos(4'B0),
|
||||
.s_axi_arregion(4'B0),
|
||||
.s_axi_aruser(1'B0),
|
||||
.s_axi_arvalid(1'D0),
|
||||
.s_axi_arready(),
|
||||
.s_axi_rid(),
|
||||
.s_axi_rdata(),
|
||||
.s_axi_rresp(),
|
||||
.s_axi_rlast(),
|
||||
.s_axi_ruser(),
|
||||
.s_axi_rvalid(),
|
||||
.s_axi_rready(1'D0),
|
||||
.m_axi_arid(),
|
||||
.m_axi_araddr(),
|
||||
.m_axi_arlen(),
|
||||
.m_axi_arsize(),
|
||||
.m_axi_arburst(),
|
||||
.m_axi_arlock(),
|
||||
.m_axi_arcache(),
|
||||
.m_axi_arprot(),
|
||||
.m_axi_arqos(),
|
||||
.m_axi_arregion(),
|
||||
.m_axi_aruser(),
|
||||
.m_axi_arvalid(),
|
||||
.m_axi_arready(1'D0),
|
||||
.m_axi_rid(1'B0),
|
||||
.m_axi_rdata(64'B0),
|
||||
.m_axi_rresp(2'B0),
|
||||
.m_axi_rlast(1'D0),
|
||||
.m_axi_ruser(1'B0),
|
||||
.m_axi_rvalid(1'D0),
|
||||
.m_axi_rready(),
|
||||
.s_axis_tvalid(1'D0),
|
||||
.s_axis_tready(),
|
||||
.s_axis_tdata(8'B0),
|
||||
.s_axis_tstrb(1'B0),
|
||||
.s_axis_tkeep(1'B0),
|
||||
.s_axis_tlast(1'D0),
|
||||
.s_axis_tid(1'B0),
|
||||
.s_axis_tdest(1'B0),
|
||||
.s_axis_tuser(4'B0),
|
||||
.m_axis_tvalid(),
|
||||
.m_axis_tready(1'D0),
|
||||
.m_axis_tdata(),
|
||||
.m_axis_tstrb(),
|
||||
.m_axis_tkeep(),
|
||||
.m_axis_tlast(),
|
||||
.m_axis_tid(),
|
||||
.m_axis_tdest(),
|
||||
.m_axis_tuser(),
|
||||
.axi_aw_injectsbiterr(1'D0),
|
||||
.axi_aw_injectdbiterr(1'D0),
|
||||
.axi_aw_prog_full_thresh(4'B0),
|
||||
.axi_aw_prog_empty_thresh(4'B0),
|
||||
.axi_aw_data_count(),
|
||||
.axi_aw_wr_data_count(),
|
||||
.axi_aw_rd_data_count(),
|
||||
.axi_aw_sbiterr(),
|
||||
.axi_aw_dbiterr(),
|
||||
.axi_aw_overflow(),
|
||||
.axi_aw_underflow(),
|
||||
.axi_aw_prog_full(),
|
||||
.axi_aw_prog_empty(),
|
||||
.axi_w_injectsbiterr(1'D0),
|
||||
.axi_w_injectdbiterr(1'D0),
|
||||
.axi_w_prog_full_thresh(10'B0),
|
||||
.axi_w_prog_empty_thresh(10'B0),
|
||||
.axi_w_data_count(),
|
||||
.axi_w_wr_data_count(),
|
||||
.axi_w_rd_data_count(),
|
||||
.axi_w_sbiterr(),
|
||||
.axi_w_dbiterr(),
|
||||
.axi_w_overflow(),
|
||||
.axi_w_underflow(),
|
||||
.axi_w_prog_full(),
|
||||
.axi_w_prog_empty(),
|
||||
.axi_b_injectsbiterr(1'D0),
|
||||
.axi_b_injectdbiterr(1'D0),
|
||||
.axi_b_prog_full_thresh(4'B0),
|
||||
.axi_b_prog_empty_thresh(4'B0),
|
||||
.axi_b_data_count(),
|
||||
.axi_b_wr_data_count(),
|
||||
.axi_b_rd_data_count(),
|
||||
.axi_b_sbiterr(),
|
||||
.axi_b_dbiterr(),
|
||||
.axi_b_overflow(),
|
||||
.axi_b_underflow(),
|
||||
.axi_b_prog_full(),
|
||||
.axi_b_prog_empty(),
|
||||
.axi_ar_injectsbiterr(1'D0),
|
||||
.axi_ar_injectdbiterr(1'D0),
|
||||
.axi_ar_prog_full_thresh(4'B0),
|
||||
.axi_ar_prog_empty_thresh(4'B0),
|
||||
.axi_ar_data_count(),
|
||||
.axi_ar_wr_data_count(),
|
||||
.axi_ar_rd_data_count(),
|
||||
.axi_ar_sbiterr(),
|
||||
.axi_ar_dbiterr(),
|
||||
.axi_ar_overflow(),
|
||||
.axi_ar_underflow(),
|
||||
.axi_ar_prog_full(),
|
||||
.axi_ar_prog_empty(),
|
||||
.axi_r_injectsbiterr(1'D0),
|
||||
.axi_r_injectdbiterr(1'D0),
|
||||
.axi_r_prog_full_thresh(10'B0),
|
||||
.axi_r_prog_empty_thresh(10'B0),
|
||||
.axi_r_data_count(),
|
||||
.axi_r_wr_data_count(),
|
||||
.axi_r_rd_data_count(),
|
||||
.axi_r_sbiterr(),
|
||||
.axi_r_dbiterr(),
|
||||
.axi_r_overflow(),
|
||||
.axi_r_underflow(),
|
||||
.axi_r_prog_full(),
|
||||
.axi_r_prog_empty(),
|
||||
.axis_injectsbiterr(1'D0),
|
||||
.axis_injectdbiterr(1'D0),
|
||||
.axis_prog_full_thresh(10'B0),
|
||||
.axis_prog_empty_thresh(10'B0),
|
||||
.axis_data_count(),
|
||||
.axis_wr_data_count(),
|
||||
.axis_rd_data_count(),
|
||||
.axis_sbiterr(),
|
||||
.axis_dbiterr(),
|
||||
.axis_overflow(),
|
||||
.axis_underflow(),
|
||||
.axis_prog_full(),
|
||||
.axis_prog_empty()
|
||||
);
|
||||
endmodule
|
||||
+14
-14
@@ -60,7 +60,7 @@
|
||||
-- Using this testbench
|
||||
--
|
||||
-- This testbench instantiates your generated FIR Compiler core
|
||||
-- instance named "fir_prbs7_invert_rep4".
|
||||
-- instance named "fir_prbs10_invert_rep2".
|
||||
--
|
||||
-- Use Vivado's Run Simulation flow to run this testbench. See the Vivado
|
||||
-- documentation for details.
|
||||
@@ -70,10 +70,10 @@ library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity tb_fir_prbs7_invert_rep4 is
|
||||
end tb_fir_prbs7_invert_rep4;
|
||||
entity tb_fir_prbs10_invert_rep2 is
|
||||
end tb_fir_prbs10_invert_rep2;
|
||||
|
||||
architecture tb of tb_fir_prbs7_invert_rep4 is
|
||||
architecture tb of tb_fir_prbs10_invert_rep2 is
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Timing constants
|
||||
@@ -110,7 +110,7 @@ architecture tb of tb_fir_prbs7_invert_rep4 is
|
||||
signal s_axis_data_tdata_data : std_logic_vector(11 downto 0) := (others => '0');
|
||||
|
||||
-- Data master channel alias signals
|
||||
signal m_axis_data_tdata_data : std_logic_vector(20 downto 0) := (others => '0');
|
||||
signal m_axis_data_tdata_data : std_logic_vector(22 downto 0) := (others => '0');
|
||||
|
||||
|
||||
begin
|
||||
@@ -119,7 +119,7 @@ begin
|
||||
-- Instantiate the DUT
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
dut : entity work.fir_prbs7_invert_rep4
|
||||
dut : entity work.fir_prbs10_invert_rep2
|
||||
port map (
|
||||
aclk => aclk,
|
||||
aresetn => aresetn,
|
||||
@@ -169,9 +169,9 @@ begin
|
||||
end loop;
|
||||
ip_count := ip_count + 1;
|
||||
wait for T_HOLD;
|
||||
-- Input rate is 1 input each 2 clock cycles: drive valid inputs at this rate
|
||||
-- Input rate is 1 input each 16 clock cycles: drive valid inputs at this rate
|
||||
s_axis_data_tvalid <= '0';
|
||||
wait for CLOCK_PERIOD * 1;
|
||||
wait for CLOCK_PERIOD * 15;
|
||||
exit when ip_count >= samples;
|
||||
end loop;
|
||||
end procedure drive_data;
|
||||
@@ -185,7 +185,7 @@ begin
|
||||
|
||||
-- Procedure to drive an impulse and let the impulse response emerge on the data master channel
|
||||
-- samples is the number of input samples to drive; default is enough for impulse response output to emerge
|
||||
procedure drive_impulse ( samples : natural := 651 ) is
|
||||
procedure drive_impulse ( samples : natural := 2062 ) is
|
||||
variable impulse : std_logic_vector(15 downto 0);
|
||||
begin
|
||||
impulse := (others => '0'); -- initialize unused bits to zero
|
||||
@@ -208,15 +208,15 @@ begin
|
||||
-- Drive another impulse, during which demonstrate use and effect of AXI handshaking signals
|
||||
drive_impulse(2); -- start of impulse; data is now zero
|
||||
s_axis_data_tvalid <= '0';
|
||||
wait for CLOCK_PERIOD * 10; -- provide no data for 5 input samples worth
|
||||
wait for CLOCK_PERIOD * 80; -- provide no data for 5 input samples worth
|
||||
drive_zeros(2); -- 2 normal input samples
|
||||
s_axis_data_tvalid <= '1';
|
||||
wait for CLOCK_PERIOD * 10; -- provide data as fast as the core can accept it for 5 input samples worth
|
||||
drive_zeros(642); -- back to normal operation
|
||||
wait for CLOCK_PERIOD * 80; -- provide data as fast as the core can accept it for 5 input samples worth
|
||||
drive_zeros(2053); -- back to normal operation
|
||||
|
||||
-- Drive another impulse, during which demonstrate:
|
||||
-- reset (aresetn)
|
||||
drive_impulse(262); -- to partway through impulse response
|
||||
drive_impulse(521); -- to partway through impulse response
|
||||
s_axis_data_tvalid <= '0';
|
||||
aresetn <= '0'; -- assert reset (active low)
|
||||
wait for CLOCK_PERIOD * 2; -- hold reset active for 2 clock cycles, as recommended in FIR Compiler Datasheet
|
||||
@@ -267,6 +267,6 @@ begin
|
||||
s_axis_data_tdata_data <= s_axis_data_tdata(11 downto 0);
|
||||
|
||||
-- Data master channel alias signals: update these only when they are valid
|
||||
m_axis_data_tdata_data <= m_axis_data_tdata(20 downto 0) when m_axis_data_tvalid = '1';
|
||||
m_axis_data_tdata_data <= m_axis_data_tdata(22 downto 0) when m_axis_data_tvalid = '1';
|
||||
|
||||
end tb;
|
||||
+3
-3
@@ -54,7 +54,7 @@
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
fir_prbs7_invert_rep4 your_instance_name (
|
||||
fir_prbs10_invert_rep2 your_instance_name (
|
||||
.aresetn(aresetn), // input wire aresetn
|
||||
.aclk(aclk), // input wire aclk
|
||||
.s_axis_data_tvalid(s_axis_data_tvalid), // input wire s_axis_data_tvalid
|
||||
@@ -65,7 +65,7 @@ fir_prbs7_invert_rep4 your_instance_name (
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file fir_prbs7_invert_rep4.v when simulating
|
||||
// the core, fir_prbs7_invert_rep4. When compiling the wrapper file, be sure to
|
||||
// You must compile the wrapper file fir_prbs10_invert_rep2.v when simulating
|
||||
// the core, fir_prbs10_invert_rep2. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
+4
-4
@@ -52,7 +52,7 @@
|
||||
-- The following code must appear in the VHDL architecture header.
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
COMPONENT fir_prbs7_invert_rep4
|
||||
COMPONENT fir_prbs10_invert_rep2
|
||||
PORT (
|
||||
aresetn : IN STD_LOGIC;
|
||||
aclk : IN STD_LOGIC;
|
||||
@@ -69,7 +69,7 @@ END COMPONENT;
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : fir_prbs7_invert_rep4
|
||||
your_instance_name : fir_prbs10_invert_rep2
|
||||
PORT MAP (
|
||||
aresetn => aresetn,
|
||||
aclk => aclk,
|
||||
@@ -81,7 +81,7 @@ your_instance_name : fir_prbs7_invert_rep4
|
||||
);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
-- You must compile the wrapper file fir_prbs7_invert_rep4.vhd when simulating
|
||||
-- the core, fir_prbs7_invert_rep4. When compiling the wrapper file, be sure to
|
||||
-- You must compile the wrapper file fir_prbs10_invert_rep2.vhd when simulating
|
||||
-- the core, fir_prbs10_invert_rep2. When compiling the wrapper file, be sure to
|
||||
-- reference the VHDL simulation library.
|
||||
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
+12
-13
@@ -1,11 +1,11 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Mon May 8 00:29:10 2023
|
||||
// Date : Fri May 12 16:05:14 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp_stub.v
|
||||
// Design : dds_32b_8b_comp
|
||||
// /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2_stub.v
|
||||
// Design : fir_prbs10_invert_rep2
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
@@ -13,16 +13,15 @@
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "dds_compiler_v6_0_18,Vivado 2019.1.3" *)
|
||||
module dds_32b_8b_comp(aclk, s_axis_config_tvalid,
|
||||
s_axis_config_tdata, m_axis_data_tvalid, m_axis_data_tdata, m_axis_phase_tvalid,
|
||||
m_axis_phase_tdata)
|
||||
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_config_tvalid,s_axis_config_tdata[63:0],m_axis_data_tvalid,m_axis_data_tdata[15:0],m_axis_phase_tvalid,m_axis_phase_tdata[31:0]" */;
|
||||
(* x_core_info = "fir_compiler_v7_2_12,Vivado 2019.1.3" *)
|
||||
module fir_prbs10_invert_rep2(aresetn, aclk, s_axis_data_tvalid,
|
||||
s_axis_data_tready, s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata)
|
||||
/* synthesis syn_black_box black_box_pad_pin="aresetn,aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[15:0],m_axis_data_tvalid,m_axis_data_tdata[23:0]" */;
|
||||
input aresetn;
|
||||
input aclk;
|
||||
input s_axis_config_tvalid;
|
||||
input [63:0]s_axis_config_tdata;
|
||||
input s_axis_data_tvalid;
|
||||
output s_axis_data_tready;
|
||||
input [15:0]s_axis_data_tdata;
|
||||
output m_axis_data_tvalid;
|
||||
output [15:0]m_axis_data_tdata;
|
||||
output m_axis_phase_tvalid;
|
||||
output [31:0]m_axis_phase_tdata;
|
||||
output [23:0]m_axis_data_tdata;
|
||||
endmodule
|
||||
+13
-13
@@ -1,36 +1,36 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Mon May 8 00:29:10 2023
|
||||
-- Date : Fri May 12 16:05:14 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp_stub.vhdl
|
||||
-- Design : dds_32b_8b_comp
|
||||
-- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2_stub.vhdl
|
||||
-- Design : fir_prbs10_invert_rep2
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity dds_32b_8b_comp is
|
||||
entity fir_prbs10_invert_rep2 is
|
||||
Port (
|
||||
aresetn : in STD_LOGIC;
|
||||
aclk : in STD_LOGIC;
|
||||
s_axis_config_tvalid : in STD_LOGIC;
|
||||
s_axis_config_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
|
||||
s_axis_data_tvalid : in STD_LOGIC;
|
||||
s_axis_data_tready : out STD_LOGIC;
|
||||
s_axis_data_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
m_axis_data_tvalid : out STD_LOGIC;
|
||||
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
m_axis_phase_tvalid : out STD_LOGIC;
|
||||
m_axis_phase_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 )
|
||||
);
|
||||
|
||||
end dds_32b_8b_comp;
|
||||
end fir_prbs10_invert_rep2;
|
||||
|
||||
architecture stub of dds_32b_8b_comp is
|
||||
architecture stub of fir_prbs10_invert_rep2 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_config_tvalid,s_axis_config_tdata[63:0],m_axis_data_tvalid,m_axis_data_tdata[15:0],m_axis_phase_tvalid,m_axis_phase_tdata[31:0]";
|
||||
attribute black_box_pad_pin of stub : architecture is "aresetn,aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[15:0],m_axis_data_tvalid,m_axis_data_tdata[23:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "dds_compiler_v6_0_18,Vivado 2019.1.3";
|
||||
attribute x_core_info of stub : architecture is "fir_compiler_v7_2_12,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+19
-19
@@ -56,7 +56,7 @@ USE ieee.numeric_std.ALL;
|
||||
LIBRARY fir_compiler_v7_2_12;
|
||||
USE fir_compiler_v7_2_12.fir_compiler_v7_2_12;
|
||||
|
||||
ENTITY fir_prbs7_invert_rep4 IS
|
||||
ENTITY fir_prbs10_invert_rep2 IS
|
||||
PORT (
|
||||
aresetn : IN STD_LOGIC;
|
||||
aclk : IN STD_LOGIC;
|
||||
@@ -66,11 +66,11 @@ ENTITY fir_prbs7_invert_rep4 IS
|
||||
m_axis_data_tvalid : OUT STD_LOGIC;
|
||||
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
|
||||
);
|
||||
END fir_prbs7_invert_rep4;
|
||||
END fir_prbs10_invert_rep2;
|
||||
|
||||
ARCHITECTURE fir_prbs7_invert_rep4_arch OF fir_prbs7_invert_rep4 IS
|
||||
ARCHITECTURE fir_prbs10_invert_rep2_arch OF fir_prbs10_invert_rep2 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fir_prbs7_invert_rep4_arch: ARCHITECTURE IS "yes";
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fir_prbs10_invert_rep2_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT fir_compiler_v7_2_12 IS
|
||||
GENERIC (
|
||||
C_XDEVICEFAMILY : STRING;
|
||||
@@ -193,16 +193,16 @@ BEGIN
|
||||
GENERIC MAP (
|
||||
C_XDEVICEFAMILY => "kintex7",
|
||||
C_ELABORATION_DIR => "./",
|
||||
C_COMPONENT_NAME => "fir_prbs7_invert_rep4",
|
||||
C_COEF_FILE => "fir_prbs7_invert_rep4.mif",
|
||||
C_COEF_FILE_LINES => 512,
|
||||
C_COMPONENT_NAME => "fir_prbs10_invert_rep2",
|
||||
C_COEF_FILE => "fir_prbs10_invert_rep2.mif",
|
||||
C_COEF_FILE_LINES => 2048,
|
||||
C_FILTER_TYPE => 0,
|
||||
C_INTERP_RATE => 1,
|
||||
C_DECIM_RATE => 1,
|
||||
C_ZERO_PACKING_FACTOR => 1,
|
||||
C_SYMMETRY => 0,
|
||||
C_NUM_FILTS => 1,
|
||||
C_NUM_TAPS => 512,
|
||||
C_NUM_TAPS => 2048,
|
||||
C_NUM_CHANNELS => 1,
|
||||
C_CHANNEL_PATTERN => "fixed",
|
||||
C_ROUND_MODE => 0,
|
||||
@@ -210,7 +210,7 @@ BEGIN
|
||||
C_NUM_RELOAD_SLOTS => 1,
|
||||
C_COL_MODE => 1,
|
||||
C_COL_PIPE_LEN => 4,
|
||||
C_COL_CONFIG => "140,116",
|
||||
C_COL_CONFIG => "128",
|
||||
C_OPTIMIZATION => 0,
|
||||
C_DATA_PATH_WIDTHS => "12",
|
||||
C_DATA_IP_PATH_WIDTHS => "12",
|
||||
@@ -223,18 +223,18 @@ BEGIN
|
||||
C_PX_PATH_SRC => "0",
|
||||
C_DATA_PATH_SIGN => "0",
|
||||
C_COEF_PATH_SIGN => "0",
|
||||
C_ACCUM_PATH_WIDTHS => "21",
|
||||
C_OUTPUT_WIDTH => 21,
|
||||
C_OUTPUT_PATH_WIDTHS => "21",
|
||||
C_ACCUM_OP_PATH_WIDTHS => "21",
|
||||
C_ACCUM_PATH_WIDTHS => "23",
|
||||
C_OUTPUT_WIDTH => 23,
|
||||
C_OUTPUT_PATH_WIDTHS => "23",
|
||||
C_ACCUM_OP_PATH_WIDTHS => "23",
|
||||
C_EXT_MULT_CNFG => "none",
|
||||
C_DATA_PATH_PSAMP_SRC => "0",
|
||||
C_OP_PATH_PSAMP_SRC => "0",
|
||||
C_NUM_MADDS => 256,
|
||||
C_NUM_MADDS => 128,
|
||||
C_OPT_MADDS => "none",
|
||||
C_OVERSAMPLING_RATE => 2,
|
||||
C_INPUT_RATE => 2,
|
||||
C_OUTPUT_RATE => 2,
|
||||
C_OVERSAMPLING_RATE => 16,
|
||||
C_INPUT_RATE => 16,
|
||||
C_OUTPUT_RATE => 16,
|
||||
C_DATA_MEMTYPE => 0,
|
||||
C_COEF_MEMTYPE => 2,
|
||||
C_IPBUFF_MEMTYPE => 2,
|
||||
@@ -244,7 +244,7 @@ BEGIN
|
||||
C_DATA_MEM_PACKING => 0,
|
||||
C_COEF_MEM_PACKING => 0,
|
||||
C_FILTS_PACKED => 0,
|
||||
C_LATENCY => 269,
|
||||
C_LATENCY => 151,
|
||||
C_HAS_ARESETn => 1,
|
||||
C_HAS_ACLKEN => 0,
|
||||
C_DATA_HAS_TLAST => 0,
|
||||
@@ -281,4 +281,4 @@ BEGIN
|
||||
m_axis_data_tready => '1',
|
||||
m_axis_data_tdata => m_axis_data_tdata
|
||||
);
|
||||
END fir_prbs7_invert_rep4_arch;
|
||||
END fir_prbs10_invert_rep2_arch;
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
+12
-13
@@ -57,7 +57,7 @@ ila_freq_comp your_instance_name (
|
||||
.clk(clk), // input wire clk
|
||||
|
||||
|
||||
.probe0(probe0), // input wire [17:0] probe0
|
||||
.probe0(probe0), // input wire [0:0] probe0
|
||||
.probe1(probe1), // input wire [17:0] probe1
|
||||
.probe2(probe2), // input wire [17:0] probe2
|
||||
.probe3(probe3), // input wire [17:0] probe3
|
||||
@@ -66,19 +66,18 @@ ila_freq_comp your_instance_name (
|
||||
.probe6(probe6), // input wire [17:0] probe6
|
||||
.probe7(probe7), // input wire [17:0] probe7
|
||||
.probe8(probe8), // input wire [17:0] probe8
|
||||
.probe9(probe9), // input wire [2:0] probe9
|
||||
.probe10(probe10), // input wire [0:0] probe10
|
||||
.probe11(probe11), // input wire [0:0] probe11
|
||||
.probe12(probe12), // input wire [0:0] probe12
|
||||
.probe13(probe13), // input wire [31:0] probe13
|
||||
.probe14(probe14), // input wire [0:0] probe14
|
||||
.probe15(probe15), // input wire [31:0] probe15
|
||||
.probe9(probe9), // input wire [10:0] probe9
|
||||
.probe10(probe10), // input wire [10:0] probe10
|
||||
.probe11(probe11), // input wire [10:0] probe11
|
||||
.probe12(probe12), // input wire [10:0] probe12
|
||||
.probe13(probe13), // input wire [0:0] probe13
|
||||
.probe14(probe14), // input wire [2:0] probe14
|
||||
.probe15(probe15), // input wire [11:0] probe15
|
||||
.probe16(probe16), // input wire [11:0] probe16
|
||||
.probe17(probe17), // input wire [11:0] probe17
|
||||
.probe18(probe18), // input wire [9:0] probe18
|
||||
.probe19(probe19), // input wire [9:0] probe19
|
||||
.probe20(probe20), // input wire [9:0] probe20
|
||||
.probe21(probe21) // input wire [9:0] probe21
|
||||
.probe17(probe17), // input wire [17:0] probe17
|
||||
.probe18(probe18), // input wire [17:0] probe18
|
||||
.probe19(probe19), // input wire [31:0] probe19
|
||||
.probe20(probe20) // input wire [11:0] probe20
|
||||
);
|
||||
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
LFS
BIN
Binary file not shown.
BIN
Binary file not shown.
+15
-16
@@ -1,7 +1,7 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Mon May 8 12:16:12 2023
|
||||
// Date : Fri May 12 16:06:03 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_stub.v
|
||||
@@ -16,10 +16,10 @@
|
||||
(* X_CORE_INFO = "ila,Vivado 2019.1.3" *)
|
||||
module ila_freq_comp(clk, probe0, probe1, probe2, probe3, probe4, probe5,
|
||||
probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17,
|
||||
probe18, probe19, probe20, probe21)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[17:0],probe1[17:0],probe2[17:0],probe3[17:0],probe4[17:0],probe5[17:0],probe6[17:0],probe7[17:0],probe8[17:0],probe9[2:0],probe10[0:0],probe11[0:0],probe12[0:0],probe13[31:0],probe14[0:0],probe15[31:0],probe16[11:0],probe17[11:0],probe18[9:0],probe19[9:0],probe20[9:0],probe21[9:0]" */;
|
||||
probe18, probe19, probe20)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[0:0],probe1[17:0],probe2[17:0],probe3[17:0],probe4[17:0],probe5[17:0],probe6[17:0],probe7[17:0],probe8[17:0],probe9[10:0],probe10[10:0],probe11[10:0],probe12[10:0],probe13[0:0],probe14[2:0],probe15[11:0],probe16[11:0],probe17[17:0],probe18[17:0],probe19[31:0],probe20[11:0]" */;
|
||||
input clk;
|
||||
input [17:0]probe0;
|
||||
input [0:0]probe0;
|
||||
input [17:0]probe1;
|
||||
input [17:0]probe2;
|
||||
input [17:0]probe3;
|
||||
@@ -28,17 +28,16 @@ module ila_freq_comp(clk, probe0, probe1, probe2, probe3, probe4, probe5,
|
||||
input [17:0]probe6;
|
||||
input [17:0]probe7;
|
||||
input [17:0]probe8;
|
||||
input [2:0]probe9;
|
||||
input [0:0]probe10;
|
||||
input [0:0]probe11;
|
||||
input [0:0]probe12;
|
||||
input [31:0]probe13;
|
||||
input [0:0]probe14;
|
||||
input [31:0]probe15;
|
||||
input [10:0]probe9;
|
||||
input [10:0]probe10;
|
||||
input [10:0]probe11;
|
||||
input [10:0]probe12;
|
||||
input [0:0]probe13;
|
||||
input [2:0]probe14;
|
||||
input [11:0]probe15;
|
||||
input [11:0]probe16;
|
||||
input [11:0]probe17;
|
||||
input [9:0]probe18;
|
||||
input [9:0]probe19;
|
||||
input [9:0]probe20;
|
||||
input [9:0]probe21;
|
||||
input [17:0]probe17;
|
||||
input [17:0]probe18;
|
||||
input [31:0]probe19;
|
||||
input [11:0]probe20;
|
||||
endmodule
|
||||
|
||||
+14
-15
@@ -1,7 +1,7 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Mon May 8 12:16:12 2023
|
||||
-- Date : Fri May 12 16:06:03 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_stub.vhdl
|
||||
@@ -15,7 +15,7 @@ use IEEE.STD_LOGIC_1164.ALL;
|
||||
entity ila_freq_comp is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe0 : in STD_LOGIC_VECTOR ( 17 downto 0 );
|
||||
probe0 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe1 : in STD_LOGIC_VECTOR ( 17 downto 0 );
|
||||
probe2 : in STD_LOGIC_VECTOR ( 17 downto 0 );
|
||||
probe3 : in STD_LOGIC_VECTOR ( 17 downto 0 );
|
||||
@@ -24,19 +24,18 @@ entity ila_freq_comp is
|
||||
probe6 : in STD_LOGIC_VECTOR ( 17 downto 0 );
|
||||
probe7 : in STD_LOGIC_VECTOR ( 17 downto 0 );
|
||||
probe8 : in STD_LOGIC_VECTOR ( 17 downto 0 );
|
||||
probe9 : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
probe10 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe11 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe12 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe13 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe14 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe15 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe9 : in STD_LOGIC_VECTOR ( 10 downto 0 );
|
||||
probe10 : in STD_LOGIC_VECTOR ( 10 downto 0 );
|
||||
probe11 : in STD_LOGIC_VECTOR ( 10 downto 0 );
|
||||
probe12 : in STD_LOGIC_VECTOR ( 10 downto 0 );
|
||||
probe13 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe14 : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
probe15 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe16 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe17 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe18 : in STD_LOGIC_VECTOR ( 9 downto 0 );
|
||||
probe19 : in STD_LOGIC_VECTOR ( 9 downto 0 );
|
||||
probe20 : in STD_LOGIC_VECTOR ( 9 downto 0 );
|
||||
probe21 : in STD_LOGIC_VECTOR ( 9 downto 0 )
|
||||
probe17 : in STD_LOGIC_VECTOR ( 17 downto 0 );
|
||||
probe18 : in STD_LOGIC_VECTOR ( 17 downto 0 );
|
||||
probe19 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe20 : in STD_LOGIC_VECTOR ( 11 downto 0 )
|
||||
);
|
||||
|
||||
end ila_freq_comp;
|
||||
@@ -45,7 +44,7 @@ architecture stub of ila_freq_comp is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe0[17:0],probe1[17:0],probe2[17:0],probe3[17:0],probe4[17:0],probe5[17:0],probe6[17:0],probe7[17:0],probe8[17:0],probe9[2:0],probe10[0:0],probe11[0:0],probe12[0:0],probe13[31:0],probe14[0:0],probe15[31:0],probe16[11:0],probe17[11:0],probe18[9:0],probe19[9:0],probe20[9:0],probe21[9:0]";
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe0[0:0],probe1[17:0],probe2[17:0],probe3[17:0],probe4[17:0],probe5[17:0],probe6[17:0],probe7[17:0],probe8[17:0],probe9[10:0],probe10[10:0],probe11[10:0],probe12[10:0],probe13[0:0],probe14[2:0],probe15[11:0],probe16[11:0],probe17[17:0],probe18[17:0],probe19[31:0],probe20[11:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3";
|
||||
begin
|
||||
|
||||
+13
-15
@@ -70,14 +70,13 @@ probe16,
|
||||
probe17,
|
||||
probe18,
|
||||
probe19,
|
||||
probe20,
|
||||
probe21
|
||||
probe20
|
||||
);
|
||||
|
||||
input clk;
|
||||
|
||||
|
||||
input [17 : 0] probe0;
|
||||
input [0 : 0] probe0;
|
||||
input [17 : 0] probe1;
|
||||
input [17 : 0] probe2;
|
||||
input [17 : 0] probe3;
|
||||
@@ -86,19 +85,18 @@ input [17 : 0] probe5;
|
||||
input [17 : 0] probe6;
|
||||
input [17 : 0] probe7;
|
||||
input [17 : 0] probe8;
|
||||
input [2 : 0] probe9;
|
||||
input [0 : 0] probe10;
|
||||
input [0 : 0] probe11;
|
||||
input [0 : 0] probe12;
|
||||
input [31 : 0] probe13;
|
||||
input [0 : 0] probe14;
|
||||
input [31 : 0] probe15;
|
||||
input [10 : 0] probe9;
|
||||
input [10 : 0] probe10;
|
||||
input [10 : 0] probe11;
|
||||
input [10 : 0] probe12;
|
||||
input [0 : 0] probe13;
|
||||
input [2 : 0] probe14;
|
||||
input [11 : 0] probe15;
|
||||
input [11 : 0] probe16;
|
||||
input [11 : 0] probe17;
|
||||
input [9 : 0] probe18;
|
||||
input [9 : 0] probe19;
|
||||
input [9 : 0] probe20;
|
||||
input [9 : 0] probe21;
|
||||
input [17 : 0] probe17;
|
||||
input [17 : 0] probe18;
|
||||
input [31 : 0] probe19;
|
||||
input [11 : 0] probe20;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
+74
@@ -0,0 +1,74 @@
|
||||
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
|
||||
ila_rf_auto_control your_instance_name (
|
||||
.clk(clk), // input wire clk
|
||||
|
||||
|
||||
.probe0(probe0), // input wire [0:0] probe0
|
||||
.probe1(probe1), // input wire [31:0] probe1
|
||||
.probe2(probe2), // input wire [31:0] probe2
|
||||
.probe3(probe3), // input wire [0:0] probe3
|
||||
.probe4(probe4), // input wire [0:0] probe4
|
||||
.probe5(probe5) // input wire [7:0] probe5
|
||||
);
|
||||
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file ila_rf_auto_control when simulating
|
||||
// the core, ila_rf_auto_control. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
+26
@@ -0,0 +1,26 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Fri May 12 16:03:15 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control_stub.v
|
||||
// Design : ila_rf_auto_control
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "ila,Vivado 2019.1.3" *)
|
||||
module ila_rf_auto_control(clk, probe0, probe1, probe2, probe3, probe4, probe5)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[0:0],probe1[31:0],probe2[31:0],probe3[0:0],probe4[0:0],probe5[7:0]" */;
|
||||
input clk;
|
||||
input [0:0]probe0;
|
||||
input [31:0]probe1;
|
||||
input [31:0]probe2;
|
||||
input [0:0]probe3;
|
||||
input [0:0]probe4;
|
||||
input [7:0]probe5;
|
||||
endmodule
|
||||
+36
@@ -0,0 +1,36 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Fri May 12 16:03:15 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control_stub.vhdl
|
||||
-- Design : ila_rf_auto_control
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity ila_rf_auto_control is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe0 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe1 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe2 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe3 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe4 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe5 : in STD_LOGIC_VECTOR ( 7 downto 0 )
|
||||
);
|
||||
|
||||
end ila_rf_auto_control;
|
||||
|
||||
architecture stub of ila_rf_auto_control is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe0[0:0],probe1[31:0],probe2[31:0],probe3[0:0],probe4[0:0],probe5[7:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+72
@@ -0,0 +1,72 @@
|
||||
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
`timescale 1ns / 1ps
|
||||
module ila_rf_auto_control (
|
||||
clk,
|
||||
|
||||
|
||||
probe0,
|
||||
probe1,
|
||||
probe2,
|
||||
probe3,
|
||||
probe4,
|
||||
probe5
|
||||
);
|
||||
|
||||
input clk;
|
||||
|
||||
|
||||
input [0 : 0] probe0;
|
||||
input [31 : 0] probe1;
|
||||
input [31 : 0] probe2;
|
||||
input [0 : 0] probe3;
|
||||
input [0 : 0] probe4;
|
||||
input [7 : 0] probe5;
|
||||
|
||||
|
||||
endmodule
|
||||
+78
@@ -0,0 +1,78 @@
|
||||
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
|
||||
ila_rx_data_cnt your_instance_name (
|
||||
.clk(clk), // input wire clk
|
||||
|
||||
|
||||
.probe0(probe0), // input wire [11:0] probe0
|
||||
.probe1(probe1), // input wire [11:0] probe1
|
||||
.probe2(probe2), // input wire [11:0] probe2
|
||||
.probe3(probe3), // input wire [11:0] probe3
|
||||
.probe4(probe4), // input wire [11:0] probe4
|
||||
.probe5(probe5), // input wire [11:0] probe5
|
||||
.probe6(probe6), // input wire [11:0] probe6
|
||||
.probe7(probe7), // input wire [11:0] probe7
|
||||
.probe8(probe8), // input wire [11:0] probe8
|
||||
.probe9(probe9) // input wire [12:0] probe9
|
||||
);
|
||||
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file ila_rx_data_cnt when simulating
|
||||
// the core, ila_rx_data_cnt. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
+31
@@ -0,0 +1,31 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Fri May 12 16:03:10 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.v
|
||||
// Design : ila_rx_data_cnt
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "ila,Vivado 2019.1.3" *)
|
||||
module ila_rx_data_cnt(clk, probe0, probe1, probe2, probe3, probe4, probe5,
|
||||
probe6, probe7, probe8, probe9)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0],probe8[11:0],probe9[12:0]" */;
|
||||
input clk;
|
||||
input [11:0]probe0;
|
||||
input [11:0]probe1;
|
||||
input [11:0]probe2;
|
||||
input [11:0]probe3;
|
||||
input [11:0]probe4;
|
||||
input [11:0]probe5;
|
||||
input [11:0]probe6;
|
||||
input [11:0]probe7;
|
||||
input [11:0]probe8;
|
||||
input [12:0]probe9;
|
||||
endmodule
|
||||
+40
@@ -0,0 +1,40 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Fri May 12 16:03:10 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.vhdl
|
||||
-- Design : ila_rx_data_cnt
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity ila_rx_data_cnt is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe0 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe1 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe2 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe3 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe4 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe5 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe6 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe7 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe8 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe9 : in STD_LOGIC_VECTOR ( 12 downto 0 )
|
||||
);
|
||||
|
||||
end ila_rx_data_cnt;
|
||||
|
||||
architecture stub of ila_rx_data_cnt is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0],probe8[11:0],probe9[12:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+80
@@ -0,0 +1,80 @@
|
||||
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
`timescale 1ns / 1ps
|
||||
module ila_rx_data_cnt (
|
||||
clk,
|
||||
|
||||
|
||||
probe0,
|
||||
probe1,
|
||||
probe2,
|
||||
probe3,
|
||||
probe4,
|
||||
probe5,
|
||||
probe6,
|
||||
probe7,
|
||||
probe8,
|
||||
probe9
|
||||
);
|
||||
|
||||
input clk;
|
||||
|
||||
|
||||
input [11 : 0] probe0;
|
||||
input [11 : 0] probe1;
|
||||
input [11 : 0] probe2;
|
||||
input [11 : 0] probe3;
|
||||
input [11 : 0] probe4;
|
||||
input [11 : 0] probe5;
|
||||
input [11 : 0] probe6;
|
||||
input [11 : 0] probe7;
|
||||
input [11 : 0] probe8;
|
||||
input [12 : 0] probe9;
|
||||
|
||||
|
||||
endmodule
|
||||
LFS
BIN
Binary file not shown.
BIN
Binary file not shown.
+1
-1
@@ -1,7 +1,7 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Mon May 8 11:44:03 2023
|
||||
// Date : Fri May 12 16:06:19 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.v
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Mon May 8 11:44:03 2023
|
||||
-- Date : Fri May 12 16:06:19 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.vhdl
|
||||
|
||||
+5
-1
@@ -52,7 +52,9 @@ probe_in0,
|
||||
probe_out0,
|
||||
probe_out1,
|
||||
probe_out2,
|
||||
probe_out3
|
||||
probe_out3,
|
||||
probe_out4,
|
||||
probe_out5
|
||||
);
|
||||
|
||||
input clk;
|
||||
@@ -62,6 +64,8 @@ output reg [0 : 0] probe_out0 = 'h0 ;
|
||||
output reg [7 : 0] probe_out1 = 'h0A ;
|
||||
output reg [0 : 0] probe_out2 = 'h0 ;
|
||||
output reg [31 : 0] probe_out3 = 'h00000000 ;
|
||||
output reg [0 : 0] probe_out4 = 'h0 ;
|
||||
output reg [0 : 0] probe_out5 = 'h0 ;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
+3
-1
@@ -60,7 +60,9 @@ vio_freq_comp your_instance_name (
|
||||
.probe_out0(probe_out0), // output wire [0 : 0] probe_out0
|
||||
.probe_out1(probe_out1), // output wire [7 : 0] probe_out1
|
||||
.probe_out2(probe_out2), // output wire [0 : 0] probe_out2
|
||||
.probe_out3(probe_out3) // output wire [31 : 0] probe_out3
|
||||
.probe_out3(probe_out3), // output wire [31 : 0] probe_out3
|
||||
.probe_out4(probe_out4), // output wire [0 : 0] probe_out4
|
||||
.probe_out5(probe_out5) // output wire [0 : 0] probe_out5
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
|
||||
+6
-2
@@ -59,7 +59,9 @@ COMPONENT vio_freq_comp
|
||||
probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe_out1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
probe_out2 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe_out3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
probe_out3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe_out4 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe_out5 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
@@ -75,7 +77,9 @@ your_instance_name : vio_freq_comp
|
||||
probe_out0 => probe_out0,
|
||||
probe_out1 => probe_out1,
|
||||
probe_out2 => probe_out2,
|
||||
probe_out3 => probe_out3
|
||||
probe_out3 => probe_out3,
|
||||
probe_out4 => probe_out4,
|
||||
probe_out5 => probe_out5
|
||||
);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
|
||||
LFS
BIN
Binary file not shown.
BIN
Binary file not shown.
+5
-3
@@ -1,7 +1,7 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Sun May 7 16:51:33 2023
|
||||
// Date : Fri May 12 16:01:59 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.v
|
||||
@@ -15,12 +15,14 @@
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
|
||||
module vio_freq_comp(clk, probe_in0, probe_out0, probe_out1,
|
||||
probe_out2, probe_out3)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[0:0],probe_out0[0:0],probe_out1[7:0],probe_out2[0:0],probe_out3[31:0]" */;
|
||||
probe_out2, probe_out3, probe_out4, probe_out5)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[0:0],probe_out0[0:0],probe_out1[7:0],probe_out2[0:0],probe_out3[31:0],probe_out4[0:0],probe_out5[0:0]" */;
|
||||
input clk;
|
||||
input [0:0]probe_in0;
|
||||
output [0:0]probe_out0;
|
||||
output [7:0]probe_out1;
|
||||
output [0:0]probe_out2;
|
||||
output [31:0]probe_out3;
|
||||
output [0:0]probe_out4;
|
||||
output [0:0]probe_out5;
|
||||
endmodule
|
||||
|
||||
+5
-3
@@ -1,7 +1,7 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Sun May 7 16:51:33 2023
|
||||
-- Date : Fri May 12 16:01:59 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.vhdl
|
||||
@@ -19,7 +19,9 @@ entity vio_freq_comp is
|
||||
probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out1 : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out3 : out STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||
probe_out3 : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe_out4 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out5 : out STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
|
||||
end vio_freq_comp;
|
||||
@@ -28,7 +30,7 @@ architecture stub of vio_freq_comp is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[0:0],probe_out0[0:0],probe_out1[7:0],probe_out2[0:0],probe_out3[31:0]";
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[0:0],probe_out0[0:0],probe_out1[7:0],probe_out2[0:0],probe_out3[31:0],probe_out4[0:0],probe_out5[0:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
|
||||
begin
|
||||
|
||||
+10
-3
@@ -48,7 +48,7 @@
|
||||
`timescale 1ns / 1ps
|
||||
module vio_rfcontrl (
|
||||
clk,
|
||||
probe_in0,
|
||||
probe_in0,probe_in1,
|
||||
probe_out0,
|
||||
probe_out1,
|
||||
probe_out2,
|
||||
@@ -66,11 +66,15 @@ probe_out13,
|
||||
probe_out14,
|
||||
probe_out15,
|
||||
probe_out16,
|
||||
probe_out17
|
||||
probe_out17,
|
||||
probe_out18,
|
||||
probe_out19,
|
||||
probe_out20
|
||||
);
|
||||
|
||||
input clk;
|
||||
input [15 : 0] probe_in0;
|
||||
input [0 : 0] probe_in1;
|
||||
|
||||
output reg [0 : 0] probe_out0 = 'h0 ;
|
||||
output reg [0 : 0] probe_out1 = 'h0 ;
|
||||
@@ -89,7 +93,10 @@ output reg [0 : 0] probe_out13 = 'h0 ;
|
||||
output reg [0 : 0] probe_out14 = 'h0 ;
|
||||
output reg [0 : 0] probe_out15 = 'h0 ;
|
||||
output reg [0 : 0] probe_out16 = 'h0 ;
|
||||
output reg [15 : 0] probe_out17 = 'h0000 ;
|
||||
output reg [31 : 0] probe_out17 = 'h00000000 ;
|
||||
output reg [31 : 0] probe_out18 = 'h00000000 ;
|
||||
output reg [31 : 0] probe_out19 = 'h00000000 ;
|
||||
output reg [31 : 0] probe_out20 = 'h00000000 ;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
+5
-1
@@ -57,6 +57,7 @@
|
||||
vio_rfcontrl your_instance_name (
|
||||
.clk(clk), // input wire clk
|
||||
.probe_in0(probe_in0), // input wire [15 : 0] probe_in0
|
||||
.probe_in1(probe_in1), // input wire [0 : 0] probe_in1
|
||||
.probe_out0(probe_out0), // output wire [0 : 0] probe_out0
|
||||
.probe_out1(probe_out1), // output wire [0 : 0] probe_out1
|
||||
.probe_out2(probe_out2), // output wire [15 : 0] probe_out2
|
||||
@@ -74,7 +75,10 @@ vio_rfcontrl your_instance_name (
|
||||
.probe_out14(probe_out14), // output wire [0 : 0] probe_out14
|
||||
.probe_out15(probe_out15), // output wire [0 : 0] probe_out15
|
||||
.probe_out16(probe_out16), // output wire [0 : 0] probe_out16
|
||||
.probe_out17(probe_out17) // output wire [15 : 0] probe_out17
|
||||
.probe_out17(probe_out17), // output wire [31 : 0] probe_out17
|
||||
.probe_out18(probe_out18), // output wire [31 : 0] probe_out18
|
||||
.probe_out19(probe_out19), // output wire [31 : 0] probe_out19
|
||||
.probe_out20(probe_out20) // output wire [31 : 0] probe_out20
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
|
||||
+10
-2
@@ -56,6 +56,7 @@ COMPONENT vio_rfcontrl
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
probe_in0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
probe_in1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe_out1 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe_out2 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
@@ -73,7 +74,10 @@ COMPONENT vio_rfcontrl
|
||||
probe_out14 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe_out15 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe_out16 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe_out17 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
|
||||
probe_out17 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe_out18 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe_out19 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe_out20 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
@@ -86,6 +90,7 @@ your_instance_name : vio_rfcontrl
|
||||
PORT MAP (
|
||||
clk => clk,
|
||||
probe_in0 => probe_in0,
|
||||
probe_in1 => probe_in1,
|
||||
probe_out0 => probe_out0,
|
||||
probe_out1 => probe_out1,
|
||||
probe_out2 => probe_out2,
|
||||
@@ -103,7 +108,10 @@ your_instance_name : vio_rfcontrl
|
||||
probe_out14 => probe_out14,
|
||||
probe_out15 => probe_out15,
|
||||
probe_out16 => probe_out16,
|
||||
probe_out17 => probe_out17
|
||||
probe_out17 => probe_out17,
|
||||
probe_out18 => probe_out18,
|
||||
probe_out19 => probe_out19,
|
||||
probe_out20 => probe_out20
|
||||
);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
|
||||
LFS
BIN
Binary file not shown.
projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_sim_netlist.vhdl
LFS
BIN
Binary file not shown.
+11
-7
@@ -1,7 +1,7 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Mon May 8 10:18:46 2023
|
||||
// Date : Fri May 12 15:59:09 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.v
|
||||
@@ -14,13 +14,14 @@
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
|
||||
module vio_rfcontrl(clk, probe_in0, probe_out0, probe_out1,
|
||||
probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, probe_out9,
|
||||
probe_out10, probe_out11, probe_out12, probe_out13, probe_out14, probe_out15, probe_out16,
|
||||
probe_out17)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[15:0],probe_out0[0:0],probe_out1[0:0],probe_out2[15:0],probe_out3[7:0],probe_out4[3:0],probe_out5[3:0],probe_out6[3:0],probe_out7[3:0],probe_out8[7:0],probe_out9[7:0],probe_out10[15:0],probe_out11[15:0],probe_out12[15:0],probe_out13[0:0],probe_out14[0:0],probe_out15[0:0],probe_out16[0:0],probe_out17[15:0]" */;
|
||||
module vio_rfcontrl(clk, probe_in0, probe_in1, probe_out0,
|
||||
probe_out1, probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8,
|
||||
probe_out9, probe_out10, probe_out11, probe_out12, probe_out13, probe_out14, probe_out15,
|
||||
probe_out16, probe_out17, probe_out18, probe_out19, probe_out20)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[15:0],probe_in1[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[15:0],probe_out3[7:0],probe_out4[3:0],probe_out5[3:0],probe_out6[3:0],probe_out7[3:0],probe_out8[7:0],probe_out9[7:0],probe_out10[15:0],probe_out11[15:0],probe_out12[15:0],probe_out13[0:0],probe_out14[0:0],probe_out15[0:0],probe_out16[0:0],probe_out17[31:0],probe_out18[31:0],probe_out19[31:0],probe_out20[31:0]" */;
|
||||
input clk;
|
||||
input [15:0]probe_in0;
|
||||
input [0:0]probe_in1;
|
||||
output [0:0]probe_out0;
|
||||
output [0:0]probe_out1;
|
||||
output [15:0]probe_out2;
|
||||
@@ -38,5 +39,8 @@ module vio_rfcontrl(clk, probe_in0, probe_out0, probe_out1,
|
||||
output [0:0]probe_out14;
|
||||
output [0:0]probe_out15;
|
||||
output [0:0]probe_out16;
|
||||
output [15:0]probe_out17;
|
||||
output [31:0]probe_out17;
|
||||
output [31:0]probe_out18;
|
||||
output [31:0]probe_out19;
|
||||
output [31:0]probe_out20;
|
||||
endmodule
|
||||
|
||||
+7
-3
@@ -1,7 +1,7 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Mon May 8 10:18:46 2023
|
||||
-- Date : Fri May 12 15:59:09 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.vhdl
|
||||
@@ -16,6 +16,7 @@ entity vio_rfcontrl is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe_in0 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out2 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
@@ -33,7 +34,10 @@ entity vio_rfcontrl is
|
||||
probe_out14 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out15 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out16 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out17 : out STD_LOGIC_VECTOR ( 15 downto 0 )
|
||||
probe_out17 : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe_out18 : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe_out19 : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe_out20 : out STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||
);
|
||||
|
||||
end vio_rfcontrl;
|
||||
@@ -42,7 +46,7 @@ architecture stub of vio_rfcontrl is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[15:0],probe_out0[0:0],probe_out1[0:0],probe_out2[15:0],probe_out3[7:0],probe_out4[3:0],probe_out5[3:0],probe_out6[3:0],probe_out7[3:0],probe_out8[7:0],probe_out9[7:0],probe_out10[15:0],probe_out11[15:0],probe_out12[15:0],probe_out13[0:0],probe_out14[0:0],probe_out15[0:0],probe_out16[0:0],probe_out17[15:0]";
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[15:0],probe_in1[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[15:0],probe_out3[7:0],probe_out4[3:0],probe_out5[3:0],probe_out6[3:0],probe_out7[3:0],probe_out8[7:0],probe_out9[7:0],probe_out10[15:0],probe_out11[15:0],probe_out12[15:0],probe_out13[0:0],probe_out14[0:0],probe_out15[0:0],probe_out16[0:0],probe_out17[31:0],probe_out18[31:0],probe_out19[31:0],probe_out20[31:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
|
||||
begin
|
||||
|
||||
+7759
File diff suppressed because it is too large
Load Diff
+18807
File diff suppressed because it is too large
Load Diff
+10519
File diff suppressed because it is too large
Load Diff
+2048
File diff suppressed because it is too large
Load Diff
+80
-80
@@ -1,83 +1,83 @@
|
||||
MEMORY_INITIALIZATION_RADIX = 10;
|
||||
MEMORY_INITIALIZATION_VECTOR =
|
||||
1076,
|
||||
1088,
|
||||
1100,
|
||||
1112,
|
||||
1124,
|
||||
1136,
|
||||
1148,
|
||||
1160,
|
||||
1172,
|
||||
1184,
|
||||
1196,
|
||||
1208,
|
||||
1220,
|
||||
1232,
|
||||
1244,
|
||||
1256,
|
||||
1268,
|
||||
1280,
|
||||
1292,
|
||||
1304,
|
||||
1316,
|
||||
1328,
|
||||
1340,
|
||||
1352,
|
||||
1364,
|
||||
1376,
|
||||
1388,
|
||||
1400,
|
||||
1412,
|
||||
1424,
|
||||
1436,
|
||||
1448,
|
||||
1460,
|
||||
1472,
|
||||
1484,
|
||||
1496,
|
||||
1508,
|
||||
1520,
|
||||
1532,
|
||||
1544,
|
||||
1556,
|
||||
1568,
|
||||
1580,
|
||||
1592,
|
||||
1604,
|
||||
1616,
|
||||
1628,
|
||||
1640,
|
||||
1652,
|
||||
1664,
|
||||
1676,
|
||||
1688,
|
||||
1700,
|
||||
1712,
|
||||
1724,
|
||||
1736,
|
||||
1748,
|
||||
1760,
|
||||
1772,
|
||||
1784,
|
||||
1796,
|
||||
1808,
|
||||
1820,
|
||||
1832,
|
||||
1844,
|
||||
1856,
|
||||
1868,
|
||||
1880,
|
||||
1892,
|
||||
1904,
|
||||
2124,
|
||||
2111,
|
||||
2098,
|
||||
2085,
|
||||
2072,
|
||||
2059,
|
||||
2046,
|
||||
2033,
|
||||
2020,
|
||||
2007,
|
||||
1994,
|
||||
1981,
|
||||
1968,
|
||||
1955,
|
||||
1942,
|
||||
1929,
|
||||
1916,
|
||||
1928,
|
||||
1940,
|
||||
1952,
|
||||
1964,
|
||||
1976,
|
||||
1988,
|
||||
2000,
|
||||
2012,
|
||||
2024,
|
||||
2036,
|
||||
1903,
|
||||
1890,
|
||||
1877,
|
||||
1864,
|
||||
1851,
|
||||
1838,
|
||||
1825,
|
||||
1812,
|
||||
1799,
|
||||
1786,
|
||||
1773,
|
||||
1760,
|
||||
1747,
|
||||
1734,
|
||||
1721,
|
||||
1708,
|
||||
1695,
|
||||
1682,
|
||||
1669,
|
||||
1656,
|
||||
1643,
|
||||
1630,
|
||||
1617,
|
||||
1604,
|
||||
1591,
|
||||
1578,
|
||||
1565,
|
||||
1552,
|
||||
1539,
|
||||
1526,
|
||||
1513,
|
||||
1500,
|
||||
1487,
|
||||
1474,
|
||||
1461,
|
||||
1448,
|
||||
1435,
|
||||
1422,
|
||||
1409,
|
||||
1396,
|
||||
1383,
|
||||
1370,
|
||||
1357,
|
||||
1344,
|
||||
1331,
|
||||
1318,
|
||||
1305,
|
||||
1292,
|
||||
1279,
|
||||
1266,
|
||||
1253,
|
||||
1240,
|
||||
1227,
|
||||
1214,
|
||||
1201,
|
||||
1188,
|
||||
1175,
|
||||
1162,
|
||||
1149,
|
||||
1136,
|
||||
1123,
|
||||
1110,
|
||||
1097,
|
||||
1084,
|
||||
|
||||
Executable
+2050
File diff suppressed because it is too large
Load Diff
+80
-80
@@ -1,81 +1,81 @@
|
||||
0000010000110100
|
||||
0000010001000000
|
||||
0000010001001100
|
||||
0000010001011000
|
||||
0000010001100100
|
||||
0000010001110000
|
||||
0000010001111100
|
||||
0000010010001000
|
||||
0000010010010100
|
||||
0000010010100000
|
||||
0000010010101100
|
||||
0000010010111000
|
||||
0000010011000100
|
||||
0000010011010000
|
||||
0000010011011100
|
||||
0000010011101000
|
||||
0000010011110100
|
||||
0000010100000000
|
||||
0000010100001100
|
||||
0000010100011000
|
||||
0000010100100100
|
||||
0000010100110000
|
||||
0000010100111100
|
||||
0000010101001000
|
||||
0000010101010100
|
||||
0000010101100000
|
||||
0000010101101100
|
||||
0000010101111000
|
||||
0000010110000100
|
||||
0000010110010000
|
||||
0000010110011100
|
||||
0000010110101000
|
||||
0000010110110100
|
||||
0000010111000000
|
||||
0000010111001100
|
||||
0000010111011000
|
||||
0000010111100100
|
||||
0000010111110000
|
||||
0000010111111100
|
||||
0000011000001000
|
||||
0000011000010100
|
||||
0000011000100000
|
||||
0000011000101100
|
||||
0000011000111000
|
||||
0000011001000100
|
||||
0000011001010000
|
||||
0000011001011100
|
||||
0000011001101000
|
||||
0000011001110100
|
||||
0000011010000000
|
||||
0000011010001100
|
||||
0000011010011000
|
||||
0000011010100100
|
||||
0000011010110000
|
||||
0000011010111100
|
||||
0000011011001000
|
||||
0000011011010100
|
||||
0000011011100000
|
||||
0000011011101100
|
||||
0000011011111000
|
||||
0000011100000100
|
||||
0000011100010000
|
||||
0000011100011100
|
||||
0000011100101000
|
||||
0000011100110100
|
||||
0000011101000000
|
||||
0000011101001100
|
||||
0000011101011000
|
||||
0000011101100100
|
||||
0000011101110000
|
||||
0000100001001100
|
||||
0000100000111111
|
||||
0000100000110010
|
||||
0000100000100101
|
||||
0000100000011000
|
||||
0000100000001011
|
||||
0000011111111110
|
||||
0000011111110001
|
||||
0000011111100100
|
||||
0000011111010111
|
||||
0000011111001010
|
||||
0000011110111101
|
||||
0000011110110000
|
||||
0000011110100011
|
||||
0000011110010110
|
||||
0000011110001001
|
||||
0000011101111100
|
||||
0000011110001000
|
||||
0000011110010100
|
||||
0000011110100000
|
||||
0000011110101100
|
||||
0000011110111000
|
||||
0000011111000100
|
||||
0000011111010000
|
||||
0000011111011100
|
||||
0000011111101000
|
||||
0000011111110100
|
||||
0000011101101111
|
||||
0000011101100010
|
||||
0000011101010101
|
||||
0000011101001000
|
||||
0000011100111011
|
||||
0000011100101110
|
||||
0000011100100001
|
||||
0000011100010100
|
||||
0000011100000111
|
||||
0000011011111010
|
||||
0000011011101101
|
||||
0000011011100000
|
||||
0000011011010011
|
||||
0000011011000110
|
||||
0000011010111001
|
||||
0000011010101100
|
||||
0000011010011111
|
||||
0000011010010010
|
||||
0000011010000101
|
||||
0000011001111000
|
||||
0000011001101011
|
||||
0000011001011110
|
||||
0000011001010001
|
||||
0000011001000100
|
||||
0000011000110111
|
||||
0000011000101010
|
||||
0000011000011101
|
||||
0000011000010000
|
||||
0000011000000011
|
||||
0000010111110110
|
||||
0000010111101001
|
||||
0000010111011100
|
||||
0000010111001111
|
||||
0000010111000010
|
||||
0000010110110101
|
||||
0000010110101000
|
||||
0000010110011011
|
||||
0000010110001110
|
||||
0000010110000001
|
||||
0000010101110100
|
||||
0000010101100111
|
||||
0000010101011010
|
||||
0000010101001101
|
||||
0000010101000000
|
||||
0000010100110011
|
||||
0000010100100110
|
||||
0000010100011001
|
||||
0000010100001100
|
||||
0000010011111111
|
||||
0000010011110010
|
||||
0000010011100101
|
||||
0000010011011000
|
||||
0000010011001011
|
||||
0000010010111110
|
||||
0000010010110001
|
||||
0000010010100100
|
||||
0000010010010111
|
||||
0000010010001010
|
||||
0000010001111101
|
||||
0000010001110000
|
||||
0000010001100011
|
||||
0000010001010110
|
||||
0000010001001001
|
||||
0000010000111100
|
||||
|
||||
-67
@@ -1,67 +0,0 @@
|
||||
vlib work
|
||||
vlib activehdl
|
||||
|
||||
vlib activehdl/xil_defaultlib
|
||||
vlib activehdl/xpm
|
||||
vlib activehdl/xbip_utils_v3_0_10
|
||||
vlib activehdl/axi_utils_v2_0_6
|
||||
vlib activehdl/xbip_pipe_v3_0_6
|
||||
vlib activehdl/xbip_bram18k_v3_0_6
|
||||
vlib activehdl/mult_gen_v12_0_15
|
||||
vlib activehdl/xbip_dsp48_wrapper_v3_0_4
|
||||
vlib activehdl/xbip_dsp48_addsub_v3_0_6
|
||||
vlib activehdl/xbip_dsp48_multadd_v3_0_6
|
||||
vlib activehdl/dds_compiler_v6_0_18
|
||||
|
||||
vmap xil_defaultlib activehdl/xil_defaultlib
|
||||
vmap xpm activehdl/xpm
|
||||
vmap xbip_utils_v3_0_10 activehdl/xbip_utils_v3_0_10
|
||||
vmap axi_utils_v2_0_6 activehdl/axi_utils_v2_0_6
|
||||
vmap xbip_pipe_v3_0_6 activehdl/xbip_pipe_v3_0_6
|
||||
vmap xbip_bram18k_v3_0_6 activehdl/xbip_bram18k_v3_0_6
|
||||
vmap mult_gen_v12_0_15 activehdl/mult_gen_v12_0_15
|
||||
vmap xbip_dsp48_wrapper_v3_0_4 activehdl/xbip_dsp48_wrapper_v3_0_4
|
||||
vmap xbip_dsp48_addsub_v3_0_6 activehdl/xbip_dsp48_addsub_v3_0_6
|
||||
vmap xbip_dsp48_multadd_v3_0_6 activehdl/xbip_dsp48_multadd_v3_0_6
|
||||
vmap dds_compiler_v6_0_18 activehdl/dds_compiler_v6_0_18
|
||||
|
||||
vlog -work xil_defaultlib -sv2k12 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
|
||||
vcom -work xpm -93 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
|
||||
vcom -work xbip_utils_v3_0_10 -93 \
|
||||
"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
|
||||
|
||||
vcom -work axi_utils_v2_0_6 -93 \
|
||||
"../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \
|
||||
|
||||
vcom -work xbip_pipe_v3_0_6 -93 \
|
||||
"../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \
|
||||
|
||||
vcom -work xbip_bram18k_v3_0_6 -93 \
|
||||
"../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \
|
||||
|
||||
vcom -work mult_gen_v12_0_15 -93 \
|
||||
"../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \
|
||||
|
||||
vcom -work xbip_dsp48_wrapper_v3_0_4 -93 \
|
||||
"../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd" \
|
||||
|
||||
vcom -work xbip_dsp48_addsub_v3_0_6 -93 \
|
||||
"../../../ipstatic/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd" \
|
||||
|
||||
vcom -work xbip_dsp48_multadd_v3_0_6 -93 \
|
||||
"../../../ipstatic/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd" \
|
||||
|
||||
vcom -work dds_compiler_v6_0_18 -93 \
|
||||
"../../../ipstatic/hdl/dds_compiler_v6_0_vh_rfs.vhd" \
|
||||
|
||||
vcom -work xil_defaultlib -93 \
|
||||
"../../../ip/dds_32b_8b_comp/sim/dds_32b_8b_comp.vhd" \
|
||||
|
||||
vlog -work xil_defaultlib \
|
||||
"glbl.v"
|
||||
|
||||
-14
@@ -1,14 +0,0 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
|
||||
axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
|
||||
xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,
|
||||
xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd,
|
||||
mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd,
|
||||
xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_wrapper_v3_0_4,../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,
|
||||
xbip_dsp48_addsub_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_addsub_v3_0_6,../../../ipstatic/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd,
|
||||
xbip_dsp48_multadd_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_multadd_v3_0_6,../../../ipstatic/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd,
|
||||
dds_compiler_v6_0_vh_rfs.vhd,vhdl,dds_compiler_v6_0_18,../../../ipstatic/hdl/dds_compiler_v6_0_vh_rfs.vhd,
|
||||
dds_32b_8b_comp.vhd,vhdl,xil_defaultlib,../../../ip/dds_32b_8b_comp/sim/dds_32b_8b_comp.vhd,
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
-17
@@ -1,17 +0,0 @@
|
||||
onbreak {quit -force}
|
||||
onerror {quit -force}
|
||||
|
||||
asim -t 1ps +access +r +m+dds_32b_8b_comp -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L dds_compiler_v6_0_18 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.dds_32b_8b_comp xil_defaultlib.glbl
|
||||
|
||||
do {wave.do}
|
||||
|
||||
view wave
|
||||
view structure
|
||||
|
||||
do {dds_32b_8b_comp.udo}
|
||||
|
||||
run -all
|
||||
|
||||
endsim
|
||||
|
||||
quit -force
|
||||
-14
@@ -1,14 +0,0 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
|
||||
axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
|
||||
xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,
|
||||
xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd,
|
||||
mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd,
|
||||
xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_wrapper_v3_0_4,../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,
|
||||
xbip_dsp48_addsub_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_addsub_v3_0_6,../../../ipstatic/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd,
|
||||
xbip_dsp48_multadd_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_multadd_v3_0_6,../../../ipstatic/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd,
|
||||
dds_compiler_v6_0_vh_rfs.vhd,vhdl,dds_compiler_v6_0_18,../../../ipstatic/hdl/dds_compiler_v6_0_vh_rfs.vhd,
|
||||
dds_32b_8b_comp.vhd,vhdl,xil_defaultlib,../../../ip/dds_32b_8b_comp/sim/dds_32b_8b_comp.vhd,
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
-41
@@ -1,41 +0,0 @@
|
||||
-makelib ies_lib/xil_defaultlib -sv \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
-endlib
|
||||
-makelib ies_lib/xpm \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
-endlib
|
||||
-makelib ies_lib/xbip_utils_v3_0_10 \
|
||||
"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
|
||||
-endlib
|
||||
-makelib ies_lib/axi_utils_v2_0_6 \
|
||||
"../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \
|
||||
-endlib
|
||||
-makelib ies_lib/xbip_pipe_v3_0_6 \
|
||||
"../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \
|
||||
-endlib
|
||||
-makelib ies_lib/xbip_bram18k_v3_0_6 \
|
||||
"../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \
|
||||
-endlib
|
||||
-makelib ies_lib/mult_gen_v12_0_15 \
|
||||
"../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \
|
||||
-endlib
|
||||
-makelib ies_lib/xbip_dsp48_wrapper_v3_0_4 \
|
||||
"../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd" \
|
||||
-endlib
|
||||
-makelib ies_lib/xbip_dsp48_addsub_v3_0_6 \
|
||||
"../../../ipstatic/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd" \
|
||||
-endlib
|
||||
-makelib ies_lib/xbip_dsp48_multadd_v3_0_6 \
|
||||
"../../../ipstatic/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd" \
|
||||
-endlib
|
||||
-makelib ies_lib/dds_compiler_v6_0_18 \
|
||||
"../../../ipstatic/hdl/dds_compiler_v6_0_vh_rfs.vhd" \
|
||||
-endlib
|
||||
-makelib ies_lib/xil_defaultlib \
|
||||
"../../../ip/dds_32b_8b_comp/sim/dds_32b_8b_comp.vhd" \
|
||||
-endlib
|
||||
-makelib ies_lib/xil_defaultlib \
|
||||
glbl.v
|
||||
-endlib
|
||||
|
||||
-2
@@ -1,2 +0,0 @@
|
||||
dds_32b_8b_comp.vhd,vhdl,xil_defaultlib,../../../ip/dds_32b_8b_comp/sim/dds_32b_8b_comp.vhd,
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
-16
@@ -1,16 +0,0 @@
|
||||
onbreak {quit -f}
|
||||
onerror {quit -f}
|
||||
|
||||
vsim -voptargs="+acc" -t 1ps -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L dds_compiler_v6_0_18 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.dds_32b_8b_comp xil_defaultlib.glbl
|
||||
|
||||
do {wave.do}
|
||||
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
|
||||
do {dds_32b_8b_comp.udo}
|
||||
|
||||
run -all
|
||||
|
||||
quit -force
|
||||
-67
@@ -1,67 +0,0 @@
|
||||
vlib questa_lib/work
|
||||
vlib questa_lib/msim
|
||||
|
||||
vlib questa_lib/msim/xil_defaultlib
|
||||
vlib questa_lib/msim/xpm
|
||||
vlib questa_lib/msim/xbip_utils_v3_0_10
|
||||
vlib questa_lib/msim/axi_utils_v2_0_6
|
||||
vlib questa_lib/msim/xbip_pipe_v3_0_6
|
||||
vlib questa_lib/msim/xbip_bram18k_v3_0_6
|
||||
vlib questa_lib/msim/mult_gen_v12_0_15
|
||||
vlib questa_lib/msim/xbip_dsp48_wrapper_v3_0_4
|
||||
vlib questa_lib/msim/xbip_dsp48_addsub_v3_0_6
|
||||
vlib questa_lib/msim/xbip_dsp48_multadd_v3_0_6
|
||||
vlib questa_lib/msim/dds_compiler_v6_0_18
|
||||
|
||||
vmap xil_defaultlib questa_lib/msim/xil_defaultlib
|
||||
vmap xpm questa_lib/msim/xpm
|
||||
vmap xbip_utils_v3_0_10 questa_lib/msim/xbip_utils_v3_0_10
|
||||
vmap axi_utils_v2_0_6 questa_lib/msim/axi_utils_v2_0_6
|
||||
vmap xbip_pipe_v3_0_6 questa_lib/msim/xbip_pipe_v3_0_6
|
||||
vmap xbip_bram18k_v3_0_6 questa_lib/msim/xbip_bram18k_v3_0_6
|
||||
vmap mult_gen_v12_0_15 questa_lib/msim/mult_gen_v12_0_15
|
||||
vmap xbip_dsp48_wrapper_v3_0_4 questa_lib/msim/xbip_dsp48_wrapper_v3_0_4
|
||||
vmap xbip_dsp48_addsub_v3_0_6 questa_lib/msim/xbip_dsp48_addsub_v3_0_6
|
||||
vmap xbip_dsp48_multadd_v3_0_6 questa_lib/msim/xbip_dsp48_multadd_v3_0_6
|
||||
vmap dds_compiler_v6_0_18 questa_lib/msim/dds_compiler_v6_0_18
|
||||
|
||||
vlog -work xil_defaultlib -64 -sv \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
|
||||
vcom -work xpm -64 -93 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
|
||||
vcom -work xbip_utils_v3_0_10 -64 -93 \
|
||||
"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
|
||||
|
||||
vcom -work axi_utils_v2_0_6 -64 -93 \
|
||||
"../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \
|
||||
|
||||
vcom -work xbip_pipe_v3_0_6 -64 -93 \
|
||||
"../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \
|
||||
|
||||
vcom -work xbip_bram18k_v3_0_6 -64 -93 \
|
||||
"../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \
|
||||
|
||||
vcom -work mult_gen_v12_0_15 -64 -93 \
|
||||
"../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \
|
||||
|
||||
vcom -work xbip_dsp48_wrapper_v3_0_4 -64 -93 \
|
||||
"../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd" \
|
||||
|
||||
vcom -work xbip_dsp48_addsub_v3_0_6 -64 -93 \
|
||||
"../../../ipstatic/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd" \
|
||||
|
||||
vcom -work xbip_dsp48_multadd_v3_0_6 -64 -93 \
|
||||
"../../../ipstatic/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd" \
|
||||
|
||||
vcom -work dds_compiler_v6_0_18 -64 -93 \
|
||||
"../../../ipstatic/hdl/dds_compiler_v6_0_vh_rfs.vhd" \
|
||||
|
||||
vcom -work xil_defaultlib -64 -93 \
|
||||
"../../../ip/dds_32b_8b_comp/sim/dds_32b_8b_comp.vhd" \
|
||||
|
||||
vlog -work xil_defaultlib \
|
||||
"glbl.v"
|
||||
|
||||
-1
@@ -1 +0,0 @@
|
||||
vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L dds_compiler_v6_0_18 -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.dds_32b_8b_comp xil_defaultlib.glbl -o dds_32b_8b_comp_opt
|
||||
-14
@@ -1,14 +0,0 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
|
||||
axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
|
||||
xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,
|
||||
xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd,
|
||||
mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd,
|
||||
xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_wrapper_v3_0_4,../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,
|
||||
xbip_dsp48_addsub_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_addsub_v3_0_6,../../../ipstatic/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd,
|
||||
xbip_dsp48_multadd_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_multadd_v3_0_6,../../../ipstatic/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd,
|
||||
dds_compiler_v6_0_vh_rfs.vhd,vhdl,dds_compiler_v6_0_18,../../../ipstatic/hdl/dds_compiler_v6_0_vh_rfs.vhd,
|
||||
dds_32b_8b_comp.vhd,vhdl,xil_defaultlib,../../../ip/dds_32b_8b_comp/sim/dds_32b_8b_comp.vhd,
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
-67
@@ -1,67 +0,0 @@
|
||||
vlib work
|
||||
vlib riviera
|
||||
|
||||
vlib riviera/xil_defaultlib
|
||||
vlib riviera/xpm
|
||||
vlib riviera/xbip_utils_v3_0_10
|
||||
vlib riviera/axi_utils_v2_0_6
|
||||
vlib riviera/xbip_pipe_v3_0_6
|
||||
vlib riviera/xbip_bram18k_v3_0_6
|
||||
vlib riviera/mult_gen_v12_0_15
|
||||
vlib riviera/xbip_dsp48_wrapper_v3_0_4
|
||||
vlib riviera/xbip_dsp48_addsub_v3_0_6
|
||||
vlib riviera/xbip_dsp48_multadd_v3_0_6
|
||||
vlib riviera/dds_compiler_v6_0_18
|
||||
|
||||
vmap xil_defaultlib riviera/xil_defaultlib
|
||||
vmap xpm riviera/xpm
|
||||
vmap xbip_utils_v3_0_10 riviera/xbip_utils_v3_0_10
|
||||
vmap axi_utils_v2_0_6 riviera/axi_utils_v2_0_6
|
||||
vmap xbip_pipe_v3_0_6 riviera/xbip_pipe_v3_0_6
|
||||
vmap xbip_bram18k_v3_0_6 riviera/xbip_bram18k_v3_0_6
|
||||
vmap mult_gen_v12_0_15 riviera/mult_gen_v12_0_15
|
||||
vmap xbip_dsp48_wrapper_v3_0_4 riviera/xbip_dsp48_wrapper_v3_0_4
|
||||
vmap xbip_dsp48_addsub_v3_0_6 riviera/xbip_dsp48_addsub_v3_0_6
|
||||
vmap xbip_dsp48_multadd_v3_0_6 riviera/xbip_dsp48_multadd_v3_0_6
|
||||
vmap dds_compiler_v6_0_18 riviera/dds_compiler_v6_0_18
|
||||
|
||||
vlog -work xil_defaultlib -sv2k12 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
|
||||
vcom -work xpm -93 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
|
||||
vcom -work xbip_utils_v3_0_10 -93 \
|
||||
"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
|
||||
|
||||
vcom -work axi_utils_v2_0_6 -93 \
|
||||
"../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \
|
||||
|
||||
vcom -work xbip_pipe_v3_0_6 -93 \
|
||||
"../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \
|
||||
|
||||
vcom -work xbip_bram18k_v3_0_6 -93 \
|
||||
"../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \
|
||||
|
||||
vcom -work mult_gen_v12_0_15 -93 \
|
||||
"../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \
|
||||
|
||||
vcom -work xbip_dsp48_wrapper_v3_0_4 -93 \
|
||||
"../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd" \
|
||||
|
||||
vcom -work xbip_dsp48_addsub_v3_0_6 -93 \
|
||||
"../../../ipstatic/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd" \
|
||||
|
||||
vcom -work xbip_dsp48_multadd_v3_0_6 -93 \
|
||||
"../../../ipstatic/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd" \
|
||||
|
||||
vcom -work dds_compiler_v6_0_18 -93 \
|
||||
"../../../ipstatic/hdl/dds_compiler_v6_0_vh_rfs.vhd" \
|
||||
|
||||
vcom -work xil_defaultlib -93 \
|
||||
"../../../ip/dds_32b_8b_comp/sim/dds_32b_8b_comp.vhd" \
|
||||
|
||||
vlog -work xil_defaultlib \
|
||||
"glbl.v"
|
||||
|
||||
-14
@@ -1,14 +0,0 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
|
||||
axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
|
||||
xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,
|
||||
xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd,
|
||||
mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd,
|
||||
xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_wrapper_v3_0_4,../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,
|
||||
xbip_dsp48_addsub_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_addsub_v3_0_6,../../../ipstatic/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd,
|
||||
xbip_dsp48_multadd_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_multadd_v3_0_6,../../../ipstatic/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd,
|
||||
dds_compiler_v6_0_vh_rfs.vhd,vhdl,dds_compiler_v6_0_18,../../../ipstatic/hdl/dds_compiler_v6_0_vh_rfs.vhd,
|
||||
dds_32b_8b_comp.vhd,vhdl,xil_defaultlib,../../../ip/dds_32b_8b_comp/sim/dds_32b_8b_comp.vhd,
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
-17
@@ -1,17 +0,0 @@
|
||||
onbreak {quit -force}
|
||||
onerror {quit -force}
|
||||
|
||||
asim -t 1ps +access +r +m+dds_32b_8b_comp -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L dds_compiler_v6_0_18 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.dds_32b_8b_comp xil_defaultlib.glbl
|
||||
|
||||
do {wave.do}
|
||||
|
||||
view wave
|
||||
view structure
|
||||
|
||||
do {dds_32b_8b_comp.udo}
|
||||
|
||||
run -all
|
||||
|
||||
endsim
|
||||
|
||||
quit -force
|
||||
-49
@@ -1,49 +0,0 @@
|
||||
################################################################################
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Mon May 08 00:28:50 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
1. How to run the generated simulation script:-
|
||||
|
||||
From the shell prompt in the current directory, issue the following command:-
|
||||
|
||||
./dds_32b_8b_comp.sh
|
||||
|
||||
This command will launch the 'compile', 'elaborate' and 'simulate' functions
|
||||
implemented in the script file for the 3-step flow. These functions are called
|
||||
from the main 'run' function in the script file.
|
||||
|
||||
The 'run' function first executes the 'setup' function, the purpose of which is to
|
||||
create simulator specific setup files, create design library mappings and library
|
||||
directories and copy 'glbl.v' from the Vivado software install location into the
|
||||
current directory.
|
||||
|
||||
The 'setup' function is also used for removing the simulator generated data in
|
||||
order to reset the current directory to the original state when export_simulation
|
||||
was launched from Vivado. This generated data can be removed by specifying the
|
||||
'-reset_run' switch to the './dds_32b_8b_comp.sh' script.
|
||||
|
||||
./dds_32b_8b_comp.sh -reset_run
|
||||
|
||||
To keep the generated data from the previous run but regenerate the setup files and
|
||||
library directories, use the '-noclean_files' switch.
|
||||
|
||||
./dds_32b_8b_comp.sh -noclean_files
|
||||
|
||||
For more information on the script, please type './dds_32b_8b_comp.sh -help'.
|
||||
|
||||
2. Additional design information files:-
|
||||
|
||||
export_simulation generates following additional file that can be used for fetching
|
||||
the design files information or for integrating with external custom scripts.
|
||||
|
||||
Name : file_info.txt
|
||||
Purpose: This file contains detail design file information based on the compile order
|
||||
when export_simulation was executed from Vivado. The file contains information
|
||||
about the file type, name, whether it is part of the IP, associated library
|
||||
and the file path information.
|
||||
-2
@@ -1,2 +0,0 @@
|
||||
dds_32b_8b_comp.vhd,vhdl,xil_defaultlib,../../../ip/dds_32b_8b_comp/sim/dds_32b_8b_comp.vhd,
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
-14
@@ -1,14 +0,0 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
|
||||
axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
|
||||
xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,
|
||||
xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd,
|
||||
mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd,
|
||||
xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_wrapper_v3_0_4,../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,
|
||||
xbip_dsp48_addsub_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_addsub_v3_0_6,../../../ipstatic/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd,
|
||||
xbip_dsp48_multadd_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_multadd_v3_0_6,../../../ipstatic/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd,
|
||||
dds_compiler_v6_0_vh_rfs.vhd,vhdl,dds_compiler_v6_0_18,../../../ipstatic/hdl/dds_compiler_v6_0_vh_rfs.vhd,
|
||||
dds_32b_8b_comp.vhd,vhdl,xil_defaultlib,../../../ip/dds_32b_8b_comp/sim/dds_32b_8b_comp.vhd,
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
-41
@@ -1,41 +0,0 @@
|
||||
-makelib xcelium_lib/xil_defaultlib -sv \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
-endlib
|
||||
-makelib xcelium_lib/xpm \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
-endlib
|
||||
-makelib xcelium_lib/xbip_utils_v3_0_10 \
|
||||
"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
|
||||
-endlib
|
||||
-makelib xcelium_lib/axi_utils_v2_0_6 \
|
||||
"../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \
|
||||
-endlib
|
||||
-makelib xcelium_lib/xbip_pipe_v3_0_6 \
|
||||
"../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \
|
||||
-endlib
|
||||
-makelib xcelium_lib/xbip_bram18k_v3_0_6 \
|
||||
"../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \
|
||||
-endlib
|
||||
-makelib xcelium_lib/mult_gen_v12_0_15 \
|
||||
"../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \
|
||||
-endlib
|
||||
-makelib xcelium_lib/xbip_dsp48_wrapper_v3_0_4 \
|
||||
"../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd" \
|
||||
-endlib
|
||||
-makelib xcelium_lib/xbip_dsp48_addsub_v3_0_6 \
|
||||
"../../../ipstatic/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd" \
|
||||
-endlib
|
||||
-makelib xcelium_lib/xbip_dsp48_multadd_v3_0_6 \
|
||||
"../../../ipstatic/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd" \
|
||||
-endlib
|
||||
-makelib xcelium_lib/dds_compiler_v6_0_18 \
|
||||
"../../../ipstatic/hdl/dds_compiler_v6_0_vh_rfs.vhd" \
|
||||
-endlib
|
||||
-makelib xcelium_lib/xil_defaultlib \
|
||||
"../../../ip/dds_32b_8b_comp/sim/dds_32b_8b_comp.vhd" \
|
||||
-endlib
|
||||
-makelib xcelium_lib/xil_defaultlib \
|
||||
glbl.v
|
||||
-endlib
|
||||
|
||||
-49
@@ -1,49 +0,0 @@
|
||||
################################################################################
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Mon May 08 00:28:50 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
1. How to run the generated simulation script:-
|
||||
|
||||
From the shell prompt in the current directory, issue the following command:-
|
||||
|
||||
./dds_32b_8b_comp.sh
|
||||
|
||||
This command will launch the 'compile', 'elaborate' and 'simulate' functions
|
||||
implemented in the script file for the 3-step flow. These functions are called
|
||||
from the main 'run' function in the script file.
|
||||
|
||||
The 'run' function first executes the 'setup' function, the purpose of which is to
|
||||
create simulator specific setup files, create design library mappings and library
|
||||
directories and copy 'glbl.v' from the Vivado software install location into the
|
||||
current directory.
|
||||
|
||||
The 'setup' function is also used for removing the simulator generated data in
|
||||
order to reset the current directory to the original state when export_simulation
|
||||
was launched from Vivado. This generated data can be removed by specifying the
|
||||
'-reset_run' switch to the './dds_32b_8b_comp.sh' script.
|
||||
|
||||
./dds_32b_8b_comp.sh -reset_run
|
||||
|
||||
To keep the generated data from the previous run but regenerate the setup files and
|
||||
library directories, use the '-noclean_files' switch.
|
||||
|
||||
./dds_32b_8b_comp.sh -noclean_files
|
||||
|
||||
For more information on the script, please type './dds_32b_8b_comp.sh -help'.
|
||||
|
||||
2. Additional design information files:-
|
||||
|
||||
export_simulation generates following additional file that can be used for fetching
|
||||
the design files information or for integrating with external custom scripts.
|
||||
|
||||
Name : file_info.txt
|
||||
Purpose: This file contains detail design file information based on the compile order
|
||||
when export_simulation was executed from Vivado. The file contains information
|
||||
about the file type, name, whether it is part of the IP, associated library
|
||||
and the file path information.
|
||||
-2
@@ -1,2 +0,0 @@
|
||||
dds_32b_8b_comp.vhd,vhdl,xil_defaultlib,../../../ip/dds_32b_8b_comp/sim/dds_32b_8b_comp.vhd,
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
-4
@@ -1,4 +0,0 @@
|
||||
vhdl xil_defaultlib \
|
||||
"../../../ip/dds_32b_8b_comp/sim/dds_32b_8b_comp.vhd" \
|
||||
|
||||
nosort
|
||||
+6
-6
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Mon May 08 00:28:50 CST 2023
|
||||
# Generated by export_simulation on Fri May 12 16:07:36 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
@@ -12,7 +12,7 @@
|
||||
|
||||
From the shell prompt in the current directory, issue the following command:-
|
||||
|
||||
./dds_32b_8b_comp.sh
|
||||
./fifo_rx_data.sh
|
||||
|
||||
This command will launch the 'compile', 'elaborate' and 'simulate' functions
|
||||
implemented in the script file for the 3-step flow. These functions are called
|
||||
@@ -26,16 +26,16 @@ current directory.
|
||||
The 'setup' function is also used for removing the simulator generated data in
|
||||
order to reset the current directory to the original state when export_simulation
|
||||
was launched from Vivado. This generated data can be removed by specifying the
|
||||
'-reset_run' switch to the './dds_32b_8b_comp.sh' script.
|
||||
'-reset_run' switch to the './fifo_rx_data.sh' script.
|
||||
|
||||
./dds_32b_8b_comp.sh -reset_run
|
||||
./fifo_rx_data.sh -reset_run
|
||||
|
||||
To keep the generated data from the previous run but regenerate the setup files and
|
||||
library directories, use the '-noclean_files' switch.
|
||||
|
||||
./dds_32b_8b_comp.sh -noclean_files
|
||||
./fifo_rx_data.sh -noclean_files
|
||||
|
||||
For more information on the script, please type './dds_32b_8b_comp.sh -help'.
|
||||
For more information on the script, please type './fifo_rx_data.sh -help'.
|
||||
|
||||
2. Additional design information files:-
|
||||
|
||||
+33
@@ -0,0 +1,33 @@
|
||||
vlib work
|
||||
vlib activehdl
|
||||
|
||||
vlib activehdl/xil_defaultlib
|
||||
vlib activehdl/xpm
|
||||
vlib activehdl/fifo_generator_v13_2_4
|
||||
|
||||
vmap xil_defaultlib activehdl/xil_defaultlib
|
||||
vmap xpm activehdl/xpm
|
||||
vmap fifo_generator_v13_2_4 activehdl/fifo_generator_v13_2_4
|
||||
|
||||
vlog -work xil_defaultlib -sv2k12 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
|
||||
vcom -work xpm -93 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
|
||||
vlog -work fifo_generator_v13_2_4 -v2k5 \
|
||||
"../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \
|
||||
|
||||
vcom -work fifo_generator_v13_2_4 -93 \
|
||||
"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \
|
||||
|
||||
vlog -work fifo_generator_v13_2_4 -v2k5 \
|
||||
"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \
|
||||
|
||||
vlog -work xil_defaultlib -v2k5 \
|
||||
"../../../ip/fifo_rx_data/sim/fifo_rx_data.v" \
|
||||
|
||||
vlog -work xil_defaultlib \
|
||||
"glbl.v"
|
||||
|
||||
+152
@@ -0,0 +1,152 @@
|
||||
#!/bin/bash -f
|
||||
#*********************************************************************************************************
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# Filename : fifo_rx_data.sh
|
||||
# Simulator : Aldec Active-HDL Simulator
|
||||
# Description : Simulation script for compiling, elaborating and verifying the project source files.
|
||||
# The script will automatically create the design libraries sub-directories in the run
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Fri May 12 16:07:36 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
# usage: fifo_rx_data.sh [-help]
|
||||
# usage: fifo_rx_data.sh [-lib_map_path]
|
||||
# usage: fifo_rx_data.sh [-noclean_files]
|
||||
# usage: fifo_rx_data.sh [-reset_run]
|
||||
#
|
||||
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
|
||||
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
|
||||
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
|
||||
# that points to these libraries and rerun export_simulation. For more information about this switch please
|
||||
# type 'export_simulation -help' in the Tcl shell.
|
||||
#
|
||||
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
|
||||
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
|
||||
# executing this script. Please type 'fifo_rx_data.sh -help' for more information.
|
||||
#
|
||||
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
|
||||
#
|
||||
#*********************************************************************************************************
|
||||
|
||||
|
||||
# Script info
|
||||
echo -e "fifo_rx_data.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
|
||||
|
||||
# Main steps
|
||||
run()
|
||||
{
|
||||
check_args $# $1
|
||||
setup $1 $2
|
||||
compile
|
||||
simulate
|
||||
}
|
||||
|
||||
# RUN_STEP: <compile>
|
||||
compile()
|
||||
{
|
||||
# Compile design files
|
||||
source compile.do 2>&1 | tee -a compile.log
|
||||
|
||||
}
|
||||
|
||||
# RUN_STEP: <simulate>
|
||||
simulate()
|
||||
{
|
||||
runvsimsa -l simulate.log -do "do {simulate.do}"
|
||||
}
|
||||
|
||||
# STEP: setup
|
||||
setup()
|
||||
{
|
||||
case $1 in
|
||||
"-lib_map_path" )
|
||||
if [[ ($2 == "") ]]; then
|
||||
echo -e "ERROR: Simulation library directory path not specified (type \"./fifo_rx_data.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
map_setup_file $2
|
||||
;;
|
||||
"-reset_run" )
|
||||
reset_run
|
||||
echo -e "INFO: Simulation run files deleted.\n"
|
||||
exit 0
|
||||
;;
|
||||
"-noclean_files" )
|
||||
# do not remove previous data
|
||||
;;
|
||||
* )
|
||||
map_setup_file $2
|
||||
esac
|
||||
|
||||
# Add any setup/initialization commands here:-
|
||||
|
||||
# <user specific commands>
|
||||
|
||||
}
|
||||
|
||||
# Map library.cfg file
|
||||
map_setup_file()
|
||||
{
|
||||
file="library.cfg"
|
||||
lib_map_path=""
|
||||
if [[ ($1 != "") ]]; then
|
||||
lib_map_path="$1"
|
||||
fi
|
||||
if [[ ($lib_map_path != "") ]]; then
|
||||
src_file="$lib_map_path/$file"
|
||||
if [[ -e $src_file ]]; then
|
||||
vmap -link $lib_map_path
|
||||
fi
|
||||
fi
|
||||
}
|
||||
|
||||
# Delete generated data from the previous run
|
||||
reset_run()
|
||||
{
|
||||
files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl)
|
||||
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
|
||||
file="${files_to_remove[i]}"
|
||||
if [[ -e $file ]]; then
|
||||
rm -rf $file
|
||||
fi
|
||||
done
|
||||
}
|
||||
|
||||
# Check command line arguments
|
||||
check_args()
|
||||
{
|
||||
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
|
||||
echo -e "ERROR: Unknown option specified '$2' (type \"./fifo_rx_data.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
if [[ ($2 == "-help" || $2 == "-h") ]]; then
|
||||
usage
|
||||
fi
|
||||
}
|
||||
|
||||
# Script usage
|
||||
usage()
|
||||
{
|
||||
msg="Usage: fifo_rx_data.sh [-help]\n\
|
||||
Usage: fifo_rx_data.sh [-lib_map_path]\n\
|
||||
Usage: fifo_rx_data.sh [-reset_run]\n\
|
||||
Usage: fifo_rx_data.sh [-noclean_files]\n\n\
|
||||
[-help] -- Print help information for this script\n\n\
|
||||
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
|
||||
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
|
||||
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
|
||||
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
|
||||
-noclean_files switch.\n\n\
|
||||
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
|
||||
echo -e $msg
|
||||
exit 1
|
||||
}
|
||||
|
||||
# Launch script
|
||||
run $1 $2
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user