update phase comp with cmpy; add var cal module

common/trunc_32bit_to_12bit.v

@@ -0,0 +1,515 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 2023/03/01 10:44:50
+// Design Name:
+// Module Name: trunc_32bit_to_12bit
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module trunc_32bit_to_12bit(
+    input clk,
+    input rst,
+    input [31:0] trunc_32bit_in,
+    input [4:0] vio_trunc,
+
+    output reg [11:0] trunc_12bit_out = 12'd0,
+    output reg trunc_overflow = 1'd0
+    );
+
+    always @ (posedge clk) begin
+        if(rst) begin
+            trunc_12bit_out[11:0] <= 12'd0;
+            trunc_overflow <= 1'd0;
+        end else begin
+            case(vio_trunc[4:0])
+                5'd0:begin
+                    if(trunc_32bit_in[31:31] == 1'd1 || trunc_32bit_in[31:31] == 1'd0) begin
+                        if(trunc_32bit_in[31:31] == 1'd0 &&trunc_32bit_in[19] == 1'd1 && trunc_32bit_in[31:20] != 12'd2047) begin
+                            trunc_12bit_out[11:0] <= trunc_32bit_in[31:20] + 12'd1;
+                        end
+                        else begin
+                            if(trunc_32bit_in[31:31] == 1'd1 && trunc_32bit_in[19:0] > 20'd524288) begin
+                                trunc_12bit_out[11:0] <= trunc_32bit_in[31:20] + 12'd1;
+                            end
+                            else begin
+                                trunc_12bit_out[11:0] <= trunc_32bit_in[31:20];
+                            end
+                        end
+                        trunc_overflow <= 1'd0;
+                    end else begin
+                        if(trunc_32bit_in[31] == 1'd1) begin
+                            trunc_12bit_out[11:0] <= -12'd2048;
+                        end else begin
+                            trunc_12bit_out[11:0] <= 12'd2047;
+                        end
+                        trunc_overflow <= 1'd1;
+                    end
+                end
+                5'd1:begin
+                    if(trunc_32bit_in[31:30] == 2'd3 || trunc_32bit_in[31:30] == 2'd0) begin
+                        if(trunc_32bit_in[31:30] == 2'd0 &&trunc_32bit_in[18] == 1'd1 && trunc_32bit_in[30:19] != 12'd2047) begin
+                            trunc_12bit_out[11:0] <= trunc_32bit_in[30:19] + 12'd1;
+                        end
+                        else begin
+                            if(trunc_32bit_in[31:30] == 2'd3 && trunc_32bit_in[18:0] > 19'd262144) begin
+                                trunc_12bit_out[11:0] <= trunc_32bit_in[30:19] + 12'd1;
+                            end
+                            else begin
+                                trunc_12bit_out[11:0] <= trunc_32bit_in[30:19];
+                            end
+                        end
+                        trunc_overflow <= 1'd0;
+                    end else begin
+                        if(trunc_32bit_in[31] == 1'd1) begin
+                            trunc_12bit_out[11:0] <= -12'd2048;
+                        end else begin
+                            trunc_12bit_out[11:0] <= 12'd2047;
+                        end
+                        trunc_overflow <= 1'd1;
+                    end
+                end
+                5'd2:begin
+                    if(trunc_32bit_in[31:29] == 3'd7 || trunc_32bit_in[31:29] == 3'd0) begin
+                        if(trunc_32bit_in[31:29] == 3'd0 &&trunc_32bit_in[17] == 1'd1 && trunc_32bit_in[29:18] != 12'd2047) begin
+                            trunc_12bit_out[11:0] <= trunc_32bit_in[29:18] + 12'd1;
+                        end
+                        else begin
+                            if(trunc_32bit_in[31:29] == 3'd7 && trunc_32bit_in[17:0] > 18'd131072) begin
+                                trunc_12bit_out[11:0] <= trunc_32bit_in[29:18] + 12'd1;
+                            end
+                            else begin
+                                trunc_12bit_out[11:0] <= trunc_32bit_in[29:18];
+                            end
+                        end
+                        trunc_overflow <= 1'd0;
+                    end else begin
+                        if(trunc_32bit_in[31] == 1'd1) begin
+                            trunc_12bit_out[11:0] <= -12'd2048;
+                        end else begin
+                            trunc_12bit_out[11:0] <= 12'd2047;
+                        end
+                        trunc_overflow <= 1'd1;
+                    end
+                end
+                5'd3:begin
+                    if(trunc_32bit_in[31:28] == 4'd15 || trunc_32bit_in[31:28] == 4'd0) begin
+                        if(trunc_32bit_in[31:28] == 4'd0 &&trunc_32bit_in[16] == 1'd1 && trunc_32bit_in[28:17] != 12'd2047) begin
+                            trunc_12bit_out[11:0] <= trunc_32bit_in[28:17] + 12'd1;
+                        end
+                        else begin
+                            if(trunc_32bit_in[31:28] == 4'd15 && trunc_32bit_in[16:0] > 17'd65536) begin
+                                trunc_12bit_out[11:0] <= trunc_32bit_in[28:17] + 12'd1;
+                            end
+                            else begin
+                                trunc_12bit_out[11:0] <= trunc_32bit_in[28:17];
+                            end
+                        end
+                        trunc_overflow <= 1'd0;
+                    end else begin
+                        if(trunc_32bit_in[31] == 1'd1) begin
+                            trunc_12bit_out[11:0] <= -12'd2048;
+                        end else begin
+                            trunc_12bit_out[11:0] <= 12'd2047;
+                        end
+                        trunc_overflow <= 1'd1;
+                    end
+                end
+                5'd4:begin
+                    if(trunc_32bit_in[31:27] == 5'd31 || trunc_32bit_in[31:27] == 5'd0) begin
+                        if(trunc_32bit_in[31:27] == 5'd0 &&trunc_32bit_in[15] == 1'd1 && trunc_32bit_in[27:16] != 12'd2047) begin
+                            trunc_12bit_out[11:0] <= trunc_32bit_in[27:16] + 12'd1;
+                        end
+                        else begin
+                            if(trunc_32bit_in[31:27] == 5'd31 && trunc_32bit_in[15:0] > 16'd32768) begin
+                                trunc_12bit_out[11:0] <= trunc_32bit_in[27:16] + 12'd1;
+                            end
+                            else begin
+                                trunc_12bit_out[11:0] <= trunc_32bit_in[27:16];
+                            end
+                        end
+                        trunc_overflow <= 1'd0;
+                    end else begin
+                        if(trunc_32bit_in[31] == 1'd1) begin
+                            trunc_12bit_out[11:0] <= -12'd2048;
+                        end else begin
+                            trunc_12bit_out[11:0] <= 12'd2047;
+                        end
+                        trunc_overflow <= 1'd1;
+                    end
+                end
+                5'd5:begin
+                    if(trunc_32bit_in[31:26] == 6'd63 || trunc_32bit_in[31:26] == 6'd0) begin
+                        if(trunc_32bit_in[31:26] == 6'd0 &&trunc_32bit_in[14] == 1'd1 && trunc_32bit_in[26:15] != 12'd2047) begin
+                            trunc_12bit_out[11:0] <= trunc_32bit_in[26:15] + 12'd1;
+                        end
+                        else begin
+                            if(trunc_32bit_in[31:26] == 6'd63 && trunc_32bit_in[14:0] > 15'd16384) begin
+                                trunc_12bit_out[11:0] <= trunc_32bit_in[26:15] + 12'd1;
+                            end
+                            else begin
+                                trunc_12bit_out[11:0] <= trunc_32bit_in[26:15];
+                            end
+                        end
+                        trunc_overflow <= 1'd0;
+                    end else begin
+                        if(trunc_32bit_in[31] == 1'd1) begin
+                            trunc_12bit_out[11:0] <= -12'd2048;
+                        end else begin
+                            trunc_12bit_out[11:0] <= 12'd2047;
+                        end
+                        trunc_overflow <= 1'd1;
+                    end
+                end
+                5'd6:begin
+                    if(trunc_32bit_in[31:25] == 7'd127 || trunc_32bit_in[31:25] == 7'd0) begin
+                        if(trunc_32bit_in[31:25] == 7'd0 &&trunc_32bit_in[13] == 1'd1 && trunc_32bit_in[25:14] != 12'd2047) begin
+                            trunc_12bit_out[11:0] <= trunc_32bit_in[25:14] + 12'd1;
+                        end
+                        else begin
+                            if(trunc_32bit_in[31:25] == 7'd127 && trunc_32bit_in[13:0] > 14'd8192) begin
+                                trunc_12bit_out[11:0] <= trunc_32bit_in[25:14] + 12'd1;
+                            end
+                            else begin
+                                trunc_12bit_out[11:0] <= trunc_32bit_in[25:14];
+                            end
+                        end
+                        trunc_overflow <= 1'd0;
+                    end else begin
+                        if(trunc_32bit_in[31] == 1'd1) begin
+                            trunc_12bit_out[11:0] <= -12'd2048;
+                        end else begin
+                            trunc_12bit_out[11:0] <= 12'd2047;
+                        end
+                        trunc_overflow <= 1'd1;
+                    end
+                end
+                5'd7:begin
+                    if(trunc_32bit_in[31:24] == 8'd255 || trunc_32bit_in[31:24] == 8'd0) begin
+                        if(trunc_32bit_in[31:24] == 8'd0 &&trunc_32bit_in[12] == 1'd1 && trunc_32bit_in[24:13] != 12'd2047) begin
+                            trunc_12bit_out[11:0] <= trunc_32bit_in[24:13] + 12'd1;
+                        end
+                        else begin
+                            if(trunc_32bit_in[31:24] == 8'd255 && trunc_32bit_in[12:0] > 13'd4096) begin
+                                trunc_12bit_out[11:0] <= trunc_32bit_in[24:13] + 12'd1;
+                            end
+                            else begin
+                                trunc_12bit_out[11:0] <= trunc_32bit_in[24:13];
+                            end
+                        end
+                        trunc_overflow <= 1'd0;
+                    end else begin
+                        if(trunc_32bit_in[31] == 1'd1) begin
+                            trunc_12bit_out[11:0] <= -12'd2048;
+                        end else begin
+                            trunc_12bit_out[11:0] <= 12'd2047;
+                        end
+                        trunc_overflow <= 1'd1;
+                    end
+                end
+                5'd8:begin
+                    if(trunc_32bit_in[31:23] == 9'd511 || trunc_32bit_in[31:23] == 9'd0) begin
+                        if(trunc_32bit_in[31:23] == 9'd0 &&trunc_32bit_in[11] == 1'd1 && trunc_32bit_in[23:12] != 12'd2047) begin
+                            trunc_12bit_out[11:0] <= trunc_32bit_in[23:12] + 12'd1;
+                        end
+                        else begin
+                            if(trunc_32bit_in[31:23] == 9'd511 && trunc_32bit_in[11:0] > 12'd2048) begin
+                                trunc_12bit_out[11:0] <= trunc_32bit_in[23:12] + 12'd1;
+                            end
+                            else begin
+                                trunc_12bit_out[11:0] <= trunc_32bit_in[23:12];
+                            end
+                        end
+                        trunc_overflow <= 1'd0;
+                    end else begin
+                        if(trunc_32bit_in[31] == 1'd1) begin
+                            trunc_12bit_out[11:0] <= -12'd2048;
+                        end else begin
+                            trunc_12bit_out[11:0] <= 12'd2047;
+                        end
+                        trunc_overflow <= 1'd1;
+                    end
+                end
+                5'd9:begin
+                    if(trunc_32bit_in[31:22] == 10'd1023 || trunc_32bit_in[31:22] == 10'd0) begin
+                        if(trunc_32bit_in[31:22] == 10'd0 &&trunc_32bit_in[10] == 1'd1 && trunc_32bit_in[22:11] != 12'd2047) begin
+                            trunc_12bit_out[11:0] <= trunc_32bit_in[22:11] + 12'd1;
+                        end
+                        else begin
+                            if(trunc_32bit_in[31:22] == 10'd1023 && trunc_32bit_in[10:0] > 11'd1024) begin
+                                trunc_12bit_out[11:0] <= trunc_32bit_in[22:11] + 12'd1;
+                            end
+                            else begin
+                                trunc_12bit_out[11:0] <= trunc_32bit_in[22:11];
+                            end
+                        end
+                        trunc_overflow <= 1'd0;
+                    end else begin
+                        if(trunc_32bit_in[31] == 1'd1) begin
+                            trunc_12bit_out[11:0] <= -12'd2048;
+                        end else begin
+                            trunc_12bit_out[11:0] <= 12'd2047;
+                        end
+                        trunc_overflow <= 1'd1;
+                    end
+                end
+                5'd10:begin
+                    if(trunc_32bit_in[31:21] == 11'd2047 || trunc_32bit_in[31:21] == 11'd0) begin
+                        if(trunc_32bit_in[31:21] == 11'd0 &&trunc_32bit_in[9] == 1'd1 && trunc_32bit_in[21:10] != 12'd2047) begin
+                            trunc_12bit_out[11:0] <= trunc_32bit_in[21:10] + 12'd1;
+                        end
+                        else begin
+                            if(trunc_32bit_in[31:21] == 11'd2047 && trunc_32bit_in[9:0] > 10'd512) begin
+                                trunc_12bit_out[11:0] <= trunc_32bit_in[21:10] + 12'd1;
+                            end
+                            else begin
+                                trunc_12bit_out[11:0] <= trunc_32bit_in[21:10];
+                            end
+                        end
+                        trunc_overflow <= 1'd0;
+                    end else begin
+                        if(trunc_32bit_in[31] == 1'd1) begin
+                            trunc_12bit_out[11:0] <= -12'd2048;
+                        end else begin
+                            trunc_12bit_out[11:0] <= 12'd2047;
+                        end
+                        trunc_overflow <= 1'd1;
+                    end
+                end
+                5'd11:begin
+                    if(trunc_32bit_in[31:20] == 12'd4095 || trunc_32bit_in[31:20] == 12'd0) begin
+                        if(trunc_32bit_in[31:20] == 12'd0 &&trunc_32bit_in[8] == 1'd1 && trunc_32bit_in[20:9] != 12'd2047) begin
+                            trunc_12bit_out[11:0] <= trunc_32bit_in[20:9] + 12'd1;
+                        end
+                        else begin
+                            if(trunc_32bit_in[31:20] == 12'd4095 && trunc_32bit_in[8:0] > 9'd256) begin
+                                trunc_12bit_out[11:0] <= trunc_32bit_in[20:9] + 12'd1;
+                            end
+                            else begin
+                                trunc_12bit_out[11:0] <= trunc_32bit_in[20:9];
+                            end
+                        end
+                        trunc_overflow <= 1'd0;
+                    end else begin
+                        if(trunc_32bit_in[31] == 1'd1) begin
+                            trunc_12bit_out[11:0] <= -12'd2048;
+                        end else begin
+                            trunc_12bit_out[11:0] <= 12'd2047;
+                        end
+                        trunc_overflow <= 1'd1;
+                    end
+                end
+                5'd12:begin
+                    if(trunc_32bit_in[31:19] == 13'd8191 || trunc_32bit_in[31:19] == 13'd0) begin
+                        if(trunc_32bit_in[31:19] == 13'd0 &&trunc_32bit_in[7] == 1'd1 && trunc_32bit_in[19:8] != 12'd2047) begin
+                            trunc_12bit_out[11:0] <= trunc_32bit_in[19:8] + 12'd1;
+                        end
+                        else begin
+                            if(trunc_32bit_in[31:19] == 13'd8191 && trunc_32bit_in[7:0] > 8'd128) begin
+                                trunc_12bit_out[11:0] <= trunc_32bit_in[19:8] + 12'd1;
+                            end
+                            else begin
+                                trunc_12bit_out[11:0] <= trunc_32bit_in[19:8];
+                            end
+                        end
+                        trunc_overflow <= 1'd0;
+                    end else begin
+                        if(trunc_32bit_in[31] == 1'd1) begin
+                            trunc_12bit_out[11:0] <= -12'd2048;
+                        end else begin
+                            trunc_12bit_out[11:0] <= 12'd2047;
+                        end
+                        trunc_overflow <= 1'd1;
+                    end
+                end
+                5'd13:begin
+                    if(trunc_32bit_in[31:18] == 14'd16383 || trunc_32bit_in[31:18] == 14'd0) begin
+                        if(trunc_32bit_in[31:18] == 14'd0 &&trunc_32bit_in[6] == 1'd1 && trunc_32bit_in[18:7] != 12'd2047) begin
+                            trunc_12bit_out[11:0] <= trunc_32bit_in[18:7] + 12'd1;
+                        end
+                        else begin
+                            if(trunc_32bit_in[31:18] == 14'd16383 && trunc_32bit_in[6:0] > 7'd64) begin
+                                trunc_12bit_out[11:0] <= trunc_32bit_in[18:7] + 12'd1;
+                            end
+                            else begin
+                                trunc_12bit_out[11:0] <= trunc_32bit_in[18:7];
+                            end
+                        end
+                        trunc_overflow <= 1'd0;
+                    end else begin
+                        if(trunc_32bit_in[31] == 1'd1) begin
+                            trunc_12bit_out[11:0] <= -12'd2048;
+                        end else begin
+                            trunc_12bit_out[11:0] <= 12'd2047;
+                        end
+                        trunc_overflow <= 1'd1;
+                    end
+                end
+                5'd14:begin
+                    if(trunc_32bit_in[31:17] == 15'd32767 || trunc_32bit_in[31:17] == 15'd0) begin
+                        if(trunc_32bit_in[31:17] == 15'd0 &&trunc_32bit_in[5] == 1'd1 && trunc_32bit_in[17:6] != 12'd2047) begin
+                            trunc_12bit_out[11:0] <= trunc_32bit_in[17:6] + 12'd1;
+                        end
+                        else begin
+                            if(trunc_32bit_in[31:17] == 15'd32767 && trunc_32bit_in[5:0] > 6'd32) begin
+                                trunc_12bit_out[11:0] <= trunc_32bit_in[17:6] + 12'd1;
+                            end
+                            else begin
+                                trunc_12bit_out[11:0] <= trunc_32bit_in[17:6];
+                            end
+                        end
+                        trunc_overflow <= 1'd0;
+                    end else begin
+                        if(trunc_32bit_in[31] == 1'd1) begin
+                            trunc_12bit_out[11:0] <= -12'd2048;
+                        end else begin
+                            trunc_12bit_out[11:0] <= 12'd2047;
+                        end
+                        trunc_overflow <= 1'd1;
+                    end
+                end
+                5'd15:begin
+                    if(trunc_32bit_in[31:16] == 16'd65535 || trunc_32bit_in[31:16] == 16'd0) begin
+                        if(trunc_32bit_in[31:16] == 16'd0 &&trunc_32bit_in[4] == 1'd1 && trunc_32bit_in[16:5] != 12'd2047) begin
+                            trunc_12bit_out[11:0] <= trunc_32bit_in[16:5] + 12'd1;
+                        end
+                        else begin
+                            if(trunc_32bit_in[31:16] == 16'd65535 && trunc_32bit_in[4:0] > 5'd16) begin
+                                trunc_12bit_out[11:0] <= trunc_32bit_in[16:5] + 12'd1;
+                            end
+                            else begin
+                                trunc_12bit_out[11:0] <= trunc_32bit_in[16:5];
+                            end
+                        end
+                        trunc_overflow <= 1'd0;
+                    end else begin
+                        if(trunc_32bit_in[31] == 1'd1) begin
+                            trunc_12bit_out[11:0] <= -12'd2048;
+                        end else begin
+                            trunc_12bit_out[11:0] <= 12'd2047;
+                        end
+                        trunc_overflow <= 1'd1;
+                    end
+                end
+                5'd16:begin
+                    if(trunc_32bit_in[31:15] == 17'd131071 || trunc_32bit_in[31:15] == 17'd0) begin
+                        if(trunc_32bit_in[31:15] == 17'd0 &&trunc_32bit_in[3] == 1'd1 && trunc_32bit_in[15:4] != 12'd2047) begin
+                            trunc_12bit_out[11:0] <= trunc_32bit_in[15:4] + 12'd1;
+                        end
+                        else begin
+                            if(trunc_32bit_in[31:15] == 17'd131071 && trunc_32bit_in[3:0] > 4'd8) begin
+                                trunc_12bit_out[11:0] <= trunc_32bit_in[15:4] + 12'd1;
+                            end
+                            else begin
+                                trunc_12bit_out[11:0] <= trunc_32bit_in[15:4];
+                            end
+                        end
+                        trunc_overflow <= 1'd0;
+                    end else begin
+                        if(trunc_32bit_in[31] == 1'd1) begin
+                            trunc_12bit_out[11:0] <= -12'd2048;
+                        end else begin
+                            trunc_12bit_out[11:0] <= 12'd2047;
+                        end
+                        trunc_overflow <= 1'd1;
+                    end
+                end
+                5'd17:begin
+                    if(trunc_32bit_in[31:14] == 18'd262143 || trunc_32bit_in[31:14] == 18'd0) begin
+                        if(trunc_32bit_in[31:14] == 18'd0 &&trunc_32bit_in[2] == 1'd1 && trunc_32bit_in[14:3] != 12'd2047) begin
+                            trunc_12bit_out[11:0] <= trunc_32bit_in[14:3] + 12'd1;
+                        end
+                        else begin
+                            if(trunc_32bit_in[31:14] == 18'd262143 && trunc_32bit_in[2:0] > 3'd4) begin
+                                trunc_12bit_out[11:0] <= trunc_32bit_in[14:3] + 12'd1;
+                            end
+                            else begin
+                                trunc_12bit_out[11:0] <= trunc_32bit_in[14:3];
+                            end
+                        end
+                        trunc_overflow <= 1'd0;
+                    end else begin
+                        if(trunc_32bit_in[31] == 1'd1) begin
+                            trunc_12bit_out[11:0] <= -12'd2048;
+                        end else begin
+                            trunc_12bit_out[11:0] <= 12'd2047;
+                        end
+                        trunc_overflow <= 1'd1;
+                    end
+                end
+                5'd18:begin
+                    if(trunc_32bit_in[31:13] == 19'd524287 || trunc_32bit_in[31:13] == 19'd0) begin
+                        if(trunc_32bit_in[31:13] == 19'd0 &&trunc_32bit_in[1] == 1'd1 && trunc_32bit_in[13:2] != 12'd2047) begin
+                            trunc_12bit_out[11:0] <= trunc_32bit_in[13:2] + 12'd1;
+                        end
+                        else begin
+                            if(trunc_32bit_in[31:13] == 19'd524287 && trunc_32bit_in[1:0] > 2'd2) begin
+                                trunc_12bit_out[11:0] <= trunc_32bit_in[13:2] + 12'd1;
+                            end
+                            else begin
+                                trunc_12bit_out[11:0] <= trunc_32bit_in[13:2];
+                            end
+                        end
+                        trunc_overflow <= 1'd0;
+                    end else begin
+                        if(trunc_32bit_in[31] == 1'd1) begin
+                            trunc_12bit_out[11:0] <= -12'd2048;
+                        end else begin
+                            trunc_12bit_out[11:0] <= 12'd2047;
+                        end
+                        trunc_overflow <= 1'd1;
+                    end
+                end
+                5'd19:begin
+                    if(trunc_32bit_in[31:12] == 20'd1048575 || trunc_32bit_in[31:12] == 20'd0) begin
+                        if(trunc_32bit_in[31:12] == 20'd0 &&trunc_32bit_in[0] == 1'd1 && trunc_32bit_in[12:1] != 12'd2047) begin
+                            trunc_12bit_out[11:0] <= trunc_32bit_in[12:1] + 12'd1;
+                        end
+                        else begin
+                            if(trunc_32bit_in[31:12] == 20'd1048575 && trunc_32bit_in[0:0] > 1'd1) begin
+                                trunc_12bit_out[11:0] <= trunc_32bit_in[12:1] + 12'd1;
+                            end
+                            else begin
+                                trunc_12bit_out[11:0] <= trunc_32bit_in[12:1];
+                            end
+                        end
+                        trunc_overflow <= 1'd0;
+                    end else begin
+                        if(trunc_32bit_in[31] == 1'd1) begin
+                            trunc_12bit_out[11:0] <= -12'd2048;
+                        end else begin
+                            trunc_12bit_out[11:0] <= 12'd2047;
+                        end
+                        trunc_overflow <= 1'd1;
+                    end
+                end
+                default:begin
+                    if(trunc_32bit_in[31:11] == 21'd2097151 || trunc_32bit_in[31:11] == 21'd0) begin
+                        trunc_12bit_out[11:0] <= trunc_32bit_in[11:0];
+                        trunc_overflow <= 1'd0;
+                    end else begin
+                        if(trunc_32bit_in[31] == 1'd1) begin
+                            trunc_12bit_out[11:0] <= -12'd2048;
+                        end else begin
+                            trunc_12bit_out[11:0] <= 12'd2047;
+                        end
+                        trunc_overflow <= 1'd1;
+                    end
+                end
+            endcase
+        end
+    end
+endmodule

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/README.txt

@@ -0,0 +1 @@
+The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/ip/cmpy_18x18_mult/cmpy_18x18_mult.veo

@@ -0,0 +1,71 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+// IP VLNV: xilinx.com:ip:cmpy:6.0
+// IP Revision: 17
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+cmpy_18x18_mult your_instance_name (
+  .aclk(aclk),                              // input wire aclk
+  .s_axis_a_tvalid(s_axis_a_tvalid),        // input wire s_axis_a_tvalid
+  .s_axis_a_tdata(s_axis_a_tdata),          // input wire [47 : 0] s_axis_a_tdata
+  .s_axis_b_tvalid(s_axis_b_tvalid),        // input wire s_axis_b_tvalid
+  .s_axis_b_tdata(s_axis_b_tdata),          // input wire [47 : 0] s_axis_b_tdata
+  .m_axis_dout_tvalid(m_axis_dout_tvalid),  // output wire m_axis_dout_tvalid
+  .m_axis_dout_tdata(m_axis_dout_tdata)    // output wire [79 : 0] m_axis_dout_tdata
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file cmpy_18x18_mult.v when simulating
+// the core, cmpy_18x18_mult. When compiling the wrapper file, be sure to
+// reference the Verilog simulation library.
+

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/ip/cmpy_18x18_mult/cmpy_18x18_mult.vho

@@ -0,0 +1,87 @@
+-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:cmpy:6.0
+-- IP Revision: 17
+
+-- The following code must appear in the VHDL architecture header.
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+COMPONENT cmpy_18x18_mult
+  PORT (
+    aclk : IN STD_LOGIC;
+    s_axis_a_tvalid : IN STD_LOGIC;
+    s_axis_a_tdata : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
+    s_axis_b_tvalid : IN STD_LOGIC;
+    s_axis_b_tdata : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
+    m_axis_dout_tvalid : OUT STD_LOGIC;
+    m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(79 DOWNTO 0)
+  );
+END COMPONENT;
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : cmpy_18x18_mult
+  PORT MAP (
+    aclk => aclk,
+    s_axis_a_tvalid => s_axis_a_tvalid,
+    s_axis_a_tdata => s_axis_a_tdata,
+    s_axis_b_tvalid => s_axis_b_tvalid,
+    s_axis_b_tdata => s_axis_b_tdata,
+    m_axis_dout_tvalid => m_axis_dout_tvalid,
+    m_axis_dout_tdata => m_axis_dout_tdata
+  );
+-- INST_TAG_END ------ End INSTANTIATION Template ---------
+
+-- You must compile the wrapper file cmpy_18x18_mult.vhd when simulating
+-- the core, cmpy_18x18_mult. When compiling the wrapper file, be sure to
+-- reference the VHDL simulation library.
+

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/ip/cmpy_18x18_mult/cmpy_18x18_mult_stub.v

@@ -0,0 +1,27 @@
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
+// Date        : Sun Jun 11 14:40:37 2023
+// Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
+// Command     : write_verilog -force -mode synth_stub
+//               /home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/cmpy_18x18_mult/cmpy_18x18_mult_stub.v
+// Design      : cmpy_18x18_mult
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7k410tffg900-2
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "cmpy_v6_0_17,Vivado 2019.1.3" *)
+module cmpy_18x18_mult(aclk, s_axis_a_tvalid, s_axis_a_tdata, 
+  s_axis_b_tvalid, s_axis_b_tdata, m_axis_dout_tvalid, m_axis_dout_tdata)
+/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_a_tvalid,s_axis_a_tdata[47:0],s_axis_b_tvalid,s_axis_b_tdata[47:0],m_axis_dout_tvalid,m_axis_dout_tdata[79:0]" */;
+  input aclk;
+  input s_axis_a_tvalid;
+  input [47:0]s_axis_a_tdata;
+  input s_axis_b_tvalid;
+  input [47:0]s_axis_b_tdata;
+  output m_axis_dout_tvalid;
+  output [79:0]m_axis_dout_tdata;
+endmodule

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/ip/cmpy_18x18_mult/cmpy_18x18_mult_stub.vhdl

@@ -0,0 +1,36 @@
+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
+-- Date        : Sun Jun 11 14:40:37 2023
+-- Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
+-- Command     : write_vhdl -force -mode synth_stub
+--               /home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/cmpy_18x18_mult/cmpy_18x18_mult_stub.vhdl
+-- Design      : cmpy_18x18_mult
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7k410tffg900-2
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity cmpy_18x18_mult is
+  Port ( 
+    aclk : in STD_LOGIC;
+    s_axis_a_tvalid : in STD_LOGIC;
+    s_axis_a_tdata : in STD_LOGIC_VECTOR ( 47 downto 0 );
+    s_axis_b_tvalid : in STD_LOGIC;
+    s_axis_b_tdata : in STD_LOGIC_VECTOR ( 47 downto 0 );
+    m_axis_dout_tvalid : out STD_LOGIC;
+    m_axis_dout_tdata : out STD_LOGIC_VECTOR ( 79 downto 0 )
+  );
+
+end cmpy_18x18_mult;
+
+architecture stub of cmpy_18x18_mult is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_a_tvalid,s_axis_a_tdata[47:0],s_axis_b_tvalid,s_axis_b_tdata[47:0],m_axis_dout_tvalid,m_axis_dout_tdata[79:0]";
+attribute x_core_info : string;
+attribute x_core_info of stub : architecture is "cmpy_v6_0_17,Vivado 2019.1.3";
+begin
+end;

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/ip/cmpy_18x18_mult/demo_tb/tb_cmpy_18x18_mult.vhd

@@ -0,0 +1,389 @@
+--------------------------------------------------------------------------------
+-- (c) Copyright 2011 - 2013 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--------------------------------------------------------------------------------
+-- Description:
+-- This is an example testbench for the Complex Multiplier IP core.
+-- The testbench has been generated by Vivado to accompany the IP core
+-- instance you have generated.
+--
+-- This testbench is for demonstration purposes only.  See note below for
+-- instructions on how to use it with your core.
+--
+-- See the Complex Multiplier product guide for further information
+-- about this core.
+--
+--------------------------------------------------------------------------------
+-- Using this testbench
+--
+-- This testbench instantiates your generated Complex Multiplier core
+-- instance named "cmpy_18x18_mult".
+--
+-- Use Vivado's Run Simulation flow to run this testbench.  See the Vivado
+-- documentation for details.
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+
+entity tb_cmpy_18x18_mult is
+end tb_cmpy_18x18_mult;
+
+architecture tb of tb_cmpy_18x18_mult is
+
+  -----------------------------------------------------------------------
+  -- Timing constants
+  -----------------------------------------------------------------------
+  constant CLOCK_PERIOD : time := 100 ns;
+  constant T_HOLD       : time := 10 ns;
+  constant T_STROBE     : time := CLOCK_PERIOD - (1 ns);
+  constant TEST_CYCLES  : integer := 3000;
+  constant PHASE_CYCLES : integer := 1000;
+
+  -----------------------------------------------------------------------
+  -- DUT input signals
+  -----------------------------------------------------------------------
+
+  -- General inputs
+  signal aclk               : std_logic := '0';  -- the master clock
+
+  -- Slave channel A inputs
+  signal s_axis_a_tvalid    : std_logic := '0';  -- TVALID for channel A
+  signal s_axis_a_tdata     : std_logic_vector(47 downto 0) := (others => '0');  -- TDATA for channel A
+
+  -- Slave channel B inputs
+  signal s_axis_b_tvalid    : std_logic := '0';  -- TVALID for channel B
+  signal s_axis_b_tdata     : std_logic_vector(47 downto 0) := (others => '0');  -- TDATA for channel B
+
+  -----------------------------------------------------------------------
+  -- DUT output signals
+  -----------------------------------------------------------------------
+
+  -- Master channel DOUT outputs
+  signal m_axis_dout_tvalid : std_logic := '0';  -- TVALID for channel DOUT
+  signal m_axis_dout_tdata  : std_logic_vector(79 downto 0) := (others => '0');  -- TDATA for channel DOUT
+
+  -----------------------------------------------------------------------
+  -- Aliases for AXI channel TDATA fields
+  -- These are a convenience for viewing data in a simulator waveform viewer.
+  -- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command
+  -- to prevent the simulator optimizing away these signals.
+  -----------------------------------------------------------------------
+  signal s_axis_a_tdata_real     : std_logic_vector(17 downto 0) := (others => '0');
+  signal s_axis_a_tdata_imag     : std_logic_vector(17 downto 0) := (others => '0');
+  signal s_axis_b_tdata_real     : std_logic_vector(17 downto 0) := (others => '0');
+  signal s_axis_b_tdata_imag     : std_logic_vector(17 downto 0) := (others => '0');
+  signal m_axis_dout_tdata_real  : std_logic_vector(36 downto 0) := (others => '0');
+  signal m_axis_dout_tdata_imag  : std_logic_vector(36 downto 0) := (others => '0');
+
+  -----------------------------------------------------------------------
+  -- Testbench signals
+  -----------------------------------------------------------------------
+
+  signal cycles       : integer   := 0;    -- Clock cycle counter
+
+  -----------------------------------------------------------------------
+  -- Constants, types and functions to create input data
+  -- Treat the complex multiplier as a mixer that is combining two
+  -- sinusoids exp(+/-jwt) of different frequencies and amplitudes:
+  --   channel A: exp(+jwt), frequency = clock / 30, amplitude = fullscale >> 3
+  --   channel B: exp(-jwt), frequency = clock / 32, amplitude = fullscale
+  -- The output of the complex multiplier is a sinusoid with a frequency
+  -- equal to the difference between the input frequencies.
+  -----------------------------------------------------------------------
+
+  constant IP_A_DEPTH : integer := 30;
+  constant IP_A_WIDTH : integer := 18;
+  constant IP_A_SHIFT : integer := 3;  -- bit shift for amplitude
+  constant IP_B_DEPTH : integer := 32;
+  constant IP_B_WIDTH : integer := 18;
+  constant IP_B_SHIFT : integer := 0;  -- no bit shift, max amplitude
+  type T_IP_INT_ENTRY is record
+    re : integer;
+    im : integer;
+  end record;
+  type T_IP_A_ENTRY is record
+    re : std_logic_vector(IP_A_WIDTH-1 downto 0);
+    im : std_logic_vector(IP_A_WIDTH-1 downto 0);
+  end record;
+  type T_IP_B_ENTRY is record
+    re : std_logic_vector(IP_B_WIDTH-1 downto 0);
+    im : std_logic_vector(IP_B_WIDTH-1 downto 0);
+  end record;
+  type T_IP_A_TABLE is array (0 to IP_A_DEPTH-1) of T_IP_A_ENTRY;
+  type T_IP_B_TABLE is array (0 to IP_B_DEPTH-1) of T_IP_B_ENTRY;
+
+  -- Common function to calculate sine and cosine values
+  function create_ip_entry(index, depth, width : integer) return T_IP_INT_ENTRY is
+    variable result : T_IP_INT_ENTRY;
+    variable theta : real;
+    variable limited_width : integer := width - 2;
+  begin
+    if limited_width > 30 then
+      limited_width := 30;
+    end if;
+    theta := real(index) / real(depth) * 2.0 * MATH_PI;
+    result.re := integer(round(cos(theta) * real(2**limited_width-1)));
+    result.im := integer(round(sin(theta) * real(2**limited_width-1)));
+    return result;
+  end function create_ip_entry;
+
+  -- Use separate functions to calculate channel A and B sinusoids as they return different types
+  function create_ip_a_table return T_IP_A_TABLE is
+    variable result : T_IP_A_TABLE;
+    variable entry_int : T_IP_INT_ENTRY;
+  begin
+    for i in 0 to IP_A_DEPTH-1 loop
+      entry_int := create_ip_entry(i, IP_A_DEPTH, IP_A_WIDTH - IP_A_SHIFT);
+      result(i).re := std_logic_vector(to_signed(entry_int.re, IP_A_WIDTH));
+      result(i).im := std_logic_vector(to_signed(entry_int.im, IP_A_WIDTH));
+    end loop;
+    return result;
+  end function create_ip_a_table;
+
+  function create_ip_b_table return T_IP_B_TABLE is
+    variable result : T_IP_B_TABLE;
+    variable entry_int : T_IP_INT_ENTRY;
+  begin
+    for i in 0 to IP_B_DEPTH-1 loop
+      entry_int := create_ip_entry(IP_B_DEPTH-1-i, IP_B_DEPTH, IP_B_WIDTH - IP_B_SHIFT);  -- note rotation direction
+      result(i).re := std_logic_vector(to_signed(entry_int.re, IP_B_WIDTH));
+      result(i).im := std_logic_vector(to_signed(entry_int.im, IP_B_WIDTH));
+    end loop;
+    return result;
+  end function create_ip_b_table;
+
+  -- Call the functions to create the data
+  constant IP_A_DATA : T_IP_A_TABLE := create_ip_a_table;
+  constant IP_B_DATA : T_IP_B_TABLE := create_ip_b_table;
+
+
+begin
+
+  -----------------------------------------------------------------------
+  -- Instantiate the DUT
+  -----------------------------------------------------------------------
+
+  dut : entity work.cmpy_18x18_mult
+    port map (
+      aclk                => aclk,
+      s_axis_a_tvalid     => s_axis_a_tvalid,
+      s_axis_a_tdata      => s_axis_a_tdata,
+      s_axis_b_tvalid     => s_axis_b_tvalid,
+      s_axis_b_tdata      => s_axis_b_tdata,
+      m_axis_dout_tvalid  => m_axis_dout_tvalid,
+      m_axis_dout_tdata   => m_axis_dout_tdata
+      );
+
+  -----------------------------------------------------------------------
+  -- Generate clock
+  -----------------------------------------------------------------------
+
+  clock_gen : process
+  begin
+    aclk <= '0';
+    wait for CLOCK_PERIOD;
+    loop
+      cycles <= cycles + 1;
+      aclk <= '0';
+      wait for CLOCK_PERIOD/2;
+      aclk <= '1';
+      wait for CLOCK_PERIOD/2;
+      if cycles >= TEST_CYCLES then
+        report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure;
+        wait;
+      end if;
+    end loop;
+  end process clock_gen;
+
+  -----------------------------------------------------------------------
+  -- Generate inputs
+  -----------------------------------------------------------------------
+
+  stimuli : process
+    variable ip_a_index       : integer   := 0;
+    variable ip_b_index       : integer   := 0;
+    variable a_tvalid_nxt     : std_logic := '0';
+    variable b_tvalid_nxt     : std_logic := '0';
+    variable phase2_cycles : integer := 1;
+    variable phase2_count  : integer := 0;
+    constant PHASE2_LIMIT  : integer := 30;
+  begin
+
+    -- Test is stopped in clock_gen process, use endless loop here
+    loop
+
+      -- Drive inputs T_HOLD time after rising edge of clock
+      wait until rising_edge(aclk);
+      wait for T_HOLD;
+
+      -- Drive AXI TVALID signals to demonstrate different types of operation
+      case cycles is  -- do different types of operation at different phases of the test
+        when 0 to PHASE_CYCLES * 1 - 1 =>
+          -- Phase 1: inputs always valid, no missing input data
+          a_tvalid_nxt    := '1';
+          b_tvalid_nxt    := '1';
+        when PHASE_CYCLES * 1 to PHASE_CYCLES * 2 - 1 =>
+          -- Phase 2: deprive channel A of valid transactions at an increasing rate
+          b_tvalid_nxt    := '1';
+          if phase2_count < phase2_cycles then
+            a_tvalid_nxt := '0';
+          else
+            a_tvalid_nxt := '1';
+          end if;
+          phase2_count := phase2_count + 1;
+          if phase2_count >= PHASE2_LIMIT then
+            phase2_count  := 0;
+            phase2_cycles := phase2_cycles + 1;
+          end if;
+        when PHASE_CYCLES * 2 to PHASE_CYCLES * 3 - 1 =>
+          -- Phase 3: deprive channel A of 1 out of 2 transactions, and channel B of 1 out of 3 transactions
+          if cycles mod 2 = 0 then
+            a_tvalid_nxt := '0';
+          else
+            a_tvalid_nxt := '1';
+          end if;
+          if cycles mod 3 = 0 then
+            b_tvalid_nxt := '0';
+          else
+            b_tvalid_nxt := '1';
+          end if;
+        when others =>
+          -- Test will stop imminently - do nothing
+          null;
+      end case;
+
+      -- Drive handshake signals with local variable values
+      s_axis_a_tvalid <= a_tvalid_nxt;
+      s_axis_b_tvalid <= b_tvalid_nxt;
+
+      -- Drive AXI slave channel A payload
+      -- Drive '0's on payload signals when not valid
+      if a_tvalid_nxt /= '1' then
+        s_axis_a_tdata <= (others => '0');
+      else
+        -- TDATA: Real and imaginary components are each 18 bits wide and byte-aligned at their LSBs
+        s_axis_a_tdata(17 downto 0) <= IP_A_DATA(ip_a_index).re;
+        s_axis_a_tdata(23 downto 18) <= (others => IP_A_DATA(ip_a_index).re(17));  -- sign-extend;
+        s_axis_a_tdata(41 downto 24) <= IP_A_DATA(ip_a_index).im;
+        s_axis_a_tdata(47 downto 42) <= (others => IP_A_DATA(ip_a_index).im(17));  -- sign-extend;
+      end if;
+
+      -- Drive AXI slave channel B payload
+      -- Drive '0's on payload signals when not valid
+      if b_tvalid_nxt /= '1' then
+        s_axis_b_tdata <= (others => '0');
+      else
+        -- TDATA: Real and imaginary components are each 18 bits wide and byte-aligned at their LSBs
+        s_axis_b_tdata(17 downto 0) <= IP_B_DATA(ip_b_index).re;
+        s_axis_b_tdata(23 downto 18) <= (others => IP_B_DATA(ip_b_index).re(17));  -- sign-extend
+        s_axis_b_tdata(41 downto 24) <= IP_B_DATA(ip_b_index).im;
+        s_axis_b_tdata(47 downto 42) <= (others => IP_B_DATA(ip_b_index).im(17));  -- sign-extend
+      end if;
+
+      -- Increment input data indices
+      if a_tvalid_nxt = '1' then
+        ip_a_index := ip_a_index + 1;
+        if ip_a_index = IP_A_DEPTH then
+          ip_a_index := 0;
+        end if;
+      end if;
+      if b_tvalid_nxt = '1' then
+        ip_b_index := ip_b_index + 1;
+        if ip_b_index = IP_B_DEPTH then
+          ip_b_index := 0;
+        end if;
+      end if;
+
+    end loop;
+
+  end process stimuli;
+
+  -----------------------------------------------------------------------
+  -- Check outputs
+  -----------------------------------------------------------------------
+
+  check_outputs : process
+    variable check_ok : boolean := true;
+  begin
+
+    -- Check outputs T_STROBE time after rising edge of clock
+    wait until rising_edge(aclk);
+    wait for T_STROBE;
+
+    -- Do not check the output payload values, as this requires the behavioral model
+    -- which would make this demonstration testbench unwieldy.
+    -- Instead, check the protocol of the DOUT channel:
+    -- check that the payload is valid (not X) when TVALID is high
+
+    if m_axis_dout_tvalid = '1' then
+      if is_x(m_axis_dout_tdata) then
+        report "ERROR: m_axis_dout_tdata is invalid when m_axis_dout_tvalid is high" severity error;
+        check_ok := false;
+      end if;
+
+    end if;
+
+    assert check_ok
+      report "ERROR: terminating test with failures." severity failure;
+
+  end process check_outputs;
+
+  -----------------------------------------------------------------------
+  -- Assign TDATA fields to aliases, for easy simulator waveform viewing
+  -----------------------------------------------------------------------
+
+  s_axis_a_tdata_real     <= s_axis_a_tdata(17 downto 0);
+  s_axis_a_tdata_imag     <= s_axis_a_tdata(41 downto 24);
+  s_axis_b_tdata_real     <= s_axis_b_tdata(17 downto 0);
+  s_axis_b_tdata_imag     <= s_axis_b_tdata(41 downto 24);
+  m_axis_dout_tdata_real  <= m_axis_dout_tdata(36 downto 0);
+  m_axis_dout_tdata_imag  <= m_axis_dout_tdata(76 downto 40);
+
+end tb;
+

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/ip/cmpy_18x18_mult/sim/cmpy_18x18_mult.vhd

@@ -0,0 +1,202 @@
+-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:cmpy:6.0
+-- IP Revision: 17
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY cmpy_v6_0_17;
+USE cmpy_v6_0_17.cmpy_v6_0_17;
+
+ENTITY cmpy_18x18_mult IS
+  PORT (
+    aclk : IN STD_LOGIC;
+    s_axis_a_tvalid : IN STD_LOGIC;
+    s_axis_a_tdata : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
+    s_axis_b_tvalid : IN STD_LOGIC;
+    s_axis_b_tdata : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
+    m_axis_dout_tvalid : OUT STD_LOGIC;
+    m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(79 DOWNTO 0)
+  );
+END cmpy_18x18_mult;
+
+ARCHITECTURE cmpy_18x18_mult_arch OF cmpy_18x18_mult IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF cmpy_18x18_mult_arch: ARCHITECTURE IS "yes";
+  COMPONENT cmpy_v6_0_17 IS
+    GENERIC (
+      C_VERBOSITY : INTEGER;
+      C_XDEVICEFAMILY : STRING;
+      C_XDEVICE : STRING;
+      C_A_WIDTH : INTEGER;
+      C_B_WIDTH : INTEGER;
+      C_OUT_WIDTH : INTEGER;
+      C_LATENCY : INTEGER;
+      C_MULT_TYPE : INTEGER;
+      C_OPTIMIZE_GOAL : INTEGER;
+      HAS_NEGATE : INTEGER;
+      SINGLE_OUTPUT : INTEGER;
+      ROUND : INTEGER;
+      USE_DSP_CASCADES : INTEGER;
+      C_THROTTLE_SCHEME : INTEGER;
+      C_HAS_ACLKEN : INTEGER;
+      C_HAS_ARESETN : INTEGER;
+      C_HAS_S_AXIS_A_TUSER : INTEGER;
+      C_HAS_S_AXIS_A_TLAST : INTEGER;
+      C_HAS_S_AXIS_B_TUSER : INTEGER;
+      C_HAS_S_AXIS_B_TLAST : INTEGER;
+      C_HAS_S_AXIS_CTRL_TUSER : INTEGER;
+      C_HAS_S_AXIS_CTRL_TLAST : INTEGER;
+      C_TLAST_RESOLUTION : INTEGER;
+      C_S_AXIS_A_TDATA_WIDTH : INTEGER;
+      C_S_AXIS_A_TUSER_WIDTH : INTEGER;
+      C_S_AXIS_B_TDATA_WIDTH : INTEGER;
+      C_S_AXIS_B_TUSER_WIDTH : INTEGER;
+      C_S_AXIS_CTRL_TDATA_WIDTH : INTEGER;
+      C_S_AXIS_CTRL_TUSER_WIDTH : INTEGER;
+      C_M_AXIS_DOUT_TDATA_WIDTH : INTEGER;
+      C_M_AXIS_DOUT_TUSER_WIDTH : INTEGER
+    );
+    PORT (
+      aclk : IN STD_LOGIC;
+      aclken : IN STD_LOGIC;
+      aresetn : IN STD_LOGIC;
+      s_axis_a_tvalid : IN STD_LOGIC;
+      s_axis_a_tready : OUT STD_LOGIC;
+      s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      s_axis_a_tlast : IN STD_LOGIC;
+      s_axis_a_tdata : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
+      s_axis_b_tvalid : IN STD_LOGIC;
+      s_axis_b_tready : OUT STD_LOGIC;
+      s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      s_axis_b_tlast : IN STD_LOGIC;
+      s_axis_b_tdata : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
+      s_axis_ctrl_tvalid : IN STD_LOGIC;
+      s_axis_ctrl_tready : OUT STD_LOGIC;
+      s_axis_ctrl_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      s_axis_ctrl_tlast : IN STD_LOGIC;
+      s_axis_ctrl_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      m_axis_dout_tvalid : OUT STD_LOGIC;
+      m_axis_dout_tready : IN STD_LOGIC;
+      m_axis_dout_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      m_axis_dout_tlast : OUT STD_LOGIC;
+      m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(79 DOWNTO 0)
+    );
+  END COMPONENT cmpy_v6_0_17;
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TDATA";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_dout_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_DOUT, TDATA_NUM_BYTES 10, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_b_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_B, TDATA_NUM_BYTES 6, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_a_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_A, TDATA_NUM_BYTES 6, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_CTRL:S_AXIS_B:S_AXIS_A:M_AXIS_DOUT, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 10000000, PHASE 0.000, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
+BEGIN
+  U0 : cmpy_v6_0_17
+    GENERIC MAP (
+      C_VERBOSITY => 0,
+      C_XDEVICEFAMILY => "kintex7",
+      C_XDEVICE => "xc7k410t",
+      C_A_WIDTH => 18,
+      C_B_WIDTH => 18,
+      C_OUT_WIDTH => 37,
+      C_LATENCY => 6,
+      C_MULT_TYPE => 1,
+      C_OPTIMIZE_GOAL => 0,
+      HAS_NEGATE => 0,
+      SINGLE_OUTPUT => 0,
+      ROUND => 0,
+      USE_DSP_CASCADES => 1,
+      C_THROTTLE_SCHEME => 3,
+      C_HAS_ACLKEN => 0,
+      C_HAS_ARESETN => 0,
+      C_HAS_S_AXIS_A_TUSER => 0,
+      C_HAS_S_AXIS_A_TLAST => 0,
+      C_HAS_S_AXIS_B_TUSER => 0,
+      C_HAS_S_AXIS_B_TLAST => 0,
+      C_HAS_S_AXIS_CTRL_TUSER => 0,
+      C_HAS_S_AXIS_CTRL_TLAST => 0,
+      C_TLAST_RESOLUTION => 0,
+      C_S_AXIS_A_TDATA_WIDTH => 48,
+      C_S_AXIS_A_TUSER_WIDTH => 1,
+      C_S_AXIS_B_TDATA_WIDTH => 48,
+      C_S_AXIS_B_TUSER_WIDTH => 1,
+      C_S_AXIS_CTRL_TDATA_WIDTH => 8,
+      C_S_AXIS_CTRL_TUSER_WIDTH => 1,
+      C_M_AXIS_DOUT_TDATA_WIDTH => 80,
+      C_M_AXIS_DOUT_TUSER_WIDTH => 1
+    )
+    PORT MAP (
+      aclk => aclk,
+      aclken => '1',
+      aresetn => '1',
+      s_axis_a_tvalid => s_axis_a_tvalid,
+      s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      s_axis_a_tlast => '0',
+      s_axis_a_tdata => s_axis_a_tdata,
+      s_axis_b_tvalid => s_axis_b_tvalid,
+      s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      s_axis_b_tlast => '0',
+      s_axis_b_tdata => s_axis_b_tdata,
+      s_axis_ctrl_tvalid => '0',
+      s_axis_ctrl_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      s_axis_ctrl_tlast => '0',
+      s_axis_ctrl_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
+      m_axis_dout_tvalid => m_axis_dout_tvalid,
+      m_axis_dout_tready => '0',
+      m_axis_dout_tdata => m_axis_dout_tdata
+    );
+END cmpy_18x18_mult_arch;

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd

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+`protect end_protected

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/sim_scripts/cmpy_18x18_mult/README.txt

@@ -0,0 +1,83 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required
+#             to simulate the design for a simulator, the directory structure
+#             and the generated exported files.
+#
+################################################################################
+
+1. Simulate Design
+
+To simulate design, cd to the simulator directory and execute the script.
+
+For example:-
+
+% cd questa
+% ./top.sh
+
+The export simulation flow requires the Xilinx pre-compiled simulation library
+components for the target simulator. These components are referred using the
+'-lib_map_path' switch. If this switch is specified, then the export simulation
+will automatically set this library path in the generated script and update,
+copy the simulator setup file(s) in the exported directory.
+
+If '-lib_map_path' is not specified, then the pre-compiled simulation library
+information will not be included in the exported scripts and that may cause
+simulation errors when running this script. Alternatively, you can provide the
+library information using this switch while executing the generated script.
+
+For example:-
+
+% ./top.sh -lib_map_path /design/questa/clibs
+
+Please refer to the generated script header 'Prerequisite' section for more details.
+
+2. Directory Structure
+
+By default, if the -directory switch is not specified, export_simulation will
+create the following directory structure:-
+
+<current_working_directory>/export_sim/<simulator>
+
+For example, if the current working directory is /tmp/test, export_simulation
+will create the following directory path:-
+
+/tmp/test/export_sim/questa
+
+If -directory switch is specified, export_simulation will create a simulator
+sub-directory under the specified directory path.
+
+For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
+command will create the following directory:-
+
+/tmp/test/my_test_area/func_sim/questa
+
+By default, if -simulator is not specified, export_simulation will create a
+simulator sub-directory for each simulator and export the files for each simulator
+in this sub-directory respectively.
+
+IMPORTANT: Please note that the simulation library path must be specified manually
+in the generated script for the respective simulator. Please refer to the generated
+script header 'Prerequisite' section for more details.
+
+3. Exported script and files
+
+Export simulation will create the driver shell script, setup files and copy the
+design sources in the output directory path.
+
+By default, when the -script_name switch is not specified, export_simulation will
+create the following script name:-
+
+<simulation_top>.sh  (Unix)
+When exporting the files for an IP using the -of_objects switch, export_simulation
+will create the following script name:-
+
+<ip-name>.sh  (Unix)
+Export simulation will create the setup files for the target simulator specified
+with the -simulator switch.
+
+For example, if the target simulator is "ies", export_simulation will create the
+'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
+file.
+

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/sim_scripts/cmpy_18x18_mult/activehdl/README.txt

@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Sun Jun 11 14:42:06 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./cmpy_18x18_mult.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './cmpy_18x18_mult.sh' script.
+
+./cmpy_18x18_mult.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./cmpy_18x18_mult.sh -noclean_files
+
+For more information on the script, please type './cmpy_18x18_mult.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/sim_scripts/cmpy_18x18_mult/activehdl/cmpy_18x18_mult.sh

@@ -0,0 +1,152 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : cmpy_18x18_mult.sh
+# Simulator   : Aldec Active-HDL Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Sun Jun 11 14:42:06 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: cmpy_18x18_mult.sh [-help]
+# usage: cmpy_18x18_mult.sh [-lib_map_path]
+# usage: cmpy_18x18_mult.sh [-noclean_files]
+# usage: cmpy_18x18_mult.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'cmpy_18x18_mult.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "cmpy_18x18_mult.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./cmpy_18x18_mult.sh -help\" for more information)\n"
+        exit 1
+      fi
+     map_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     map_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Map library.cfg file
+map_setup_file()
+{
+  file="library.cfg"
+  lib_map_path=""
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      vmap -link $lib_map_path
+    fi
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./cmpy_18x18_mult.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: cmpy_18x18_mult.sh [-help]\n\
+Usage: cmpy_18x18_mult.sh [-lib_map_path]\n\
+Usage: cmpy_18x18_mult.sh [-reset_run]\n\
+Usage: cmpy_18x18_mult.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/sim_scripts/cmpy_18x18_mult/activehdl/compile.do

@@ -0,0 +1,41 @@
+vlib work
+vlib activehdl
+
+vlib activehdl/xbip_utils_v3_0_10
+vlib activehdl/axi_utils_v2_0_6
+vlib activehdl/xbip_pipe_v3_0_6
+vlib activehdl/xbip_bram18k_v3_0_6
+vlib activehdl/mult_gen_v12_0_15
+vlib activehdl/cmpy_v6_0_17
+vlib activehdl/xil_defaultlib
+
+vmap xbip_utils_v3_0_10 activehdl/xbip_utils_v3_0_10
+vmap axi_utils_v2_0_6 activehdl/axi_utils_v2_0_6
+vmap xbip_pipe_v3_0_6 activehdl/xbip_pipe_v3_0_6
+vmap xbip_bram18k_v3_0_6 activehdl/xbip_bram18k_v3_0_6
+vmap mult_gen_v12_0_15 activehdl/mult_gen_v12_0_15
+vmap cmpy_v6_0_17 activehdl/cmpy_v6_0_17
+vmap xil_defaultlib activehdl/xil_defaultlib
+
+vcom -work xbip_utils_v3_0_10 -93 \
+"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
+
+vcom -work axi_utils_v2_0_6 -93 \
+"../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \
+
+vcom -work xbip_pipe_v3_0_6 -93 \
+"../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \
+
+vcom -work xbip_bram18k_v3_0_6 -93 \
+"../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \
+
+vcom -work mult_gen_v12_0_15 -93 \
+"../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \
+
+vcom -work cmpy_v6_0_17 -93 \
+"../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -93 \
+"../../../ip/cmpy_18x18_mult/sim/cmpy_18x18_mult.vhd" \
+
+

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/sim_scripts/cmpy_18x18_mult/activehdl/file_info.txt

@@ -0,0 +1,7 @@
+xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
+axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
+xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,
+xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd,
+mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd,
+cmpy_v6_0_vh_rfs.vhd,vhdl,cmpy_v6_0_17,../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd,
+cmpy_18x18_mult.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_18x18_mult/sim/cmpy_18x18_mult.vhd,

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/sim_scripts/cmpy_18x18_mult/activehdl/simulate.do

@@ -0,0 +1,17 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim -t 1ps +access +r +m+cmpy_18x18_mult -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L cmpy_v6_0_17 -L xil_defaultlib -L secureip -O5 xil_defaultlib.cmpy_18x18_mult
+
+do {wave.do}
+
+view wave
+view structure
+
+do {cmpy_18x18_mult.udo}
+
+run -all
+
+endsim
+
+quit -force

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/sim_scripts/cmpy_18x18_mult/activehdl/wave.do

@@ -0,0 +1 @@
+add wave *

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/sim_scripts/cmpy_18x18_mult/ies/README.txt

@@ -0,0 +1,48 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Sun Jun 11 14:42:06 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./cmpy_18x18_mult.sh
+
+This command will launch the 'execute' function for the single-step flow. This
+function is called from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './cmpy_18x18_mult.sh' script.
+
+./cmpy_18x18_mult.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./cmpy_18x18_mult.sh -noclean_files
+
+For more information on the script, please type './cmpy_18x18_mult.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/sim_scripts/cmpy_18x18_mult/ies/cmpy_18x18_mult.sh

@@ -0,0 +1,173 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : cmpy_18x18_mult.sh
+# Simulator   : Cadence Incisive Enterprise Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Sun Jun 11 14:42:06 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: cmpy_18x18_mult.sh [-help]
+# usage: cmpy_18x18_mult.sh [-lib_map_path]
+# usage: cmpy_18x18_mult.sh [-noclean_files]
+# usage: cmpy_18x18_mult.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'cmpy_18x18_mult.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Set the compiled library directory
+ref_lib_dir="."
+
+# Command line options
+irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
+
+# Design libraries
+design_libs=(xbip_utils_v3_0_10 axi_utils_v2_0_6 xbip_pipe_v3_0_6 xbip_bram18k_v3_0_6 mult_gen_v12_0_15 cmpy_v6_0_17 xil_defaultlib)
+
+# Simulation root library directory
+sim_lib_dir="ies_lib"
+
+# Script info
+echo -e "cmpy_18x18_mult.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  execute
+}
+
+# RUN_STEP: <execute>
+execute()
+{
+  irun $irun_opts \
+       -reflib "$ref_lib_dir/unisim:unisim" \
+       -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
+       -reflib "$ref_lib_dir/secureip:secureip" \
+       -reflib "$ref_lib_dir/unimacro:unimacro" \
+       -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
+       -top xil_defaultlib.cmpy_18x18_mult \
+       -f run.f
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./cmpy_18x18_mult.sh -help\" for more information)\n"
+        exit 1
+      else
+        ref_lib_dir=$2
+      fi
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./cmpy_18x18_mult.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: cmpy_18x18_mult.sh [-help]\n\
+Usage: cmpy_18x18_mult.sh [-lib_map_path]\n\
+Usage: cmpy_18x18_mult.sh [-reset_run]\n\
+Usage: cmpy_18x18_mult.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/sim_scripts/cmpy_18x18_mult/ies/file_info.txt

@@ -0,0 +1,7 @@
+xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
+axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
+xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,
+xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd,
+mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd,
+cmpy_v6_0_vh_rfs.vhd,vhdl,cmpy_v6_0_17,../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd,
+cmpy_18x18_mult.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_18x18_mult/sim/cmpy_18x18_mult.vhd,

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/sim_scripts/cmpy_18x18_mult/ies/run.f

@@ -0,0 +1,22 @@
+-makelib ies_lib/xbip_utils_v3_0_10 \
+  "../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
+-endlib
+-makelib ies_lib/axi_utils_v2_0_6 \
+  "../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \
+-endlib
+-makelib ies_lib/xbip_pipe_v3_0_6 \
+  "../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \
+-endlib
+-makelib ies_lib/xbip_bram18k_v3_0_6 \
+  "../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \
+-endlib
+-makelib ies_lib/mult_gen_v12_0_15 \
+  "../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \
+-endlib
+-makelib ies_lib/cmpy_v6_0_17 \
+  "../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../ip/cmpy_18x18_mult/sim/cmpy_18x18_mult.vhd" \
+-endlib
+

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/sim_scripts/cmpy_18x18_mult/modelsim/README.txt

@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Sun Jun 11 14:42:06 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./cmpy_18x18_mult.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './cmpy_18x18_mult.sh' script.
+
+./cmpy_18x18_mult.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./cmpy_18x18_mult.sh -noclean_files
+
+For more information on the script, please type './cmpy_18x18_mult.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/sim_scripts/cmpy_18x18_mult/modelsim/cmpy_18x18_mult.sh

@@ -0,0 +1,168 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : cmpy_18x18_mult.sh
+# Simulator   : Mentor Graphics ModelSim Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Sun Jun 11 14:42:06 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: cmpy_18x18_mult.sh [-help]
+# usage: cmpy_18x18_mult.sh [-lib_map_path]
+# usage: cmpy_18x18_mult.sh [-noclean_files]
+# usage: cmpy_18x18_mult.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'cmpy_18x18_mult.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "cmpy_18x18_mult.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./cmpy_18x18_mult.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+  file="modelsim.ini"
+  lib_map_path="<SPECIFY_COMPILED_LIB_PATH>"
+  if [[ ($1 != "" && -e $1) ]]; then
+    lib_map_path="$1"
+  else
+    echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    cp $src_file .
+  fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+  lib_dir="modelsim_lib"
+  if [[ -e $lib_dir ]]; then
+    rm -rf $lib_dir
+  fi
+
+  mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./cmpy_18x18_mult.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: cmpy_18x18_mult.sh [-help]\n\
+Usage: cmpy_18x18_mult.sh [-lib_map_path]\n\
+Usage: cmpy_18x18_mult.sh [-reset_run]\n\
+Usage: cmpy_18x18_mult.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/sim_scripts/cmpy_18x18_mult/modelsim/compile.do

@@ -0,0 +1,41 @@
+vlib modelsim_lib/work
+vlib modelsim_lib/msim
+
+vlib modelsim_lib/msim/xbip_utils_v3_0_10
+vlib modelsim_lib/msim/axi_utils_v2_0_6
+vlib modelsim_lib/msim/xbip_pipe_v3_0_6
+vlib modelsim_lib/msim/xbip_bram18k_v3_0_6
+vlib modelsim_lib/msim/mult_gen_v12_0_15
+vlib modelsim_lib/msim/cmpy_v6_0_17
+vlib modelsim_lib/msim/xil_defaultlib
+
+vmap xbip_utils_v3_0_10 modelsim_lib/msim/xbip_utils_v3_0_10
+vmap axi_utils_v2_0_6 modelsim_lib/msim/axi_utils_v2_0_6
+vmap xbip_pipe_v3_0_6 modelsim_lib/msim/xbip_pipe_v3_0_6
+vmap xbip_bram18k_v3_0_6 modelsim_lib/msim/xbip_bram18k_v3_0_6
+vmap mult_gen_v12_0_15 modelsim_lib/msim/mult_gen_v12_0_15
+vmap cmpy_v6_0_17 modelsim_lib/msim/cmpy_v6_0_17
+vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
+
+vcom -work xbip_utils_v3_0_10 -64 -93 \
+"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
+
+vcom -work axi_utils_v2_0_6 -64 -93 \
+"../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \
+
+vcom -work xbip_pipe_v3_0_6 -64 -93 \
+"../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \
+
+vcom -work xbip_bram18k_v3_0_6 -64 -93 \
+"../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \
+
+vcom -work mult_gen_v12_0_15 -64 -93 \
+"../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \
+
+vcom -work cmpy_v6_0_17 -64 -93 \
+"../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -64 -93 \
+"../../../ip/cmpy_18x18_mult/sim/cmpy_18x18_mult.vhd" \
+
+

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/sim_scripts/cmpy_18x18_mult/modelsim/file_info.txt

@@ -0,0 +1,7 @@
+xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
+axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
+xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,
+xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd,
+mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd,
+cmpy_v6_0_vh_rfs.vhd,vhdl,cmpy_v6_0_17,../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd,
+cmpy_18x18_mult.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_18x18_mult/sim/cmpy_18x18_mult.vhd,

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/sim_scripts/cmpy_18x18_mult/modelsim/simulate.do

@@ -0,0 +1,16 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -voptargs="+acc" -t 1ps -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L cmpy_v6_0_17 -L xil_defaultlib -L secureip -lib xil_defaultlib xil_defaultlib.cmpy_18x18_mult
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {cmpy_18x18_mult.udo}
+
+run -all
+
+quit -force

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/sim_scripts/cmpy_18x18_mult/modelsim/wave.do

@@ -0,0 +1 @@
+add wave *

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/sim_scripts/cmpy_18x18_mult/questa/README.txt

@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Sun Jun 11 14:42:06 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./cmpy_18x18_mult.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './cmpy_18x18_mult.sh' script.
+
+./cmpy_18x18_mult.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./cmpy_18x18_mult.sh -noclean_files
+
+For more information on the script, please type './cmpy_18x18_mult.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/sim_scripts/cmpy_18x18_mult/questa/cmpy_18x18_mult.sh

@@ -0,0 +1,173 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : cmpy_18x18_mult.sh
+# Simulator   : Mentor Graphics Questa Advanced Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Sun Jun 11 14:42:06 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: cmpy_18x18_mult.sh [-help]
+# usage: cmpy_18x18_mult.sh [-lib_map_path]
+# usage: cmpy_18x18_mult.sh [-noclean_files]
+# usage: cmpy_18x18_mult.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'cmpy_18x18_mult.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "cmpy_18x18_mult.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  source elaborate.do 2>&1 | tee -a elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./cmpy_18x18_mult.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+  file="modelsim.ini"
+  lib_map_path=""
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    cp $src_file .
+  fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+  lib_dir="questa_lib"
+  if [[ -e $lib_dir ]]; then
+    rm -rf $lib_dir
+  fi
+
+  mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./cmpy_18x18_mult.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: cmpy_18x18_mult.sh [-help]\n\
+Usage: cmpy_18x18_mult.sh [-lib_map_path]\n\
+Usage: cmpy_18x18_mult.sh [-reset_run]\n\
+Usage: cmpy_18x18_mult.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/sim_scripts/cmpy_18x18_mult/questa/compile.do

@@ -0,0 +1,41 @@
+vlib questa_lib/work
+vlib questa_lib/msim
+
+vlib questa_lib/msim/xbip_utils_v3_0_10
+vlib questa_lib/msim/axi_utils_v2_0_6
+vlib questa_lib/msim/xbip_pipe_v3_0_6
+vlib questa_lib/msim/xbip_bram18k_v3_0_6
+vlib questa_lib/msim/mult_gen_v12_0_15
+vlib questa_lib/msim/cmpy_v6_0_17
+vlib questa_lib/msim/xil_defaultlib
+
+vmap xbip_utils_v3_0_10 questa_lib/msim/xbip_utils_v3_0_10
+vmap axi_utils_v2_0_6 questa_lib/msim/axi_utils_v2_0_6
+vmap xbip_pipe_v3_0_6 questa_lib/msim/xbip_pipe_v3_0_6
+vmap xbip_bram18k_v3_0_6 questa_lib/msim/xbip_bram18k_v3_0_6
+vmap mult_gen_v12_0_15 questa_lib/msim/mult_gen_v12_0_15
+vmap cmpy_v6_0_17 questa_lib/msim/cmpy_v6_0_17
+vmap xil_defaultlib questa_lib/msim/xil_defaultlib
+
+vcom -work xbip_utils_v3_0_10 -64 -93 \
+"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
+
+vcom -work axi_utils_v2_0_6 -64 -93 \
+"../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \
+
+vcom -work xbip_pipe_v3_0_6 -64 -93 \
+"../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \
+
+vcom -work xbip_bram18k_v3_0_6 -64 -93 \
+"../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \
+
+vcom -work mult_gen_v12_0_15 -64 -93 \
+"../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \
+
+vcom -work cmpy_v6_0_17 -64 -93 \
+"../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -64 -93 \
+"../../../ip/cmpy_18x18_mult/sim/cmpy_18x18_mult.vhd" \
+
+

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/sim_scripts/cmpy_18x18_mult/questa/elaborate.do

@@ -0,0 +1 @@
+vopt -64 +acc -l elaborate.log -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L cmpy_v6_0_17 -L xil_defaultlib -L secureip -work xil_defaultlib xil_defaultlib.cmpy_18x18_mult -o cmpy_18x18_mult_opt

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/sim_scripts/cmpy_18x18_mult/questa/file_info.txt

@@ -0,0 +1,7 @@
+xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
+axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
+xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,
+xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd,
+mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd,
+cmpy_v6_0_vh_rfs.vhd,vhdl,cmpy_v6_0_17,../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd,
+cmpy_18x18_mult.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_18x18_mult/sim/cmpy_18x18_mult.vhd,

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/sim_scripts/cmpy_18x18_mult/questa/simulate.do

@@ -0,0 +1,16 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -t 1ps -lib xil_defaultlib cmpy_18x18_mult_opt
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {cmpy_18x18_mult.udo}
+
+run -all
+
+quit -force

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/sim_scripts/cmpy_18x18_mult/questa/wave.do

@@ -0,0 +1 @@
+add wave *

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/sim_scripts/cmpy_18x18_mult/riviera/README.txt

@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Sun Jun 11 14:42:06 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./cmpy_18x18_mult.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './cmpy_18x18_mult.sh' script.
+
+./cmpy_18x18_mult.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./cmpy_18x18_mult.sh -noclean_files
+
+For more information on the script, please type './cmpy_18x18_mult.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/sim_scripts/cmpy_18x18_mult/riviera/cmpy_18x18_mult.sh

@@ -0,0 +1,152 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : cmpy_18x18_mult.sh
+# Simulator   : Aldec Riviera-PRO Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Sun Jun 11 14:42:06 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: cmpy_18x18_mult.sh [-help]
+# usage: cmpy_18x18_mult.sh [-lib_map_path]
+# usage: cmpy_18x18_mult.sh [-noclean_files]
+# usage: cmpy_18x18_mult.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'cmpy_18x18_mult.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "cmpy_18x18_mult.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./cmpy_18x18_mult.sh -help\" for more information)\n"
+        exit 1
+      fi
+     map_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     map_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Map library.cfg file
+map_setup_file()
+{
+  file="library.cfg"
+  lib_map_path=""
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      vmap -link $lib_map_path
+    fi
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./cmpy_18x18_mult.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: cmpy_18x18_mult.sh [-help]\n\
+Usage: cmpy_18x18_mult.sh [-lib_map_path]\n\
+Usage: cmpy_18x18_mult.sh [-reset_run]\n\
+Usage: cmpy_18x18_mult.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/sim_scripts/cmpy_18x18_mult/riviera/compile.do

@@ -0,0 +1,41 @@
+vlib work
+vlib riviera
+
+vlib riviera/xbip_utils_v3_0_10
+vlib riviera/axi_utils_v2_0_6
+vlib riviera/xbip_pipe_v3_0_6
+vlib riviera/xbip_bram18k_v3_0_6
+vlib riviera/mult_gen_v12_0_15
+vlib riviera/cmpy_v6_0_17
+vlib riviera/xil_defaultlib
+
+vmap xbip_utils_v3_0_10 riviera/xbip_utils_v3_0_10
+vmap axi_utils_v2_0_6 riviera/axi_utils_v2_0_6
+vmap xbip_pipe_v3_0_6 riviera/xbip_pipe_v3_0_6
+vmap xbip_bram18k_v3_0_6 riviera/xbip_bram18k_v3_0_6
+vmap mult_gen_v12_0_15 riviera/mult_gen_v12_0_15
+vmap cmpy_v6_0_17 riviera/cmpy_v6_0_17
+vmap xil_defaultlib riviera/xil_defaultlib
+
+vcom -work xbip_utils_v3_0_10 -93 \
+"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
+
+vcom -work axi_utils_v2_0_6 -93 \
+"../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \
+
+vcom -work xbip_pipe_v3_0_6 -93 \
+"../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \
+
+vcom -work xbip_bram18k_v3_0_6 -93 \
+"../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \
+
+vcom -work mult_gen_v12_0_15 -93 \
+"../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \
+
+vcom -work cmpy_v6_0_17 -93 \
+"../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -93 \
+"../../../ip/cmpy_18x18_mult/sim/cmpy_18x18_mult.vhd" \
+
+

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/sim_scripts/cmpy_18x18_mult/riviera/file_info.txt

@@ -0,0 +1,7 @@
+xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
+axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
+xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,
+xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd,
+mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd,
+cmpy_v6_0_vh_rfs.vhd,vhdl,cmpy_v6_0_17,../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd,
+cmpy_18x18_mult.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_18x18_mult/sim/cmpy_18x18_mult.vhd,

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/sim_scripts/cmpy_18x18_mult/riviera/simulate.do

@@ -0,0 +1,17 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim -t 1ps +access +r +m+cmpy_18x18_mult -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L cmpy_v6_0_17 -L xil_defaultlib -L secureip -O5 xil_defaultlib.cmpy_18x18_mult
+
+do {wave.do}
+
+view wave
+view structure
+
+do {cmpy_18x18_mult.udo}
+
+run -all
+
+endsim
+
+quit -force

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/sim_scripts/cmpy_18x18_mult/riviera/wave.do

@@ -0,0 +1 @@
+add wave *

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/sim_scripts/cmpy_18x18_mult/vcs/README.txt

@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Sun Jun 11 14:42:06 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./cmpy_18x18_mult.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './cmpy_18x18_mult.sh' script.
+
+./cmpy_18x18_mult.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./cmpy_18x18_mult.sh -noclean_files
+
+For more information on the script, please type './cmpy_18x18_mult.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/sim_scripts/cmpy_18x18_mult/vcs/cmpy_18x18_mult.sh

@@ -0,0 +1,241 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : cmpy_18x18_mult.sh
+# Simulator   : Synopsys Verilog Compiler Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Sun Jun 11 14:42:06 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: cmpy_18x18_mult.sh [-help]
+# usage: cmpy_18x18_mult.sh [-lib_map_path]
+# usage: cmpy_18x18_mult.sh [-noclean_files]
+# usage: cmpy_18x18_mult.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'cmpy_18x18_mult.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Command line options
+vlogan_opts="-full64"
+vhdlan_opts="-full64"
+vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log"
+vcs_sim_opts="-ucli -licqueue -l simulate.log"
+
+# Design libraries
+design_libs=(xbip_utils_v3_0_10 axi_utils_v2_0_6 xbip_pipe_v3_0_6 xbip_bram18k_v3_0_6 mult_gen_v12_0_15 cmpy_v6_0_17 xil_defaultlib)
+
+# Simulation root library directory
+sim_lib_dir="vcs_lib"
+
+# Script info
+echo -e "cmpy_18x18_mult.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  vhdlan -work xbip_utils_v3_0_10 $vhdlan_opts \
+    "$ref_dir/../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work axi_utils_v2_0_6 $vhdlan_opts \
+    "$ref_dir/../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work xbip_pipe_v3_0_6 $vhdlan_opts \
+    "$ref_dir/../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work xbip_bram18k_v3_0_6 $vhdlan_opts \
+    "$ref_dir/../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work mult_gen_v12_0_15 $vhdlan_opts \
+    "$ref_dir/../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work cmpy_v6_0_17 $vhdlan_opts \
+    "$ref_dir/../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work xil_defaultlib $vhdlan_opts \
+    "$ref_dir/../../../ip/cmpy_18x18_mult/sim/cmpy_18x18_mult.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  vcs $vcs_elab_opts xil_defaultlib.cmpy_18x18_mult -o cmpy_18x18_mult_simv
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  ./cmpy_18x18_mult_simv $vcs_sim_opts -do simulate.do
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./cmpy_18x18_mult.sh -help\" for more information)\n"
+        exit 1
+      fi
+      create_lib_mappings $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+      create_lib_mappings $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Define design library mappings
+create_lib_mappings()
+{
+  file="synopsys_sim.setup"
+  if [[ -e $file ]]; then
+    if [[ ($1 == "") ]]; then
+      return
+    else
+      rm -rf $file
+    fi
+  fi
+
+  touch $file
+
+  lib_map_path=""
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    mapping="$lib:$sim_lib_dir/$lib"
+    echo $mapping >> $file
+  done
+
+  if [[ ($lib_map_path != "") ]]; then
+    incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup"
+    echo $incl_ref >> $file
+  fi
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(ucli.key cmpy_18x18_mult_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc cmpy_18x18_mult_simv.daidir)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./cmpy_18x18_mult.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: cmpy_18x18_mult.sh [-help]\n\
+Usage: cmpy_18x18_mult.sh [-lib_map_path]\n\
+Usage: cmpy_18x18_mult.sh [-reset_run]\n\
+Usage: cmpy_18x18_mult.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/sim_scripts/cmpy_18x18_mult/vcs/file_info.txt

@@ -0,0 +1,7 @@
+xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
+axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
+xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,
+xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd,
+mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd,
+cmpy_v6_0_vh_rfs.vhd,vhdl,cmpy_v6_0_17,../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd,
+cmpy_18x18_mult.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_18x18_mult/sim/cmpy_18x18_mult.vhd,

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/sim_scripts/cmpy_18x18_mult/vcs/simulate.do

@@ -0,0 +1,2 @@
+run
+quit

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/sim_scripts/cmpy_18x18_mult/xcelium/README.txt

@@ -0,0 +1,48 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Sun Jun 11 14:42:06 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./cmpy_18x18_mult.sh
+
+This command will launch the 'execute' function for the single-step flow. This
+function is called from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './cmpy_18x18_mult.sh' script.
+
+./cmpy_18x18_mult.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./cmpy_18x18_mult.sh -noclean_files
+
+For more information on the script, please type './cmpy_18x18_mult.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/sim_scripts/cmpy_18x18_mult/xcelium/cmpy_18x18_mult.sh

@@ -0,0 +1,173 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : cmpy_18x18_mult.sh
+# Simulator   : Cadence Xcelium Parallel Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Sun Jun 11 14:42:06 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: cmpy_18x18_mult.sh [-help]
+# usage: cmpy_18x18_mult.sh [-lib_map_path]
+# usage: cmpy_18x18_mult.sh [-noclean_files]
+# usage: cmpy_18x18_mult.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'cmpy_18x18_mult.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Set the compiled library directory
+ref_lib_dir="."
+
+# Command line options
+xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
+
+# Design libraries
+design_libs=(xbip_utils_v3_0_10 axi_utils_v2_0_6 xbip_pipe_v3_0_6 xbip_bram18k_v3_0_6 mult_gen_v12_0_15 cmpy_v6_0_17 xil_defaultlib)
+
+# Simulation root library directory
+sim_lib_dir="xcelium_lib"
+
+# Script info
+echo -e "cmpy_18x18_mult.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  execute
+}
+
+# RUN_STEP: <execute>
+execute()
+{
+  xrun $xrun_opts \
+       -reflib "$ref_lib_dir/unisim:unisim" \
+       -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
+       -reflib "$ref_lib_dir/secureip:secureip" \
+       -reflib "$ref_lib_dir/unimacro:unimacro" \
+       -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
+       -top xil_defaultlib.cmpy_18x18_mult \
+       -f run.f
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./cmpy_18x18_mult.sh -help\" for more information)\n"
+        exit 1
+      else
+        ref_lib_dir=$2
+      fi
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./cmpy_18x18_mult.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: cmpy_18x18_mult.sh [-help]\n\
+Usage: cmpy_18x18_mult.sh [-lib_map_path]\n\
+Usage: cmpy_18x18_mult.sh [-reset_run]\n\
+Usage: cmpy_18x18_mult.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/sim_scripts/cmpy_18x18_mult/xcelium/file_info.txt

@@ -0,0 +1,7 @@
+xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
+axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
+xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,
+xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd,
+mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd,
+cmpy_v6_0_vh_rfs.vhd,vhdl,cmpy_v6_0_17,../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd,
+cmpy_18x18_mult.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_18x18_mult/sim/cmpy_18x18_mult.vhd,

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/sim_scripts/cmpy_18x18_mult/xcelium/run.f

@@ -0,0 +1,22 @@
+-makelib xcelium_lib/xbip_utils_v3_0_10 \
+  "../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
+-endlib
+-makelib xcelium_lib/axi_utils_v2_0_6 \
+  "../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \
+-endlib
+-makelib xcelium_lib/xbip_pipe_v3_0_6 \
+  "../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \
+-endlib
+-makelib xcelium_lib/xbip_bram18k_v3_0_6 \
+  "../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \
+-endlib
+-makelib xcelium_lib/mult_gen_v12_0_15 \
+  "../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \
+-endlib
+-makelib xcelium_lib/cmpy_v6_0_17 \
+  "../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  "../../../ip/cmpy_18x18_mult/sim/cmpy_18x18_mult.vhd" \
+-endlib
+

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/sim_scripts/cmpy_18x18_mult/xsim/README.txt

@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Sun Jun 11 14:42:06 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./cmpy_18x18_mult.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './cmpy_18x18_mult.sh' script.
+
+./cmpy_18x18_mult.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./cmpy_18x18_mult.sh -noclean_files
+
+For more information on the script, please type './cmpy_18x18_mult.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/sim_scripts/cmpy_18x18_mult/xsim/cmd.tcl

@@ -0,0 +1,12 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+  if { [llength [get_objects]] > 0} {
+    add_wave /
+    set_property needs_save false [current_wave_config]
+  } else {
+     send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+  }
+}
+
+run -all
+quit

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/sim_scripts/cmpy_18x18_mult/xsim/cmpy_18x18_mult.sh

@@ -0,0 +1,212 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : cmpy_18x18_mult.sh
+# Simulator   : Xilinx Vivado Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Sun Jun 11 14:42:06 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: cmpy_18x18_mult.sh [-help]
+# usage: cmpy_18x18_mult.sh [-lib_map_path]
+# usage: cmpy_18x18_mult.sh [-noclean_files]
+# usage: cmpy_18x18_mult.sh [-reset_run]
+#
+#*********************************************************************************************************
+
+# Command line options
+xv_boost_lib_path=/home/josh/Software/Xilinx/Vivado/2019.1/tps/boost_1_64_0
+xvhdl_opts="--relax"
+
+
+# Script info
+echo -e "cmpy_18x18_mult.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  xvhdl $xvhdl_opts -prj vhdl.prj 2>&1 | tee compile.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  xelab --relax --debug typical --mt auto -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L cmpy_v6_0_17 -L xil_defaultlib -L secureip -L xpm --snapshot cmpy_18x18_mult xil_defaultlib.cmpy_18x18_mult -log elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  xsim cmpy_18x18_mult -key {Behavioral:sim_1:Functional:cmpy_18x18_mult} -tclbatch cmd.tcl -log simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./cmpy_18x18_mult.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy xsim.ini file
+copy_setup_file()
+{
+  file="xsim.ini"
+  lib_map_path="/home/josh/Software/Xilinx/Vivado/2019.1/data/xsim"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      cp $src_file .
+    fi
+
+    # Map local design libraries to xsim.ini
+    map_local_libs
+
+  fi
+}
+
+# Map local design libraries
+map_local_libs()
+{
+  updated_mappings=()
+  local_mappings=()
+
+  # Local design libraries
+  local_libs=()
+
+  if [[ 0 == ${#local_libs[@]} ]]; then
+    return
+  fi
+
+  file="xsim.ini"
+  file_backup="xsim.ini.bak"
+
+  if [[ -e $file ]]; then
+    rm -f $file_backup
+    # Create a backup copy of the xsim.ini file
+    cp $file $file_backup
+    # Read libraries from backup file and search in local library collection
+    while read -r line
+    do
+      IN=$line
+      # Split mapping entry with '=' delimiter to fetch library name and mapping
+      read lib_name mapping <<<$(IFS="="; echo $IN)
+      # If local library found, then construct the local mapping and add to local mapping collection
+      if `echo ${local_libs[@]} | grep -wq $lib_name` ; then
+        line="$lib_name=xsim.dir/$lib_name"
+        local_mappings+=("$lib_name")
+      fi
+      # Add to updated library mapping collection
+      updated_mappings+=("$line")
+    done < "$file_backup"
+    # Append local libraries not found originally from xsim.ini
+    for (( i=0; i<${#local_libs[*]}; i++ )); do
+      lib_name="${local_libs[i]}"
+      if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then
+        line="$lib_name=xsim.dir/$lib_name"
+        updated_mappings+=("$line")
+      fi
+    done
+    # Write updated mappings in xsim.ini
+    rm -f $file
+    for (( i=0; i<${#updated_mappings[*]}; i++ )); do
+      lib_name="${updated_mappings[i]}"
+      echo $lib_name >> $file
+    done
+  else
+    for (( i=0; i<${#local_libs[*]}; i++ )); do
+      lib_name="${local_libs[i]}"
+      mapping="$lib_name=xsim.dir/$lib_name"
+      echo $mapping >> $file
+    done
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb cmpy_18x18_mult.wdb xsim.dir)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./cmpy_18x18_mult.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: cmpy_18x18_mult.sh [-help]\n\
+Usage: cmpy_18x18_mult.sh [-lib_map_path]\n\
+Usage: cmpy_18x18_mult.sh [-reset_run]\n\
+Usage: cmpy_18x18_mult.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/sim_scripts/cmpy_18x18_mult/xsim/file_info.txt

@@ -0,0 +1 @@
+cmpy_18x18_mult.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_18x18_mult/sim/cmpy_18x18_mult.vhd,

modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/sim_scripts/cmpy_18x18_mult/xsim/vhdl.prj

@@ -0,0 +1,4 @@
+vhdl xil_defaultlib  \
+"../../../ip/cmpy_18x18_mult/sim/cmpy_18x18_mult.vhd" \
+
+nosort

modules/xc7k410tffg900-2/var_cal/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/7ceac1c5ccccf5df/7ceac1c5ccccf5df.xci

@@ -0,0 +1,62 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>ipcache</spirit:library>
+  <spirit:name>7ceac1c5ccccf5df</spirit:name>
+  <spirit:version>0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>cmpy_18x18_mult</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="cmpy" spirit:version="6.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.FREQ_HZ">10000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.APortWidth">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARESETN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ATUSERWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BPortWidth">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BTUSERWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CTRLTUSERWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">cmpy_18x18_mult</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FlowControl">NonBlocking</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HasATLAST">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HasATUSER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HasBTLAST">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HasBTUSER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HasCTRLTLAST">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HasCTRLTUSER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LatencyConfig">Automatic</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MinimumLatency">6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MultType">Use_Mults</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OptimizeGoal">Resources</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OutTLASTBehv">Null</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OutputWidth">37</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RoundMode">Truncate</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">7ceac1c5ccccf5df</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">c296bec2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">17</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>

modules/xc7k410tffg900-2/var_cal/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/7ceac1c5ccccf5df/cmpy_18x18_mult_stub.v

@@ -0,0 +1,27 @@
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
+// Date        : Sun Jun 11 14:40:37 2023
+// Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
+// Command     : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ cmpy_18x18_mult_stub.v
+// Design      : cmpy_18x18_mult
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7k410tffg900-2
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "cmpy_v6_0_17,Vivado 2019.1.3" *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, s_axis_a_tvalid, s_axis_a_tdata, 
+  s_axis_b_tvalid, s_axis_b_tdata, m_axis_dout_tvalid, m_axis_dout_tdata)
+/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_a_tvalid,s_axis_a_tdata[47:0],s_axis_b_tvalid,s_axis_b_tdata[47:0],m_axis_dout_tvalid,m_axis_dout_tdata[79:0]" */;
+  input aclk;
+  input s_axis_a_tvalid;
+  input [47:0]s_axis_a_tdata;
+  input s_axis_b_tvalid;
+  input [47:0]s_axis_b_tdata;
+  output m_axis_dout_tvalid;
+  output [79:0]m_axis_dout_tdata;
+endmodule

modules/xc7k410tffg900-2/var_cal/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/7ceac1c5ccccf5df/cmpy_18x18_mult_stub.vhdl

@@ -0,0 +1,36 @@
+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
+-- Date        : Sun Jun 11 14:40:37 2023
+-- Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
+-- Command     : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+--               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ cmpy_18x18_mult_stub.vhdl
+-- Design      : cmpy_18x18_mult
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7k410tffg900-2
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
+  Port ( 
+    aclk : in STD_LOGIC;
+    s_axis_a_tvalid : in STD_LOGIC;
+    s_axis_a_tdata : in STD_LOGIC_VECTOR ( 47 downto 0 );
+    s_axis_b_tvalid : in STD_LOGIC;
+    s_axis_b_tdata : in STD_LOGIC_VECTOR ( 47 downto 0 );
+    m_axis_dout_tvalid : out STD_LOGIC;
+    m_axis_dout_tdata : out STD_LOGIC_VECTOR ( 79 downto 0 )
+  );
+
+end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
+
+architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_a_tvalid,s_axis_a_tdata[47:0],s_axis_b_tvalid,s_axis_b_tdata[47:0],m_axis_dout_tvalid,m_axis_dout_tdata[79:0]";
+attribute x_core_info : string;
+attribute x_core_info of stub : architecture is "cmpy_v6_0_17,Vivado 2019.1.3";
+begin
+end;

modules/xc7k410tffg900-2/var_cal/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf

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modules/xc7k410tffg900-2/var_cal/ip/managed_ip_project/managed_ip_project.cache/wt/java_command_handlers.wdf

@@ -0,0 +1,7 @@
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modules/xc7k410tffg900-2/var_cal/ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc

@@ -0,0 +1,3 @@
+version:1
+6d6f64655f636f756e7465727c4755494d6f6465:2
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modules/xc7k410tffg900-2/var_cal/ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf

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modules/xc7k410tffg900-2/var_cal/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml

@@ -0,0 +1,55 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<document>
+<!--The data in this file is primarily intended for consumption by Xilinx tools.
+The structure and the elements are likely to change over the next few releases.
+This means code written to parse this file will need to be revisited each subsequent release.-->
+<application name="pa" timeStamp="Sun Jun 11 14:42:15 2023">
+<section name="Project Information" visible="false">
+<property name="ProjectID" value="2ee901c2f78f4976b486c1628de6e6c5" type="ProjectID"/>
+<property name="ProjectIteration" value="1" type="ProjectIteration"/>
+</section>
+<section name="PlanAhead Usage" visible="true">
+<item name="Project Data">
+<property name="SrcSetCount" value="1" type="SrcSetCount"/>
+<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
+<property name="DesignMode" value="RTL" type="DesignMode"/>
+<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
+<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
+</item>
+<item name="Java Command Handlers">
+<property name="CloseProject" value="2" type="JavaHandler"/>
+<property name="CustomizeCore" value="1" type="JavaHandler"/>
+<property name="NewIPLocationHandler" value="1" type="JavaHandler"/>
+<property name="OpenPreviousIPHandler" value="1" type="JavaHandler"/>
+<property name="ToolsSettings" value="1" type="JavaHandler"/>
+</item>
+<item name="Gui Handlers">
+<property name="BaseDialog_OK" value="5" type="GuiHandlerData"/>
+<property name="CoreTreeTablePanel_CORE_TREE_TABLE" value="3" type="GuiHandlerData"/>
+<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="2" type="GuiHandlerData"/>
+<property name="FPGAChooser_FPGA_TABLE" value="1" type="GuiHandlerData"/>
+<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="2" type="GuiHandlerData"/>
+<property name="GettingStartedView_MANAGE_IP" value="1" type="GuiHandlerData"/>
+<property name="GettingStartedView_START_USING_VIVADO_WITH_IP_CATALOG" value="1" type="GuiHandlerData"/>
+<property name="MainMenuMgr_FILE" value="4" type="GuiHandlerData"/>
+<property name="MainMenuMgr_PROJECT" value="2" type="GuiHandlerData"/>
+<property name="MainMenuMgr_TOOLS" value="2" type="GuiHandlerData"/>
+<property name="NewIPProjectWizard_IP_LOCATION" value="1" type="GuiHandlerData"/>
+<property name="NewIPProjectWizard_PART" value="1" type="GuiHandlerData"/>
+<property name="PACommandNames_CLOSE_PROJECT" value="2" type="GuiHandlerData"/>
+<property name="RDICommands_CUSTOM_COMMANDS" value="1" type="GuiHandlerData"/>
+<property name="RDICommands_SETTINGS" value="1" type="GuiHandlerData"/>
+<property name="SettingsDialog_PROJECT_TREE" value="1" type="GuiHandlerData"/>
+<property name="SettingsProjectIPPage_USE_CORE_CONTAINERS_FOR_IP" value="1" type="GuiHandlerData"/>
+<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="1" type="GuiHandlerData"/>
+<property name="SrcMenu_IP_DOCUMENTATION" value="2" type="GuiHandlerData"/>
+<property name="SyntheticaGettingStartedView_RECENT_IP_LOCATIONS" value="1" type="GuiHandlerData"/>
+</item>
+<item name="Other">
+<property name="GuiMode" value="10" type="GuiMode"/>
+<property name="BatchMode" value="0" type="BatchMode"/>
+<property name="TclMode" value="6" type="TclMode"/>
+</item>
+</section>
+</application>
+</document>

modules/xc7k410tffg900-2/var_cal/ip/managed_ip_project/managed_ip_project.hw/managed_ip_project.lpr

@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2019.1.3 (64-bit)                   -->
+<!--                                                              -->
+<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.        -->
+
+<labtools version="1" minor="0"/>

modules/xc7k410tffg900-2/var_cal/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_1.xml

@@ -0,0 +1,8 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="cmpy_18x18_mult_synth_1" LaunchDir="/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x18_mult_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+

modules/xc7k410tffg900-2/var_cal/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x18_mult_synth_1/.vivado.begin.rst

@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+    <Process Command="vivado" Owner="josh" Host="JOSH-ASUS-Z690" Pid="2190314" HostCore="20" HostMemory="65588992">
+    </Process>
+</ProcessHandle>

modules/xc7k410tffg900-2/var_cal/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x18_mult_synth_1/ISEWrap.js

@@ -0,0 +1,270 @@
+//
+//  Vivado(TM)
+//  ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
+//  Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. 
+//
+
+// GLOBAL VARIABLES
+var ISEShell = new ActiveXObject( "WScript.Shell" );
+var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
+var ISERunDir = "";
+var ISELogFile = "runme.log";
+var ISELogFileStr = null;
+var ISELogEcho = true;
+var ISEOldVersionWSH = false;
+
+
+
+// BOOTSTRAP
+ISEInit();
+
+
+
+//
+// ISE FUNCTIONS
+//
+function ISEInit() {
+
+  // 1. RUN DIR setup
+  var ISEScrFP = WScript.ScriptFullName;
+  var ISEScrN = WScript.ScriptName;
+  ISERunDir = 
+    ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
+
+  // 2. LOG file setup
+  ISELogFileStr = ISEOpenFile( ISELogFile );
+
+  // 3. LOG echo?
+  var ISEScriptArgs = WScript.Arguments;
+  for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
+    if ( ISEScriptArgs(loopi) == "-quiet" ) {
+      ISELogEcho = false;
+      break;
+    }
+  }
+
+  // 4. WSH version check
+  var ISEOptimalVersionWSH = 5.6;
+  var ISECurrentVersionWSH = WScript.Version;
+  if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
+
+    ISEStdErr( "" );
+    ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
+	       ISEOptimalVersionWSH + " or higher. Downloads" );
+    ISEStdErr( "         for upgrading your Windows Scripting Host can be found here: " );
+    ISEStdErr( "             http://msdn.microsoft.com/downloads/list/webdev.asp" );
+    ISEStdErr( "" );
+
+    ISEOldVersionWSH = true;
+  }
+
+}
+
+function ISEStep( ISEProg, ISEArgs ) {
+
+  // CHECK for a STOP FILE
+  if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
+    ISEStdErr( "" );
+    ISEStdErr( "*** Halting run - EA reset detected ***" );
+    ISEStdErr( "" );
+    WScript.Quit( 1 );
+  }
+
+  // WRITE STEP HEADER to LOG
+  ISEStdOut( "" );
+  ISEStdOut( "*** Running " + ISEProg );
+  ISEStdOut( "    with args " + ISEArgs );
+  ISEStdOut( "" );
+
+  // LAUNCH!
+  var ISEExitCode = ISEExec( ISEProg, ISEArgs );  
+  if ( ISEExitCode != 0 ) {
+    WScript.Quit( ISEExitCode );
+  }
+
+}
+
+function ISEExec( ISEProg, ISEArgs ) {
+
+  var ISEStep = ISEProg;
+  if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
+    ISEProg += ".bat";
+  }
+
+  var ISECmdLine = ISEProg + " " + ISEArgs;
+  var ISEExitCode = 1;
+
+  if ( ISEOldVersionWSH ) { // WSH 5.1
+
+    // BEGIN file creation
+    ISETouchFile( ISEStep, "begin" );
+
+    // LAUNCH!
+    ISELogFileStr.Close();
+    ISECmdLine = 
+      "%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
+    ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
+    ISELogFileStr = ISEOpenFile( ISELogFile );
+
+  } else {  // WSH 5.6
+
+    // LAUNCH!
+    ISEShell.CurrentDirectory = ISERunDir;
+
+    // Redirect STDERR to STDOUT
+    ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
+    var ISEProcess = ISEShell.Exec( ISECmdLine );
+    
+    // BEGIN file creation
+    var wbemFlagReturnImmediately = 0x10;
+    var wbemFlagForwardOnly = 0x20;
+    var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
+    var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
+    var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
+    var NOC = 0;
+    var NOLP = 0;
+    var TPM = 0;
+
+    var cpuInfos = new Enumerator(processor);
+    for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
+        var cpuInfo = cpuInfos.item();
+        NOC += cpuInfo.NumberOfCores;
+        NOLP += cpuInfo.NumberOfLogicalProcessors;
+    }
+    var csInfos = new Enumerator(computerSystem);
+    for(;!csInfos.atEnd(); csInfos.moveNext()) {
+        var csInfo = csInfos.item();
+        TPM += csInfo.TotalPhysicalMemory;
+    }
+
+    var ISEHOSTCORE = NOLP
+    var ISEMEMTOTAL = TPM
+
+    var ISENetwork = WScript.CreateObject( "WScript.Network" );
+    var ISEHost = ISENetwork.ComputerName;
+    var ISEUser = ISENetwork.UserName;
+    var ISEPid = ISEProcess.ProcessID;
+    var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
+    ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
+    ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
+    ISEBeginFile.WriteLine( "    <Process Command=\"" + ISEProg + 
+			    "\" Owner=\"" + ISEUser + 
+			    "\" Host=\"" + ISEHost + 
+			    "\" Pid=\"" + ISEPid +
+			    "\" HostCore=\"" + ISEHOSTCORE +
+			    "\" HostMemory=\"" + ISEMEMTOTAL +
+			    "\">" );
+    ISEBeginFile.WriteLine( "    </Process>" );
+    ISEBeginFile.WriteLine( "</ProcessHandle>" );
+    ISEBeginFile.Close();
+    
+    var ISEOutStr = ISEProcess.StdOut;
+    var ISEErrStr = ISEProcess.StdErr;
+    
+    // WAIT for ISEStep to finish
+    while ( ISEProcess.Status == 0 ) {
+      
+      // dump stdout then stderr - feels a little arbitrary
+      while ( !ISEOutStr.AtEndOfStream ) {
+        ISEStdOut( ISEOutStr.ReadLine() );
+      }  
+      
+      WScript.Sleep( 100 );
+    }
+
+    ISEExitCode = ISEProcess.ExitCode;
+  }
+
+  ISELogFileStr.Close();
+
+  // END/ERROR file creation
+  if ( ISEExitCode != 0 ) {    
+    ISETouchFile( ISEStep, "error" );
+    
+  } else {
+    ISETouchFile( ISEStep, "end" );
+  }
+
+  return ISEExitCode;
+}
+
+
+//
+// UTILITIES
+//
+function ISEStdOut( ISELine ) {
+
+  ISELogFileStr.WriteLine( ISELine );
+  
+  if ( ISELogEcho ) {
+    WScript.StdOut.WriteLine( ISELine );
+  }
+}
+
+function ISEStdErr( ISELine ) {
+  
+  ISELogFileStr.WriteLine( ISELine );
+
+  if ( ISELogEcho ) {
+    WScript.StdErr.WriteLine( ISELine );
+  }
+}
+
+function ISETouchFile( ISERoot, ISEStatus ) {
+
+  var ISETFile = 
+    ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
+  ISETFile.Close();
+}
+
+function ISEOpenFile( ISEFilename ) {
+
+  // This function has been updated to deal with a problem seen in CR #870871.
+  // In that case the user runs a script that runs impl_1, and then turns around
+  // and runs impl_1 -to_step write_bitstream. That second run takes place in
+  // the same directory, which means we may hit some of the same files, and in
+  // particular, we will open the runme.log file. Even though this script closes
+  // the file (now), we see cases where a subsequent attempt to open the file
+  // fails. Perhaps the OS is slow to release the lock, or the disk comes into
+  // play? In any case, we try to work around this by first waiting if the file
+  // is already there for an arbitrary 5 seconds. Then we use a try-catch block
+  // and try to open the file 10 times with a one second delay after each attempt.
+  // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
+  // If there is an unrecognized exception when trying to open the file, we output
+  // an error message and write details to an exception.log file.
+  var ISEFullPath = ISERunDir + "/" + ISEFilename;
+  if (ISEFileSys.FileExists(ISEFullPath)) {
+    // File is already there. This could be a problem. Wait in case it is still in use.
+    WScript.Sleep(5000);
+  }
+  var i;
+  for (i = 0; i < 10; ++i) {
+    try {
+      return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
+    } catch (exception) {
+      var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
+      if (error_code == 52) { // 52 is bad file name or number.
+        // Wait a second and try again.
+        WScript.Sleep(1000);
+        continue;
+      } else {
+        WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+        var exceptionFilePath = ISERunDir + "/exception.log";
+        if (!ISEFileSys.FileExists(exceptionFilePath)) {
+          WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
+          var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
+          exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+          exceptionFile.WriteLine("\tException name: " + exception.name);
+          exceptionFile.WriteLine("\tException error code: " + error_code);
+          exceptionFile.WriteLine("\tException message: " + exception.message);
+          exceptionFile.Close();
+        }
+        throw exception;
+      }
+    }
+  }
+  // If we reached this point, we failed to open the file after 10 attempts.
+  // We need to error out.
+  WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
+  WScript.Quit(1);
+}

modules/xc7k410tffg900-2/var_cal/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x18_mult_synth_1/ISEWrap.sh

@@ -0,0 +1,67 @@
+#!/bin/sh
+
+#
+#  Vivado(TM)
+#  ISEWrap.sh: Vivado Runs Script for UNIX
+#  Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. 
+#
+
+HD_LOG=$1
+shift
+
+# CHECK for a STOP FILE
+if [ -f .stop.rst ]
+then
+echo ""                                        >> $HD_LOG
+echo "*** Halting run - EA reset detected ***" >> $HD_LOG
+echo ""                                        >> $HD_LOG
+exit 1
+fi
+
+ISE_STEP=$1
+shift
+
+# WRITE STEP HEADER to LOG
+echo ""                      >> $HD_LOG
+echo "*** Running $ISE_STEP" >> $HD_LOG
+echo "    with args $@"      >> $HD_LOG
+echo ""                      >> $HD_LOG
+
+# LAUNCH!
+$ISE_STEP "$@" >> $HD_LOG 2>&1 &
+
+# BEGIN file creation
+ISE_PID=$!
+if [ X != X$HOSTNAME ]
+then
+ISE_HOST=$HOSTNAME #bash
+else
+ISE_HOST=$HOST     #csh
+fi
+ISE_USER=$USER
+
+ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
+ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
+
+ISE_BEGINFILE=.$ISE_STEP.begin.rst
+/bin/touch $ISE_BEGINFILE
+echo "<?xml version=\"1.0\"?>"                                                                     >> $ISE_BEGINFILE
+echo "<ProcessHandle Version=\"1\" Minor=\"0\">"                                                   >> $ISE_BEGINFILE
+echo "    <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
+echo "    </Process>"                                                                              >> $ISE_BEGINFILE
+echo "</ProcessHandle>"                                                                            >> $ISE_BEGINFILE
+
+# WAIT for ISEStep to finish
+wait $ISE_PID
+
+# END/ERROR file creation
+RETVAL=$?
+if [ $RETVAL -eq 0 ]
+then
+    /bin/touch .$ISE_STEP.end.rst
+else
+    /bin/touch .$ISE_STEP.error.rst
+fi
+
+exit $RETVAL
+

modules/xc7k410tffg900-2/var_cal/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x18_mult_synth_1/cmpy_18x18_mult.tcl

@@ -0,0 +1,169 @@
+# 
+# Synthesis run script generated by Vivado
+# 
+
+set TIME_start [clock seconds] 
+proc create_report { reportName command } {
+  set status "."
+  append status $reportName ".fail"
+  if { [file exists $status] } {
+    eval file delete [glob $status]
+  }
+  send_msg_id runtcl-4 info "Executing : $command"
+  set retval [eval catch { $command } msg]
+  if { $retval != 0 } {
+    set fp [open $status w]
+    close $fp
+    send_msg_id runtcl-5 warning "$msg"
+  }
+}
+set_param project.vivado.isBlockSynthRun true
+set_msg_config -msgmgr_mode ooc_run
+create_project -in_memory -part xc7k410tffg900-2
+
+set_param project.singleFileAddWarning.threshold 0
+set_param project.compositeFile.enableAutoGeneration 0
+set_param synth.vivado.isSynthRun true
+set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
+set_property webtalk.parent_dir /home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/managed_ip_project/managed_ip_project.cache/wt [current_project]
+set_property parent.project_path /home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/managed_ip_project/managed_ip_project.xpr [current_project]
+set_property default_lib xil_defaultlib [current_project]
+set_property target_language Verilog [current_project]
+set_property ip_output_repo /home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/managed_ip_project/managed_ip_project.cache/ip [current_project]
+set_property ip_cache_permissions {read write} [current_project]
+read_ip -quiet /home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/cmpy_18x18_mult/cmpy_18x18_mult.xci
+set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/cmpy_18x18_mult/cmpy_18x18_mult_ooc.xdc]
+
+# Mark all dcp files as not used in implementation to prevent them from being
+# stitched into the results of this synthesis run. Any black boxes in the
+# design are intentionally left as such for best results. Dcp files will be
+# stitched into the design at a later time, either when this synthesis run is
+# opened, or when it is stitched into a dependent implementation run.
+foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
+  set_property used_in_implementation false $dcp
+}
+read_xdc dont_touch.xdc
+set_property used_in_implementation false [get_files dont_touch.xdc]
+set_param ips.enableIPCacheLiteLoad 1
+
+set cached_ip [config_ip_cache -export -no_bom  -dir /home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x18_mult_synth_1 -new_name cmpy_18x18_mult -ip [get_ips cmpy_18x18_mult]]
+
+if { $cached_ip eq {} } {
+close [open __synthesis_is_running__ w]
+
+synth_design -top cmpy_18x18_mult -part xc7k410tffg900-2 -mode out_of_context
+
+#---------------------------------------------------------
+# Generate Checkpoint/Stub/Simulation Files For IP Cache
+#---------------------------------------------------------
+# disable binary constraint mode for IPCache checkpoints
+set_param constraints.enableBinaryConstraints false
+
+catch {
+ write_checkpoint -force -noxdef -rename_prefix cmpy_18x18_mult_ cmpy_18x18_mult.dcp
+
+ set ipCachedFiles {}
+ write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ cmpy_18x18_mult_stub.v
+ lappend ipCachedFiles cmpy_18x18_mult_stub.v
+
+ write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ cmpy_18x18_mult_stub.vhdl
+ lappend ipCachedFiles cmpy_18x18_mult_stub.vhdl
+
+ write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ cmpy_18x18_mult_sim_netlist.v
+ lappend ipCachedFiles cmpy_18x18_mult_sim_netlist.v
+
+ write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ cmpy_18x18_mult_sim_netlist.vhdl
+ lappend ipCachedFiles cmpy_18x18_mult_sim_netlist.vhdl
+set TIME_taken [expr [clock seconds] - $TIME_start]
+
+ config_ip_cache -add -dcp cmpy_18x18_mult.dcp -move_files $ipCachedFiles -use_project_ipc  -synth_runtime $TIME_taken  -ip [get_ips cmpy_18x18_mult]
+}
+
+rename_ref -prefix_all cmpy_18x18_mult_
+
+# disable binary constraint mode for synth run checkpoints
+set_param constraints.enableBinaryConstraints false
+write_checkpoint -force -noxdef cmpy_18x18_mult.dcp
+create_report "cmpy_18x18_mult_synth_1_synth_report_utilization_0" "report_utilization -file cmpy_18x18_mult_utilization_synth.rpt -pb cmpy_18x18_mult_utilization_synth.pb"
+
+if { [catch {
+  file copy -force /home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x18_mult_synth_1/cmpy_18x18_mult.dcp /home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/cmpy_18x18_mult/cmpy_18x18_mult.dcp
+} _RESULT ] } { 
+  send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
+  error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
+}
+
+if { [catch {
+  write_verilog -force -mode synth_stub /home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/cmpy_18x18_mult/cmpy_18x18_mult_stub.v
+} _RESULT ] } { 
+  puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
+}
+
+if { [catch {
+  write_vhdl -force -mode synth_stub /home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/cmpy_18x18_mult/cmpy_18x18_mult_stub.vhdl
+} _RESULT ] } { 
+  puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
+}
+
+if { [catch {
+  write_verilog -force -mode funcsim /home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/cmpy_18x18_mult/cmpy_18x18_mult_sim_netlist.v
+} _RESULT ] } { 
+  puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
+}
+
+if { [catch {
+  write_vhdl -force -mode funcsim /home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/cmpy_18x18_mult/cmpy_18x18_mult_sim_netlist.vhdl
+} _RESULT ] } { 
+  puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
+}
+
+
+} else {
+
+
+if { [catch {
+  file copy -force /home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x18_mult_synth_1/cmpy_18x18_mult.dcp /home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/cmpy_18x18_mult/cmpy_18x18_mult.dcp
+} _RESULT ] } { 
+  send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
+  error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
+}
+
+if { [catch {
+  file rename -force /home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x18_mult_synth_1/cmpy_18x18_mult_stub.v /home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/cmpy_18x18_mult/cmpy_18x18_mult_stub.v
+} _RESULT ] } { 
+  puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
+}
+
+if { [catch {
+  file rename -force /home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x18_mult_synth_1/cmpy_18x18_mult_stub.vhdl /home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/cmpy_18x18_mult/cmpy_18x18_mult_stub.vhdl
+} _RESULT ] } { 
+  puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
+}
+
+if { [catch {
+  file rename -force /home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x18_mult_synth_1/cmpy_18x18_mult_sim_netlist.v /home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/cmpy_18x18_mult/cmpy_18x18_mult_sim_netlist.v
+} _RESULT ] } { 
+  puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
+}
+
+if { [catch {
+  file rename -force /home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x18_mult_synth_1/cmpy_18x18_mult_sim_netlist.vhdl /home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/cmpy_18x18_mult/cmpy_18x18_mult_sim_netlist.vhdl
+} _RESULT ] } { 
+  puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
+}
+
+}; # end if cached_ip 
+
+if {[file isdir /home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/ip/cmpy_18x18_mult]} {
+  catch { 
+    file copy -force /home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/cmpy_18x18_mult/cmpy_18x18_mult_stub.v /home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/ip/cmpy_18x18_mult
+  }
+}
+
+if {[file isdir /home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/ip/cmpy_18x18_mult]} {
+  catch { 
+    file copy -force /home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/cmpy_18x18_mult/cmpy_18x18_mult_stub.vhdl /home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/ip_user_files/ip/cmpy_18x18_mult
+  }
+}
+file delete __synthesis_is_running__
+close [open __synthesis_is_complete__ w]

modules/xc7k410tffg900-2/var_cal/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x18_mult_synth_1/cmpy_18x18_mult.vds

@@ -0,0 +1,467 @@
+#-----------------------------------------------------------
+# Vivado v2019.1.3 (64-bit)
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+# IP Build 2633630 on Wed Sep  4 12:30:14 MDT 2019
+# Start of session at: Sun Jun 11 14:40:18 2023
+# Process ID: 2190353
+# Current directory: /home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x18_mult_synth_1
+# Command line: vivado -log cmpy_18x18_mult.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source cmpy_18x18_mult.tcl
+# Log file: /home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x18_mult_synth_1/cmpy_18x18_mult.vds
+# Journal file: /home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x18_mult_synth_1/vivado.jou
+#-----------------------------------------------------------
+source cmpy_18x18_mult.tcl -notrace
+Command: synth_design -top cmpy_18x18_mult -part xc7k410tffg900-2 -mode out_of_context
+Starting synth_design
+Attempting to get a license for feature 'Synthesis' and/or device 'xc7k410t'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k410t'
+INFO: [Device 21-403] Loading part xc7k410tffg900-2
+INFO: Launching helper process for spawning children vivado processes
+INFO: Helper process launched with PID 2190385 
+---------------------------------------------------------------------------------
+Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1825.012 ; gain = 152.719 ; free physical = 2583 ; free virtual = 42035
+---------------------------------------------------------------------------------
+INFO: [Synth 8-638] synthesizing module 'cmpy_18x18_mult' [/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/cmpy_18x18_mult/synth/cmpy_18x18_mult.vhd:71]
+	Parameter C_VERBOSITY bound to: 0 - type: integer 
+	Parameter C_XDEVICEFAMILY bound to: kintex7 - type: string 
+	Parameter C_XDEVICE bound to: xc7k410t - type: string 
+	Parameter C_A_WIDTH bound to: 18 - type: integer 
+	Parameter C_B_WIDTH bound to: 18 - type: integer 
+	Parameter C_OUT_WIDTH bound to: 37 - type: integer 
+	Parameter C_LATENCY bound to: 6 - type: integer 
+	Parameter C_MULT_TYPE bound to: 1 - type: integer 
+	Parameter C_OPTIMIZE_GOAL bound to: 0 - type: integer 
+	Parameter HAS_NEGATE bound to: 0 - type: integer 
+	Parameter SINGLE_OUTPUT bound to: 0 - type: integer 
+	Parameter ROUND bound to: 0 - type: integer 
+	Parameter USE_DSP_CASCADES bound to: 1 - type: integer 
+	Parameter C_THROTTLE_SCHEME bound to: 3 - type: integer 
+	Parameter C_HAS_ACLKEN bound to: 0 - type: integer 
+	Parameter C_HAS_ARESETN bound to: 0 - type: integer 
+	Parameter C_HAS_S_AXIS_A_TUSER bound to: 0 - type: integer 
+	Parameter C_HAS_S_AXIS_A_TLAST bound to: 0 - type: integer 
+	Parameter C_HAS_S_AXIS_B_TUSER bound to: 0 - type: integer 
+	Parameter C_HAS_S_AXIS_B_TLAST bound to: 0 - type: integer 
+	Parameter C_HAS_S_AXIS_CTRL_TUSER bound to: 0 - type: integer 
+	Parameter C_HAS_S_AXIS_CTRL_TLAST bound to: 0 - type: integer 
+	Parameter C_TLAST_RESOLUTION bound to: 0 - type: integer 
+	Parameter C_S_AXIS_A_TDATA_WIDTH bound to: 48 - type: integer 
+	Parameter C_S_AXIS_A_TUSER_WIDTH bound to: 1 - type: integer 
+	Parameter C_S_AXIS_B_TDATA_WIDTH bound to: 48 - type: integer 
+	Parameter C_S_AXIS_B_TUSER_WIDTH bound to: 1 - type: integer 
+	Parameter C_S_AXIS_CTRL_TDATA_WIDTH bound to: 8 - type: integer 
+	Parameter C_S_AXIS_CTRL_TUSER_WIDTH bound to: 1 - type: integer 
+	Parameter C_M_AXIS_DOUT_TDATA_WIDTH bound to: 80 - type: integer 
+	Parameter C_M_AXIS_DOUT_TUSER_WIDTH bound to: 1 - type: integer 
+INFO: [Synth 8-3491] module 'cmpy_v6_0_17' declared at '/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/cmpy_18x18_mult/hdl/cmpy_v6_0_vh_rfs.vhd:13922' bound to instance 'U0' of component 'cmpy_v6_0_17' [/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/cmpy_18x18_mult/synth/cmpy_18x18_mult.vhd:155]
+INFO: [Synth 8-256] done synthesizing module 'cmpy_18x18_mult' (11#1) [/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/cmpy_18x18_mult/synth/cmpy_18x18_mult.vhd:71]
+WARNING: [Synth 8-3331] design mult_gen_v12_0_15_delay_line__parameterized1 has unconnected port CLK
+WARNING: [Synth 8-3331] design mult_gen_v12_0_15_delay_line__parameterized1 has unconnected port CE
+WARNING: [Synth 8-3331] design mult_gen_v12_0_15_delay_line__parameterized1 has unconnected port SCLR
+WARNING: [Synth 8-3331] design mult_gen_v12_0_15_delay_line__parameterized0 has unconnected port CE
+WARNING: [Synth 8-3331] design mult_gen_v12_0_15_delay_line__parameterized0 has unconnected port SCLR
+WARNING: [Synth 8-3331] design mult_gen_v12_0_15_delay_line has unconnected port CE
+WARNING: [Synth 8-3331] design mult_gen_v12_0_15_delay_line has unconnected port SCLR
+WARNING: [Synth 8-3331] design dsp__parameterized1 has unconnected port SUBTRACT
+WARNING: [Synth 8-3331] design dsp__parameterized1 has unconnected port CARRY_IN
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_delay_line__parameterized3 has unconnected port CLK
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_delay_line__parameterized3 has unconnected port CE
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_delay_line__parameterized3 has unconnected port SCLR
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_delay_line__parameterized2 has unconnected port CE
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_delay_line__parameterized2 has unconnected port SCLR
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_delay_line__parameterized1 has unconnected port CLK
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_delay_line__parameterized1 has unconnected port CE
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_delay_line__parameterized1 has unconnected port SCLR
+WARNING: [Synth 8-3331] design mult_gen_v12_0_15_delay_line__parameterized3 has unconnected port CLK
+WARNING: [Synth 8-3331] design mult_gen_v12_0_15_delay_line__parameterized3 has unconnected port CE
+WARNING: [Synth 8-3331] design mult_gen_v12_0_15_delay_line__parameterized3 has unconnected port SCLR
+WARNING: [Synth 8-3331] design mult_gen_v12_0_15_delay_line__parameterized2 has unconnected port CLK
+WARNING: [Synth 8-3331] design mult_gen_v12_0_15_delay_line__parameterized2 has unconnected port CE
+WARNING: [Synth 8-3331] design mult_gen_v12_0_15_delay_line__parameterized2 has unconnected port SCLR
+WARNING: [Synth 8-3331] design dsp__parameterized0 has unconnected port SUBTRACT
+WARNING: [Synth 8-3331] design dsp__parameterized0 has unconnected port CARRY_IN
+WARNING: [Synth 8-3331] design dsp has unconnected port CARRY_IN
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_delay_line__parameterized4 has unconnected port CLK
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_delay_line__parameterized4 has unconnected port CE
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_delay_line__parameterized4 has unconnected port SCLR
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_delay_line__parameterized0 has unconnected port CLK
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_delay_line__parameterized0 has unconnected port CE
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_delay_line__parameterized0 has unconnected port SCLR
+WARNING: [Synth 8-3331] design input_negation has unconnected port NEGATE_R
+WARNING: [Synth 8-3331] design input_negation has unconnected port NEGATE_I
+WARNING: [Synth 8-3331] design input_negation has unconnected port CLK
+WARNING: [Synth 8-3331] design input_negation has unconnected port CE
+WARNING: [Synth 8-3331] design input_negation has unconnected port SCLR
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_synth has unconnected port CE
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_synth has unconnected port SCLR
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_synth has unconnected port ROUND_CY
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_synth has unconnected port SO_START
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_delay_line has unconnected port SCLR
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port aclken
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port aresetn
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tuser[0]
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tlast
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[47]
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[46]
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[45]
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[44]
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[43]
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[42]
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[23]
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[22]
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[21]
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[20]
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[19]
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[18]
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_b_tuser[0]
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_b_tlast
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_b_tdata[47]
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_b_tdata[46]
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_b_tdata[45]
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_b_tdata[44]
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_b_tdata[43]
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_b_tdata[42]
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_b_tdata[23]
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_b_tdata[22]
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_b_tdata[21]
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_b_tdata[20]
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_b_tdata[19]
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_b_tdata[18]
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tvalid
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tuser[0]
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tlast
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[7]
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[6]
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[5]
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[4]
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[3]
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[2]
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[1]
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[0]
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port m_axis_dout_tready
+---------------------------------------------------------------------------------
+Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1947.762 ; gain = 275.469 ; free physical = 2639 ; free virtual = 42094
+---------------------------------------------------------------------------------
+
+Report Check Netlist: 
++------+------------------+-------+---------+-------+------------------+
+|      |Item              |Errors |Warnings |Status |Description       |
++------+------------------+-------+---------+-------+------------------+
+|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
++------+------------------+-------+---------+-------+------------------+
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1947.762 ; gain = 275.469 ; free physical = 2640 ; free virtual = 42094
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1947.762 ; gain = 275.469 ; free physical = 2640 ; free virtual = 42094
+---------------------------------------------------------------------------------
+INFO: [Netlist 29-17] Analyzing 3 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-570] Preparing netlist for logic optimization
+
+Processing XDC Constraints
+Initializing timing engine
+Parsing XDC File [/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/cmpy_18x18_mult/cmpy_18x18_mult_ooc.xdc] for cell 'U0'
+Finished Parsing XDC File [/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/cmpy_18x18_mult/cmpy_18x18_mult_ooc.xdc] for cell 'U0'
+Parsing XDC File [/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x18_mult_synth_1/dont_touch.xdc]
+Finished Parsing XDC File [/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x18_mult_synth_1/dont_touch.xdc]
+Completed Processing XDC Constraints
+
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2048.512 ; gain = 0.000 ; free physical = 2533 ; free virtual = 41988
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2048.512 ; gain = 0.000 ; free physical = 2533 ; free virtual = 41988
+---------------------------------------------------------------------------------
+Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 2048.512 ; gain = 376.219 ; free physical = 2603 ; free virtual = 42059
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Loading Part and Timing Information
+---------------------------------------------------------------------------------
+Loading part: xc7k410tffg900-2
+---------------------------------------------------------------------------------
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 2048.512 ; gain = 376.219 ; free physical = 2603 ; free virtual = 42059
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying 'set_property' XDC Constraints
+---------------------------------------------------------------------------------
+Applied set_property DONT_TOUCH = true for U0. (constraint file  /home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x18_mult_synth_1/dont_touch.xdc, line 9).
+---------------------------------------------------------------------------------
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 2048.512 ; gain = 376.219 ; free physical = 2603 ; free virtual = 42059
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2048.512 ; gain = 376.219 ; free physical = 2605 ; free virtual = 42062
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start RTL Component Statistics 
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Component Statistics 
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start RTL Hierarchical Component Statistics 
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Hierarchical Component Statistics
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Part Resource Summary
+---------------------------------------------------------------------------------
+Part Resources:
+DSPs: 1540 (col length:140)
+BRAMs: 1590 (col length: RAMB18 140 RAMB36 70)
+---------------------------------------------------------------------------------
+Finished Part Resource Summary
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Cross Boundary and Area Optimization
+---------------------------------------------------------------------------------
+Warning: Parallel synthesis criteria is not met 
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port aclken
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port aresetn
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tuser[0]
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tlast
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[47]
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[46]
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[45]
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[44]
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[43]
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[42]
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[23]
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[22]
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[21]
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[20]
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[19]
+WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[18]
+INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][17]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][24]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][18]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][24]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][19]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][24]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][20]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][24]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][21]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][24]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][22]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][24]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][23]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][24]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[0]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[0]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[1]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[1]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[2]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[2]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[3]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[3]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[4]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[4]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[5]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[5]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[6]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[6]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[7]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[7]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[8]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[8]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[9]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[9]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[10]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[10]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[11]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[11]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[12]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[12]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[13]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[13]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[14]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[14]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[15]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[15]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[16]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[16]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[17]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[18]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[18]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[19]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[19]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[20]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[20]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[21]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[21]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[22]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[22]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[23]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[23]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[24]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[24]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[24]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][0]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][0]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][1]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][1]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][2]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][2]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][3]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][3]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][4]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][4]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][5]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][5]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][6]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][6]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][7]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][7]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][8]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][8]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][9]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][9]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][10]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][10]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][11]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][11]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][12]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][12]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][13]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][13]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][14]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][14]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][15]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][15]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][16]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][16]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][17]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][18]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][19]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][20]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][21]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][22]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][23]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][24]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[17]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[24]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[18]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[24]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[19]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[24]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[20]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[24]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[21]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[24]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[22]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[24]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[23]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[24]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][17]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][18]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][19]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][20]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][21]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][22]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
+INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][24]'
+---------------------------------------------------------------------------------
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2048.512 ; gain = 376.219 ; free physical = 2608 ; free virtual = 42068
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start Applying XDC Timing Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2048.512 ; gain = 376.219 ; free physical = 2463 ; free virtual = 41924
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Timing Optimization
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Timing Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2048.512 ; gain = 376.219 ; free physical = 2462 ; free virtual = 41924
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start Technology Mapping
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Technology Mapping : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2048.512 ; gain = 376.219 ; free physical = 2457 ; free virtual = 41918
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished IO Insertion : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 2048.512 ; gain = 376.219 ; free physical = 2457 ; free virtual = 41918
+---------------------------------------------------------------------------------
+
+Report Check Netlist: 
++------+------------------+-------+---------+-------+------------------+
+|      |Item              |Errors |Warnings |Status |Description       |
++------+------------------+-------+---------+-------+------------------+
+|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
++------+------------------+-------+---------+-------+------------------+
+---------------------------------------------------------------------------------
+Start Renaming Generated Instances
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 2048.512 ; gain = 376.219 ; free physical = 2457 ; free virtual = 41918
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start Rebuilding User Hierarchy
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 2048.512 ; gain = 376.219 ; free physical = 2457 ; free virtual = 41918
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Ports
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 2048.512 ; gain = 376.219 ; free physical = 2457 ; free virtual = 41918
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 2048.512 ; gain = 376.219 ; free physical = 2457 ; free virtual = 41918
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Nets
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 2048.512 ; gain = 376.219 ; free physical = 2457 ; free virtual = 41918
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Writing Synthesis Report
+---------------------------------------------------------------------------------
+
+Report BlackBoxes: 
++-+--------------+----------+
+| |BlackBox name |Instances |
++-+--------------+----------+
++-+--------------+----------+
+
+Report Cell Usage: 
++------+----------+------+
+|      |Cell      |Count |
++------+----------+------+
+|1     |DSP48E1   |     2|
+|2     |DSP48E1_1 |     1|
+|3     |LUT2      |     1|
+|4     |SRL16E    |    37|
+|5     |FDRE      |    92|
++------+----------+------+
+---------------------------------------------------------------------------------
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 2048.512 ; gain = 376.219 ; free physical = 2457 ; free virtual = 41918
+---------------------------------------------------------------------------------
+Synthesis finished with 0 errors, 0 critical warnings and 42 warnings.
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 2048.512 ; gain = 275.469 ; free physical = 2521 ; free virtual = 41983
+Synthesis Optimization Complete : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 2048.512 ; gain = 376.219 ; free physical = 2521 ; free virtual = 41983
+INFO: [Project 1-571] Translating synthesized netlist
+INFO: [Netlist 29-17] Analyzing 3 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2048.512 ; gain = 0.000 ; free physical = 2465 ; free virtual = 41926
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+INFO: [Common 17-83] Releasing license: Synthesis
+88 Infos, 100 Warnings, 0 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2048.512 ; gain = 654.051 ; free physical = 2553 ; free virtual = 42015
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2048.512 ; gain = 0.000 ; free physical = 2553 ; free virtual = 42015
+WARNING: [Constraints 18-5210] No constraints selected for write.
+Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
+INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x18_mult_synth_1/cmpy_18x18_mult.dcp' has been generated.
+WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used.
+INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP cmpy_18x18_mult, cache-ID = 7ceac1c5ccccf5df
+INFO: [Coretcl 2-1174] Renamed 16 cell refs.
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2048.512 ; gain = 0.000 ; free physical = 2551 ; free virtual = 42013
+WARNING: [Constraints 18-5210] No constraints selected for write.
+Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
+INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x18_mult_synth_1/cmpy_18x18_mult.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_utilization -file cmpy_18x18_mult_utilization_synth.rpt -pb cmpy_18x18_mult_utilization_synth.pb
+INFO: [Common 17-206] Exiting Vivado at Sun Jun 11 14:40:37 2023...

modules/xc7k410tffg900-2/var_cal/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x18_mult_synth_1/cmpy_18x18_mult_utilization_synth.rpt

@@ -0,0 +1,179 @@
+Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
+| Date         : Sun Jun 11 14:40:37 2023
+| Host         : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
+| Command      : report_utilization -file cmpy_18x18_mult_utilization_synth.rpt -pb cmpy_18x18_mult_utilization_synth.pb
+| Design       : cmpy_18x18_mult
+| Device       : 7k410tffg900-2
+| Design State : Synthesized
+-------------------------------------------------------------------------------------------------------------------------
+
+Utilization Design Information
+
+Table of Contents
+-----------------
+1. Slice Logic
+1.1 Summary of Registers by Type
+2. Memory
+3. DSP
+4. IO and GT Specific
+5. Clocking
+6. Specific Feature
+7. Primitives
+8. Black Boxes
+9. Instantiated Netlists
+
+1. Slice Logic
+--------------
+
++----------------------------+------+-------+-----------+-------+
+|          Site Type         | Used | Fixed | Available | Util% |
++----------------------------+------+-------+-----------+-------+
+| Slice LUTs*                |   38 |     0 |    254200 |  0.01 |
+|   LUT as Logic             |    1 |     0 |    254200 | <0.01 |
+|   LUT as Memory            |   37 |     0 |     90600 |  0.04 |
+|     LUT as Distributed RAM |    0 |     0 |           |       |
+|     LUT as Shift Register  |   37 |     0 |           |       |
+| Slice Registers            |   92 |     0 |    508400 |  0.02 |
+|   Register as Flip Flop    |   92 |     0 |    508400 |  0.02 |
+|   Register as Latch        |    0 |     0 |    508400 |  0.00 |
+| F7 Muxes                   |    0 |     0 |    127100 |  0.00 |
+| F8 Muxes                   |    0 |     0 |     63550 |  0.00 |
++----------------------------+------+-------+-----------+-------+
+* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
+
+
+1.1 Summary of Registers by Type
+--------------------------------
+
++-------+--------------+-------------+--------------+
+| Total | Clock Enable | Synchronous | Asynchronous |
++-------+--------------+-------------+--------------+
+| 0     |            _ |           - |            - |
+| 0     |            _ |           - |          Set |
+| 0     |            _ |           - |        Reset |
+| 0     |            _ |         Set |            - |
+| 0     |            _ |       Reset |            - |
+| 0     |          Yes |           - |            - |
+| 0     |          Yes |           - |          Set |
+| 0     |          Yes |           - |        Reset |
+| 0     |          Yes |         Set |            - |
+| 92    |          Yes |       Reset |            - |
++-------+--------------+-------------+--------------+
+
+
+2. Memory
+---------
+
++----------------+------+-------+-----------+-------+
+|    Site Type   | Used | Fixed | Available | Util% |
++----------------+------+-------+-----------+-------+
+| Block RAM Tile |    0 |     0 |       795 |  0.00 |
+|   RAMB36/FIFO* |    0 |     0 |       795 |  0.00 |
+|   RAMB18       |    0 |     0 |      1590 |  0.00 |
++----------------+------+-------+-----------+-------+
+* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
+
+
+3. DSP
+------
+
++----------------+------+-------+-----------+-------+
+|    Site Type   | Used | Fixed | Available | Util% |
++----------------+------+-------+-----------+-------+
+| DSPs           |    3 |     0 |      1540 |  0.19 |
+|   DSP48E1 only |    3 |       |           |       |
++----------------+------+-------+-----------+-------+
+
+
+4. IO and GT Specific
+---------------------
+
++-----------------------------+------+-------+-----------+-------+
+|          Site Type          | Used | Fixed | Available | Util% |
++-----------------------------+------+-------+-----------+-------+
+| Bonded IOB                  |    0 |     0 |       500 |  0.00 |
+| Bonded IPADs                |    0 |     0 |        50 |  0.00 |
+| Bonded OPADs                |    0 |     0 |        32 |  0.00 |
+| PHY_CONTROL                 |    0 |     0 |        10 |  0.00 |
+| PHASER_REF                  |    0 |     0 |        10 |  0.00 |
+| OUT_FIFO                    |    0 |     0 |        40 |  0.00 |
+| IN_FIFO                     |    0 |     0 |        40 |  0.00 |
+| IDELAYCTRL                  |    0 |     0 |        10 |  0.00 |
+| IBUFDS                      |    0 |     0 |       480 |  0.00 |
+| GTXE2_COMMON                |    0 |     0 |         4 |  0.00 |
+| GTXE2_CHANNEL               |    0 |     0 |        16 |  0.00 |
+| PHASER_OUT/PHASER_OUT_PHY   |    0 |     0 |        40 |  0.00 |
+| PHASER_IN/PHASER_IN_PHY     |    0 |     0 |        40 |  0.00 |
+| IDELAYE2/IDELAYE2_FINEDELAY |    0 |     0 |       500 |  0.00 |
+| ODELAYE2/ODELAYE2_FINEDELAY |    0 |     0 |       150 |  0.00 |
+| IBUFDS_GTE2                 |    0 |     0 |         8 |  0.00 |
+| ILOGIC                      |    0 |     0 |       500 |  0.00 |
+| OLOGIC                      |    0 |     0 |       500 |  0.00 |
++-----------------------------+------+-------+-----------+-------+
+
+
+5. Clocking
+-----------
+
++------------+------+-------+-----------+-------+
+|  Site Type | Used | Fixed | Available | Util% |
++------------+------+-------+-----------+-------+
+| BUFGCTRL   |    0 |     0 |        32 |  0.00 |
+| BUFIO      |    0 |     0 |        40 |  0.00 |
+| MMCME2_ADV |    0 |     0 |        10 |  0.00 |
+| PLLE2_ADV  |    0 |     0 |        10 |  0.00 |
+| BUFMRCE    |    0 |     0 |        20 |  0.00 |
+| BUFHCE     |    0 |     0 |       168 |  0.00 |
+| BUFR       |    0 |     0 |        40 |  0.00 |
++------------+------+-------+-----------+-------+
+
+
+6. Specific Feature
+-------------------
+
++-------------+------+-------+-----------+-------+
+|  Site Type  | Used | Fixed | Available | Util% |
++-------------+------+-------+-----------+-------+
+| BSCANE2     |    0 |     0 |         4 |  0.00 |
+| CAPTUREE2   |    0 |     0 |         1 |  0.00 |
+| DNA_PORT    |    0 |     0 |         1 |  0.00 |
+| EFUSE_USR   |    0 |     0 |         1 |  0.00 |
+| FRAME_ECCE2 |    0 |     0 |         1 |  0.00 |
+| ICAPE2      |    0 |     0 |         2 |  0.00 |
+| PCIE_2_1    |    0 |     0 |         1 |  0.00 |
+| STARTUPE2   |    0 |     0 |         1 |  0.00 |
+| XADC        |    0 |     0 |         1 |  0.00 |
++-------------+------+-------+-----------+-------+
+
+
+7. Primitives
+-------------
+
++----------+------+---------------------+
+| Ref Name | Used | Functional Category |
++----------+------+---------------------+
+| FDRE     |   92 |        Flop & Latch |
+| SRL16E   |   37 |  Distributed Memory |
+| DSP48E1  |    3 |    Block Arithmetic |
+| LUT2     |    1 |                 LUT |
++----------+------+---------------------+
+
+
+8. Black Boxes
+--------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
+9. Instantiated Netlists
+------------------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+

modules/xc7k410tffg900-2/var_cal/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x18_mult_synth_1/dont_touch.xdc

@@ -0,0 +1,16 @@
+# This file is automatically generated.
+# It contains project source information necessary for synthesis and implementation.
+
+# IP: /home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/cmpy_18x18_mult/cmpy_18x18_mult.xci
+# IP: The module: 'cmpy_18x18_mult' is the root of the design. Do not add the DONT_TOUCH constraint.
+
+# XDC: /home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/cmpy_18x18_mult/cmpy_18x18_mult_ooc.xdc
+# XDC: The top module name and the constraint reference have the same name: 'cmpy_18x18_mult'. Do not add the DONT_TOUCH constraint.
+set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet
+
+# IP: /home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/cmpy_18x18_mult/cmpy_18x18_mult.xci
+# IP: The module: 'cmpy_18x18_mult' is the root of the design. Do not add the DONT_TOUCH constraint.
+
+# XDC: /home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/cmpy_18x18_mult/cmpy_18x18_mult_ooc.xdc
+# XDC: The top module name and the constraint reference have the same name: 'cmpy_18x18_mult'. Do not add the DONT_TOUCH constraint.
+#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet

modules/xc7k410tffg900-2/var_cal/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x18_mult_synth_1/gen_run.xml

@@ -0,0 +1,45 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<GenRun Id="cmpy_18x18_mult_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1686465618">
+  <File Type="RDS-UTIL-PB" Name="cmpy_18x18_mult_utilization_synth.pb"/>
+  <File Type="RDS-UTIL" Name="cmpy_18x18_mult_utilization_synth.rpt"/>
+  <File Type="RDS-RDS" Name="cmpy_18x18_mult.vds"/>
+  <File Type="RDS-DCP" Name="cmpy_18x18_mult.dcp"/>
+  <File Type="PA-TCL" Name="cmpy_18x18_mult.tcl"/>
+  <File Type="REPORTS-TCL" Name="cmpy_18x18_mult_reports.tcl"/>
+  <FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/cmpy_18x18_mult">
+    <File Path="$PPRDIR/../cmpy_18x18_mult/cmpy_18x18_mult.xci">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="TopModule" Val="cmpy_18x18_mult"/>
+      <Option Name="UseBlackboxStub" Val="1"/>
+    </Config>
+  </FileSet>
+  <FileSet Name="constrs_in" Type="BlockSrcs" RelSrcDir="$PSRCDIR/cmpy_18x18_mult">
+    <File Path="$PPRDIR/../cmpy_18x18_mult/cmpy_18x18_mult.xci">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="TopModule" Val="cmpy_18x18_mult"/>
+      <Option Name="UseBlackboxStub" Val="1"/>
+    </Config>
+  </FileSet>
+  <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
+    <Filter Type="Utils"/>
+    <Config>
+      <Option Name="TopAutoSet" Val="TRUE"/>
+    </Config>
+  </FileSet>
+  <Strategy Version="1" Minor="2">
+    <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
+    <Step Id="synth_design"/>
+  </Strategy>
+</GenRun>

modules/xc7k410tffg900-2/var_cal/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x18_mult_synth_1/htr.txt

@@ -0,0 +1,9 @@
+#
+# Vivado(TM)
+# htr.txt: a Vivado-generated description of how-to-repeat the
+#          the basic steps of a run.  Note that runme.bat/sh needs
+#          to be invoked for Vivado to track run status.
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+#
+
+vivado -log cmpy_18x18_mult.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source cmpy_18x18_mult.tcl

modules/xc7k410tffg900-2/var_cal/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x18_mult_synth_1/project.wdf

@@ -0,0 +1,32 @@
+version:1
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:30:00:00
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+eof:2002839254

modules/xc7k410tffg900-2/var_cal/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x18_mult_synth_1/rundef.js

@@ -0,0 +1,40 @@
+//
+// Vivado(TM)
+// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+//
+
+echo "This script was generated under a different operating system."
+echo "Please update the PATH variable below, before executing this script"
+exit
+
+var WshShell = new ActiveXObject( "WScript.Shell" );
+var ProcEnv = WshShell.Environment( "Process" );
+var PathVal = ProcEnv("PATH");
+if ( PathVal.length == 0 ) {
+  PathVal = "/home/josh/Software/Xilinx/SDK/2019.1/bin:/home/josh/Software/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/home/josh/Software/Xilinx/Vivado/2019.1/bin;";
+} else {
+  PathVal = "/home/josh/Software/Xilinx/SDK/2019.1/bin:/home/josh/Software/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/home/josh/Software/Xilinx/Vivado/2019.1/bin;" + PathVal;
+}
+
+ProcEnv("PATH") = PathVal;
+
+var RDScrFP = WScript.ScriptFullName;
+var RDScrN = WScript.ScriptName;
+var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
+var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
+eval( EAInclude(ISEJScriptLib) );
+
+
+ISEStep( "vivado",
+         "-log cmpy_18x18_mult.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source cmpy_18x18_mult.tcl" );
+
+
+
+function EAInclude( EAInclFilename ) {
+  var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
+  var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
+  var EAIFContents = EAInclFile.ReadAll();
+  EAInclFile.Close();
+  return EAIFContents;
+}

modules/xc7k410tffg900-2/var_cal/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x18_mult_synth_1/runme.bat

@@ -0,0 +1,11 @@
+@echo off
+
+rem  Vivado (TM)
+rem  runme.bat: a Vivado-generated Script
+rem  Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+
+
+set HD_SDIR=%~dp0
+cd /d "%HD_SDIR%"
+set PATH=%SYSTEMROOT%\system32;%PATH%
+cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*

modules/xc7k410tffg900-2/var_cal/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x18_mult_synth_1/runme.sh

@@ -0,0 +1,39 @@
+#!/bin/sh
+
+# 
+# Vivado(TM)
+# runme.sh: a Vivado-generated Runs Script for UNIX
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+# 
+
+if [ -z "$PATH" ]; then
+  PATH=/home/josh/Software/Xilinx/SDK/2019.1/bin:/home/josh/Software/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/home/josh/Software/Xilinx/Vivado/2019.1/bin
+else
+  PATH=/home/josh/Software/Xilinx/SDK/2019.1/bin:/home/josh/Software/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/home/josh/Software/Xilinx/Vivado/2019.1/bin:$PATH
+fi
+export PATH
+
+if [ -z "$LD_LIBRARY_PATH" ]; then
+  LD_LIBRARY_PATH=
+else
+  LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
+fi
+export LD_LIBRARY_PATH
+
+HD_PWD='/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x18_mult_synth_1'
+cd "$HD_PWD"
+
+HD_LOG=runme.log
+/bin/touch $HD_LOG
+
+ISEStep="./ISEWrap.sh"
+EAStep()
+{
+     $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
+     if [ $? -ne 0 ]
+     then
+         exit
+     fi
+}
+
+EAStep vivado -log cmpy_18x18_mult.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source cmpy_18x18_mult.tcl

modules/xc7k410tffg900-2/var_cal/ip/managed_ip_project/managed_ip_project.xpr

@@ -0,0 +1,241 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2019.1.3 (64-bit)              -->
+<!--                                                         -->
+<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.   -->
+
+<Project Version="7" Minor="40" Path="/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/managed_ip_project/managed_ip_project.xpr">
+  <DefaultLaunch Dir="$PRUNDIR"/>
+  <Configuration>
+    <Option Name="Id" Val="3affc23807f54e3d898d10bc07b7ab4d"/>
+    <Option Name="Part" Val="xc7k410tffg900-2"/>
+    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+    <Option Name="CompiledLibDirXSim" Val=""/>
+    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+    <Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
+    <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+    <Option Name="BoardPart" Val=""/>
+    <Option Name="SourceMgmtMode" Val="None"/>
+    <Option Name="ActiveSimSet" Val="sim_1"/>
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>
+    <Option Name="ProjectType" Val="Managed_IP"/>
+    <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+    <Option Name="IPCachePermission" Val="read"/>
+    <Option Name="IPCachePermission" Val="write"/>
+    <Option Name="EnableCoreContainer" Val="TRUE"/>
+    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+    <Option Name="IPUserFilesDir" Val="$PPRDIR/../ip_user_files"/>
+    <Option Name="IPStaticSourceDir" Val="$PPRDIR/../ip_user_files/ipstatic"/>
+    <Option Name="EnableBDX" Val="FALSE"/>
+    <Option Name="DSAVendor" Val="xilinx"/>
+    <Option Name="DSANumComputeUnits" Val="60"/>
+    <Option Name="WTXSimLaunchSim" Val="0"/>
+    <Option Name="WTModelSimLaunchSim" Val="0"/>
+    <Option Name="WTQuestaLaunchSim" Val="0"/>
+    <Option Name="WTIesLaunchSim" Val="0"/>
+    <Option Name="WTVcsLaunchSim" Val="0"/>
+    <Option Name="WTRivieraLaunchSim" Val="0"/>
+    <Option Name="WTActivehdlLaunchSim" Val="0"/>
+    <Option Name="WTXSimExportSim" Val="2"/>
+    <Option Name="WTModelSimExportSim" Val="2"/>
+    <Option Name="WTQuestaExportSim" Val="2"/>
+    <Option Name="WTIesExportSim" Val="2"/>
+    <Option Name="WTVcsExportSim" Val="2"/>
+    <Option Name="WTRivieraExportSim" Val="2"/>
+    <Option Name="WTActivehdlExportSim" Val="2"/>
+    <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+    <Option Name="XSimRadix" Val="hex"/>
+    <Option Name="XSimTimeUnit" Val="ns"/>
+    <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+    <Option Name="XSimTraceLimit" Val="65536"/>
+    <Option Name="SimTypes" Val="rtl"/>
+    <Option Name="SimTypes" Val="bfm"/>
+    <Option Name="SimTypes" Val="tlm"/>
+    <Option Name="SimTypes" Val="tlm_dpi"/>
+    <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+  </Configuration>
+  <FileSets Version="1" Minor="31">
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
+      <Filter Type="Srcs"/>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <Config>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
+      <Filter Type="Srcs"/>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
+      <Filter Type="Utils"/>
+      <Config>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="cmpy_18x18_mult" Type="BlockSrcs" RelSrcDir="$PSRCDIR/cmpy_18x18_mult">
+      <File Path="$PPRDIR/../cmpy_18x18_mult.xcix">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../cmpy_18x18_mult/cmpy_18x18_mult.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="cmpy_18x18_mult"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="Questa">
+      <Option Name="Description" Val="Questa Advanced Simulator"/>
+    </Simulator>
+    <Simulator Name="IES">
+      <Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
+    </Simulator>
+    <Simulator Name="Xcelium">
+      <Option Name="Description" Val="Xcelium Parallel Simulator"/>
+    </Simulator>
+    <Simulator Name="VCS">
+      <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+    </Simulator>
+    <Simulator Name="Riviera">
+      <Option Name="Description" Val="Riviera-PRO Simulator"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="10">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7k410tffg900-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+    </Run>
+    <Run Id="cmpy_18x18_mult_synth_1" Type="Ft3:Synth" SrcSet="cmpy_18x18_mult" Part="xc7k410tffg900-2" ConstrsSet="cmpy_18x18_mult" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/cmpy_18x18_mult_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+    </Run>
+    <Run Id="cmpy_18x18_mult_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="cmpy_18x18_mult" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="cmpy_18x18_mult_synth_1" IncludeInArchive="false" GenFullBitstream="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+    </Run>
+  </Runs>
+  <Board/>
+  <DashboardSummary Version="1" Minor="0">
+    <Dashboards>
+      <Dashboard Name="default_dashboard">
+        <Gadgets>
+          <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+          </Gadget>
+          <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+          </Gadget>
+          <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+          </Gadget>
+          <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+          </Gadget>
+          <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+            <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+            <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+          </Gadget>
+          <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+          </Gadget>
+        </Gadgets>
+      </Dashboard>
+      <CurrentDashboard>default_dashboard</CurrentDashboard>
+    </Dashboards>
+  </DashboardSummary>
+  <BootPmcSettings Version="1" Minor="0">
+    <Parameters>
+      <Parameter Name="PMC_CDO.ATTRS.LOADADDR" Value="" Type="string"/>
+      <Parameter Name="BOOT.PMC.QSPI_ENABLE" Value="0" Type="string"/>
+      <Parameter Name="BOOT.PMC.QSPI_FB_CLK" Value="0" Type="string"/>
+      <Parameter Name="BOOT.PMC.QSPI_FREQ" Value="300" Type="string"/>
+      <Parameter Name="BOOT.PMC.QSPI_BUS_WIDTH" Value="x1" Type="string"/>
+      <Parameter Name="BOOT.PMC.QSPI_DATA_MODE" Value="Single" Type="string"/>
+      <Parameter Name="BOOT.PMC.SD0_ENABLE" Value="0" Type="string"/>
+      <Parameter Name="BOOT.PMC.SD0_FREQ" Value="200" Type="string"/>
+      <Parameter Name="BOOT.PMC.SD0_SLOT_TYPE" Value="SD 2.0" Type="string"/>
+      <Parameter Name="BOOT.PMC.SD0_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
+      <Parameter Name="BOOT.PMC.SD1_ENABLE" Value="0" Type="string"/>
+      <Parameter Name="BOOT.PMC.SD1_FREQ" Value="200" Type="string"/>
+      <Parameter Name="BOOT.PMC.SD1_SLOT_TYPE" Value="SD 2.0" Type="string"/>
+      <Parameter Name="BOOT.PMC.SD1_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
+      <Parameter Name="BOOT.PMC.OSPI_ENABLE" Value="0" Type="string"/>
+      <Parameter Name="BOOT.PMC.OSPI_FREQ" Value="300" Type="string"/>
+      <Parameter Name="BOOT.USB_ENABLE" Value="0" Type="string"/>
+      <Parameter Name="BOOT.PMC.SMAP_ENABLE" Value="0" Type="string"/>
+      <Parameter Name="BOOT.PMC.SMAP_DATA_WIDTH" Value="32 Bit" Type="string"/>
+      <Parameter Name="BOOT.PMC.OSC_FREQ" Value="33.333" Type="string"/>
+      <Parameter Name="BOOT.SECONDARY.PCIE_ENABLE" Value="0" Type="string"/>
+    </Parameters>
+  </BootPmcSettings>
+</Project>

modules/xc7k410tffg900-2/var_cal/rtl/var_cal.v

@@ -0,0 +1,212 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//      _           _        ____
+//     | | ___  ___| |__    / ___| __ _  ___
+//  _  | |/ _ \/ __| '_ \  | |  _ / _` |/ _ \
+// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
+//  \___/ \___/|___/_| |_|  \____|\__,_|\___/
+//
+// Create Date: 06/11/2023 02:41:47 PM
+// Design Name:
+// Module Name: var_cal
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module var_cal
+#(
+    parameter ACCUM_NUM = 16384,
+    parameter DATA_I_WIDTH = 30,
+    parameter DATA_O_WIDTH = 32,
+    parameter CMPY_WIDTH = 18
+)
+(
+    input clk                           ,
+    input rst                           ,
+
+    input cal_start                     ,
+    input cal_auto_en                   ,
+    output cal_busy                     ,
+
+    input din_valid                     ,
+    input [DATA_I_WIDTH-1 : 0] din_real ,
+    input [DATA_I_WIDTH-1 : 0] din_imag ,
+
+    output var_valid                    ,
+    output [DATA_O_WIDTH-1 : 0] var
+);
+
+integer i;
+
+localparam CMPY_VALID_WIDTH = CMPY_WIDTH-1; // 17-bit valid data to protect cmpy from overflow
+localparam DATA_MULT_FULL_WIDTH = 2*CMPY_VALID_WIDTH+1;
+localparam DATA_MULT_VALID_WIDTH = 2*CMPY_VALID_WIDTH;
+localparam AXIS_DATA_I_WIDTH = 8*((CMPY_VALID_WIDTH-1)/8+1)    ; // axis data width of input real/image data
+localparam AXIS_DATA_P_WIDTH = 8*((DATA_MULT_FULL_WIDTH-1)/8+1); // axis data width of cmpy output real/image data
+
+// status control
+reg cal_start_auto = 'b0;
+reg cal_start_d1 = 'b0;
+reg cal_start_d2 = 'b0;
+reg cal_busy_buf = 'b0;
+reg [$clog2(ACCUM_NUM)-1 : 0] cnt_accum = 'b0;
+reg last_data = 'b0;
+reg last_data_d [0:6]; // 6 for cmpy, 1 for register output
+
+assign cal_busy = cal_busy_buf;
+assign var_valid = last_data_d[6];
+
+always @(posedge clk) begin
+    if (rst) begin
+        cal_start_auto <= 'b0;
+    end
+    else begin
+        if (~cal_busy_buf) begin
+            cal_start_auto = ~cal_start_auto;
+        end
+        else begin
+            cal_start_auto <= cal_start_auto;
+        end
+    end
+end
+
+always @(posedge clk) begin
+    cal_start_d1 <= cal_auto_en ? cal_start_auto : cal_start;
+    cal_start_d2 <= cal_start_d1;
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        cal_busy_buf <= 'b0;
+    end
+    else begin
+        if ((cal_start_d1 ^ cal_start_d2) && din_valid) begin
+            cal_busy_buf <= 1'b1;
+        end
+        else if (cnt_accum == ACCUM_NUM-1) begin
+            cal_busy_buf <= 'b0;
+        end
+        else begin
+            cal_busy_buf <= cal_busy_buf;
+        end
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        cnt_accum <= 'b0;
+    end
+    else begin
+        cnt_accum <= cal_busy ? (cnt_accum + 1'b1) : 'b0;
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        last_data <= 'b0;
+    end
+    else begin
+        last_data <= (cnt_accum == ACCUM_NUM-1) ? 1'b1 : 1'b0;
+    end
+end
+
+always @(posedge clk) begin
+    last_data_d[0] <= last_data;
+
+    for (i = 0; i < 6; i = i + 1) begin
+        last_data_d[i+1] <= last_data_d[i];
+    end
+end
+
+// cmpy
+wire [AXIS_DATA_I_WIDTH-1 : 0] cmpy_i_real;
+wire [AXIS_DATA_I_WIDTH-1 : 0] cmpy_i_imag;
+wire [AXIS_DATA_P_WIDTH-1 : 0] cmpy_p_raw_real;
+wire [AXIS_DATA_P_WIDTH-1 : 0] cmpy_p_raw_imag;
+wire [DATA_O_WIDTH-1 : 0] cmpy_p_real;
+wire [DATA_O_WIDTH-1 : 0] cmpy_p_imag;
+
+if (CMPY_WIDTH > DATA_I_WIDTH) begin
+    // append zeros
+    assign cmpy_i_real = {{(AXIS_DATA_I_WIDTH-CMPY_VALID_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real,{(CMPY_VALID_WIDTH-DATA_I_WIDTH){1'b0}}};
+    assign cmpy_i_imag = {{(AXIS_DATA_I_WIDTH-CMPY_VALID_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag,{(CMPY_VALID_WIDTH-DATA_I_WIDTH){1'b0}}};
+end
+else begin
+    // truncate msb
+    assign cmpy_i_real = {{(AXIS_DATA_I_WIDTH-CMPY_VALID_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real[DATA_I_WIDTH-1 -: CMPY_VALID_WIDTH]};
+    assign cmpy_i_imag = {{(AXIS_DATA_I_WIDTH-CMPY_VALID_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag[DATA_I_WIDTH-1 -: CMPY_VALID_WIDTH]};
+end
+
+if (DATA_O_WIDTH > DATA_MULT_VALID_WIDTH) begin
+    // append zeros
+    assign cmpy_p_real = {cmpy_p_raw_real[0 +: DATA_MULT_VALID_WIDTH],{(DATA_O_WIDTH-DATA_MULT_VALID_WIDTH){1'b0}}};
+    assign cmpy_p_imag = {cmpy_p_raw_imag[0 +: DATA_MULT_VALID_WIDTH],{(DATA_O_WIDTH-DATA_MULT_VALID_WIDTH){1'b0}}};
+end
+else begin
+    // truncate msb
+    assign cmpy_p_real = cmpy_p_raw_real[DATA_MULT_VALID_WIDTH-1 -: DATA_O_WIDTH];
+    assign cmpy_p_imag = cmpy_p_raw_imag[DATA_MULT_VALID_WIDTH-1 -: DATA_O_WIDTH];
+end
+
+wire [2*AXIS_DATA_I_WIDTH-1:0] cmpy_a;
+wire [2*AXIS_DATA_I_WIDTH-1:0] cmpy_b;
+wire [2*AXIS_DATA_P_WIDTH-1:0] cmpy_p;
+wire cmpy_p_vld;
+
+assign cmpy_a = {cmpy_i_imag,cmpy_i_real};
+assign cmpy_b = {-cmpy_i_imag,cmpy_i_real};
+assign {cmpy_p_raw_imag,cmpy_p_raw_real} = cmpy_p;
+
+cmpy_18x18_mult u_cmpy_18x18
+(
+    .aclk               (clk        ), // input wire aclk
+    .s_axis_a_tvalid    (cal_busy   ), // input wire s_axis_a_tvalid
+    .s_axis_a_tdata     (cmpy_a     ), // input wire [31 : 0] s_axis_a_tdata
+    .s_axis_b_tvalid    (cal_busy   ), // input wire s_axis_b_tvalid
+    .s_axis_b_tdata     (cmpy_b     ), // input wire [31 : 0] s_axis_b_tdata
+    .m_axis_dout_tvalid (cmpy_p_vld ), // output wire m_axis_dout_tvalid
+    .m_axis_dout_tdata  (cmpy_p     )  // output wire [63 : 0] m_axis_dout_tdata
+);
+
+// accumulation
+reg [DATA_O_WIDTH+$clog2(ACCUM_NUM) : 0] accum = 'b0;
+reg [DATA_O_WIDTH-1 : 0] var_buf = 'b0;
+
+assign var = var_buf;
+
+always @(posedge clk) begin
+    if (rst) begin
+        accum <= 'b0;
+    end
+    else begin
+        if (cmpy_p_vld) begin
+            accum <= accum + cmpy_p_real;
+        end
+        else begin
+            accum <= 'b0;
+        end
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        var_buf <= 'b0;
+    end
+    else if (last_data_d[5]) begin
+        var_buf <= accum[DATA_O_WIDTH+$clog2(ACCUM_NUM) -: DATA_O_WIDTH];
+    end
+end
+
+endmodule

modules/xc7k410tffg900-2/var_cal/testbenches/tb_var_cal.v

@@ -0,0 +1,78 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 06/11/2023 03:49:38 PM
+// Design Name:
+// Module Name: tb_var_cal
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module tb_var_cal;
+
+reg clk = 1'b1;
+reg rst = 1'b1;
+
+reg cal_start = 1'b0;
+reg cal_auto_en = 1'b0;
+wire cal_busy;
+
+reg din_valid = 1'b0;
+reg [29:0] din_real = 'b0;
+reg [29:0] din_imag = 'b0;
+
+wire var_valid;
+wire [31:0] var;
+
+var_cal u_var_cal
+(
+    .clk        (clk        ),
+    .rst        (rst        ),
+
+    .cal_start  (cal_start  ),
+    .cal_auto_en(cal_auto_en),
+    .cal_busy   (cal_busy   ),
+
+    .din_valid  (din_valid  ),
+    .din_real   (din_real   ),
+    .din_imag   (din_imag   ),
+
+    .var_valid  (var_valid  ),
+    .var        (var        )
+);
+
+integer i;
+integer r_file;
+
+initial begin
+    #102
+    rst = 1'b0;
+    #100
+    din_valid = 1'b1;
+    // cal_start = 1'b1;
+    cal_auto_en = 1'b1;
+
+    r_file = $fopen("./../../../../../testbenches/singletone.csv","r");
+    for (i = 0; i <= 32768; i = i + 1) begin
+        @(posedge clk)
+        $fscanf(r_file,"%d,%d",din_real,din_imag);
+    end
+    $fclose(r_file);
+    $stop;
+end
+
+always #10 clk = ~clk;
+
+endmodule