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add new dl814 dj control

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josh
2023-05-19 16:56:17 +08:00
parent 8f77175e44
commit dcfe84872e
749 changed files with 214766 additions and 0 deletions
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projects/dl814_dj/dl814_dj_new_48m/rtl/rf_auto_switch_freq.v
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2023/05/06 15:37:29
// Design Name:
// Module Name: rf_auto_switch_freq
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module rf_auto_switch_freq(
input clk ,
input rst ,
// vio control
input start , // rise-edge active, if start, change freq word to the first
input auto_test_enable , // rise-edge active
input rf_ctrl_mode , // 1 : auto switch, 0 : manual switch
input switch_next_freq , // rise-edge active
input switch_last_freq , // rise-edge active
input [31:0] cnt_valid_to_switch , // clock number from valid to switch
input [31:0] test_slot_length ,
// input
input [11:0] freq_hop_words_vio ,
input hop_words_valid_vio ,
input freq_hop_switch_vio ,
// output
output reg [11:0] freq_hop_words_auto = 12'd0 ,
output reg hop_words_valid_auto = 1'd0 ,
output reg freq_hop_switch_auto = 1'd0 ,
output reg sync_signal = 1'b0 // sync signal from DJ to JD
);
//************************* rise-edge detect ***********************************
reg start_d1 = 1'b0;
reg start_d2 = 1'b0;
reg start_pulse = 1'b0;
reg switch_next_freq_d1 = 1'b0;
reg switch_next_freq_d2 = 1'b0;
reg [9:0] switch_next_freq_pulse = 10'd0;
reg switch_last_freq_d1 = 1'b0;
reg switch_last_freq_d2 = 1'b0;
reg [9:0] switch_last_freq_pulse = 10'd0;
reg auto_test_enable_d1 = 1'b0;
reg auto_test_enable_d2 = 1'b0;
reg auto_test_enable_pulse = 1'b0;
always @ (posedge clk)
if(rst) begin
start_d1 <= 1'b0;
start_d2 <= 1'b0;
start_pulse <= 1'b0;
switch_next_freq_d1 <= 1'b0;
switch_next_freq_d2 <= 1'b0;
switch_next_freq_pulse <= 10'd0;
switch_last_freq_d1 <= 1'b0;
switch_last_freq_d2 <= 1'b0;
switch_last_freq_pulse <= 10'd0;
auto_test_enable_d1 <= 1'b0;
auto_test_enable_d2 <= 1'b0;
auto_test_enable_pulse <= 1'b0;
end else begin
start_d1 <= start;
start_d2 <= start_d1;
start_pulse <= start_d1 & ~start_d2;
switch_next_freq_d1 <= switch_next_freq;
switch_next_freq_d2 <= switch_next_freq_d1;
switch_next_freq_pulse[0] <= switch_next_freq_d1 & ~switch_next_freq_d2;
switch_next_freq_pulse[9:1] <= switch_next_freq_pulse[8:0];
switch_last_freq_d1 <= switch_last_freq;
switch_last_freq_d2 <= switch_last_freq_d1;
switch_last_freq_pulse[0] <= switch_last_freq_d1 & ~switch_last_freq_d2;
switch_last_freq_pulse[9:1] <= switch_last_freq_pulse[8:0];
auto_test_enable_d1 <= auto_test_enable;
auto_test_enable_d2 <= auto_test_enable_d1;
auto_test_enable_pulse <= auto_test_enable_d1 & ~auto_test_enable_d2;
end
//************************ auto test logic *************************************
reg auto_test_enable_reg = 1'b0;
reg [31:0] auto_test_cnt = 32'd0;
reg [7:0] freq_word_cnt = 8'd0; // range 0 -> 80
always @ (posedge clk)
if(rst | start_pulse)
auto_test_enable_reg <= 1'b0;
else if(auto_test_enable_pulse && ~auto_test_enable_reg)
auto_test_enable_reg <= 1'b1;
else if(auto_test_cnt == test_slot_length && freq_word_cnt == 8'd80)
auto_test_enable_reg <= 1'b0;
always @ (posedge clk)
if(rst | start_pulse)
auto_test_cnt <= 32'd0;
else if(auto_test_cnt == test_slot_length)
auto_test_cnt <= 32'd0;
else if(auto_test_enable_reg)
auto_test_cnt <= auto_test_cnt + 1'b1;
//******************** local freq word control *********************************
reg [11:0] local_freq_word = 12'd0;
reg local_freq_word_valid = 1'b0;
reg local_freq_word_switch = 1'b0;
wire [10:0] rom_freq_word_dout;
// 2 clock latency
rom_freq_word rom_freq_word_inst(
.clka (clk ),
.addra (freq_word_cnt[6:0] ),
.douta (rom_freq_word_dout )
);
always @ (posedge clk)
if(rst | start_pulse)
freq_word_cnt <= 8'd0;
else if(freq_word_cnt == 8'd80 && switch_next_freq_pulse[0])
freq_word_cnt <= 8'd0;
else if(freq_word_cnt == 8'd80 && auto_test_cnt == test_slot_length)
freq_word_cnt <= 8'd0;
else if(freq_word_cnt == 8'd0 && switch_last_freq_pulse[0])
freq_word_cnt <= 8'd80;
else if(auto_test_cnt == test_slot_length)
freq_word_cnt <= freq_word_cnt + 1'b1;
else if(switch_next_freq_pulse[0])
freq_word_cnt <= freq_word_cnt + 1'b1;
else if(switch_last_freq_pulse[0])
freq_word_cnt <= freq_word_cnt - 1'b1;
else
freq_word_cnt <= freq_word_cnt;
always @ (posedge clk)
if(rst | start_pulse)
local_freq_word_valid <= 1'b0;
else if(switch_next_freq_pulse[4] | switch_last_freq_pulse[4] | auto_test_cnt == 32'd4)
local_freq_word_valid <= 1'b1;
else if(auto_test_cnt == 32'd104)
local_freq_word_valid <= 1'b0;
reg [31:0] freq_word_valid_cnt = 32'd0;
always @ (posedge clk)
if(rst | start_pulse)
freq_word_valid_cnt <= 32'd0;
else if(freq_word_valid_cnt == cnt_valid_to_switch)
freq_word_valid_cnt <= 32'd0;
else if(local_freq_word_valid)
freq_word_valid_cnt <= freq_word_valid_cnt + 1'b1;
else if(freq_word_valid_cnt != 32'd0)
freq_word_valid_cnt <= freq_word_valid_cnt + 1'b1;
else
freq_word_valid_cnt <= freq_word_valid_cnt;
always @ (posedge clk)
if(rst | start_pulse)
local_freq_word_switch <= 1'b0;
else if(freq_word_valid_cnt == cnt_valid_to_switch - 32'd100)
local_freq_word_switch <= 1'b1;
else if(freq_word_valid_cnt == cnt_valid_to_switch)
local_freq_word_switch <= 1'b0;
always @ (posedge clk)
if(rst | start_pulse)
local_freq_word <= 12'd0;
else
local_freq_word <= rom_freq_word_dout;
//******************** output freq switch signal *******************************
// freq_hop_words_auto
always @ (posedge clk)
if(rst | start_pulse)
freq_hop_words_auto <= 12'd0;
else if(rf_ctrl_mode)
freq_hop_words_auto <= local_freq_word;
else
freq_hop_words_auto <= freq_hop_words_vio;
// hop_words_valid_auto
always @ (posedge clk)
if(rst | start_pulse)
hop_words_valid_auto <= 1'b0;
else if(rf_ctrl_mode)
hop_words_valid_auto <= local_freq_word_valid;
else
hop_words_valid_auto <= hop_words_valid_vio;
// freq_hop_switch_auto
always @ (posedge clk)
if(rst | start_pulse)
freq_hop_switch_auto <= 1'b0;
else if(rf_ctrl_mode)
freq_hop_switch_auto <= local_freq_word_switch;
else
freq_hop_switch_auto <= freq_hop_switch_vio;
// sync_signal
always @ (posedge clk)
if(rst | start_pulse)
sync_signal <= 1'b0;
else if(~freq_hop_switch_auto & local_freq_word_switch)
sync_signal <= ~sync_signal;
endmodule
projects/dl814_dj/dl814_dj_new_48m/rtl/rf_control.v
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2022/01/13 12:04:17
// Design Name:
// Module Name: rf_control
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module rf_control(
input clk , //192Mclk
input rst ,
input [5:0] tx_gain_manual , //发射增益输入
input [5:0] rx_gain_manual , //接收增益输入
input gain_on_vio , //vio设置参数or自动切换
input [1:0] rf_txrx_vio , //发射通道或者接收通道
input [1:0] rf_txrx_net , //受网络层控制
input rf_vio_set , //vio设置参数or自动切换
input [11:0] tx_freq_hop_words , //tx跳频频率控制字
input tx_hop_words_valid , //tx跳频频率控制字有效脉冲
input tx_freq_hop_switch , //tx频点切换脉冲
input [11:0] rx_freq_hop_words , //rx跳频频率控制字
input rx_hop_words_valid , //rx跳频频率控制字有效脉冲
input rx_freq_hop_switch , //rx频点切换脉冲
input [11:0] freq_hop_words_vio , //vio设置跳频频率控制字
input hop_words_valid_vio , //vio设置跳频频率控制字有效脉冲
input freq_hop_switch_vio , //vio设置频点切换脉冲
// 新增4个引脚
output reg clk_12M = 1'd0 , // 串行输入时钟
output reg CS_rf = 1'd1 , // 发送使能输入CS
output reg tx_gain = 1'd0 , //发射通道增益
input rx_gain ,
output reg tx_gain_on = 1'd0 , //发射通道开关
// output reg rx_gain = 1'd0 , //接收通道增益
output reg rx_gain_on = 1'd0 , //发射通道开关
output reg [11:0] freq_hop_words = 12'd0 , //跳频频率控制字
output reg hop_words_valid = 1'd0 , //跳频频率控制字有效脉冲
output reg freq_hop_switch = 1'd0 , //频点切换脉冲
output reg freq_hop_switch_out = 1'd0 ,
output reg [11:0] freq_hop_words_sweep = 12'd0
);
reg rst_D1_1 = 1'd0;
reg rst_D1_2 = 1'd0;
reg rst_D1_3 = 1'd0;
always @(posedge clk) begin
rst_D1_1 <= rst ;
rst_D1_2 <= rst ;
rst_D1_3 <= rst ;
end
//--------------------------------------------------------------------------------------------------
//发射通道增益、开关设置
always @(posedge clk) begin
if(rst_D1_1)
tx_gain_on <= 1'b0 ;
else if(gain_on_vio)
tx_gain_on <= (rf_txrx_vio[1:0] == 2'd1) ? 1'd1 :1'd0 ;
else
tx_gain_on <= (rf_txrx_net[1:0] == 2'd1) ? 1'd1 :1'd0 ;
end
//--------------------------------------------------------------------------------------------------
//接收通道增益、开关设置
reg [5:0] rx_gain_div2 = 5'd0;
always @(posedge clk) begin
if(rst_D1_2)
rx_gain_on <= 1'b0 ;
else if(gain_on_vio)
rx_gain_on <= (rf_txrx_vio[1:0] == 2'd2) ? 1'd1 :1'd0 ;
else
rx_gain_on <= (rf_txrx_net[1:0] == 2'd2) ? 1'd1 :1'd0 ;
end
//--------------------------------------------------------------------------------------------------
//跳频设置vio控制or网络层设置
reg [11:0] freq_hop_words_net = 12'd0 ;
reg hop_words_valid_net = 1'd0 ;
reg freq_hop_switch_net = 1'd0 ;
always @(posedge clk) begin
if(rst_D1_3)begin
freq_hop_words_net [11:0] <= 12'd0 ;
hop_words_valid_net <= 1'd0 ;
freq_hop_switch_net <= 1'd0 ;
end
else if(rf_txrx_net[1:0] == 2'd1)begin
freq_hop_words_net [11:0] <= tx_freq_hop_words[11:0] ;
hop_words_valid_net <= tx_hop_words_valid ;
freq_hop_switch_net <= tx_freq_hop_switch ;
end
else if(rf_txrx_net[1:0] == 2'd2)begin
freq_hop_words_net [11:0] <= rx_freq_hop_words[11:0] ;
hop_words_valid_net <= rx_hop_words_valid ;
freq_hop_switch_net <= rx_freq_hop_switch ;
end
else begin
freq_hop_words_net [11:0] <= freq_hop_words_net [11:0] ;
hop_words_valid_net <= 1'd0 ;
freq_hop_switch_net <= 1'd0 ;
end
end
// reg [11:0] freq_hop_words_sweep = 12'd0;
reg hop_words_valid_sweep = 1'd0;
reg freq_hop_switch_sweep = 1'd0;
reg hop_words_valid_manual = 1'd0;
reg freq_hop_switch_manual = 1'd0;
reg [11:0] freq_hop_words_manual = 12'd0 ;
wire freq_swicth_start;
always @(posedge clk) begin
if(rst_D1_3)begin
freq_hop_words [11:0] <= 12'd0 ;
hop_words_valid <= 1'd0 ;
freq_hop_switch <= 1'd0 ;
freq_hop_switch_out <= 1'd0 ;
end
else if(rf_vio_set)begin // rf_vio_set为1频率控制字控
freq_hop_words [11:0] <= freq_hop_words_vio[11:0] ;
hop_words_valid <= hop_words_valid_vio ;
freq_hop_switch <= freq_hop_switch_vio ;
freq_hop_switch_out <= freq_hop_switch_vio ;
end
else if(freq_swicth_start)begin
freq_hop_words [11:0] <= freq_hop_words_sweep[11:0] ;
hop_words_valid <= hop_words_valid_sweep ;
freq_hop_switch <= freq_hop_switch_sweep ;
freq_hop_switch_out <= freq_hop_switch_sweep ;
end
else begin
freq_hop_words [11:0] <= freq_hop_words_manual[11:0] ;
hop_words_valid <= hop_words_valid_manual ;
freq_hop_switch <= freq_hop_switch_manual ;
freq_hop_switch_out <= freq_hop_switch_manual ;
end
end
// 12M时钟生成
// reg clk_12M = 1'd0 ;
reg [2:0] cnt_8 = 3'd0 ;
reg clk_switch = 1'd0 ;
// 8位计数器
always@(posedge clk) begin
if(rst_D1_1) begin
cnt_8 <= 3'd0 ;
clk_switch <= 1'd0 ;
end
else if(cnt_8 == 3'd7)begin
cnt_8 <= 3'd0 ;
clk_switch <= 1'd1 ;
end
else begin
cnt_8 <= cnt_8 + 3'd1 ;
clk_switch <= 1'd0 ;
end
end
always@(posedge clk) begin // 产生12M时钟
if(clk_switch == 1'd1)begin
clk_12M <= ~clk_12M ;
end
else begin
clk_12M <= clk_12M ;
end
end
// 发送使能输入
// reg CS_rf = 1'd1;
wire CS_rf_flag;
reg CS_rf_flag_D1 = 1'd0;
wire [31:0] cnt_frechange_top ;
wire [31:0] switch_delay_time ;
wire freq_hop_change ;
wire [11:0] freq_hop_words_vio1 ;
wire [11:0] freq_hop_words_vio2 ;
wire [31:0] valid_delay_time_max ;
wire [63:0] slot_vio_time ;
wire [4:0] cnt_slot_max ;
wire [7:0] MOSI_tx_atte ;
wire [7:0] MOSI_rx_atte ;
// 发送使能输入vio_rftx_en
vio_rf_test vio_rf_test (
.clk(clk_12M), // input wire clk
.probe_out0(CS_rf_flag), // output wire [0 : 0] probe_out0
.probe_out1(MOSI_tx_atte), // output wire [0 : 0] probe_out0
.probe_out2(MOSI_rx_atte), // output wire [0 : 0] probe_out0
.probe_out3(cnt_frechange_top),
.probe_out4(freq_hop_change), // 切换频率开始
.probe_out5(freq_hop_words_vio1[11:0]),
.probe_out6(freq_hop_words_vio2[11:0]),
.probe_out7(switch_delay_time[31:0]), // valid和switch之间的时间
.probe_out8(valid_delay_time_max[31:0]), // valid和switch的切换时间
.probe_out9(slot_vio_time[63:0]), // 一个频点的时间
.probe_out10(cnt_slot_max[4:0]),
.probe_out11(freq_swicth_start)
);
always@(posedge clk_12M)begin
CS_rf_flag_D1 <= CS_rf_flag;
end
// 中频-射频数据输出MOSI
reg MOSI = 1'd0 ;
wire [31:0] MOSI_data;
reg [7:0] MOSI_head = 8'h5A;
// wire [7:0] MOSI_tx_atte ;
// wire [7:0] MOSI_rx_atte ;
reg [7:0] MOSI_recv = 8'hA5;
assign MOSI_data = {MOSI_head,MOSI_tx_atte,MOSI_rx_atte,MOSI_recv};
reg [3:0] state_MOSI = 4'd0;
reg [7:0] cnt_64 = 8'd0;
always@(posedge clk_12M) begin
if(rst_D1_1) begin
state_MOSI <= 4'd0;
cnt_64 <= 8'd0;
end
else begin
case(state_MOSI)
4'd0:begin // 等待发送指令
if(CS_rf_flag && !CS_rf_flag_D1)begin
state_MOSI <= 4'd1;
end
else begin
state_MOSI <= 4'd0;
end
end
4'd1:begin // 发送数据
CS_rf <= 1'd0;
if(cnt_64 == 8'd31)begin
cnt_64 <= 8'd0;
tx_gain <= MOSI_data[0];
state_MOSI <= 4'd2;
end
else begin
cnt_64 <= cnt_64 + 8'd1;
tx_gain <= MOSI_data[31 - cnt_64];
state_MOSI <= 4'd1;
end
end
4'd2:begin
CS_rf <= 1'd1;
state_MOSI <= 4'd0;
tx_gain <= 1'd0;
end
endcase
end
end
// 扫频信号
// 通过vio选择控制频点的方式
reg [31:0] cnt_frechange;
always@(posedge clk) begin
if(rst_D1_1)begin
cnt_frechange <= 32'd0;
end
else begin
if(cnt_frechange == cnt_frechange_top) begin
cnt_frechange <= 32'd0;
end
else begin
cnt_frechange <= cnt_frechange + 32'd1;
end
end
end
always@(posedge clk) begin
if(rst_D1_2)begin
freq_hop_words_sweep <= 12'd0;
hop_words_valid_sweep <= 1'd0;
freq_hop_switch_sweep <= 1'd0;
end
else if(cnt_frechange == cnt_frechange_top) begin
if(freq_hop_words_sweep == 12'd3500) begin
freq_hop_words_sweep <= 12'd0;
end
else begin
freq_hop_words_sweep <= freq_hop_words_sweep + 12'd1;
end
hop_words_valid_sweep <= 1'd0;
freq_hop_switch_sweep <= 1'd1;
end
else if(cnt_frechange == cnt_frechange_top - 32'd1920000) begin
freq_hop_words_sweep <= freq_hop_words_sweep;
hop_words_valid_sweep <= 1'd1;
freq_hop_switch_sweep <= 1'd0;
end
else begin
freq_hop_words_sweep <= freq_hop_words_sweep;
hop_words_valid_sweep <= 1'd0;
freq_hop_switch_sweep <= 1'd0;
end
end
// 控制时隙长短
reg [31:0] delay_time = 32'd0;
reg hop_words_valid_manual_long = 1'd0;
reg [31:0] valid_delay_time = 32'd0;
reg [31:0] freq_hop_switch_delay_time = 32'd0;
reg [63:0] slot_time_cnt = 64'd0;
reg [4:0] state_vio_time = 5'd0;
reg [4:0] cnt_slot = 5'd0;
reg freq_hop_change_D1 = 1'd0;
reg freq_hop_change_D2 = 1'd0;
reg freq_hop_change_D3 = 1'd0;
always@(posedge clk) begin
freq_hop_change_D1 <= freq_hop_change;
freq_hop_change_D2 <= freq_hop_change_D1;
freq_hop_change_D3 <= freq_hop_change_D2;
end
always@(posedge clk) begin
if(rst_D1_1) begin
state_vio_time <= 5'd0;
freq_hop_words_manual <= freq_hop_words_vio1;
end
else begin
case(state_vio_time)
5'd0:begin // 等待切换频率开始
if(!freq_hop_change_D1 && freq_hop_change)begin
state_vio_time <= 5'd1;
slot_time_cnt <= 64'd1 + slot_time_cnt;
if(freq_hop_words_manual == freq_hop_words_vio1) begin
freq_hop_words_manual <= freq_hop_words_vio2;
end
else if(freq_hop_words_manual == freq_hop_words_vio2) begin
freq_hop_words_manual <= freq_hop_words_vio1;
end
else begin
freq_hop_words_manual <= freq_hop_words_vio1;
end
end
else begin
state_vio_time <= 5'd0;
freq_hop_words_manual <= freq_hop_words_manual;
end
end
5'd1:begin // 等待valid信号拉高完毕
if(valid_delay_time == valid_delay_time_max) begin
hop_words_valid_manual <= 1'd0;
valid_delay_time <= 32'd0;
state_vio_time <= 5'd2;
end
else begin
hop_words_valid_manual <= 1'd1;
valid_delay_time <= valid_delay_time + 32'd1;
state_vio_time <= 5'd1;
end
slot_time_cnt <= 64'd1 + slot_time_cnt;
end
5'd2:begin // 等待switch信号
if(delay_time == switch_delay_time) begin
freq_hop_switch_manual <= 1'd1;
delay_time <= 32'd0;
state_vio_time <= 5'd3;
end
else begin
freq_hop_switch_manual <= 1'd0;
delay_time <= 32'd1 + delay_time;
state_vio_time <= 5'd2;
end
slot_time_cnt <= 64'd1 + slot_time_cnt;
end
5'd3:begin // 等待switch信号拉高完毕
if(freq_hop_switch_delay_time == valid_delay_time_max) begin
freq_hop_switch_manual <= 1'd0;
freq_hop_switch_delay_time <= 32'd0;
state_vio_time <= 5'd4;
end
else begin
freq_hop_switch_manual <= 1'd1;
freq_hop_switch_delay_time <= freq_hop_switch_delay_time + 32'd1;
state_vio_time <= 5'd3;
end
slot_time_cnt <= 64'd1 + slot_time_cnt;
end
5'd4:begin // 等待时隙结束
if(slot_time_cnt == slot_vio_time)begin
if(cnt_slot == cnt_slot_max - 5'd1) begin
cnt_slot <= 5'd0;
state_vio_time <= 5'd0;
slot_time_cnt <= 64'd0;
end
else begin
state_vio_time <= 5'd1;
slot_time_cnt <= 64'd0;
cnt_slot <= cnt_slot + 5'd1;
end
end
else begin
state_vio_time <= 5'd4;
slot_time_cnt <= 64'd1 + slot_time_cnt;
cnt_slot <= cnt_slot;
end
end
default:begin
if(!freq_hop_change_D1 && freq_hop_change)begin
state_vio_time <= 5'd1;
end
else begin
state_vio_time <= 5'd0;
end
end
endcase
end
end
endmodule
projects/dl814_dj/dl814_dj_new_48m/rtl/system_top.v
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
// _ _ ____
// | | ___ ___| |__ / ___| __ _ ___
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
// \___/ \___/|___/_| |_| \____|\__,_|\___/
//
// Create Date: 2022/06/07 21:17:23
// Design Name:
// Module Name: system_top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module system_top
(
// *************************************************************************
// *************************** Clocks and Resets ***************************
// *************************************************************************
input sysclk_p , // FPGA_LOGIC_CLK_IN, derived from ad9528, 122.88mhz
input sysclk_n ,
input refclk_p , // FPGA_JESD204B_CLK_IN_1, derived from ad9528, 122.88mhz
input refclk_n ,
input sysref_p ,
input sysref_n ,
// *************************************************************************
// *************************** AD9528 Interface ****************************
// *************************************************************************
// spi interface
output spi_csn_ad9528 ,
output spi_clk_ad9528 ,
output spi_mosi_ad9528 ,
input spi_miso_ad9528 ,
// control signals
output ad9528_reset_b ,
output ad9528_sysref_req ,
// *************************************************************************
// *************************** AD9371 Interface ****************************
// *************************************************************************
// 204b interface, only lane 0 and lane 1 are used
output rx_sync_p ,
output rx_sync_n ,
input tx_sync_p ,
input tx_sync_n ,
input [ 1:0] rx_data_p ,
input [ 1:0] rx_data_n ,
output [ 1:0] tx_data_p ,
output [ 1:0] tx_data_n ,
// spi interface
output spi_csn_ad9371 ,
output spi_clk_ad9371 ,
output spi_mosi_ad9371 ,
input spi_miso_ad9371 ,
// control signals
output ad9371_test ,
output ad9371_reset_b ,
input ad9371_gpint ,
// *************************************************************************
// ****************************** RF Control *******************************
// *************************************************************************
output tx_gain ,
input rx_gain ,
output clk_12M ,
output CS_rf ,
output tx_gain_on ,
output rx_gain_on ,
output [11:0] freq_hop_words ,
output hop_words_valid ,
output freq_hop_switch ,
// *************************************************************************
// ******************* DDR and Fixed-io (Do NOT Modify) ********************
// *************************************************************************
// ddr
inout [14:0] ddr_addr ,
inout [ 2:0] ddr_ba ,
inout ddr_cas_n ,
inout ddr_ck_n ,
inout ddr_ck_p ,
inout ddr_cke ,
inout ddr_cs_n ,
inout [ 3:0] ddr_dm ,
inout [31:0] ddr_dq ,
inout [ 3:0] ddr_dqs_n ,
inout [ 3:0] ddr_dqs_p ,
inout ddr_odt ,
inout ddr_ras_n ,
inout ddr_reset_n ,
inout ddr_we_n ,
// fixed-io
inout fixed_io_ddr_vrn ,
inout fixed_io_ddr_vrp ,
inout [53:0] fixed_io_mio ,
inout fixed_io_ps_clk ,
inout fixed_io_ps_porb ,
inout fixed_io_ps_srstb ,
// *************************************************************************
// ************************* Sync Signal ***********************************
// *************************************************************************
output sync_signal_out ,
output reg sync_gnd = 1'b0
);
////////////////////////////////////////////////////////////////////////////////
/////////////////////////// System Clock Generation ////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// system main clock, mmcm is included in block design
wire sys_clk ; // 122.88mhz
wire sys_clk_2x ; // 245.76mhz
wire sys_rst ;
// optional siganl clock, can be changed to whatever frequency you want
wire sig_clk ; // 245.76mhz
wire sig_clk_ld ;
wire sig_rst ;
assign sig_rst = ~sig_clk_ld;
sig_clk_gen u_sig_clk_gen
(
// Clock out ports
.clk_out1 (sig_clk ), // output clk_out1
// Status and control signals
.reset (sys_rst ), // input reset
.locked (sig_clk_ld ), // output locked
// Clock in ports
.clk_in1 (sys_clk ) // input clk_in1
);
////////////////////////////////////////////////////////////////////////////////
//////////////////////////// Block Design Interface ////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// gpio
wire [15:0] gpio_i ;
wire [15:0] gpio_o ;
assign gpio_i[15:5] = gpio_o[15:5];
assign ad9528_reset_b = gpio_o[4]; // ad9528 reset pin
assign ad9528_sysref_req = gpio_o[3]; // ad9528 sysref requset pin
assign ad9371_test = gpio_o[2];
assign ad9371_reset_b = gpio_o[1];
assign gpio_i[0] = ad9371_gpint ; // ad9371 gpio interrupt pin
// ad9371 jesd204b signals
wire rx_rstn ;
wire [63:0] rx_tdata ;
wire rx_tvalid ;
wire tx_rstn ;
wire [63:0] tx_tdata ;
wire tx_tready ;
// spi interface
wire spi_clk ;
wire spi_mosi ;
reg spi_miso ;
assign spi_clk_ad9528 = spi_clk ;
assign spi_clk_ad9371 = spi_clk ;
assign spi_mosi_ad9528 = spi_mosi ;
assign spi_mosi_ad9371 = spi_mosi ;
always @(*) begin
if (~spi_csn_ad9528)
spi_miso = spi_miso_ad9528;
else if (~spi_csn_ad9371)
spi_miso = spi_miso_ad9371;
else
spi_miso = 1'bz;
end
system_bd_wrapper u_system_bd
(
// ddr
.ddr_addr (ddr_addr ), // inout [14:0]ddr_addr
.ddr_ba (ddr_ba ), // inout [2:0]ddr_ba
.ddr_cas_n (ddr_cas_n ), // inout ddr_cas_n
.ddr_ck_n (ddr_ck_n ), // inout ddr_ck_n
.ddr_ck_p (ddr_ck_p ), // inout ddr_ck_p
.ddr_cke (ddr_cke ), // inout ddr_cke
.ddr_cs_n (ddr_cs_n ), // inout ddr_cs_n
.ddr_dm (ddr_dm ), // inout [3:0]ddr_dm
.ddr_dq (ddr_dq ), // inout [31:0]ddr_dq
.ddr_dqs_n (ddr_dqs_n ), // inout [3:0]ddr_dqs_n
.ddr_dqs_p (ddr_dqs_p ), // inout [3:0]ddr_dqs_p
.ddr_odt (ddr_odt ), // inout ddr_odt
.ddr_ras_n (ddr_ras_n ), // inout ddr_ras_n
.ddr_reset_n (ddr_reset_n ), // inout ddr_reset_n
.ddr_we_n (ddr_we_n ), // inout ddr_we_n
// fixed io
.fixed_io_ddr_vrn (fixed_io_ddr_vrn ), // inout fixed_io_ddr_vrn
.fixed_io_ddr_vrp (fixed_io_ddr_vrp ), // inout fixed_io_ddr_vrp
.fixed_io_mio (fixed_io_mio ), // inout [53:0]fixed_io_mio
.fixed_io_ps_clk (fixed_io_ps_clk ), // inout fixed_io_ps_clk
.fixed_io_ps_porb (fixed_io_ps_porb ), // inout fixed_io_ps_porb
.fixed_io_ps_srstb (fixed_io_ps_srstb ), // inout fixed_io_ps_srstb
// gpio, for control signals
.gpio_i (gpio_i[15:0] ), // input [15:0]gpio_i
.gpio_o (gpio_o[15:0] ), // output [15:0]gpio_o
// spi interface
.spi_miso (spi_miso ), // input spi_miso
.spi_mosi (spi_mosi ), // output spi_mosi
.spi_sclk (spi_clk ), // output spi_sclk
.spi_ss_0 (spi_csn_ad9528 ), // output spi_ss_0
.spi_ss_1 (spi_csn_ad9371 ), // output spi_ss_1
.spi_ss_2 ( ), // output spi_ss_2
// system main clock
.sysclk_p (sysclk_p ), // input sysclk_p
.sysclk_n (sysclk_n ), // input sysclk_n
.sys_clk (sys_clk ), // output sys_clk
.sys_rst (sys_rst ), // output sys_rst
// jesd 204b interface
.refclk_p (refclk_p ), // input refclk_p
.refclk_n (refclk_n ), // input refclk_n
.sysref_p (sysref_p ), // input sysref_p
.sysref_n (sysref_n ), // input sysref_n
.rxp_in (rx_data_p[1:0] ), // input [1:0]rxp_in
.rxn_in (rx_data_n[1:0] ), // input [1:0]rxn_in
.rx_sync_p (rx_sync_p ), // output rx_sync_p
.rx_sync_n (rx_sync_n ), // output rx_sync_n
.rx_rstn (rx_rstn ), // output rx_rstn
.rx_tdata (rx_tdata[63:0] ), // output [63:0]rx_tdata
.rx_tvalid (rx_tvalid ), // output rx_tvalid
.txp_out (tx_data_p[1:0] ), // output [1:0]txp_out
.txn_out (tx_data_n[1:0] ), // output [1:0]txn_out
.tx_sync_p (tx_sync_p ), // input tx_sync_p
.tx_sync_n (tx_sync_n ), // input tx_sync_n
.tx_rstn (tx_rstn ), // output tx_rstn
.tx_tdata (tx_tdata[63:0] ), // input [63:0]tx_tdata
.tx_tready (tx_tready ) // output tx_tready
);
////////////////////////////////////////////////////////////////////////////////
//////////////////////////// RF Control Interface //////////////////////////////
////////////////////////////////////////////////////////////////////////////////
wire gain_on_vio ;
wire [1:0] rf_txrx_vio ;
wire rf_vio_set ;
wire [5:0] tx_gain_manual ;
wire [5:0] rx_gain_manual ;
wire [11:0] freq_hop_words_vio ;
wire hop_words_valid_vio ;
wire freq_hop_switch_vio ;
wire freq_hop_switch_out ;
wire [11:0] freq_hop_words_sweep;
// rf auto switch frequency function
wire auto_test_enable_vio;
wire rf_auto_start_vio ;
wire rf_ctrl_mode_vio ;
wire switch_next_freq_vio;
wire switch_last_freq_vio;
wire [31:0] cnt_valid_to_switch_vio;
wire [31:0] test_slot_length_vio;
wire [11:0] freq_hop_words_auto ;
wire hop_words_valid_auto;
wire freq_hop_switch_auto;
rf_auto_switch_freq u_rf_auto_switch_freq
(
.clk (sys_clk ),
.rst (sys_rst ),
// vio control
.start (rf_auto_start_vio ), // rise-edge active, if start, change freq word to the first
.auto_test_enable (auto_test_enable_vio ), // rise-edge active
.rf_ctrl_mode (rf_ctrl_mode_vio ), // 1 : auto switch, 0 : manual switch
.switch_next_freq (switch_next_freq_vio ), // rise-edge active
.switch_last_freq (switch_last_freq_vio ), // rise-edge active
.cnt_valid_to_switch (cnt_valid_to_switch_vio ), // the clock number from valid to switch
.test_slot_length (test_slot_length_vio[31:0] ),
// input
.freq_hop_words_vio (freq_hop_words_vio[11:0] ),
.hop_words_valid_vio (hop_words_valid_vio ),
.freq_hop_switch_vio (freq_hop_switch_vio ),
// output
.freq_hop_words_auto (freq_hop_words_auto[11:0] ),
.hop_words_valid_auto (hop_words_valid_auto ),
.freq_hop_switch_auto (freq_hop_switch_auto ),
.sync_signal (sync_signal_out )
);
rf_control u_rf_control
(
.clk (sys_clk ),
.rst (sys_rst ),
//input
.gain_on_vio (gain_on_vio ),
.rf_txrx_vio (rf_txrx_vio[1:0] ),
.rf_txrx_net (2'd0 ),
.tx_gain_manual (tx_gain_manual[5:0] ),
.rx_gain_manual (rx_gain_manual[5:0] ),
//0:net->control 1:vio->control
.rf_vio_set (rf_vio_set ),
//vio hop control
.freq_hop_words_vio (freq_hop_words_auto[10:0] ),
.hop_words_valid_vio (hop_words_valid_auto ),
.freq_hop_switch_vio (freq_hop_switch_auto ),
//tx hop control
.tx_freq_hop_words (11'b0 ),
.tx_hop_words_valid (1'b0 ),
.tx_freq_hop_switch (1'b0 ),
//rx hop control
.rx_freq_hop_words (11'b0 ),
.rx_hop_words_valid (1'b0 ),
.rx_freq_hop_switch (1'b0 ),
//output
.clk_12M (clk_12M ),
.CS_rf (CS_rf ),
.tx_gain (tx_gain ),
.tx_gain_on (tx_gain_on ),
.rx_gain (rx_gain ),
.rx_gain_on (rx_gain_on ),
.freq_hop_words (freq_hop_words[11:0] ),
.hop_words_valid (hop_words_valid ),
.freq_hop_switch (freq_hop_switch ),
.freq_hop_switch_out (freq_hop_switch_out ),
.freq_hop_words_sweep (freq_hop_words_sweep )
);
////////////////////////////////////////////////////////////////////////////////
///////////////////////////// Tx Baseband Signals //////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// baseband signal
wire [15:0] tx_1_i;
wire [15:0] tx_1_q;
wire [15:0] tx_2_i;
wire [15:0] tx_2_q;
assign tx_tdata =
{
tx_2_q[7:0], tx_2_q[15:8], tx_2_i[7:0], tx_2_i[15:8],
tx_1_q[7:0], tx_1_q[15:8], tx_1_i[7:0], tx_1_i[15:8]
};
wire [15:0] tx_data_i;
wire [15:0] tx_data_q;
assign tx_1_i = tx_data_i;
assign tx_1_q = tx_data_q;
assign tx_2_i = tx_data_i;
assign tx_2_q = tx_data_q;
// <--------------------------------------------------------------------------->
// <--------------------- insert transmitter logic below ---------------------->
// <--------------------------------------------------------------------------->
wire [ 2:0] waveform_sel;
wire sweep_on ;
wire [31:0] freq_set ;
wire [ 1:0] iq_sel ;
wire [ 3:0] bb_rshift ;
tx_control u_tx_wave
(
.sys_clk (sys_clk ), // input sys_clk
.sys_rst (sys_rst ), // input sys_rst
.sig_clk (sig_clk ), // input sig_clk
.sig_rst (sig_rst ), // input sig_rst
.tx_data_i (tx_data_i ), // output [15:0] tx_data_i
.tx_data_q (tx_data_q ), // output [15:0] tx_data_q
// debug ports
.waveform_sel (waveform_sel ), // input [ 2:0] waveform_sel
.sweep_on (sweep_on ), // input sweep_on
.freq_set (freq_set ), // input [31:0] freq_set
.iq_sel (iq_sel ), // input [ 1:0] iq_sel
.bb_rshift (bb_rshift ) // input [ 3:0] bb_rshift
);
////////////////////////////////////////////////////////////////////////////////
///////////////////////////// Rx Baseband Signals //////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// rx signal
wire [15:0] rx_1_i;
wire [15:0] rx_1_q;
wire [15:0] rx_2_i;
wire [15:0] rx_2_q;
assign rx_1_i = { rx_tdata[ 7: 0] , rx_tdata[15: 8]};
assign rx_1_q = { rx_tdata[23:16] , rx_tdata[31:24]};
assign rx_2_i = { rx_tdata[39:32] , rx_tdata[47:40]};
assign rx_2_q = { rx_tdata[55:48] , rx_tdata[63:56]};
// <--------------------------------------------------------------------------->
// <----------------------- insert receiver logic below ----------------------->
// <--------------------------------------------------------------------------->
////////////////////////////////////////////////////////////////////////////////
//////////////////////////////// ILAs and VIOs /////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
ila_2x16x131072 u_ila_tx
(
.clk (sys_clk ), // input wire clk
.probe0 (tx_data_i ), // input wire [15:0] probe0
.probe1 (tx_data_q ) // input wire [15:0] probe1
);
ila_4x16x131072 u_ila_rx
(
.clk (sys_clk ), // input wire clk
.probe0 (rx_1_i ), // input wire [15:0] probe0
.probe1 (rx_1_q ), // input wire [15:0] probe1
.probe2 (rx_2_i ), // input wire [15:0] probe2
.probe3 (rx_2_q ) // input wire [15:0] probe3
);
ila_ctrl_signal u_ila_ctrl_signal
(
.clk (sys_clk ), // input wire clk
.probe0 (u_system_bd.system_bd_i.jesd204b.jesd_reset ), // input wire [0:0] probe0
.probe1 (u_system_bd.system_bd_i.jesd204b.rx_sync ), // input wire [0:0] probe1
.probe2 (rx_rstn ), // input wire [0:0] probe2
.probe3 (u_system_bd.system_bd_i.jesd204b.tx_sync ), // input wire [0:0] probe3
.probe4 (tx_rstn ), // input wire [0:0] probe4
.probe5 (u_system_bd.system_bd_i.jesd204b.sysref ) // input wire [0:0] probe5
);
vio_manual_ctrl u_vio_manual_ctrl
(
.clk (sys_clk ), // input wire clk
.probe_out0 (waveform_sel ), // output wire [2 : 0] probe_out0
.probe_out1 (sweep_on ), // output wire [0 : 0] probe_out1
.probe_out2 (freq_set ), // output wire [31 : 0] probe_out2
.probe_out3 (iq_sel ), // output wire [1 : 0] probe_out3
.probe_out4 (bb_rshift ) // output wire [3 : 0] probe_out4
);
vio_rf_control u_vio_rf_control
(
.clk (sys_clk ), // input wire clk
.probe_out0 (gain_on_vio ), // output wire [0 : 0] probe_out0
.probe_out1 (rf_txrx_vio[1:0] ), // output wire [1 : 0] probe_out1
.probe_out2 (rf_vio_set ), // output wire [0 : 0] probe_out2
.probe_out3 (tx_gain_manual[5:0] ), // output wire [5 : 0] probe_out3
.probe_out4 (rx_gain_manual[5:0] ), // output wire [5 : 0] probe_out4
.probe_out5 (freq_hop_words_vio[11:0] ), // output wire [10 : 0] probe_out5
.probe_out6 (hop_words_valid_vio ), // output wire [0 : 0] probe_out6
.probe_out7 (freq_hop_switch_vio ), // output wire [0 : 0] probe_out7
.probe_out8 (self_check_dout ), // output wire [0 : 0] probe_out8
.probe_out9 (rf_auto_start_vio ), // output wire [0 : 0] probe_out9
.probe_out10 (rf_ctrl_mode_vio ), // output wire [0 : 0] probe_out10
.probe_out11 (switch_next_freq_vio ), // output wire [0 : 0] probe_out11
.probe_out12 (switch_last_freq_vio ), // output wire [0 : 0] probe_out12
.probe_out13 (cnt_valid_to_switch_vio[31:0] ), // output wire [31: 0] probe_out13
.probe_out14 (auto_test_enable_vio ), // output wire [0 : 0] probe_out14
.probe_out15 (test_slot_length_vio[31:0] ), // output wire [31: 0] probe_out15
.probe_in0 (freq_hop_words_auto[10:0] ) // input wire [10: 0] probe_in0
);
ila_rf_test ila_rf_test
(
.clk (sys_clk ), // input wire clk
.probe0 (freq_hop_words[11:0] ), // input wire [11:0] probe0
.probe1 (tx_gain_on ), // input wire [0:0] probe1
.probe2 (rx_gain ), // input wire [0:0] probe2
.probe3 (rx_gain_on ), // input wire [0:0] probe3
.probe4 (tx_gain ), // input wire [0:0] probe4
.probe5 (hop_words_valid ), // input wire [0:0] probe5
.probe6 (freq_hop_switch ), // input wire [0:0] probe6
.probe7 (clk_12M ), // input wire [0:0] probe7
.probe8 (CS_rf ), // input wire [0:0] probe8
.probe9 (freq_hop_words_sweep ) // input wire [11:0] probe9
);
endmodule
projects/dl814_dj/dl814_dj_new_48m/rtl/tx_control.v
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2023/03/21 18:35:38
// Design Name:
// Module Name: tx_control
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tx_control
(
input sys_clk , // 122.88MHz
input sys_rst ,
input sig_clk , // 48MHz
input sig_rst ,
output [15:0] tx_data_i ,
output [15:0] tx_data_q ,
// debug ports
input [ 2:0] waveform_sel ,
input sweep_on ,
input [31:0] freq_set ,
input [ 1:0] iq_sel ,
input [ 3:0] bb_rshift
);
// pn seq
wire [15:0] tx_pn_seq_i;
wire [15:0] tx_pn_seq_q;
tx_pn_seq_6mcps #(
.DATA_WIDTH (16),
.BIT_DATA (1024'b0000000100100010000011001001101000010010101000011110101110101101101100000000110000011011001100001010110101110001101111110001000111100111101101101000000010100001011010101000111110111100100101100000100110010001010001101101110000001111000111011111110010000110001011011101000011010101100111100101101100100000100010010011000000101100010100111011001110001011111101010001011101101011000011001101101010000011101001111010011010100100111000001111100111001101111010001010101101111100001001110100011101011111011010010000100001010010101100011100111111101100001000110100111001001111000011011101100011000111101111101001001010000001101000110010111010010110100010001011001101001010010001100001110110111100000101110010101110011101110111001100111010101110111101100101000100110110001000011100101111100101001100110010101010011111100110001101011110011010110100110001001011100001011110101010101111111101000001010100101111000101011110111010100110111001000111000111111111100000001110000111111011100010011111000110011111010110010110010010010000000001),
.BIT_DATA_LEN (1024)
) u_tx_pn_seq
(
.sys_clk (sys_clk ), // 122.88MHz
.sys_rst (sys_rst ),
.sig_clk (sig_clk ), // 48MHz
.sig_rst (sig_rst ),
.tx_data_i (tx_pn_seq_i),
.tx_data_q (tx_pn_seq_q)
);
// qpsk
wire [15:0] tx_qpsk_i;
wire [15:0] tx_qpsk_q;
tx_qpsk #(
.DATA_WIDTH (16 ),
.SQUARE_INTERP (32 ),
.CLK_FREQ (122880000 )
) u_tx_qpsk
(
.clk (sys_clk ),
.rst (sys_rst ),
.tx_data_i (tx_qpsk_i ),
.tx_data_q (tx_qpsk_q ),
// debug ports
.waveform_sel (waveform_sel[1:0] ),
.sweep_on (sweep_on ),
.freq_set (freq_set ),
.iq_sel (iq_sel ),
.bb_rshift (bb_rshift )
);
// output
reg [15:0] tx_data_buf_i = 'b0;
reg [15:0] tx_data_buf_q = 'b0;
assign tx_data_i = tx_data_buf_i;
assign tx_data_q = tx_data_buf_q;
always @(posedge sys_clk) begin
if (sys_rst) begin
tx_data_buf_i <= 'b0;
tx_data_buf_q <= 'b0;
end
else if (waveform_sel[2]) begin
tx_data_buf_i <= tx_pn_seq_i;
tx_data_buf_q <= tx_pn_seq_q;
end
else begin
tx_data_buf_i <= tx_qpsk_i;
tx_data_buf_q <= tx_qpsk_q;
end
end
endmodule
projects/dl814_dj/dl814_dj_new_48m/rtl/tx_pn_seq_6mcps.v
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2023/03/21 16:09:18
// Design Name:
// Module Name: tx_pn_seq_6mcps
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tx_pn_seq_6mcps
#(
parameter DATA_WIDTH = 12, // need to be <= 16
parameter BIT_DATA = 128'b00000011000010100011110010001011001110101001111101000011100010010011011010110111101100011010010111011100110010101011111110000001, // inverse pseudorandom bit sequence, [0,flip(PRSB7)]
parameter BIT_DATA_LEN = 128,
parameter SQUARE_INTERP = 8
)
(
input sys_clk , // 122.88MHz
input sys_rst ,
input sig_clk , // 48MHz
input sig_rst ,
output [DATA_WIDTH-1:0] tx_data_i ,
output [DATA_WIDTH-1:0] tx_data_q
);
localparam MAX_DATA_WIDTH = 16;
integer i;
genvar m;
////////////////////////////////////////////////////////////////////////////////
///////////////////////////////// Data Counter /////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// symbol & interpolation counter
reg [$clog2(SQUARE_INTERP*BIT_DATA_LEN)-1 : 0] cnt = 'b0;
always @(posedge sig_clk) begin
if (sig_rst) begin
cnt <= 'b0;
end
else begin
cnt <= (cnt == SQUARE_INTERP*BIT_DATA_LEN - 1) ? 'b0 : cnt + 16'b1;
end
end
////////////////////////////////////////////////////////////////////////////////
//////////////////////////// Square Shaping Filter /////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// address
reg [$clog2(BIT_DATA_LEN)-1 : 0] hsq_data_addr = 'b0;
always @(posedge sig_clk) begin
if (sig_rst) begin
hsq_data_addr <= 'b0;
end
else
hsq_data_addr <= {cnt[$clog2(SQUARE_INTERP) +: $clog2(BIT_DATA_LEN)]};
end
// bit data
reg hsq_data = 'b0;
always @(posedge sig_clk) begin
if (sig_rst) begin
hsq_data <= 'b0;
end
else begin
hsq_data <= BIT_DATA[hsq_data_addr];
end
end
// square shaping-filter
reg [MAX_DATA_WIDTH-1 : 0] hsq_wave [0:1];
always @(posedge sig_clk) begin
if (sig_rst) begin
for (i = 0; i < 2; i = i + 1) begin
hsq_wave[i] <= 'b0;
end
end
else begin
hsq_wave[0] <= hsq_data ? {1'b0,{(MAX_DATA_WIDTH-2){1'b1}},1'b1} : {1'b1,{(MAX_DATA_WIDTH-2){1'b0}},1'b1};
hsq_wave[1] <= hsq_data ? {1'b1,{(MAX_DATA_WIDTH-2){1'b0}},1'b1} : {1'b0,{(MAX_DATA_WIDTH-2){1'b1}},1'b1};
end
end
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// Resampling //////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
wire cdc_fifo_s_axis_valid [0:1];
wire cdc_fifo_s_axis_ready [0:1];
wire [15:0] cdc_fifo_s_axis_tdata [0:1];
wire lpf_s_axis_valid [0:1];
wire lpf_s_axis_ready [0:1];
wire [15:0] lpf_s_axis_tdata [0:1];
wire lpf_m_axis_valid [0:1];
wire [39:0] lpf_m_axis_tdata [0:1];
generate
for (m = 0; m < 2; m = m + 1) begin: cdc_resample
assign cdc_fifo_s_axis_tdata[m] = hsq_wave[m];
assign cdc_fifo_s_axis_valid[m] = ~sig_rst;
fifo_48m_to_122p88m u_fifo_cdc
(
.wr_rst_busy ( ), // output wire wr_rst_busy
.rd_rst_busy ( ), // output wire rd_rst_busy
.m_aclk (sys_clk ), // input wire m_aclk
.s_aclk (sig_clk ), // input wire s_aclk
.s_aresetn (~sig_rst ), // input wire s_aresetn
.s_axis_tvalid (cdc_fifo_s_axis_valid[m] ), // input wire s_axis_tvalid
.s_axis_tready (cdc_fifo_s_axis_ready[m] ), // output wire s_axis_tready
.s_axis_tdata (cdc_fifo_s_axis_tdata[m] ), // input wire [15 : 0] s_axis_tdata
.m_axis_tvalid (lpf_s_axis_valid[m] ), // output wire m_axis_tvalid
.m_axis_tready (lpf_s_axis_ready[m] ), // input wire m_axis_tready
.m_axis_tdata (lpf_s_axis_tdata[m] ) // output wire [15 : 0] m_axis_tdata
);
lpf_125k u_resample_lpf
(
.aclk (sys_clk ), // input wire aclk
.s_axis_data_tvalid (lpf_s_axis_valid[m] ), // input wire s_axis_data_tvalid
.s_axis_data_tready (lpf_s_axis_ready[m] ), // output wire s_axis_data_tready
.s_axis_data_tdata (lpf_s_axis_tdata[m] ), // input wire [15 : 0] s_axis_data_tdata
.m_axis_data_tvalid (lpf_m_axis_valid[m] ), // output wire m_axis_data_tvalid
.m_axis_data_tdata (lpf_m_axis_tdata[m] ) // output wire [39 : 0] m_axis_data_tdata
);
end
endgenerate
assign tx_data_i = lpf_m_axis_tdata[0][31 -: DATA_WIDTH];
assign tx_data_q = lpf_m_axis_tdata[1][31 -: DATA_WIDTH];
endmodule
projects/dl814_dj/dl814_dj_new_48m/rtl/tx_wave.v
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/23/2023 06:52:21 PM
// Design Name:
// Module Name: tx_wave
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tx_wave(
);
endmodule