Archived
change rotate to radians, fix phase comp port connections
This commit is contained in:
+64
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<?xml version="1.0" encoding="UTF-8"?>
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<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
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<spirit:library>ipcache</spirit:library>
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<spirit:name>35ef934e18fcbb85</spirit:name>
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<spirit:version>0</spirit:version>
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<spirit:componentInstances>
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<spirit:componentInstance>
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<spirit:instanceName>atan2_16b</spirit:instanceName>
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<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="cordic" spirit:version="6.0"/>
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<spirit:configurableElementValues>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.FREQ_HZ">1000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.FREQ_HZ">100000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.FREQ_HZ">100000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACLKEN">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARESETN">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Architectural_Configuration">Parallel</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coarse_Rotation">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Compensation_Scaling">No_Scale_Compensation</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">atan2_16b</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Format">SignedFraction</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Functional_Selection">Arc_Tan</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Width">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Iterations">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Width">16</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phase_Format">Radians</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pipelining_Mode">Maximum</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Precision">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Round_Mode">Truncate</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cartesian_has_tlast">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cartesian_has_tuser">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cartesian_tuser_width">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.flow_control">NonBlocking</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.optimize_goal">Performance</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.out_tlast_behv">Null</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.out_tready">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.phase_has_tlast">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.phase_has_tuser">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.phase_tuser_width">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">35ef934e18fcbb85</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">fa73b4fd</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">22</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">15</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.3</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
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</spirit:configurableElementValues>
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</spirit:componentInstance>
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</spirit:componentInstances>
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</spirit:design>
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+25
@@ -0,0 +1,25 @@
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// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Mon Jun 5 20:29:00 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
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||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
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||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ atan2_16b_stub.v
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// Design : atan2_16b
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||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
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||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
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||||
(* x_core_info = "cordic_v6_0_15,Vivado 2019.1.3" *)
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module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, s_axis_cartesian_tvalid,
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s_axis_cartesian_tdata, m_axis_dout_tvalid, m_axis_dout_tdata)
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/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_cartesian_tvalid,s_axis_cartesian_tdata[31:0],m_axis_dout_tvalid,m_axis_dout_tdata[15:0]" */;
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input aclk;
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input s_axis_cartesian_tvalid;
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input [31:0]s_axis_cartesian_tdata;
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output m_axis_dout_tvalid;
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output [15:0]m_axis_dout_tdata;
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endmodule
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||||
+34
@@ -0,0 +1,34 @@
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-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Mon Jun 5 20:29:00 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ atan2_16b_stub.vhdl
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||||
-- Design : atan2_16b
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||||
-- Purpose : Stub declaration of top-level module interface
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||||
-- Device : xc7k410tffg900-2
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||||
-- --------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
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Port (
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aclk : in STD_LOGIC;
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s_axis_cartesian_tvalid : in STD_LOGIC;
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||||
s_axis_cartesian_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
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m_axis_dout_tvalid : out STD_LOGIC;
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||||
m_axis_dout_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 )
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);
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||||
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end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
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architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
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attribute syn_black_box : boolean;
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attribute black_box_pad_pin : string;
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attribute syn_black_box of stub : architecture is true;
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||||
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_cartesian_tvalid,s_axis_cartesian_tdata[31:0],m_axis_dout_tvalid,m_axis_dout_tdata[15:0]";
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attribute x_core_info : string;
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||||
attribute x_core_info of stub : architecture is "cordic_v6_0_15,Vivado 2019.1.3";
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begin
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end;
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+65
@@ -0,0 +1,65 @@
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<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>ipcache</spirit:library>
|
||||
<spirit:name>6d0942f1ca8f60d5</spirit:name>
|
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<spirit:version>0</spirit:version>
|
||||
<spirit:componentInstances>
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<spirit:componentInstance>
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<spirit:instanceName>rotate_16b</spirit:instanceName>
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<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="cordic" spirit:version="6.0"/>
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<spirit:configurableElementValues>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.FREQ_HZ">1000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.FREQ_HZ">100000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.FREQ_HZ">100000000</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACLKEN">false</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARESETN">false</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Architectural_Configuration">Parallel</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coarse_Rotation">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Compensation_Scaling">No_Scale_Compensation</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">rotate_16b</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Format">SignedFraction</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Functional_Selection">Rotate</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Width">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Iterations">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Width">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phase_Format">Radians</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pipelining_Mode">Maximum</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Precision">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Round_Mode">Truncate</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cartesian_has_tlast">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cartesian_has_tuser">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cartesian_tuser_width">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.flow_control">NonBlocking</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.optimize_goal">Performance</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.out_tlast_behv">Null</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.out_tready">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.phase_has_tlast">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.phase_has_tuser">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.phase_tuser_width">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">6d0942f1ca8f60d5</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">fa73b4fd</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">24</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">15</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
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+28
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// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Mon Jun 5 20:28:45 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rotate_16b_stub.v
|
||||
// Design : rotate_16b
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "cordic_v6_0_15,Vivado 2019.1.3" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, s_axis_phase_tvalid,
|
||||
s_axis_phase_tdata, s_axis_cartesian_tvalid, s_axis_cartesian_tdata,
|
||||
m_axis_dout_tvalid, m_axis_dout_tdata)
|
||||
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_phase_tvalid,s_axis_phase_tdata[15:0],s_axis_cartesian_tvalid,s_axis_cartesian_tdata[31:0],m_axis_dout_tvalid,m_axis_dout_tdata[31:0]" */;
|
||||
input aclk;
|
||||
input s_axis_phase_tvalid;
|
||||
input [15:0]s_axis_phase_tdata;
|
||||
input s_axis_cartesian_tvalid;
|
||||
input [31:0]s_axis_cartesian_tdata;
|
||||
output m_axis_dout_tvalid;
|
||||
output [31:0]m_axis_dout_tdata;
|
||||
endmodule
|
||||
+36
@@ -0,0 +1,36 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Mon Jun 5 20:28:45 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rotate_16b_stub.vhdl
|
||||
-- Design : rotate_16b
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
aclk : in STD_LOGIC;
|
||||
s_axis_phase_tvalid : in STD_LOGIC;
|
||||
s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
s_axis_cartesian_tvalid : in STD_LOGIC;
|
||||
s_axis_cartesian_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axis_dout_tvalid : out STD_LOGIC;
|
||||
m_axis_dout_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_phase_tvalid,s_axis_phase_tdata[15:0],s_axis_cartesian_tvalid,s_axis_cartesian_tdata[31:0],m_axis_dout_tvalid,m_axis_dout_tdata[31:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "cordic_v6_0_15,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+6
-6
@@ -1,13 +1,13 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:3238:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3634:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3636:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:33:00:00
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6d616e6167655f6970:39:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:333234:00:00
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
@@ -24,16 +24,16 @@ version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f636c6f73655f70726f6a656374:3130:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f636f70795f6970:3133:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f67656e65726174655f636f6d706f736974655f66696c65:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6f70656e5f69705f6c6f636174696f6e:37:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6f70656e5f69705f6c6f636174696f6e:38:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f72657365745f636f6d706f736974655f66696c65:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f67726573736469616c6f675f6261636b67726f756e64:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f64656c657465:31:00:00
|
||||
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|
||||
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|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d706c656f757470757470726f647563746469616c6f675f67656e65726174655f6f75747075745f70726f64756374735f696d6d6564696174656c79:3139:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d706c656f757470757470726f647563746469616c6f675f67656e65726174655f6f75747075745f70726f64756374735f696d6d6564696174656c79:3231:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d706c656f757470757470726f647563746469616c6f675f72657365745f6f75747075745f70726f6475637473:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f636f6e666967757261626c655f69705f66696c6573:3135:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6d616b655f6c6f63616c5f636f70795f6f665f74686573655f66696c65735f696e746f:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f69705f646f63756d656e746174696f6e:3139:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636167657474696e6773746172746564766965775f726563656e745f69705f6c6f636174696f6e73:36:00:00
|
||||
eof:162730464
|
||||
eof:1509944053
|
||||
|
||||
+3
-3
@@ -6,8 +6,8 @@ version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:39:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6d616e616765636f6d706f7369746574617267657473:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657769706c6f636174696f6e68616e646c6572:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e69706c6f636174696f6e68616e646c6572:38:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e69706c6f636174696f6e68616e646c6572:39:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726576696f7573697068616e646c6572:36:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726f6a656374:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265637573746f6d697a65636f7265:3630:00:00
|
||||
eof:63932490
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265637573746f6d697a65636f7265:3632:00:00
|
||||
eof:3995730525
|
||||
|
||||
+1
-1
@@ -1,3 +1,3 @@
|
||||
version:1
|
||||
6d6f64655f636f756e7465727c4755494d6f6465:14
|
||||
6d6f64655f636f756e7465727c4755494d6f6465:15
|
||||
eof:
|
||||
|
||||
+5
-5
@@ -1,7 +1,7 @@
|
||||
version:1
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:7863376b343130746666673930302d32:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:696c615f387831325f38313932:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:6174616e325f313662:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
@@ -33,7 +33,7 @@ version:1
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a353873:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323332332e3438304d42:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3930362e3039304d42:00:00
|
||||
eof:3884629691
|
||||
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a313773:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323039312e3437374d42:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3639302e3535394d42:00:00
|
||||
eof:3006227906
|
||||
|
||||
+10
-10
@@ -3,7 +3,7 @@
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="pa" timeStamp="Sun May 7 16:50:26 2023">
|
||||
<application name="pa" timeStamp="Mon Jun 5 20:29:05 2023">
|
||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="cf48733ed6784c129006f962746a20c1" type="ProjectID"/>
|
||||
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
|
||||
@@ -24,21 +24,21 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
<property name="EditDelete" value="9" type="JavaHandler"/>
|
||||
<property name="ManageCompositeTargets" value="5" type="JavaHandler"/>
|
||||
<property name="NewIPLocationHandler" value="1" type="JavaHandler"/>
|
||||
<property name="OpenIPLocationHandler" value="8" type="JavaHandler"/>
|
||||
<property name="OpenIPLocationHandler" value="9" type="JavaHandler"/>
|
||||
<property name="OpenPreviousIPHandler" value="6" type="JavaHandler"/>
|
||||
<property name="OpenProject" value="1" type="JavaHandler"/>
|
||||
<property name="RecustomizeCore" value="60" type="JavaHandler"/>
|
||||
<property name="RecustomizeCore" value="62" type="JavaHandler"/>
|
||||
</item>
|
||||
<item name="Gui Handlers">
|
||||
<property name="BaseDialog_CANCEL" value="28" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_OK" value="64" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_OK" value="66" type="GuiHandlerData"/>
|
||||
<property name="CmdMsgDialog_OK" value="3" type="GuiHandlerData"/>
|
||||
<property name="CopyIPHandler_DESTINATION_IP_NAME" value="12" type="GuiHandlerData"/>
|
||||
<property name="CoreTreeTablePanel_CORE_TREE_TABLE" value="15" type="GuiHandlerData"/>
|
||||
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="19" type="GuiHandlerData"/>
|
||||
<property name="FPGAChooser_FPGA_TABLE" value="1" type="GuiHandlerData"/>
|
||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="318" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_MANAGE_IP" value="9" type="GuiHandlerData"/>
|
||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="324" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_MANAGE_IP" value="10" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_OPEN_PROJECT" value="1" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_START_USING_VIVADO_WITH_IP_CATALOG" value="3" type="GuiHandlerData"/>
|
||||
<property name="HACGCIPSymbol_SHOW_DISABLED_PORTS" value="1" type="GuiHandlerData"/>
|
||||
@@ -55,13 +55,13 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
<property name="PACommandNames_CLOSE_PROJECT" value="10" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_COPY_IP" value="13" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_GENERATE_COMPOSITE_FILE" value="3" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_OPEN_IP_LOCATION" value="7" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_OPEN_IP_LOCATION" value="8" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_RESET_COMPOSITE_FILE" value="2" type="GuiHandlerData"/>
|
||||
<property name="ProgressDialog_BACKGROUND" value="5" type="GuiHandlerData"/>
|
||||
<property name="RDICommands_DELETE" value="1" type="GuiHandlerData"/>
|
||||
<property name="RemoveSourcesDialog_ALSO_DELETE" value="8" type="GuiHandlerData"/>
|
||||
<property name="SimpleOutputProductDialog_CLOSE_DIALOG_UNSAVED_CHANGES_WILL" value="6" type="GuiHandlerData"/>
|
||||
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="19" type="GuiHandlerData"/>
|
||||
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="21" type="GuiHandlerData"/>
|
||||
<property name="SimpleOutputProductDialog_RESET_OUTPUT_PRODUCTS" value="1" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_ADD_CONFIGURABLE_IP_FILES" value="15" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_MAKE_LOCAL_COPY_OF_THESE_FILES_INTO" value="1" type="GuiHandlerData"/>
|
||||
@@ -69,9 +69,9 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
<property name="SyntheticaGettingStartedView_RECENT_IP_LOCATIONS" value="6" type="GuiHandlerData"/>
|
||||
</item>
|
||||
<item name="Other">
|
||||
<property name="GuiMode" value="116" type="GuiMode"/>
|
||||
<property name="GuiMode" value="9" type="GuiMode"/>
|
||||
<property name="BatchMode" value="0" type="BatchMode"/>
|
||||
<property name="TclMode" value="82" type="TclMode"/>
|
||||
<property name="TclMode" value="4" type="TclMode"/>
|
||||
</item>
|
||||
</section>
|
||||
</application>
|
||||
|
||||
+8
@@ -0,0 +1,8 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="rotate_16b_synth_1" LaunchDir="/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
</Runs>
|
||||
|
||||
+8
@@ -0,0 +1,8 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="atan2_16b_synth_1" LaunchDir="/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
</Runs>
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="add_s24_s32_s32_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681300767">
|
||||
<File Type="RDS-UTIL" Name="add_s24_s32_s32_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="add_s24_s32_s32_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="add_s24_s32_s32_utilization_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="add_s24_s32_s32.vds"/>
|
||||
<File Type="RDS-DCP" Name="add_s24_s32_s32.dcp"/>
|
||||
<File Type="PA-TCL" Name="add_s24_s32_s32.tcl"/>
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="ant_clk_gen_stg1_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681300767">
|
||||
<File Type="RDS-UTIL" Name="ant_clk_gen_stg1_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="ant_clk_gen_stg1_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="ant_clk_gen_stg1_utilization_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="ant_clk_gen_stg1.vds"/>
|
||||
<File Type="RDS-DCP" Name="ant_clk_gen_stg1.dcp"/>
|
||||
<File Type="PA-TCL" Name="ant_clk_gen_stg1.tcl"/>
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="ant_clk_gen_stg2_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681300767">
|
||||
<File Type="RDS-UTIL" Name="ant_clk_gen_stg2_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="ant_clk_gen_stg2_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="ant_clk_gen_stg2_utilization_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="ant_clk_gen_stg2.vds"/>
|
||||
<File Type="RDS-DCP" Name="ant_clk_gen_stg2.dcp"/>
|
||||
<File Type="PA-TCL" Name="ant_clk_gen_stg2.tcl"/>
|
||||
|
||||
+1
-1
@@ -1,5 +1,5 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado" Owner="josh" Host="JOSH-ASUS-Z690" Pid="277330" HostCore="20" HostMemory="65589000">
|
||||
<Process Command="vivado" Owner="josh" Host="JOSH-ASUS-Z690" Pid="1070164" HostCore="20" HostMemory="65588996">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
|
||||
BIN
Binary file not shown.
-2
@@ -17,8 +17,6 @@ proc create_report { reportName command } {
|
||||
send_msg_id runtcl-5 warning "$msg"
|
||||
}
|
||||
}
|
||||
set_param simulator.modelsimInstallPath /home/josh/Software/Mentor/modeltech/bin
|
||||
set_param simulator.vcsmxInstallPath /usr/synopsys/vcs/T-2022.06/bin
|
||||
set_param project.vivado.isBlockSynthRun true
|
||||
set_msg_config -msgmgr_mode ooc_run
|
||||
create_project -in_memory -part xc7k410tffg900-2
|
||||
|
||||
+50
-51
@@ -2,8 +2,8 @@
|
||||
# Vivado v2019.1.3 (64-bit)
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
# Start of session at: Wed Apr 12 19:59:29 2023
|
||||
# Process ID: 277922
|
||||
# Start of session at: Mon Jun 5 20:28:34 2023
|
||||
# Process ID: 1070203
|
||||
# Current directory: /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1
|
||||
# Command line: vivado -log atan2_16b.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source atan2_16b.tcl
|
||||
# Log file: /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b.vds
|
||||
@@ -16,9 +16,9 @@ Attempting to get a license for feature 'Synthesis' and/or device 'xc7k410t'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k410t'
|
||||
INFO: [Device 21-403] Loading part xc7k410tffg900-2
|
||||
INFO: Launching helper process for spawning children vivado processes
|
||||
INFO: Helper process launched with PID 278285
|
||||
INFO: Helper process launched with PID 1070336
|
||||
---------------------------------------------------------------------------------
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 1824.492 ; gain = 152.719 ; free physical = 675 ; free virtual = 44056
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1825.977 ; gain = 153.719 ; free physical = 1830 ; free virtual = 37269
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-638] synthesizing module 'atan2_16b' [/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/atan2_16b/synth/atan2_16b.vhd:69]
|
||||
Parameter C_ARCHITECTURE bound to: 2 - type: integer
|
||||
@@ -34,7 +34,7 @@ INFO: [Synth 8-638] synthesizing module 'atan2_16b' [/home/josh/Workspace/vivado
|
||||
Parameter C_INPUT_WIDTH bound to: 16 - type: integer
|
||||
Parameter C_ITERATIONS bound to: 0 - type: integer
|
||||
Parameter C_OUTPUT_WIDTH bound to: 16 - type: integer
|
||||
Parameter C_PHASE_FORMAT bound to: 1 - type: integer
|
||||
Parameter C_PHASE_FORMAT bound to: 0 - type: integer
|
||||
Parameter C_PIPELINE_MODE bound to: -2 - type: integer
|
||||
Parameter C_PRECISION bound to: 0 - type: integer
|
||||
Parameter C_ROUND_MODE bound to: 0 - type: integer
|
||||
@@ -155,7 +155,7 @@ WARNING: [Synth 8-3331] design c_addsub_v12_0_13_legacy has unconnected port a_s
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_legacy has unconnected port b_signed
|
||||
INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1926.211 ; gain = 254.438 ; free physical = 6153 ; free virtual = 48543
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1926.695 ; gain = 254.438 ; free physical = 2821 ; free virtual = 38104
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
@@ -168,10 +168,10 @@ Report Check Netlist:
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1926.211 ; gain = 254.438 ; free physical = 6276 ; free virtual = 48667
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1926.695 ; gain = 254.438 ; free physical = 2820 ; free virtual = 38105
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1926.211 ; gain = 254.438 ; free physical = 6276 ; free virtual = 48666
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1926.695 ; gain = 254.438 ; free physical = 2820 ; free virtual = 38105
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Netlist 29-17] Analyzing 1931 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
@@ -185,30 +185,30 @@ Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/ma
|
||||
Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/dont_touch.xdc]
|
||||
Completed Processing XDC Constraints
|
||||
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2090.992 ; gain = 0.000 ; free physical = 6905 ; free virtual = 49302
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2091.477 ; gain = 0.000 ; free physical = 2695 ; free virtual = 37993
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2090.992 ; gain = 0.000 ; free physical = 6897 ; free virtual = 49296
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2091.477 ; gain = 0.000 ; free physical = 2695 ; free virtual = 37993
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 7497 ; free virtual = 49905
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2766 ; free virtual = 38073
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7k410tffg900-2
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 7497 ; free virtual = 49905
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2766 ; free virtual = 38073
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying 'set_property' XDC Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
Applied set_property DONT_TOUCH = true for U0. (constraint file /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/dont_touch.xdc, line 9).
|
||||
---------------------------------------------------------------------------------
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 7496 ; free virtual = 49904
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2766 ; free virtual = 38073
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 7580 ; free virtual = 50002
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2763 ; free virtual = 38072
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
@@ -276,26 +276,25 @@ INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[17]' (FDR) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[19]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[18]' (FDR) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[19]'
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[19] )
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[0]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[0]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[10]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[1]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[2]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[3]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[4]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[5]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[6]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[7]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[8]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[9]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[10]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[11]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[12]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[13]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[14]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[15]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[17]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[18]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[18]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[19]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[6]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[11]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[7]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[8]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[8]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[9]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[9]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[12]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[10]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[13]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[11]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[14]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[12]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[15]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[13]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[16]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[14]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[18]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[15]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[19]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[17]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 8146 ; free virtual = 50611
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2788 ; free virtual = 38104
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
@@ -307,13 +306,13 @@ Report RTL Partitions:
|
||||
Start Applying XDC Timing Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:25 ; elapsed = 00:00:29 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 8656 ; free virtual = 51196
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2643 ; free virtual = 37981
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:25 ; elapsed = 00:00:29 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 8735 ; free virtual = 51282
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2637 ; free virtual = 37975
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
@@ -325,7 +324,7 @@ Report RTL Partitions:
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:25 ; elapsed = 00:00:30 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 8641 ; free virtual = 51225
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2634 ; free virtual = 37976
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
@@ -349,7 +348,7 @@ Start Final Netlist Cleanup
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:26 ; elapsed = 00:00:30 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 8644 ; free virtual = 51253
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2632 ; free virtual = 37976
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
@@ -362,7 +361,7 @@ Report Check Netlist:
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:26 ; elapsed = 00:00:30 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 8643 ; free virtual = 51252
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2632 ; free virtual = 37976
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
@@ -374,25 +373,25 @@ Report RTL Partitions:
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:26 ; elapsed = 00:00:30 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 8614 ; free virtual = 51232
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2632 ; free virtual = 37976
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:26 ; elapsed = 00:00:30 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 8609 ; free virtual = 51229
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2632 ; free virtual = 37976
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:26 ; elapsed = 00:00:30 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 8600 ; free virtual = 51220
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2632 ; free virtual = 37976
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:26 ; elapsed = 00:00:30 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 8599 ; free virtual = 51220
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2632 ; free virtual = 37976
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
@@ -408,46 +407,46 @@ Report Cell Usage:
|
||||
+------+--------+------+
|
||||
| |Cell |Count |
|
||||
+------+--------+------+
|
||||
|1 |LUT1 | 69|
|
||||
|2 |LUT2 | 344|
|
||||
|3 |LUT3 | 527|
|
||||
|1 |LUT1 | 65|
|
||||
|2 |LUT2 | 335|
|
||||
|3 |LUT3 | 537|
|
||||
|4 |LUT4 | 32|
|
||||
|5 |MUXCY | 838|
|
||||
|6 |SRL16E | 5|
|
||||
|7 |SRLC32E | 1|
|
||||
|8 |XORCY | 806|
|
||||
|9 |FDRE | 929|
|
||||
|9 |FDRE | 930|
|
||||
+------+--------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:26 ; elapsed = 00:00:30 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 8598 ; free virtual = 51219
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2632 ; free virtual = 37976
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 308 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 2090.992 ; gain = 254.438 ; free physical = 8624 ; free virtual = 51252
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:26 ; elapsed = 00:00:31 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 8622 ; free virtual = 51251
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 2091.477 ; gain = 254.438 ; free physical = 2684 ; free virtual = 38028
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2684 ; free virtual = 38028
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
INFO: [Netlist 29-17] Analyzing 1644 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2090.992 ; gain = 0.000 ; free physical = 9379 ; free virtual = 52041
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2091.477 ; gain = 0.000 ; free physical = 2623 ; free virtual = 37972
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
A total of 222 instances were transformed.
|
||||
(MUXCY,XORCY) => CARRY4: 222 instances
|
||||
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
70 Infos, 100 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
69 Infos, 100 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2090.992 ; gain = 697.527 ; free physical = 9577 ; free virtual = 52238
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2090.992 ; gain = 0.000 ; free physical = 9589 ; free virtual = 52251
|
||||
synth_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 2091.477 ; gain = 696.496 ; free physical = 2715 ; free virtual = 38064
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2091.477 ; gain = 0.000 ; free physical = 2715 ; free virtual = 38064
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b.dcp' has been generated.
|
||||
WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used.
|
||||
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP atan2_16b, cache-ID = d02f40fcf613a5a3
|
||||
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP atan2_16b, cache-ID = 35ef934e18fcbb85
|
||||
INFO: [Coretcl 2-1174] Renamed 350 cell refs.
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2115.004 ; gain = 0.000 ; free physical = 10245 ; free virtual = 52938
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2115.488 ; gain = 0.000 ; free physical = 2711 ; free virtual = 38080
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file atan2_16b_utilization_synth.rpt -pb atan2_16b_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Wed Apr 12 20:00:13 2023...
|
||||
INFO: [Common 17-206] Exiting Vivado at Mon Jun 5 20:29:01 2023...
|
||||
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
+1
-1
@@ -1,7 +1,7 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Wed Apr 12 20:00:12 2023
|
||||
// Date : Mon Jun 5 20:29:00 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_stub.v
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Wed Apr 12 20:00:12 2023
|
||||
-- Date : Mon Jun 5 20:29:01 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_stub.vhdl
|
||||
|
||||
BIN
Binary file not shown.
+10
-10
@@ -1,7 +1,7 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
| Date : Wed Apr 12 20:00:12 2023
|
||||
| Date : Mon Jun 5 20:29:00 2023
|
||||
| Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
| Command : report_utilization -file atan2_16b_utilization_synth.rpt -pb atan2_16b_utilization_synth.pb
|
||||
| Design : atan2_16b
|
||||
@@ -30,13 +30,13 @@ Table of Contents
|
||||
+----------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+----------------------------+------+-------+-----------+-------+
|
||||
| Slice LUTs* | 961 | 0 | 254200 | 0.38 |
|
||||
| LUT as Logic | 955 | 0 | 254200 | 0.38 |
|
||||
| Slice LUTs* | 958 | 0 | 254200 | 0.38 |
|
||||
| LUT as Logic | 952 | 0 | 254200 | 0.37 |
|
||||
| LUT as Memory | 6 | 0 | 90600 | <0.01 |
|
||||
| LUT as Distributed RAM | 0 | 0 | | |
|
||||
| LUT as Shift Register | 6 | 0 | | |
|
||||
| Slice Registers | 929 | 0 | 508400 | 0.18 |
|
||||
| Register as Flip Flop | 929 | 0 | 508400 | 0.18 |
|
||||
| Slice Registers | 930 | 0 | 508400 | 0.18 |
|
||||
| Register as Flip Flop | 930 | 0 | 508400 | 0.18 |
|
||||
| Register as Latch | 0 | 0 | 508400 | 0.00 |
|
||||
| F7 Muxes | 0 | 0 | 127100 | 0.00 |
|
||||
| F8 Muxes | 0 | 0 | 63550 | 0.00 |
|
||||
@@ -59,7 +59,7 @@ Table of Contents
|
||||
| 0 | Yes | - | Set |
|
||||
| 0 | Yes | - | Reset |
|
||||
| 0 | Yes | Set | - |
|
||||
| 929 | Yes | Reset | - |
|
||||
| 930 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
@@ -153,11 +153,11 @@ Table of Contents
|
||||
+----------+------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+----------+------+---------------------+
|
||||
| FDRE | 929 | Flop & Latch |
|
||||
| LUT3 | 527 | LUT |
|
||||
| LUT2 | 344 | LUT |
|
||||
| FDRE | 930 | Flop & Latch |
|
||||
| LUT3 | 537 | LUT |
|
||||
| LUT2 | 335 | LUT |
|
||||
| CARRY4 | 222 | CarryLogic |
|
||||
| LUT1 | 69 | LUT |
|
||||
| LUT1 | 65 | LUT |
|
||||
| LUT4 | 32 | LUT |
|
||||
| SRL16E | 5 | Distributed Memory |
|
||||
| SRLC32E | 1 | Distributed Memory |
|
||||
|
||||
+12
-9
@@ -1,20 +1,23 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="atan2_16b_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681300767">
|
||||
<File Type="RDS-UTIL" Name="atan2_16b_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="atan2_16b_utilization_synth.pb"/>
|
||||
<File Type="RDS-RDS" Name="atan2_16b.vds"/>
|
||||
<GenRun Id="atan2_16b_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1685968113">
|
||||
<File Type="VDS-TIMING-PB" Name="atan2_16b_timing_summary_synth.pb"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="atan2_16b_timing_summary_synth.rpt"/>
|
||||
<File Type="RDS-DCP" Name="atan2_16b.dcp"/>
|
||||
<File Type="PA-TCL" Name="atan2_16b.tcl"/>
|
||||
<File Type="RDS-UTIL-PB" Name="atan2_16b_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="atan2_16b_utilization_synth.rpt"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="atan2_16b_drc_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="atan2_16b.vds"/>
|
||||
<File Type="REPORTS-TCL" Name="atan2_16b_reports.tcl"/>
|
||||
<File Type="PA-TCL" Name="atan2_16b.tcl"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/atan2_16b">
|
||||
<File Path="$PPRDIR/../rx_pre_process/atan2_16b/atan2_16b.xci">
|
||||
<File Path="$PPRDIR/../rx_pre_process/atan2_16b.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../rx_pre_process/atan2_16b.xcix">
|
||||
<File Path="$PPRDIR/../rx_pre_process/atan2_16b/atan2_16b.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
@@ -27,14 +30,14 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_in" Type="BlockSrcs" RelSrcDir="$PSRCDIR/atan2_16b">
|
||||
<File Path="$PPRDIR/../rx_pre_process/atan2_16b/atan2_16b.xci">
|
||||
<File Path="$PPRDIR/../rx_pre_process/atan2_16b.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../rx_pre_process/atan2_16b.xcix">
|
||||
<File Path="$PPRDIR/../rx_pre_process/atan2_16b/atan2_16b.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
|
||||
+20
-11
@@ -1,13 +1,13 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3136:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3330:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:3136:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:3136:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:3138:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:3138:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00
|
||||
@@ -25,15 +25,24 @@ version:1
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c6669666f5f67656e657261746f725f7631335f325f345c6669666f5f416e744374726c:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c6669666f5f67656e657261746f725f7631335f325f345c6669666f5f6163636f725f636463:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c6669666f5f67656e657261746f725f7631335f325f345c6669666f5f7765696768745f636463:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f327831327831303234:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f3278313278313331303732:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f3478313278313331303732:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f387831325f327833305f313331303732:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f387831325f327833305f38313932:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f387831325f38313932:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f3878313278313331303732:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f416e744374726c:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f63616c:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f7266636f6e74726c:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f72785f7072655f616e74:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f72785f7072655f737973:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c626c6b5f6d656d5f67656e5f76385f345f335c72616d5f686f705f64617461:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c636f726469635f76365f305f31355c726f746174655f313662:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f616e745f7264:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f616e745f74657374:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f636c6b5f6c645f7264:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f6d616e75616c5f6374726c:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f72665f7264:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f7266636f6e74726c:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00
|
||||
@@ -43,12 +52,12 @@ version:1
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3331:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3331:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3331:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3331:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3331:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3331:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3331:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3735:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3735:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3735:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3735:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3735:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3735:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3735:00:00
|
||||
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3239373561633434643362303430613962303236326565396330623238613761:506172656e742050412070726f6a656374204944:00
|
||||
eof:2529481700
|
||||
eof:1296303891
|
||||
|
||||
+2
-2
@@ -12,9 +12,9 @@ var WshShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ProcEnv = WshShell.Environment( "Process" );
|
||||
var PathVal = ProcEnv("PATH");
|
||||
if ( PathVal.length == 0 ) {
|
||||
PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;";
|
||||
PathVal = "/home/josh/Software/Xilinx/SDK/2019.1/bin:/home/josh/Software/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/home/josh/Software/Xilinx/Vivado/2019.1/bin;";
|
||||
} else {
|
||||
PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;" + PathVal;
|
||||
PathVal = "/home/josh/Software/Xilinx/SDK/2019.1/bin:/home/josh/Software/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/home/josh/Software/Xilinx/Vivado/2019.1/bin;" + PathVal;
|
||||
}
|
||||
|
||||
ProcEnv("PATH") = PathVal;
|
||||
|
||||
+2
-2
@@ -7,9 +7,9 @@
|
||||
#
|
||||
|
||||
if [ -z "$PATH" ]; then
|
||||
PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin
|
||||
PATH=/home/josh/Software/Xilinx/SDK/2019.1/bin:/home/josh/Software/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/home/josh/Software/Xilinx/Vivado/2019.1/bin
|
||||
else
|
||||
PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin:$PATH
|
||||
PATH=/home/josh/Software/Xilinx/SDK/2019.1/bin:/home/josh/Software/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/home/josh/Software/Xilinx/Vivado/2019.1/bin:$PATH
|
||||
fi
|
||||
export PATH
|
||||
|
||||
|
||||
BIN
Binary file not shown.
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="cmpy_12x12_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681300767">
|
||||
<File Type="RDS-UTIL" Name="cmpy_12x12_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="cmpy_12x12_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="cmpy_12x12_utilization_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="cmpy_12x12.vds"/>
|
||||
<File Type="RDS-DCP" Name="cmpy_12x12.dcp"/>
|
||||
<File Type="PA-TCL" Name="cmpy_12x12.tcl"/>
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="cmpy_16x12_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681300768">
|
||||
<File Type="RDS-UTIL" Name="cmpy_16x12_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="cmpy_16x12_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="cmpy_16x12_utilization_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="cmpy_16x12.vds"/>
|
||||
<File Type="RDS-DCP" Name="cmpy_16x12.dcp"/>
|
||||
<File Type="PA-TCL" Name="cmpy_16x12.tcl"/>
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="fifo_AntCtrl_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681300768">
|
||||
<File Type="RDS-UTIL" Name="fifo_AntCtrl_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="fifo_AntCtrl_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="fifo_AntCtrl_utilization_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="fifo_AntCtrl.vds"/>
|
||||
<File Type="RDS-DCP" Name="fifo_AntCtrl.dcp"/>
|
||||
<File Type="PA-TCL" Name="fifo_AntCtrl.tcl"/>
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="ila_2x12x1024_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681303807">
|
||||
<File Type="RDS-UTIL" Name="ila_2x12x1024_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="ila_2x12x1024_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="ila_2x12x1024_utilization_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="ila_2x12x1024.vds"/>
|
||||
<File Type="RDS-DCP" Name="ila_2x12x1024.dcp"/>
|
||||
<File Type="PA-TCL" Name="ila_2x12x1024.tcl"/>
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="ila_8x12_2x30_131072_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681303790">
|
||||
<File Type="RDS-UTIL" Name="ila_8x12_2x30_131072_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="ila_8x12_2x30_131072_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="ila_8x12_2x30_131072_utilization_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="ila_8x12_2x30_131072.vds"/>
|
||||
<File Type="RDS-DCP" Name="ila_8x12_2x30_131072.dcp"/>
|
||||
<File Type="PA-TCL" Name="ila_8x12_2x30_131072.tcl"/>
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="ila_8x12_2x30_8192_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681882578">
|
||||
<File Type="RDS-UTIL-PB" Name="ila_8x12_2x30_8192_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="ila_8x12_2x30_8192_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="ila_8x12_2x30_8192_utilization_synth.pb"/>
|
||||
<File Type="RDS-RDS" Name="ila_8x12_2x30_8192.vds"/>
|
||||
<File Type="RDS-DCP" Name="ila_8x12_2x30_8192.dcp"/>
|
||||
<File Type="PA-TCL" Name="ila_8x12_2x30_8192.tcl"/>
|
||||
|
||||
+6
-11
@@ -1,14 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="ila_8x12_8192_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1683449288">
|
||||
<File Type="VDS-TIMING-PB" Name="ila_8x12_8192_timing_summary_synth.pb"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="ila_8x12_8192_timing_summary_synth.rpt"/>
|
||||
<File Type="RDS-DCP" Name="ila_8x12_8192.dcp"/>
|
||||
<File Type="REPORTS-TCL" Name="ila_8x12_8192_reports.tcl"/>
|
||||
<File Type="PA-TCL" Name="ila_8x12_8192.tcl"/>
|
||||
<File Type="RDS-RDS" Name="ila_8x12_8192.vds"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="ila_8x12_8192_drc_synth.rpt"/>
|
||||
<File Type="RDS-UTIL" Name="ila_8x12_8192_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="ila_8x12_8192_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="ila_8x12_8192_utilization_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="ila_8x12_8192.vds"/>
|
||||
<File Type="RDS-DCP" Name="ila_8x12_8192.dcp"/>
|
||||
<File Type="PA-TCL" Name="ila_8x12_8192.tcl"/>
|
||||
<File Type="REPORTS-TCL" Name="ila_8x12_8192_reports.tcl"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ila_8x12_8192">
|
||||
<File Path="$PPRDIR/../basic_driver/ila_8x12_8192/ila_8x12_8192.xci">
|
||||
<FileInfo>
|
||||
@@ -56,9 +53,7 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="ram_hop_data_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681300768">
|
||||
<File Type="RDS-UTIL" Name="ram_hop_data_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="ram_hop_data_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="ram_hop_data_utilization_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="ram_hop_data.vds"/>
|
||||
<File Type="RDS-DCP" Name="ram_hop_data.dcp"/>
|
||||
<File Type="PA-TCL" Name="ram_hop_data.tcl"/>
|
||||
|
||||
+1
-1
@@ -1,5 +1,5 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado" Owner="josh" Host="JOSH-ASUS-Z690" Pid="277393" HostCore="20" HostMemory="65589000">
|
||||
<Process Command="vivado" Owner="josh" Host="JOSH-ASUS-Z690" Pid="1069888" HostCore="20" HostMemory="65588996">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
|
||||
+12
-9
@@ -1,20 +1,23 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="rotate_16b_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681300768">
|
||||
<File Type="RDS-UTIL" Name="rotate_16b_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="rotate_16b_utilization_synth.pb"/>
|
||||
<File Type="RDS-RDS" Name="rotate_16b.vds"/>
|
||||
<GenRun Id="rotate_16b_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1685968098">
|
||||
<File Type="VDS-TIMING-PB" Name="rotate_16b_timing_summary_synth.pb"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="rotate_16b_timing_summary_synth.rpt"/>
|
||||
<File Type="RDS-DCP" Name="rotate_16b.dcp"/>
|
||||
<File Type="PA-TCL" Name="rotate_16b.tcl"/>
|
||||
<File Type="RDS-UTIL-PB" Name="rotate_16b_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="rotate_16b_utilization_synth.rpt"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="rotate_16b_drc_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="rotate_16b.vds"/>
|
||||
<File Type="REPORTS-TCL" Name="rotate_16b_reports.tcl"/>
|
||||
<File Type="PA-TCL" Name="rotate_16b.tcl"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/rotate_16b">
|
||||
<File Path="$PPRDIR/../rx_pre_process/rotate_16b/rotate_16b.xci">
|
||||
<File Path="$PPRDIR/../rx_pre_process/rotate_16b.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../rx_pre_process/rotate_16b.xcix">
|
||||
<File Path="$PPRDIR/../rx_pre_process/rotate_16b/rotate_16b.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
@@ -27,14 +30,14 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_in" Type="BlockSrcs" RelSrcDir="$PSRCDIR/rotate_16b">
|
||||
<File Path="$PPRDIR/../rx_pre_process/rotate_16b/rotate_16b.xci">
|
||||
<File Path="$PPRDIR/../rx_pre_process/rotate_16b.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../rx_pre_process/rotate_16b.xcix">
|
||||
<File Path="$PPRDIR/../rx_pre_process/rotate_16b/rotate_16b.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
|
||||
+20
-11
@@ -1,13 +1,13 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3136:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3330:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:3136:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:3136:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:3138:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:3138:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00
|
||||
@@ -25,15 +25,24 @@ version:1
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c6669666f5f67656e657261746f725f7631335f325f345c6669666f5f416e744374726c:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c6669666f5f67656e657261746f725f7631335f325f345c6669666f5f6163636f725f636463:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c6669666f5f67656e657261746f725f7631335f325f345c6669666f5f7765696768745f636463:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f327831327831303234:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f3278313278313331303732:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f3478313278313331303732:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f387831325f327833305f313331303732:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f387831325f327833305f38313932:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f387831325f38313932:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f3878313278313331303732:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f416e744374726c:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f63616c:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f7266636f6e74726c:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f72785f7072655f616e74:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f72785f7072655f737973:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c626c6b5f6d656d5f67656e5f76385f345f335c72616d5f686f705f64617461:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c636f726469635f76365f305f31355c726f746174655f313662:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f616e745f7264:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f616e745f74657374:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f636c6b5f6c645f7264:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f6d616e75616c5f6374726c:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f72665f7264:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f7266636f6e74726c:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00
|
||||
@@ -43,12 +52,12 @@ version:1
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3331:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3331:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3331:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3331:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3331:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3331:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3331:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3734:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3734:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3734:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3734:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3734:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3734:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3734:00:00
|
||||
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3239373561633434643362303430613962303236326565396330623238613761:506172656e742050412070726f6a656374204944:00
|
||||
eof:2529481700
|
||||
eof:4010926639
|
||||
|
||||
BIN
Binary file not shown.
-2
@@ -17,8 +17,6 @@ proc create_report { reportName command } {
|
||||
send_msg_id runtcl-5 warning "$msg"
|
||||
}
|
||||
}
|
||||
set_param simulator.modelsimInstallPath /home/josh/Software/Mentor/modeltech/bin
|
||||
set_param simulator.vcsmxInstallPath /usr/synopsys/vcs/T-2022.06/bin
|
||||
set_param project.vivado.isBlockSynthRun true
|
||||
set_msg_config -msgmgr_mode ooc_run
|
||||
create_project -in_memory -part xc7k410tffg900-2
|
||||
|
||||
+33
-33
@@ -2,8 +2,8 @@
|
||||
# Vivado v2019.1.3 (64-bit)
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
# Start of session at: Wed Apr 12 19:59:29 2023
|
||||
# Process ID: 277934
|
||||
# Start of session at: Mon Jun 5 20:28:19 2023
|
||||
# Process ID: 1069927
|
||||
# Current directory: /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1
|
||||
# Command line: vivado -log rotate_16b.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source rotate_16b.tcl
|
||||
# Log file: /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b.vds
|
||||
@@ -16,9 +16,9 @@ Attempting to get a license for feature 'Synthesis' and/or device 'xc7k410t'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k410t'
|
||||
INFO: [Device 21-403] Loading part xc7k410tffg900-2
|
||||
INFO: Launching helper process for spawning children vivado processes
|
||||
INFO: Helper process launched with PID 278356
|
||||
INFO: Helper process launched with PID 1070047
|
||||
---------------------------------------------------------------------------------
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 1824.559 ; gain = 152.719 ; free physical = 655 ; free virtual = 44036
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1825.973 ; gain = 153.719 ; free physical = 1803 ; free virtual = 38052
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-638] synthesizing module 'rotate_16b' [/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/rotate_16b/synth/rotate_16b.vhd:71]
|
||||
Parameter C_ARCHITECTURE bound to: 2 - type: integer
|
||||
@@ -34,7 +34,7 @@ INFO: [Synth 8-638] synthesizing module 'rotate_16b' [/home/josh/Workspace/vivad
|
||||
Parameter C_INPUT_WIDTH bound to: 16 - type: integer
|
||||
Parameter C_ITERATIONS bound to: 0 - type: integer
|
||||
Parameter C_OUTPUT_WIDTH bound to: 16 - type: integer
|
||||
Parameter C_PHASE_FORMAT bound to: 1 - type: integer
|
||||
Parameter C_PHASE_FORMAT bound to: 0 - type: integer
|
||||
Parameter C_PIPELINE_MODE bound to: -2 - type: integer
|
||||
Parameter C_PRECISION bound to: 0 - type: integer
|
||||
Parameter C_ROUND_MODE bound to: 0 - type: integer
|
||||
@@ -132,7 +132,7 @@ WARNING: [Synth 8-3331] design cordic_v6_0_15_viv has unconnected port s_axis_ca
|
||||
WARNING: [Synth 8-3331] design cordic_v6_0_15_viv has unconnected port s_axis_cartesian_tlast
|
||||
WARNING: [Synth 8-3331] design cordic_v6_0_15_viv has unconnected port m_axis_dout_tready
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1926.277 ; gain = 254.438 ; free physical = 4487 ; free virtual = 46871
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1927.691 ; gain = 255.438 ; free physical = 1974 ; free virtual = 38030
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
@@ -145,10 +145,10 @@ Report Check Netlist:
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1926.277 ; gain = 254.438 ; free physical = 4434 ; free virtual = 46818
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1927.691 ; gain = 255.438 ; free physical = 1969 ; free virtual = 38025
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1926.277 ; gain = 254.438 ; free physical = 4434 ; free virtual = 46818
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1927.691 ; gain = 255.438 ; free physical = 1969 ; free virtual = 38025
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Netlist 29-17] Analyzing 2136 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
@@ -162,30 +162,30 @@ Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/ma
|
||||
Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/dont_touch.xdc]
|
||||
Completed Processing XDC Constraints
|
||||
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2091.059 ; gain = 0.000 ; free physical = 5179 ; free virtual = 47564
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2089.504 ; gain = 0.000 ; free physical = 1855 ; free virtual = 37773
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2091.059 ; gain = 0.000 ; free physical = 5192 ; free virtual = 47577
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2089.504 ; gain = 0.000 ; free physical = 1941 ; free virtual = 37859
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 2091.059 ; gain = 419.219 ; free physical = 6861 ; free virtual = 49252
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 2089.504 ; gain = 417.250 ; free physical = 1845 ; free virtual = 37746
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7k410tffg900-2
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 2091.059 ; gain = 419.219 ; free physical = 6859 ; free virtual = 49250
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 2089.504 ; gain = 417.250 ; free physical = 1845 ; free virtual = 37745
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying 'set_property' XDC Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
Applied set_property DONT_TOUCH = true for U0. (constraint file /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/dont_touch.xdc, line 9).
|
||||
---------------------------------------------------------------------------------
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 2091.059 ; gain = 419.219 ; free physical = 6859 ; free virtual = 49250
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 2089.504 ; gain = 417.250 ; free physical = 1842 ; free virtual = 37743
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 2091.059 ; gain = 419.219 ; free physical = 6762 ; free virtual = 49155
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 2089.504 ; gain = 417.250 ; free physical = 1845 ; free virtual = 37674
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
@@ -291,7 +291,7 @@ INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synt
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[12].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg'
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg )
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:20 ; elapsed = 00:00:23 . Memory (MB): peak = 2091.059 ; gain = 419.219 ; free physical = 6901 ; free virtual = 49303
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 2089.504 ; gain = 417.250 ; free physical = 1845 ; free virtual = 37646
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
@@ -303,13 +303,13 @@ Report RTL Partitions:
|
||||
Start Applying XDC Timing Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2091.059 ; gain = 419.219 ; free physical = 8181 ; free virtual = 50627
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 2089.504 ; gain = 417.250 ; free physical = 1827 ; free virtual = 37278
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2091.059 ; gain = 419.219 ; free physical = 8146 ; free virtual = 50611
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 2089.504 ; gain = 417.250 ; free physical = 1824 ; free virtual = 37272
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
@@ -321,7 +321,7 @@ Report RTL Partitions:
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2091.059 ; gain = 419.219 ; free physical = 8062 ; free virtual = 50544
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 2089.504 ; gain = 417.250 ; free physical = 1832 ; free virtual = 37277
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
@@ -345,7 +345,7 @@ Start Final Netlist Cleanup
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2091.059 ; gain = 419.219 ; free physical = 8068 ; free virtual = 50573
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 2089.504 ; gain = 417.250 ; free physical = 1825 ; free virtual = 37253
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
@@ -358,7 +358,7 @@ Report Check Netlist:
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2091.059 ; gain = 419.219 ; free physical = 8067 ; free virtual = 50573
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 2089.504 ; gain = 417.250 ; free physical = 1823 ; free virtual = 37251
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
@@ -370,25 +370,25 @@ Report RTL Partitions:
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2091.059 ; gain = 419.219 ; free physical = 8047 ; free virtual = 50558
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 2089.504 ; gain = 417.250 ; free physical = 1816 ; free virtual = 37240
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2091.059 ; gain = 419.219 ; free physical = 8046 ; free virtual = 50557
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 2089.504 ; gain = 417.250 ; free physical = 1816 ; free virtual = 37240
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2091.059 ; gain = 419.219 ; free physical = 8045 ; free virtual = 50557
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 2089.504 ; gain = 417.250 ; free physical = 1816 ; free virtual = 37240
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2091.059 ; gain = 419.219 ; free physical = 8043 ; free virtual = 50556
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 2089.504 ; gain = 417.250 ; free physical = 1815 ; free virtual = 37239
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
@@ -417,17 +417,17 @@ Report Cell Usage:
|
||||
|11 |FDRE | 1105|
|
||||
+------+--------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2091.059 ; gain = 419.219 ; free physical = 8043 ; free virtual = 50556
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 2089.504 ; gain = 417.250 ; free physical = 1815 ; free virtual = 37239
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 321 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2091.059 ; gain = 254.438 ; free physical = 8084 ; free virtual = 50598
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2091.059 ; gain = 419.219 ; free physical = 8084 ; free virtual = 50598
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 2089.504 ; gain = 255.438 ; free physical = 1866 ; free virtual = 37290
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 2089.504 ; gain = 417.250 ; free physical = 1866 ; free virtual = 37290
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
INFO: [Netlist 29-17] Analyzing 1888 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2091.059 ; gain = 0.000 ; free physical = 8651 ; free virtual = 51195
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2089.504 ; gain = 0.000 ; free physical = 1903 ; free virtual = 37167
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
A total of 257 instances were transformed.
|
||||
(MUXCY,XORCY) => CARRY4: 257 instances
|
||||
@@ -435,17 +435,17 @@ INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
66 Infos, 100 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.059 ; gain = 698.051 ; free physical = 8736 ; free virtual = 51283
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2091.059 ; gain = 0.000 ; free physical = 8736 ; free virtual = 51283
|
||||
synth_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 2089.504 ; gain = 694.527 ; free physical = 1998 ; free virtual = 37256
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2089.504 ; gain = 0.000 ; free physical = 1998 ; free virtual = 37256
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b.dcp' has been generated.
|
||||
WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used.
|
||||
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP rotate_16b, cache-ID = 2387465c02ffa019
|
||||
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP rotate_16b, cache-ID = 6d0942f1ca8f60d5
|
||||
INFO: [Coretcl 2-1174] Renamed 371 cell refs.
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2115.070 ; gain = 0.000 ; free physical = 8680 ; free virtual = 51280
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2113.516 ; gain = 0.000 ; free physical = 1975 ; free virtual = 37247
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file rotate_16b_utilization_synth.rpt -pb rotate_16b_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Wed Apr 12 20:00:11 2023...
|
||||
INFO: [Common 17-206] Exiting Vivado at Mon Jun 5 20:28:47 2023...
|
||||
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
+1
-1
@@ -1,7 +1,7 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Wed Apr 12 20:00:10 2023
|
||||
// Date : Mon Jun 5 20:28:46 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b_stub.v
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Wed Apr 12 20:00:10 2023
|
||||
-- Date : Mon Jun 5 20:28:46 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b_stub.vhdl
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
| Date : Wed Apr 12 20:00:10 2023
|
||||
| Date : Mon Jun 5 20:28:46 2023
|
||||
| Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
| Command : report_utilization -file rotate_16b_utilization_synth.rpt -pb rotate_16b_utilization_synth.pb
|
||||
| Design : rotate_16b
|
||||
|
||||
+2
-2
@@ -12,9 +12,9 @@ var WshShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ProcEnv = WshShell.Environment( "Process" );
|
||||
var PathVal = ProcEnv("PATH");
|
||||
if ( PathVal.length == 0 ) {
|
||||
PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;";
|
||||
PathVal = "/home/josh/Software/Xilinx/SDK/2019.1/bin:/home/josh/Software/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/home/josh/Software/Xilinx/Vivado/2019.1/bin;";
|
||||
} else {
|
||||
PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;" + PathVal;
|
||||
PathVal = "/home/josh/Software/Xilinx/SDK/2019.1/bin:/home/josh/Software/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/home/josh/Software/Xilinx/Vivado/2019.1/bin;" + PathVal;
|
||||
}
|
||||
|
||||
ProcEnv("PATH") = PathVal;
|
||||
|
||||
+2
-2
@@ -7,9 +7,9 @@
|
||||
#
|
||||
|
||||
if [ -z "$PATH" ]; then
|
||||
PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin
|
||||
PATH=/home/josh/Software/Xilinx/SDK/2019.1/bin:/home/josh/Software/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/home/josh/Software/Xilinx/Vivado/2019.1/bin
|
||||
else
|
||||
PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin:$PATH
|
||||
PATH=/home/josh/Software/Xilinx/SDK/2019.1/bin:/home/josh/Software/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/home/josh/Software/Xilinx/Vivado/2019.1/bin:$PATH
|
||||
fi
|
||||
export PATH
|
||||
|
||||
|
||||
BIN
Binary file not shown.
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="vio_ant_rd_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681300768">
|
||||
<File Type="RDS-UTIL" Name="vio_ant_rd_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="vio_ant_rd_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="vio_ant_rd_utilization_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="vio_ant_rd.vds"/>
|
||||
<File Type="RDS-DCP" Name="vio_ant_rd.dcp"/>
|
||||
<File Type="PA-TCL" Name="vio_ant_rd.tcl"/>
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="vio_ant_test_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681300768">
|
||||
<File Type="RDS-UTIL" Name="vio_ant_test_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="vio_ant_test_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="vio_ant_test_utilization_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="vio_ant_test.vds"/>
|
||||
<File Type="RDS-DCP" Name="vio_ant_test.dcp"/>
|
||||
<File Type="PA-TCL" Name="vio_ant_test.tcl"/>
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="vio_rf_rd_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681300768">
|
||||
<File Type="RDS-UTIL" Name="vio_rf_rd_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="vio_rf_rd_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="vio_rf_rd_utilization_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="vio_rf_rd.vds"/>
|
||||
<File Type="RDS-DCP" Name="vio_rf_rd.dcp"/>
|
||||
<File Type="PA-TCL" Name="vio_rf_rd.tcl"/>
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="vio_rfcontrl_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681300768">
|
||||
<File Type="RDS-UTIL" Name="vio_rfcontrl_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="vio_rfcontrl_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="vio_rfcontrl_utilization_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="vio_rfcontrl.vds"/>
|
||||
<File Type="RDS-DCP" Name="vio_rfcontrl.dcp"/>
|
||||
<File Type="PA-TCL" Name="vio_rfcontrl.tcl"/>
|
||||
|
||||
@@ -39,13 +39,13 @@
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="74"/>
|
||||
<Option Name="WTModelSimExportSim" Val="74"/>
|
||||
<Option Name="WTQuestaExportSim" Val="74"/>
|
||||
<Option Name="WTIesExportSim" Val="74"/>
|
||||
<Option Name="WTVcsExportSim" Val="74"/>
|
||||
<Option Name="WTRivieraExportSim" Val="74"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="74"/>
|
||||
<Option Name="WTXSimExportSim" Val="76"/>
|
||||
<Option Name="WTModelSimExportSim" Val="76"/>
|
||||
<Option Name="WTQuestaExportSim" Val="76"/>
|
||||
<Option Name="WTIesExportSim" Val="76"/>
|
||||
<Option Name="WTVcsExportSim" Val="76"/>
|
||||
<Option Name="WTRivieraExportSim" Val="76"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="76"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
@@ -817,9 +817,7 @@
|
||||
</Run>
|
||||
<Run Id="ila_8x12_8192_synth_1" Type="Ft3:Synth" SrcSet="ila_8x12_8192" Part="xc7k410tffg900-2" ConstrsSet="ila_8x12_8192" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ila_8x12_8192_synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
@@ -1100,9 +1098,7 @@
|
||||
</Run>
|
||||
<Run Id="ila_8x12_8192_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="ila_8x12_8192" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ila_8x12_8192_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
|
||||
Reference in New Issue
Block a user