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initial commit, add dds_par module

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josh
2024-01-15 09:36:08 +08:00
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common/ApproxAbs.v
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2019/11/15 20:02:47
// Design Name:
// Module Name: ApproxAbs
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ApproxAbs(
input clk,
input Nd,
input [27:0] Dini,
input [27:0] Dinq,
output reg Abs_Rdy = 1'b0,
output reg [28:0] Abs_Dout= 29'd0
);
// 第一级延迟：把输入变负值：
//===============================================================
reg [27:0] Din_I_neg;
always @(posedge clk)begin
if(Dini==28'b1000_0000_0000_0000_0000_0000_0000)begin
Din_I_neg <= 28'b0111_1111_1111_1111_1111_1111_1111;
end else begin
Din_I_neg <= -Dini;
end
end
reg [27:0] Din_Q_neg;
always @(posedge clk)begin
if(Dinq==28'b1000_0000_0000_0000_0000_0000_0000)begin
Din_Q_neg <= 28'b0111_1111_1111_1111_1111_1111_1111;
end else begin
Din_Q_neg <= -Dinq;
end
end
// 第二级延迟：求绝对值：
//===============================================================
reg [27:0] Din_I_D1;
reg [27:0] Din_Q_D1;
always @(posedge clk)begin
Din_I_D1 <= Dini;
Din_Q_D1 <= Dinq;
end
reg [27:0] Abs_Din_I;
reg [27:0] Abs_Din_Q;
always @(posedge clk)begin
if(Din_I_D1[27]==1'b1)
Abs_Din_I <= Din_I_neg;
else
Abs_Din_I <= Din_I_D1;
if(Din_Q_D1[27]==1'b1)
Abs_Din_Q <= Din_Q_neg;
else
Abs_Din_Q <= Din_Q_D1;
end
// 第三级延迟：确定I/Q两路绝对值的大小关系：
//===============================================================
reg [27:0] AbsIQ_max;
reg [27:0] AbsIQ_min;
always @(posedge clk)begin
if (Abs_Din_I>=Abs_Din_Q) begin
AbsIQ_max <= Abs_Din_I;
AbsIQ_min <= Abs_Din_Q;
end else begin
AbsIQ_max <= Abs_Din_Q;
AbsIQ_min <= Abs_Din_I;
end
end
// 第四级延迟：MXQ选择的系数：7/8和1/2：
//===============================================================
reg [27:0] AbsIQ_max_7by8;
reg [27:0] AbsIQ_min_1by2;
always @ (posedge clk) begin
AbsIQ_max_7by8[27:0] <= AbsIQ_max[27:0]-{3'b000,AbsIQ_max[27:3]};
AbsIQ_min_1by2[27:0] <= {AbsIQ_min[27],AbsIQ_min[27:1]};
end
// 第五级延迟：1bit位扩展求和：
// (MXQ)中间将最大延迟一个clk赋给 Dout_Temp2,使 Dout_Temp2与 Dout_Temp在同一个clk下进行比较。
//===============================================================
reg [28:0] Dout_Temp;
reg [28:0] Dout_Temp1;
reg [28:0] Dout_Temp2;
always @(posedge clk) begin
Dout_Temp <= {1'b0,AbsIQ_max_7by8[27:0]}+{1'b0,AbsIQ_min_1by2[27:0]};
Dout_Temp1 <= {1'b0,AbsIQ_max[27:0]};
Dout_Temp2 <= Dout_Temp1[28:0];
end
// (MXQ)第六级延迟：输出求和值与I/Q两路绝对值最大值比较之后的最大值：
reg [28:0] Dout;
always @(posedge clk) begin
if(Dout_Temp[28:0]>=Dout_Temp2[27:0])
Dout[28:0] <= Dout_Temp[28:0];
else
Dout[28:0] <= Dout_Temp2[28:0];
end
// 产生Dout_valid，与Din_valid有七级延迟：
reg Dout_valid_b6;
reg Dout_valid_b5;
reg Dout_valid_b4;
reg Dout_valid_b3;
reg Dout_valid_b2;
reg Dout_valid_b1;
always@(posedge clk) begin //(MXQ)必须加 posedge clk ,否则仿真有问题，内存溢出
Dout_valid_b6 <= Nd;
Dout_valid_b5 <= Dout_valid_b6;
Dout_valid_b4 <= Dout_valid_b5;
Dout_valid_b3 <= Dout_valid_b4;
Dout_valid_b2 <= Dout_valid_b3;
Dout_valid_b1 <= Dout_valid_b2;
Abs_Rdy <= Dout_valid_b1;
end
always @ (posedge clk) begin
if(Dout_valid_b1)
Abs_Dout <= Dout;
else
Abs_Dout <= 29'd0;
end
endmodule
common/ApproxModuli_26bit.v
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2020/12/16 14:26:28
// Design Name:
// Module Name: ApproxModuli_26bit
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ApproxModuli_26bit(
input clk,
input din_valid,
input [25:0] din_I,
input [25:0] din_Q,
output reg dout_valid = 0,
output reg [25:0] dout = 0
);
reg [25:0] din_I_D1 = 0, din_Q_D1 = 0, din_I_D2 = 0, din_Q_D2 = 0;
reg [25:0] Sub1_s = 0;
reg [25:0] Xmax = 0, Xmin = 0;
always @(posedge clk)
begin
if(din_valid)
din_I_D1[25:0] <= (din_I[25]==1'b0)? din_I[25:0]:-din_I[25:0];
else
din_I_D1[25:0] <= 26'd0;
din_I_D2[25:0] <= din_I_D1[25:0];
if(din_valid)
din_Q_D1[25:0] <= (din_Q[25]==1'b0)? din_Q[25:0]:-din_Q[25:0];
else
din_Q_D1[25:0] <= 26'd0;
din_Q_D2[25:0] <= din_Q_D1[25:0];
Sub1_s[25:0] <= din_I_D1[25:0] - din_Q_D1[25:0];
if(Sub1_s[25])
Xmax[25:0] <= din_Q_D2[25:0];
else
Xmax[25:0] <= din_I_D2[25:0];
if(Sub1_s[25])
Xmin[25:0] <= din_I_D2[25:0];
else
Xmin[25:0] <= din_Q_D2[25:0];
end
reg [25:0] Xmax_D1 = 0, Xmax_31by32 = 0, Xmax_13by16 = 0;
reg [25:0] Xmin_9by32 = 0, Xmin_19by32 = 0;
always @(posedge clk)
begin
Xmax_D1[25:0] <= Xmax[25:0];
Xmax_31by32[25:0] <= Xmax[25:0] - {5'd0, Xmax[25:5]};
Xmax_13by16[25:0] <= Xmax[25:0] - {3'd0, Xmax[25:3]} - {4'd0, Xmax[25:4]};
Xmin_9by32[25:0] <= {2'd0, Xmin[25:2]} + {5'd0, Xmin[25:5]};
Xmin_19by32[25:0] <= {1'd0, Xmin[25:1]} + {4'd0, Xmin[25:4]} + {5'd0, Xmin[25:5]};
end
reg [25:0] t1 = 0, t2 = 0, t3 = 0;
always @(posedge clk)
begin
t1[25:0] <= Xmax_D1[25:0];
t2[25:0] <= Xmax_31by32[25:0] + Xmin_9by32[25:0];
t3[25:0] <= Xmax_13by16[25:0] + Xmin_19by32[25:0];
end
reg [25:0] sub2_s = 0;
reg [25:0] sub3_a = 0, sub3_b = 0, sub3_s = 0;
reg [25:0] sub3_a_D1 = 0, sub3_b_D1 = 0;
reg [25:0] t1_D1 = 0, t2_D1 = 0, t3_D1 = 0;
always @(posedge clk)
begin
t1_D1[25:0] <= t1[25:0];
t2_D1[25:0] <= t2[25:0];
t3_D1[25:0] <= t3[25:0];
sub2_s[25:0] <= t1[25:0] - t2[25:0];
if(sub2_s[25])
sub3_a[25:0] <= t2_D1[25:0];
else
sub3_a[25:0] <= t1_D1[25:0];
sub3_b[25:0] <= t3_D1[25:0];
sub3_a_D1[25:0] <= sub3_a[25:0];
sub3_b_D1[25:0] <= sub3_b[25:0];
sub3_s[25:0] <= sub3_a[25:0] - sub3_b[25:0];
if(sub3_s[25])
dout[25:0] <= sub3_b_D1[25:0];
else
dout[25:0] <= sub3_a_D1[25:0];
end
reg din_valid_D1 = 0, din_valid_D2 = 0, din_valid_D3 = 0, din_valid_D4 = 0;
reg din_valid_D5 = 0, din_valid_D6 = 0, din_valid_D7 = 0, din_valid_D8 = 0;
always @(posedge clk)
begin
din_valid_D1 <= din_valid;
din_valid_D2 <= din_valid_D1;
din_valid_D3 <= din_valid_D2;
din_valid_D4 <= din_valid_D3;
din_valid_D5 <= din_valid_D4;
din_valid_D6 <= din_valid_D5;
din_valid_D7 <= din_valid_D6;
din_valid_D8 <= din_valid_D7;
dout_valid <= din_valid_D8;
end
endmodule
common/adder_tree_ppl.v
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
// _ _ ____
// | | ___ ___| |__ / ___| __ _ ___
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
// \___/ \___/|___/_| |_| \____|\__,_|\___/
//
// Create Date: 2022/11/13 16:05:53
// Design Name:
// Module Name: adder_tree_ppl
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// REF: https://blog.csdn.net/jiang1960034308/article/details/118078073
// https://github.com/raiker/tarsier/tree/master/src/
//
//////////////////////////////////////////////////////////////////////////////////
module adder_tree_ppl
#(
parameter DATA_I_WIDTH = 8,
parameter DATA_NUM = 5,
parameter DELAY_STAGE = $clog2(DATA_NUM), // necessary for pipeline delay stage
localparam DATA_O_WIDTH = DATA_I_WIDTH + $clog2(DATA_NUM),
localparam DATA_NUM_A = DATA_NUM / 2,
localparam DATA_NUM_B = DATA_NUM - DATA_NUM_A,
localparam DATA_O_WIDTH_A = DATA_I_WIDTH + $clog2(DATA_NUM_A),
localparam DATA_O_WIDTH_B = DATA_I_WIDTH + $clog2(DATA_NUM_B)
)
(
// clock & reset
input clk,
input rst,
// input data
input din_valid,
input signed [DATA_NUM*DATA_I_WIDTH-1 : 0] din_data,
// output data
output dout_valid,
output signed [DATA_O_WIDTH-1 : 0] dout_data
);
if (DATA_NUM == 1) begin
if (DELAY_STAGE == 1) begin
// buffer when an extra delay stage is needed
reg dout_valid_buf = 'b0;
reg signed [DATA_O_WIDTH-1 : 0] dout_data_buf = 'b0;
always@(posedge clk) begin
dout_valid_buf <= (rst) ? 'b0 : din_valid;
dout_data_buf <= (rst) ? 'b0 : din_data;
end
assign dout_valid = dout_valid_buf;
assign dout_data = dout_data_buf;
end
else begin
assign dout_valid = din_valid;
assign dout_data = din_data;
end
end
else begin
reg dout_valid_buf = 'b0;
reg signed [DATA_O_WIDTH-1 : 0] dout_data_buf = 'b0;
wire din_valid_a;
wire din_valid_b;
wire signed [DATA_I_WIDTH * DATA_NUM_A - 1:0] din_data_a;
wire signed [DATA_I_WIDTH * DATA_NUM_B - 1:0] din_data_b;
wire dout_valid_a;
wire dout_valid_b;
wire signed [DATA_O_WIDTH_A-1:0] dout_data_a;
wire signed [DATA_O_WIDTH_B-1:0] dout_data_b;
assign din_valid_a = din_valid;
assign din_valid_b = din_valid;
assign din_data_a = din_data[DATA_I_WIDTH * DATA_NUM_A - 1: 0];
assign din_data_b = din_data[DATA_NUM * DATA_I_WIDTH - 1: DATA_I_WIDTH * DATA_NUM_A];
//divide set into two chunks, conquer
adder_tree_ppl #(
.DATA_I_WIDTH (DATA_I_WIDTH ),
.DATA_NUM (DATA_NUM_A ),
.DELAY_STAGE (DELAY_STAGE - 1)
) subtree_a (
// clock & reset
.clk (clk ),
.rst (rst ),
// input data
.din_valid (din_valid_a ),
.din_data (din_data_a ),
// output data
.dout_valid (dout_valid_a ),
.dout_data (dout_data_a )
);
adder_tree_ppl #(
.DATA_I_WIDTH (DATA_I_WIDTH ),
.DATA_NUM (DATA_NUM_B ),
.DELAY_STAGE (DELAY_STAGE - 1)
) subtree_b (
// clock & reset
.clk (clk ),
.rst (rst ),
// input data
.din_valid (din_valid_b ),
.din_data (din_data_b ),
// output data
.dout_valid (dout_valid_b ),
.dout_data (dout_data_b )
);
always@(posedge clk) begin
if (rst) begin
dout_valid_buf <= 'b0;
dout_data_buf <= 'b0;
end
else begin
dout_valid_buf <= dout_valid_a & dout_valid_b;
dout_data_buf <= dout_data_a + dout_data_b;
end
end
assign dout_valid = dout_valid_buf;
assign dout_data = dout_data_buf;
end
endmodule
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
// _ _ ____
// | | ___ ___| |__ / ___| __ _ ___
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
// \___/ \___/|___/_| |_| \____|\__,_|\___/
//
// Create Date: 2022/11/13 16:40:15
// Last Modified Data: 2022/11/02
// Design Name:
// Module Name: tb_adder_tree_pip
// Project Name:
// Target Devices:
// Tool Versions:
// Description: testbench for [adder_tree_ppl]
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// module tb_adder_tree_ppl;
// localparam DATA_I_WIDTH = 16;
// localparam DATA_NUM = 9;
// reg clk = 1'b1;
// reg rst = 1'b1;
// reg din_valid = 1'b0;
// reg [DATA_NUM*DATA_I_WIDTH-1 : 0] din_data = 'b0;
// wire dout_valid;
// wire [DATA_I_WIDTH+$clog2(DATA_NUM)-1 : 0] dout_data;
// adder_tree_ppl #(
// .DATA_I_WIDTH (DATA_I_WIDTH ),
// .DATA_NUM (DATA_NUM )
// ) u_adder_tree_ppl
// (
// // clock & reset
// .clk (clk ),
// .rst (rst ),
// // input data
// .din_valid (din_valid ),
// .din_data (din_data ),
// // output data
// .dout_valid (dout_valid ),
// .dout_data (dout_data )
// );
// initial begin
// #102
// rst = 1'b0;
// #200
// @(posedge clk) begin
// din_valid = 1'b1;
// din_data = {
// 16'd1,
// 16'd2,
// 16'd3,
// 16'd4,
// 16'd5,
// 16'd6,
// 16'd7,
// 16'd8,
// 16'd9
// };
// end
// @(posedge clk) begin
// din_valid = 1'b1;
// din_data = {
// 16'd1230,
// 16'd1231,
// 16'd1232,
// 16'd1233,
// 16'd1234,
// 16'd1235,
// 16'd1236,
// 16'd1237,
// 16'd1238
// };
// end
// @(posedge clk) din_valid = 1'b0;
// end
// always #5 clk = ~clk;
// endmodule
common/trunc_32bit_to_12bit.v
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2023/03/01 10:44:50
// Design Name:
// Module Name: trunc_32bit_to_12bit
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module trunc_32bit_to_12bit(
input clk,
input rst,
input [31:0] trunc_32bit_in,
input [4:0] vio_trunc,
output reg [11:0] trunc_12bit_out = 12'd0,
output reg trunc_overflow = 1'd0
);
always @ (posedge clk) begin
if(rst) begin
trunc_12bit_out[11:0] <= 12'd0;
trunc_overflow <= 1'd0;
end else begin
case(vio_trunc[4:0])
5'd0:begin
if(trunc_32bit_in[31:31] == 1'd1 || trunc_32bit_in[31:31] == 1'd0) begin
if(trunc_32bit_in[31:31] == 1'd0 &&trunc_32bit_in[19] == 1'd1 && trunc_32bit_in[31:20] != 12'd2047) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[31:20] + 12'd1;
end
else begin
if(trunc_32bit_in[31:31] == 1'd1 && trunc_32bit_in[19:0] > 20'd524288) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[31:20] + 12'd1;
end
else begin
trunc_12bit_out[11:0] <= trunc_32bit_in[31:20];
end
end
trunc_overflow <= 1'd0;
end else begin
if(trunc_32bit_in[31] == 1'd1) begin
trunc_12bit_out[11:0] <= -12'd2048;
end else begin
trunc_12bit_out[11:0] <= 12'd2047;
end
trunc_overflow <= 1'd1;
end
end
5'd1:begin
if(trunc_32bit_in[31:30] == 2'd3 || trunc_32bit_in[31:30] == 2'd0) begin
if(trunc_32bit_in[31:30] == 2'd0 &&trunc_32bit_in[18] == 1'd1 && trunc_32bit_in[30:19] != 12'd2047) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[30:19] + 12'd1;
end
else begin
if(trunc_32bit_in[31:30] == 2'd3 && trunc_32bit_in[18:0] > 19'd262144) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[30:19] + 12'd1;
end
else begin
trunc_12bit_out[11:0] <= trunc_32bit_in[30:19];
end
end
trunc_overflow <= 1'd0;
end else begin
if(trunc_32bit_in[31] == 1'd1) begin
trunc_12bit_out[11:0] <= -12'd2048;
end else begin
trunc_12bit_out[11:0] <= 12'd2047;
end
trunc_overflow <= 1'd1;
end
end
5'd2:begin
if(trunc_32bit_in[31:29] == 3'd7 || trunc_32bit_in[31:29] == 3'd0) begin
if(trunc_32bit_in[31:29] == 3'd0 &&trunc_32bit_in[17] == 1'd1 && trunc_32bit_in[29:18] != 12'd2047) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[29:18] + 12'd1;
end
else begin
if(trunc_32bit_in[31:29] == 3'd7 && trunc_32bit_in[17:0] > 18'd131072) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[29:18] + 12'd1;
end
else begin
trunc_12bit_out[11:0] <= trunc_32bit_in[29:18];
end
end
trunc_overflow <= 1'd0;
end else begin
if(trunc_32bit_in[31] == 1'd1) begin
trunc_12bit_out[11:0] <= -12'd2048;
end else begin
trunc_12bit_out[11:0] <= 12'd2047;
end
trunc_overflow <= 1'd1;
end
end
5'd3:begin
if(trunc_32bit_in[31:28] == 4'd15 || trunc_32bit_in[31:28] == 4'd0) begin
if(trunc_32bit_in[31:28] == 4'd0 &&trunc_32bit_in[16] == 1'd1 && trunc_32bit_in[28:17] != 12'd2047) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[28:17] + 12'd1;
end
else begin
if(trunc_32bit_in[31:28] == 4'd15 && trunc_32bit_in[16:0] > 17'd65536) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[28:17] + 12'd1;
end
else begin
trunc_12bit_out[11:0] <= trunc_32bit_in[28:17];
end
end
trunc_overflow <= 1'd0;
end else begin
if(trunc_32bit_in[31] == 1'd1) begin
trunc_12bit_out[11:0] <= -12'd2048;
end else begin
trunc_12bit_out[11:0] <= 12'd2047;
end
trunc_overflow <= 1'd1;
end
end
5'd4:begin
if(trunc_32bit_in[31:27] == 5'd31 || trunc_32bit_in[31:27] == 5'd0) begin
if(trunc_32bit_in[31:27] == 5'd0 &&trunc_32bit_in[15] == 1'd1 && trunc_32bit_in[27:16] != 12'd2047) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[27:16] + 12'd1;
end
else begin
if(trunc_32bit_in[31:27] == 5'd31 && trunc_32bit_in[15:0] > 16'd32768) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[27:16] + 12'd1;
end
else begin
trunc_12bit_out[11:0] <= trunc_32bit_in[27:16];
end
end
trunc_overflow <= 1'd0;
end else begin
if(trunc_32bit_in[31] == 1'd1) begin
trunc_12bit_out[11:0] <= -12'd2048;
end else begin
trunc_12bit_out[11:0] <= 12'd2047;
end
trunc_overflow <= 1'd1;
end
end
5'd5:begin
if(trunc_32bit_in[31:26] == 6'd63 || trunc_32bit_in[31:26] == 6'd0) begin
if(trunc_32bit_in[31:26] == 6'd0 &&trunc_32bit_in[14] == 1'd1 && trunc_32bit_in[26:15] != 12'd2047) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[26:15] + 12'd1;
end
else begin
if(trunc_32bit_in[31:26] == 6'd63 && trunc_32bit_in[14:0] > 15'd16384) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[26:15] + 12'd1;
end
else begin
trunc_12bit_out[11:0] <= trunc_32bit_in[26:15];
end
end
trunc_overflow <= 1'd0;
end else begin
if(trunc_32bit_in[31] == 1'd1) begin
trunc_12bit_out[11:0] <= -12'd2048;
end else begin
trunc_12bit_out[11:0] <= 12'd2047;
end
trunc_overflow <= 1'd1;
end
end
5'd6:begin
if(trunc_32bit_in[31:25] == 7'd127 || trunc_32bit_in[31:25] == 7'd0) begin
if(trunc_32bit_in[31:25] == 7'd0 &&trunc_32bit_in[13] == 1'd1 && trunc_32bit_in[25:14] != 12'd2047) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[25:14] + 12'd1;
end
else begin
if(trunc_32bit_in[31:25] == 7'd127 && trunc_32bit_in[13:0] > 14'd8192) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[25:14] + 12'd1;
end
else begin
trunc_12bit_out[11:0] <= trunc_32bit_in[25:14];
end
end
trunc_overflow <= 1'd0;
end else begin
if(trunc_32bit_in[31] == 1'd1) begin
trunc_12bit_out[11:0] <= -12'd2048;
end else begin
trunc_12bit_out[11:0] <= 12'd2047;
end
trunc_overflow <= 1'd1;
end
end
5'd7:begin
if(trunc_32bit_in[31:24] == 8'd255 || trunc_32bit_in[31:24] == 8'd0) begin
if(trunc_32bit_in[31:24] == 8'd0 &&trunc_32bit_in[12] == 1'd1 && trunc_32bit_in[24:13] != 12'd2047) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[24:13] + 12'd1;
end
else begin
if(trunc_32bit_in[31:24] == 8'd255 && trunc_32bit_in[12:0] > 13'd4096) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[24:13] + 12'd1;
end
else begin
trunc_12bit_out[11:0] <= trunc_32bit_in[24:13];
end
end
trunc_overflow <= 1'd0;
end else begin
if(trunc_32bit_in[31] == 1'd1) begin
trunc_12bit_out[11:0] <= -12'd2048;
end else begin
trunc_12bit_out[11:0] <= 12'd2047;
end
trunc_overflow <= 1'd1;
end
end
5'd8:begin
if(trunc_32bit_in[31:23] == 9'd511 || trunc_32bit_in[31:23] == 9'd0) begin
if(trunc_32bit_in[31:23] == 9'd0 &&trunc_32bit_in[11] == 1'd1 && trunc_32bit_in[23:12] != 12'd2047) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[23:12] + 12'd1;
end
else begin
if(trunc_32bit_in[31:23] == 9'd511 && trunc_32bit_in[11:0] > 12'd2048) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[23:12] + 12'd1;
end
else begin
trunc_12bit_out[11:0] <= trunc_32bit_in[23:12];
end
end
trunc_overflow <= 1'd0;
end else begin
if(trunc_32bit_in[31] == 1'd1) begin
trunc_12bit_out[11:0] <= -12'd2048;
end else begin
trunc_12bit_out[11:0] <= 12'd2047;
end
trunc_overflow <= 1'd1;
end
end
5'd9:begin
if(trunc_32bit_in[31:22] == 10'd1023 || trunc_32bit_in[31:22] == 10'd0) begin
if(trunc_32bit_in[31:22] == 10'd0 &&trunc_32bit_in[10] == 1'd1 && trunc_32bit_in[22:11] != 12'd2047) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[22:11] + 12'd1;
end
else begin
if(trunc_32bit_in[31:22] == 10'd1023 && trunc_32bit_in[10:0] > 11'd1024) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[22:11] + 12'd1;
end
else begin
trunc_12bit_out[11:0] <= trunc_32bit_in[22:11];
end
end
trunc_overflow <= 1'd0;
end else begin
if(trunc_32bit_in[31] == 1'd1) begin
trunc_12bit_out[11:0] <= -12'd2048;
end else begin
trunc_12bit_out[11:0] <= 12'd2047;
end
trunc_overflow <= 1'd1;
end
end
5'd10:begin
if(trunc_32bit_in[31:21] == 11'd2047 || trunc_32bit_in[31:21] == 11'd0) begin
if(trunc_32bit_in[31:21] == 11'd0 &&trunc_32bit_in[9] == 1'd1 && trunc_32bit_in[21:10] != 12'd2047) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[21:10] + 12'd1;
end
else begin
if(trunc_32bit_in[31:21] == 11'd2047 && trunc_32bit_in[9:0] > 10'd512) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[21:10] + 12'd1;
end
else begin
trunc_12bit_out[11:0] <= trunc_32bit_in[21:10];
end
end
trunc_overflow <= 1'd0;
end else begin
if(trunc_32bit_in[31] == 1'd1) begin
trunc_12bit_out[11:0] <= -12'd2048;
end else begin
trunc_12bit_out[11:0] <= 12'd2047;
end
trunc_overflow <= 1'd1;
end
end
5'd11:begin
if(trunc_32bit_in[31:20] == 12'd4095 || trunc_32bit_in[31:20] == 12'd0) begin
if(trunc_32bit_in[31:20] == 12'd0 &&trunc_32bit_in[8] == 1'd1 && trunc_32bit_in[20:9] != 12'd2047) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[20:9] + 12'd1;
end
else begin
if(trunc_32bit_in[31:20] == 12'd4095 && trunc_32bit_in[8:0] > 9'd256) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[20:9] + 12'd1;
end
else begin
trunc_12bit_out[11:0] <= trunc_32bit_in[20:9];
end
end
trunc_overflow <= 1'd0;
end else begin
if(trunc_32bit_in[31] == 1'd1) begin
trunc_12bit_out[11:0] <= -12'd2048;
end else begin
trunc_12bit_out[11:0] <= 12'd2047;
end
trunc_overflow <= 1'd1;
end
end
5'd12:begin
if(trunc_32bit_in[31:19] == 13'd8191 || trunc_32bit_in[31:19] == 13'd0) begin
if(trunc_32bit_in[31:19] == 13'd0 &&trunc_32bit_in[7] == 1'd1 && trunc_32bit_in[19:8] != 12'd2047) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[19:8] + 12'd1;
end
else begin
if(trunc_32bit_in[31:19] == 13'd8191 && trunc_32bit_in[7:0] > 8'd128) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[19:8] + 12'd1;
end
else begin
trunc_12bit_out[11:0] <= trunc_32bit_in[19:8];
end
end
trunc_overflow <= 1'd0;
end else begin
if(trunc_32bit_in[31] == 1'd1) begin
trunc_12bit_out[11:0] <= -12'd2048;
end else begin
trunc_12bit_out[11:0] <= 12'd2047;
end
trunc_overflow <= 1'd1;
end
end
5'd13:begin
if(trunc_32bit_in[31:18] == 14'd16383 || trunc_32bit_in[31:18] == 14'd0) begin
if(trunc_32bit_in[31:18] == 14'd0 &&trunc_32bit_in[6] == 1'd1 && trunc_32bit_in[18:7] != 12'd2047) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[18:7] + 12'd1;
end
else begin
if(trunc_32bit_in[31:18] == 14'd16383 && trunc_32bit_in[6:0] > 7'd64) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[18:7] + 12'd1;
end
else begin
trunc_12bit_out[11:0] <= trunc_32bit_in[18:7];
end
end
trunc_overflow <= 1'd0;
end else begin
if(trunc_32bit_in[31] == 1'd1) begin
trunc_12bit_out[11:0] <= -12'd2048;
end else begin
trunc_12bit_out[11:0] <= 12'd2047;
end
trunc_overflow <= 1'd1;
end
end
5'd14:begin
if(trunc_32bit_in[31:17] == 15'd32767 || trunc_32bit_in[31:17] == 15'd0) begin
if(trunc_32bit_in[31:17] == 15'd0 &&trunc_32bit_in[5] == 1'd1 && trunc_32bit_in[17:6] != 12'd2047) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[17:6] + 12'd1;
end
else begin
if(trunc_32bit_in[31:17] == 15'd32767 && trunc_32bit_in[5:0] > 6'd32) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[17:6] + 12'd1;
end
else begin
trunc_12bit_out[11:0] <= trunc_32bit_in[17:6];
end
end
trunc_overflow <= 1'd0;
end else begin
if(trunc_32bit_in[31] == 1'd1) begin
trunc_12bit_out[11:0] <= -12'd2048;
end else begin
trunc_12bit_out[11:0] <= 12'd2047;
end
trunc_overflow <= 1'd1;
end
end
5'd15:begin
if(trunc_32bit_in[31:16] == 16'd65535 || trunc_32bit_in[31:16] == 16'd0) begin
if(trunc_32bit_in[31:16] == 16'd0 &&trunc_32bit_in[4] == 1'd1 && trunc_32bit_in[16:5] != 12'd2047) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[16:5] + 12'd1;
end
else begin
if(trunc_32bit_in[31:16] == 16'd65535 && trunc_32bit_in[4:0] > 5'd16) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[16:5] + 12'd1;
end
else begin
trunc_12bit_out[11:0] <= trunc_32bit_in[16:5];
end
end
trunc_overflow <= 1'd0;
end else begin
if(trunc_32bit_in[31] == 1'd1) begin
trunc_12bit_out[11:0] <= -12'd2048;
end else begin
trunc_12bit_out[11:0] <= 12'd2047;
end
trunc_overflow <= 1'd1;
end
end
5'd16:begin
if(trunc_32bit_in[31:15] == 17'd131071 || trunc_32bit_in[31:15] == 17'd0) begin
if(trunc_32bit_in[31:15] == 17'd0 &&trunc_32bit_in[3] == 1'd1 && trunc_32bit_in[15:4] != 12'd2047) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[15:4] + 12'd1;
end
else begin
if(trunc_32bit_in[31:15] == 17'd131071 && trunc_32bit_in[3:0] > 4'd8) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[15:4] + 12'd1;
end
else begin
trunc_12bit_out[11:0] <= trunc_32bit_in[15:4];
end
end
trunc_overflow <= 1'd0;
end else begin
if(trunc_32bit_in[31] == 1'd1) begin
trunc_12bit_out[11:0] <= -12'd2048;
end else begin
trunc_12bit_out[11:0] <= 12'd2047;
end
trunc_overflow <= 1'd1;
end
end
5'd17:begin
if(trunc_32bit_in[31:14] == 18'd262143 || trunc_32bit_in[31:14] == 18'd0) begin
if(trunc_32bit_in[31:14] == 18'd0 &&trunc_32bit_in[2] == 1'd1 && trunc_32bit_in[14:3] != 12'd2047) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[14:3] + 12'd1;
end
else begin
if(trunc_32bit_in[31:14] == 18'd262143 && trunc_32bit_in[2:0] > 3'd4) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[14:3] + 12'd1;
end
else begin
trunc_12bit_out[11:0] <= trunc_32bit_in[14:3];
end
end
trunc_overflow <= 1'd0;
end else begin
if(trunc_32bit_in[31] == 1'd1) begin
trunc_12bit_out[11:0] <= -12'd2048;
end else begin
trunc_12bit_out[11:0] <= 12'd2047;
end
trunc_overflow <= 1'd1;
end
end
5'd18:begin
if(trunc_32bit_in[31:13] == 19'd524287 || trunc_32bit_in[31:13] == 19'd0) begin
if(trunc_32bit_in[31:13] == 19'd0 &&trunc_32bit_in[1] == 1'd1 && trunc_32bit_in[13:2] != 12'd2047) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[13:2] + 12'd1;
end
else begin
if(trunc_32bit_in[31:13] == 19'd524287 && trunc_32bit_in[1:0] > 2'd2) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[13:2] + 12'd1;
end
else begin
trunc_12bit_out[11:0] <= trunc_32bit_in[13:2];
end
end
trunc_overflow <= 1'd0;
end else begin
if(trunc_32bit_in[31] == 1'd1) begin
trunc_12bit_out[11:0] <= -12'd2048;
end else begin
trunc_12bit_out[11:0] <= 12'd2047;
end
trunc_overflow <= 1'd1;
end
end
5'd19:begin
if(trunc_32bit_in[31:12] == 20'd1048575 || trunc_32bit_in[31:12] == 20'd0) begin
if(trunc_32bit_in[31:12] == 20'd0 &&trunc_32bit_in[0] == 1'd1 && trunc_32bit_in[12:1] != 12'd2047) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[12:1] + 12'd1;
end
else begin
if(trunc_32bit_in[31:12] == 20'd1048575 && trunc_32bit_in[0:0] > 1'd1) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[12:1] + 12'd1;
end
else begin
trunc_12bit_out[11:0] <= trunc_32bit_in[12:1];
end
end
trunc_overflow <= 1'd0;
end else begin
if(trunc_32bit_in[31] == 1'd1) begin
trunc_12bit_out[11:0] <= -12'd2048;
end else begin
trunc_12bit_out[11:0] <= 12'd2047;
end
trunc_overflow <= 1'd1;
end
end
default:begin
if(trunc_32bit_in[31:11] == 21'd2097151 || trunc_32bit_in[31:11] == 21'd0) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[11:0];
trunc_overflow <= 1'd0;
end else begin
if(trunc_32bit_in[31] == 1'd1) begin
trunc_12bit_out[11:0] <= -12'd2048;
end else begin
trunc_12bit_out[11:0] <= 12'd2047;
end
trunc_overflow <= 1'd1;
end
end
endcase
end
end
endmodule
common/truncate_manual.v
+43
View File
@@ -0,0 +1,43 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04/21/2023 11:37:14 AM
// Design Name:
// Module Name: truncate_manual
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module truncate_manual
#(
DATA_I_WIDTH = 30,
DATA_O_WIDTH = 12
)
(
input clk,
input rst,
input [DATA_I_WIDTH-1 : 0] data_in,
input data_in_valid,
input [$clog2(DATA_I_WIDTH)-1 : 0] trunc_pos,
output [DATA_O_WIDTH-1 : 0] data_out,
output data_out_valid
);
assign data_out = data_in[trunc_pos -: DATA_O_WIDTH];
endmodule